Test program debug device, semiconductor test device, test program debug method, and test method

The present invention relates to a test program debugging apparatus, a semiconductor testing apparatus, a test program debugging method, and a test method. In particular, the present invention is a test program debugging device and a test program debugging method for virtually executing a test program for a semiconductor test device to debug the test program, and a semiconductor for testing a device under test by executing the test program. Regarding test equipment and test methods.

The semiconductor test apparatus supplies a test pattern to the device under test by executing a test program for the semiconductor test apparatus, and performs various tests on the device under test. This test program consists of a huge number of instructions that specify test conditions, test pattern generation, test pattern comparison, etc., and is created or modified according to the type of semiconductor test equipment and the type of device under test. Then, when the test program is created or changed, it is necessary to verify whether or not the test program operates normally. Therefore, conventionally, the test program is verified by causing the test program debug device that simulates the semiconductor test device and the device under test to execute the test program using a general-purpose computer such as a workstation (for example, a patent). See Reference 1.). Patent Document 1 Japanese Patent Application Laid-Open No. 2001-51025

<p> However, as described above, since the test program is composed of a huge number of instructions, it takes a lot of time to execute the test program. In addition, the conventional test program debug device cannot execute only some instructions of the test program, and verifies only the instructions of some test items among a plurality of test items, or multiple tests. Even if only the instructions for generating some test patterns of the patterns are verified, all the instructions of the test program must be executed. Therefore, there is a problem that it takes a lot of time to verify the test program.</p><p> Therefore, an object of the present invention is to provide a test apparatus capable of solving the above problems. This purpose is achieved by a combination of the features described in the independent clause in the claims. Dependent terms also define further advantageous embodiments of the present invention.</p>

<p> According to the first aspect of the present invention, it is a test program debugging device that debugs a test program for a semiconductor test device, and is a test device simulator that simulates the device under test, and a semiconductor test by executing the test program. It is equipped with a semiconductor test equipment simulator that simulates the equipment and supplies a test pattern to the device simulator under test.</p><p> The semiconductor test equipment simulator is a non-verification included in a verification range acquisition unit that acquires a verification range that is the range of instructions to be verified in the test program and a non-verification range that is a range other than the verification range in the test program. Among the range instructions, the instruction simplification unit that simplifies non-setting instructions other than the setting instruction for setting the device simulator under test, and the verification range instruction, setting instruction, and instruction simplification unit included in the verification range It has an instruction execution unit that executes a simplified non-setting instruction.</p><p> The non-setting instruction includes, as a non-setting instruction, a pattern generation instruction for generating a test pattern and a pattern comparison instruction for comparing the output pattern output from the device simulator under test with the expected value for the test pattern. The instruction simplification unit may simplify the pattern generation instruction and the pattern comparison instruction, and the instruction execution unit may execute the verification range instruction and the setting instruction, and the simplified pattern generation instruction and the pattern comparison instruction.</p><p> The instruction simplification unit sets the non-setting instruction as an instruction that is not executed by the instruction execution unit, and the instruction execution unit executes the verification range instruction and the setting instruction, and does not have to execute the non-setting instruction.</p><p> According to the second embodiment of the present invention, it is a test program debugging device that debugs a test program for a semiconductor test device, and is a test device simulator that simulates the device under test, and a semiconductor test by executing the test program. It is equipped with a semiconductor test equipment simulator that simulates the equipment and transfers test patterns to the device simulator under test.</p><p> The semiconductor test equipment simulator acquires the verification range, which is the range of instructions to be verified in the test program, and the device simulator under test is included in the non-verification range, which is the range other than the verification range in the test program. Among the verification range instructions, the simulation based on the non-setting instruction other than the setting instruction for setting the device simulator under test is simplified and executed.</p><p> The device simulator under test holds an output pattern for the test pattern supplied from the semiconductor test device simulator in advance, and holds the output pattern for the test pattern from the semiconductor test device simulator based on the non-setting instruction in advance. May be output.</p><p> According to the third aspect of the present invention, it is a semiconductor test apparatus that tests a device under test by executing a test program, and is a test range that is a range of instructions to be used for testing the device under test in the test program. Of the non-test range commands included in the non-test range that is the range other than the test range of the test program and the test range acquisition unit, the non-setting commands other than the setting command for setting the device under test It is provided with an instruction simplification unit that simplifies the above, and an instruction execution unit that executes a test range instruction, a setting instruction, and a non-setting instruction simplified by the instruction simplification unit included in the test range.</p><p> The non-setting instruction includes, as a non-setting instruction, a pattern generation instruction for generating a test pattern and a pattern comparison instruction for comparing the test pattern output from the device under test with the expected value for the test pattern. The simplification unit may simplify the pattern generation instruction and the pattern comparison instruction, and the instruction execution unit may execute the test range instruction and the setting instruction, and the simplified pattern generation instruction and the pattern comparison instruction.</p><p> According to the fourth aspect of the present invention, the device under test simulator that simulates the device under test and the test program for the semiconductor test apparatus are executed to simulate the semiconductor test apparatus, and the test pattern is applied to the device under test simulator. It is a test program debugging method by a test program debugging device equipped with a semiconductor test device simulator to be supplied, and a stage of acquiring a verification range which is a range of instructions to be verified in the test program and a verification range of the test program. Among the non-verification range instructions included in the non-verification range, which is a range other than the above, the stage of simplifying the non-setting instructions other than the setting instruction for setting the device simulator to be tested, and the verification range instruction included in the verification range. , A setting instruction, and a stage of executing a simplified non-setting instruction.</p><p> According to the fifth aspect of the present invention, a test method for testing a device under test by executing a test program, which is a range of instructions to be used for testing the device under test in the test program. Simplify the non-setting instructions other than the setting instruction for setting the device under test among the non-test range instructions included in the non-test range that is the range other than the test range in the acquisition stage and the test program. It comprises a step and a step of executing a test range instruction, a setting instruction, and a simplified non-setting instruction included in the test range.</p><p> The outline of the above invention does not list all the necessary features of the present invention, and a subcombination of these feature groups can also be an invention.</p>

<figref num="1">It is a figure which shows an example of the structure of the test program debug apparatus 100.</figref><figref num="2">It is a figure which shows an example of the structure of the semiconductor test apparatus 200.</figref><figref num="3">It is a figure which shows an example of the structure of the test program 110 and the pattern program 300.</figref>

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims, and all combinations of features described in the embodiments are inventions. It is not always essential for the solution of.

FIG. 1 shows an example of the configuration of the test program debugging device 100 according to the embodiment of the present invention. The test program debug device 100 is realized by a general-purpose computer such as a workstation, and by simulating the operation of the semiconductor test device 200 and the device under test 202, it is verified whether or not the test program 110 operates normally. Debug. As described above, since the test program debug device 100 simulates the semiconductor test device 200 and the device under test 202, first, the configuration and operation of the actual semiconductor test device 200 will be described with reference to FIG.

FIG. 2 shows an example of the configuration of the semiconductor test apparatus 200 according to the embodiment of the present invention. The semiconductor test apparatus 200 includes a test module 206 that is connected to the device under test 202 and passes a test pattern to the device under test 202, a test module control unit 204 that controls the test module 206, and a test module control unit 204 and a test. It includes a tester bus 222 that connects to the module 206. The test module control unit 204 includes a test program 110, an application program 210, a language analysis execution unit 212, a tester library 214, and a tester bus driver 216. Then, the application program 210 functions as a test range acquisition unit 218 and an instruction simplification unit 220. Further, the test module 206 has a register 224, a memory 226, and a test execution unit 228.

The test program 110 describes the contents of the test to be performed on the device 202 to be tested. The language analysis execution unit 212 analyzes the syntax of the test program 110 and operates the semiconductor test apparatus 200 according to the test program 110. The application program 210 operates in cooperation with the test program 110 and the language analysis execution unit 212, and controls the application of the test pattern to the device under test 202. The tester library 214 converts the instruction of the test program 110 that has been parsed by the language analysis execution unit 212 into a register-level instruction to generate pattern data and set the test module 206, and also to the test module 206. In response to this, the measurement operation is instructed. Then, the tester bus driver 216 transfers the pattern data generated by the tester library 214 to the register 224 via the tester bus 222.

The register 224 stores the pattern data generated by the tester library 214, and supplies the stored pattern data to the test execution unit 228 directly or via the memory 226. Then, the test execution unit 228 tests the device under test 202 based on the pattern data stored in the register 224 or the memory 226, and stores the test result in the register 224 or the memory 226. Then, the tester bus driver 216 takes the test result stored in the register 224 or the memory 226 into the tester library 214 via the tester bus 222. Then, the application program 210 performs quality determination of the device under test 202, characteristic analysis of the device 202 under test, and the like based on the test results taken into the tester library 214.

The test program debugging device 100 shown in FIG. 1 simulates the operations of the semiconductor test device 200 and the device under test 202 described above, verifies whether or not the test program 110 operates normally, and performs debugging. Next, the configuration and operation of the test program debugging device 100 will be described with reference to FIG.

The test program debug device 100 executes the test device simulator 104 that simulates the device under test 202 and the test program 110 to simulate the semiconductor test device 200, and supplies a test pattern to the device under test 202. It is equipped with the device simulator 102. The semiconductor test device simulator 102 is a virtual connection between the test module emulator 108 that emulates the test module 206, the emulator control unit 106 that controls the test module emulator 108, and the emulator control unit 106 and the test module emulator 108. It has a tester bus 124 and a test result analysis determination unit 136 that analyzes the test results of the device simulator 104 under test.

The emulator control unit 106 includes a test program 110, an application program 112, a language analysis execution unit 114, a tester library 116, and a tester bus emulator 118. Then, the application program 112 functions as a verification range acquisition unit 120 and an instruction simplification unit 122. Further, the test module emulator 108 includes a virtual register 126, a virtual memory 128, and a virtual test execution unit 130.

The emulator control unit 106 performs the same operation as the test module control unit 204 shown in FIG. 2, and controls the test module emulator 108 that realizes the operation of the test module 206 shown in FIG. 2 by software. The test program 110 is a port of the test program 110 shown in FIG. 2, and is the target of debugging by the test program debugging apparatus 100. The language analysis execution unit 114 analyzes the syntax of the test program 110 and operates the semiconductor test apparatus simulator 102 according to the test program 110. The application program 112 operates in cooperation with the test program 110 and the language analysis execution unit 114, and controls the application of the test pattern to the device simulator 104 under test. The tester library 116 is an example of the instruction execution unit of the present invention, and converts the instruction of the test program 110 that has been parsed by the language analysis execution unit 114 into a register-level instruction to generate pattern data and a test module. In addition to setting the emulator 108, the test module emulator 108 is instructed to perform measurement operations. Then, the tester bus emulator 118 transfers the pattern data generated by the tester library 116 to the virtual register 126 via the virtual tester bus 124.

The virtual register 126 stores the pattern data generated by the tester library 116, and supplies the stored pattern data to the virtual test execution unit 130 directly or via the virtual memory 128. Then, the virtual test execution unit 130 performs a virtual test of the device simulator 104 under test based on the pattern data stored in the virtual register 126 or the virtual memory 128, and stores the virtual test result in the virtual register 126 or the virtual memory 128. To do. Then, the tester bus emulator 118 takes in the virtual test result stored in the virtual register 126 or the virtual memory 128 into the tester library 116 via the virtual tester bus 124. Then, the test result analysis determination unit 136 compares and examines the virtual test result stored in the tester library 116, the virtual register 126, or the virtual memory 128 with the expected value of the virtual test result generated in advance. Then, the test result analysis determination unit 136 verifies whether the test program 110 is operating normally, and notifies the user of the verification result. For example, when the virtual test result and the expected value are different, the line number of the test program 110, which is the source of the virtual test result, is displayed on the monitor or printed by a printer.

FIG. 3 shows an example of the configuration of the test program 110 and the pattern program 300. The test program 110 provides a test condition instruction group 304 that defines the test conditions and a measurement instruction group 306 that measures the output pattern from the device under test 202 or the test module emulator 108 for each test number 302 that is an identifier of the test item. Have. The measurement instruction group 306 is for the setting instruction 308 which is an instruction for setting the test module 206 or the test module emulator 108, the pattern generation instruction 310 which is an instruction for generating a test pattern, and the test pattern. It includes a pattern comparison instruction 312 that compares the output pattern output from the device under test 202 or the device simulator 104 under test with a pre-generated expected value. The setting instruction 308 is, for example, the setting of a register value. Further, the pattern program 300 is called by the pattern generation instruction 310 and has information for generating a test pattern. Specifically, the pattern program 300 holds the pattern data 316 indicating the test pattern in association with the address 314 of the test pattern.

The test program debugging device 100 shown in FIG. 1 verifies the test program 110 by sequentially executing the test program 110 shown in FIG. 3, but the range of instructions that the user should verify in the test program 110 or the range of instructions to be verified in the test program 110. The pattern program 300 may select a range of pattern data to be verified and verify some instructions of the selected test program 110.

That is, the verification range acquisition unit 120 acquires the verification range, which is the range of the instructions to be verified in the test program 110, based on the user's instruction input. For example, when the test number 302 or the range of the test number 302 in the test program 110 is specified by the user, the verification range acquisition unit 120 acquires the range of the test number 302 or the test number 302 as the verification range. Further, the verification range acquisition unit 120 may acquire the range of the test pattern to be verified in the pattern program 300 as the verification range based on the input of the user's instruction. For example, when the range of the test pattern address 314 or the test pattern address 314 in the pattern program 300 is specified by the user, the verification range acquisition unit 120 uses the test pattern of the specified test pattern address 314 or is specified. The test pattern in the range of the address 314 of the test pattern may be acquired as the verification range. Further, when the address 314 of the test pattern and the range of the count in the pattern program 300 are specified by the user, the verification range acquisition unit 120 verifies the test pattern of the specified count range from the address 314 of the specified test pattern. It may be acquired as a range. If none of the test pattern address 314, the test pattern address range, and the test pattern address 314 and the count range are specified, the verification range acquisition unit 120 will perform all test patterns of the pattern program 300. May be obtained as the verification range.

Then, the instruction simplification unit 122 is a device to be tested among the non-verification range instructions which are the instructions included in the non-verification range which is the range other than the verification range acquired by the verification range acquisition unit 120 in the test program 110. Simplify the non-setting instruction, which is an instruction other than the setting instruction 308, which is an instruction for setting the simulator 104. For example, the instruction simplification unit 122 simplifies the pattern generation instruction 310 and the pattern comparison instruction 312, which are non-setting instructions, and converts them into simple instructions. For example, the instruction simplification unit 122 detects a test pattern execution instruction provided before the pattern generation instruction 310, and simplifies the instruction after the test pattern execution instruction in the test item including the test pattern execution instruction. To do.

Then, the tester library 116 includes a verification range instruction which is an instruction included in the verification range acquired by the verification range acquisition unit 120, a setting instruction 308 among the non-verification range instructions, and an instruction simplification unit 122 among the non-verification range instructions. Executes the non-configuration instruction simplified by the test module emulator 108 to operate. Further, the instruction simplification unit 122 may set the non-setting instruction as an instruction that is not executed by the tester library 116 as another example of simplification of the non-setting instruction. Then, the tester library 116 executes the verification range instruction and the setting instruction, and does not have to execute the non-setting instruction.

As described above, by simplifying the instructions other than the verification range acquired from the user, the verification range specified by the user can be verified in a short time. Further, among the instructions other than the verification range acquired from the user, some instructions of the test program 110 are set as the verification range by performing the setting instruction such as the register value of the device simulator 104 under test without simplification. Even in this case, since the device simulator 104 under test can be operated in the same environment as when verifying all of the test program 110, the test program 110 can be verified accurately.

Further, in another example, instead of the simplification of the non-setting instruction by the instruction simplification unit 122, the device simulator 104 under test may simplify and execute the simulation based on the non-setting instruction. Specifically, the device simulator 104 under test has an output pattern table 138 that holds in advance an output pattern for a test pattern supplied from the semiconductor test device simulator 102. Then, the device simulator 104 under test outputs an output pattern that is held in advance in association with the test pattern for the test pattern from the semiconductor test device simulator 102 based on the non-setting instruction. As a result, the simulation time by the device simulator 104 under test can be reduced, and the verification range can be quickly verified.

Further, the semiconductor test apparatus 200 shown in FIG. 2 tests the device under test 202 by sequentially executing the test program 110 shown in FIG. 3, and the range of instructions that the user should test in the test program 110. Alternatively, The pattern program 300 may select a range of pattern data to be tested and test a portion of the selected test program 110.

That is, the test range acquisition unit 218 acquires the test range, which is the range of the instructions to be tested in the test program 110, based on the user's instruction input. For example, when the test number 302 or the range of the test number 302 in the test program 110 is specified by the user, the test range acquisition unit 218 acquires the test number 302 or the range of the test number 302 as the test range. Further, the test range acquisition unit 218 may acquire the range of the test pattern to be tested in the pattern program 300 as the test range based on the input of the user's instruction. For example, when the range of the test pattern address 314 or the test pattern address 314 in the pattern program 300 is specified by the user, the test range acquisition unit 218 is specified as the test pattern of the specified test pattern address 314. The test pattern in the range of the address 314 of the test pattern may be acquired as the test range. When the address 314 of the test pattern and the count range in the pattern program 300 are specified by the user, the test range acquisition unit 218 tests the test pattern in the specified count range from the address 314 of the specified test pattern. It may be acquired as a range. If none of the test pattern address 314, the test pattern address range, and the test pattern address 314 and the count range are specified, the test range acquisition unit 218 will perform all test patterns in the pattern program 300. May be obtained as a test range.

Then, the instruction simplification unit 220 is a device to be tested among the non-test range instructions that are included in the non-test range that is a range other than the test range acquired by the test range acquisition unit 218 in the test program 110. Simplify the non-setting instruction, which is an instruction other than the setting instruction 308, which is an instruction for setting 202. For example, the instruction simplification unit 220 simplifies the pattern generation instruction 310 and the pattern comparison instruction 312, which are non-setting instructions, and converts them into simple instructions. Then, the tester library 214 includes a test range instruction which is an instruction included in the test range acquired by the test range acquisition unit 218, a setting instruction 308 among the non-test range instructions, and an instruction simplification unit 220 among the non-test range instructions. Executes the non-configuration instruction simplified by the test module 206 to operate. Further, the instruction simplification unit 220 may set the non-setting instruction as an instruction that is not executed by the tester library 214 as another example of simplification of the non-setting instruction. Then, the tester library 214 executes the test range instruction and the setting instruction, and does not have to execute the non-setting instruction.

As described above, by simplifying the instructions other than the test range acquired from the user, the test range specified by the user can be tested in a short time. Further, among the instructions other than the test range acquired from the user, a part of the test program 110 is set as the test range by performing the setting instruction such as the register value of the device under test 202 without simplification. However, since the device 202 under test can be operated in the same environment as when testing all of the test program 110, the test program 110 can be tested accurately.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be made to the above embodiments. It is clear from the claims that the form with such modifications or improvements may also be included in the technical scope of the invention.

100 Test program debug device 102 Semiconductor test equipment simulator 104 Device simulator to be tested 106 Emulator control unit 108 Test module emulator 110 test program 112 Application program 114 Language Analysis Execution Department 116 Tester library 118 Tester Bus Emulator 120 Verification range acquisition section 122 Instruction simplification section 124 Virtual tester bus 126 Virtual register 128 virtual memory 130 Virtual test execution unit 136 Test result analysis judgment unit 138 Output pattern table 200 Semiconductor test equipment 202 Device under test 204 Test module control unit 206 test module 210 application program 212 Language Analysis Execution Department 214 tester library 216 Tester Bus Driver 218 Test range acquisition section 220 Instruction Simplification Department 222 tester bus 224 register 226 memory 228 Test Execution Department 300 pattern program 302 test number 304 Test condition instruction group 306 Measurement instruction group 308 Setting instruction 310 pattern generation instruction 312 Pattern comparison instruction 314 Test pattern address 316 pattern data