JP2010141351A

Micro-electronics element structure

Abstract

Problem to be solved.To provide a microelectronic device structure capable of forming a GaN-based switching device having a high yield voltage. The microelectronic device structure of the present invention is (a) about 1 × 10.16/cm3A first GaN layer having the following dopant concentration, (b) a second conductive GaN layer overlaid on the first GaN layer, and (c) overlaid on the second conductive GaN layer and Approximately 1 x 1016/cm3A third GaN layer with a thickness of at least about 2.5 μm at the following dopant concentrations and (d) at least one metal contact that forms a metal-to-semiconductor bond with the GaN layer above the third GaN layer. And. [Selection diagram] Fig. 1

JP2010141351A, drawing sheet 1 — Sheet 1 of 20

Term

Projected expiry 19 February 2030.

31 claims: 26 independent, 5 dependent

1
( a ) 約 1×10 16 /cm 3 以下のドーパント濃度を持つ第1のGaN層と、 ( b ) 上記第1のGaN層上に重なる第2の伝導性GaN層と、 ( c ) 上記第2の伝導性GaN層上に重なり、かつ約1×10 16 /cm 3 以下のドーパント濃度で少なくとも約2.5μmの厚さを持つ第3のGaN層と、 ( d ) 上記第3のGaN層の上方の、そのGaN層と金属対半導体接合を形成する少なくとも一つの金属コンタクトとを備えたマイクロエレクトロニクス素子構造。
2
請求項1のマイクロエレクトロニクス素子構造において、さらに、基板を備え、上記第1のGaN層は上記基板に重なっているマイクロエレクトロニクス素子構造。
3
請求項2のマイクロエレクトロニクス素子構造において、上記基板は異種基板を含み、さらに、上記第1のGaN層と上記異種基板との間に配置された核形成バッファ層を備えるマイクロエレクトロニクス素子構造。
4
請求項 3 のマイクロエレクトロニクス素子構造において、上記異種基板は、サファイア、SiおよびSiCからなる群から選択された材料を備えるマイクロエレクトロニクス素子構造。
5
請求項 3 のマイクロエレクトロニクス素子構造において、上記異種基板はサファイアを備えるマイクロエレクトロニクス素子構造。
6
請求項 1から5までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第3のGaN層は厚さで10μmを下回るマイクロエレクトロニクス素子構造。
7
請求項 1から5までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第3のGaN層は厚さで20μmを下回るマイクロエレクトロニクス素子構造。
8
請求項 1から5までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第3のGaN層は厚さで50μmを下回るマイクロエレクトロニクス素子構造。
9
請求項 1から8までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第2の伝導性GaN層は緊張減少用ドーパントでドープされているマイクロエレクトロニクス素子構造。
10
請求項 1から8までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第2の伝導性GaN層はゲルマニウムでドープされているマイクロエレクトロニクス素子構造。
11
請求項 1から10までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第1のGaN層は約0.6μmの厚さを持ち、上記第2の伝導性GaN層は約2.0μmの厚さで約1.5×10 19 /cm 3 のドーパント濃度を持つマイクロエレクトロニクス素子構造。
12
請求項 1から10までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第1のGaN層は約0.6μmの厚さを持ち、また、上記第2の伝導性GaN層は約0.5μmの厚さで約1.5×10 19 /cm 3 のドーパント濃度を持つマイクロエレクトロニクス素子構造。
13
請求項 1から8までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第2の伝導性GaN層は、第1のドーパント濃度の第1の伝導性GaNサブ層と、第2のドーパント濃度の第2の伝導性GaNサブ層とを備え、上記第1の伝導性GaNサブ層は上記第1のGaN層に隣接し、上記第2の伝導性GaNサブ層は上記第3のGaN層に隣接し、また、上記第1のドーパント濃度は上記第2のドーパント濃度よりも下回るマイクロエレクトロニクス素子構造。
14
請求項13のマイクロエレクトロニクス素子構造において、上記第1のGaN層は約0.6μmの厚さを持ち、上記第1の伝導性GaNサブ層は約1.9μmの厚さで約2.0×10 18 /cm 3 のドーパント濃度を持ち、また、上記第2の伝導性GaNサブ層は約0.1μmの厚さで約1.5×10 19 /cm 3 のドーパント濃度を持つマイクロエレクトロニクス素子構造。
15
(a) 5 ×10 6 /cm 2 以下の転位欠陥密度によって特徴付けられた上面を持つn型伝導性の第1のGaN層と、 (b) 上記伝導性GaN層の上方に形成され、1 ×10 15 /cm 3 以下のドーパント濃度で10 μmを超える厚さを持つ第2のGaN層と、 (c) 上記第2のGaN層の上方に形成されたp型伝導性の第3のGaN層と、 (d) 上記第3のGaN層上に重なる少なくとも一つの金属コンタクトとを備えたマイクロエレクトロニクス素子構造。
16
請求項 15 のマイクロエレクトロニクス素子構造において、上記第1のGaN層が自立のGaN構造を備えているマイクロエレクトロニクス素子構造。
17
( a ) 約 1×10 16 /cm 3 以下のドーパント濃度を持つ第1のGaN層と、 ( b ) 上記第1のGaN層上に重なるn型伝導性の第2のGaN層と、 ( c ) 上記n型伝導性の第2のGaN層上に重なり、かつ約1×10 16 /cm 3 以下のドーパント濃度で少なくとも約2.5μmの厚さを持つ第3のGaN層と、 ( d ) 上記第3のGaN層上に形成されたp型伝導性の第4のGaN層と、 ( e ) 上記第4のGaN層上に重なる少なくとも一つの金属コンタクトとを備えたマイクロエレクトロニクス素子構造。
18
請求項17のマイクロエレクトロニクス素子構造において、さらに、基板を備え、上記第1のGaN層は上記基板に重なっているマイクロエレクトロニクス素子構造。
19
請求項18のマイクロエレクトロニクス素子構造において、上記基板は異種基板を含み、さらに、上記第1のGaN層と上記異種基板との間に配置された核形成バッファ層を備えるマイクロエレクトロニクス素子構造。
20
請求項 19 のマイクロエレクトロニクス素子構造において、上記異種基板は、サファイア、SiおよびSiCからなる群から選択された材料を備えるマイクロエレクトロニクス素子構造。
21
請求項 19 のマイクロエレクトロニクス素子構造において、上記異種基板はサファイアを備えるマイクロエレクトロニクス素子構造。
22
請求項 17から21までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第3のGaN層は厚さで10μmを下回るマイクロエレクトロニクス素子構造。
23
請求項 17から21までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第3のGaN層は厚さで20μmを下回るマイクロエレクトロニクス素子構造。
24
請求項 17から21までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第3のGaN層は厚さで50μmを下回るマイクロエレクトロニクス素子構造。
25
請求項 17から24までのいずれか一つのマイクロエレクトロニクス素子構造において、上記n型伝導性の第2のGaN層は緊張減少用ドーパントでドープされているマイクロエレクトロニクス素子構造。
26
請求項 17から24までのいずれか一つのマイクロエレクトロニクス素子構造において、上記n型伝導性の第2のGaN層はゲルマニウムでドープされているマイクロエレクトロニクス素子構造。
27
請求項 17から21までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第1のGaN層は約0.6μmの厚さを持ち、また、上記n型伝導性の第2のGaN層は約2.0μmの厚さで約1.5×10 19 /cm 3 のドーパント濃度を持つマイクロエレクトロニクス素子構造。
28
請求項 17から21までのいずれか一つのマイクロエレクトロニクス素子構造において、上記第1のGaN層は約0.6μmの厚さを持ち、また、上記n型伝導性の第2のGaN層は約0.5μmの厚さで約1.5×10 19 /cm 3 のドーパント濃度を持つマイクロエレクトロニクス素子構造。
29
請求項 17から21までのいずれか一つのマイクロエレクトロニクス素子構造において、上記n型伝導性の第2のGaN層は、第1のドーパント濃度の第1の伝導性GaNサブ層と、第2のドーパント濃度の第2の伝導性GaNサブ層とを備え、上記第1の伝導性GaNサブ層は上記第1のGaN層に隣接し、上記第2の伝導性GaNサブ層は上記第3のGaN層に隣接し、また、上記第1のドーパント濃度は上記第2のドーパント濃度よりも下回るマイクロエレクトロニクス素子構造。
30
請求項 29 のマイクロエレクトロニクス素子構造において、上記第1のGaN層は約0.6μmの厚さを持ち、上記第1の伝導性GaNサブ層は約1.9μmの厚さで約2.0×10 18 /cm 3 のドーパント濃度を持ち、また、上記第2の伝導性GaNサブ層は約0.1μmの厚さで約1.5×10 19 /cm 3 のドーパント濃度を持つマイクロエレクトロニクス素子構造。
31
請求項 1から30までのいずれか一つのマイクロエレクトロニクス素子構造において、メサ型ショットキーダイオードとプレーナ型ショットキーダイオードとからなる群から選択されたショットキーダイオードを備えるマイクロエレクトロニクス素子構造。

Independent claims31

63 paragraphs, as filed

The present invention constitutes various switching elements with high yield voltage.Microelectronic device structureRegarding.

As a background to the present invention, the disclosures of the following documents are thereby combined by reference as a whole.

Brandic et al., "High Voltage (450V) GaN Schottky Rectifier" Applied Phys Lett., Vol.74, No.9, pp.1266-1268 (March 1, 1999) ) Trivedi et al., "Performance Evaluation of High Power Wide Bandgap Semiconductor Rectifiers" Journal of Applied Physics (J. Appl. Phys.), Vol.85, No.9, pp.6889-6897 (1999) May 1st) A US patent issued on December 5, 2000 under the name of Robert P. Vaudo et al. For "GaN-based devices using a thick (Ga, Al, In) N base layer". No. 6,156,581 Robert P. Vaudeville for "Low Defect Density (Ga, Al, In) N and the HVPE Process for Making It" US Pat. No. 6,440,823 issued on August 27, 2002 under the name of Vaudo) et al. "Methods for obtaining improved epitaxy quality (surface texture and defect density) on self-contained nitride (aluminum, indium, gallium) ((AL, IN, GA) N) substrates for optoelectronics and electronics devices. US Pat. No. 6,447,604 issued on September 10, 2002 in the name of Jeffrey S. Flynn et al.

(Ga, Al, In) N-based materials (hereinafter, generally referred to as "GaN" throughout this specification) are used to fabricate high-voltage, high-power microelectronics switching devices. It is a promising group of semiconductor materials. Microelectronics switching elements include Schottky diode rectifiers, PN diodes, PIN diodes, thyristors with PNPN junctions, and N.+-PIP+It includes, but is not limited to, collision electron avalanche / traveling time elements (IMPATTs) with junctions.

As shown in Table 1, GaN has several basic properties that make it advantageous for high power switching applications. The wide bandgap of GaN gives GaN a higher theoretical breakdown electric field than 4H-SiC. In addition, GaN has higher electron mobility and maximum velocity than 4H-SiC. The thermal conductivity of GaN is lower than that of 4H-SiC, but comparable to that of Si. Si is currently the most common material used to make high power switching devices.

(table 1) Properties of candidate material at 300K<img file="JP2010141351A_D0001.tif" /> * Theoretical maximum

Therefore, thicker semiconductor layers and lower dopant concentrations in such semiconductor layers, higher yield voltages of switching devices are made by using such semiconductor layers. Therefore, a thick, low-doped epitaxial semiconductor layer is required to fabricate switching devices that support high yield voltages.

To obtain a sufficiently high yield voltage, the thickness and doping requirements for the GaN layer are lower than those for SiC or SiC. In particular, Figure 1 is a plot of the predicted doping and thickness requirements for GaN-based rectifiers. For example, to make a rectifier with a reverse breakdown voltage of 5 kV, the background doping concentration n = 1 × 1016atoms / cm3A GaN layer with a thickness of about 20 μm is required.

AlGaN alloys have a larger bandgap (up to 6.2 eV) and higher theoretical breakdown voltage than simple GaN materials, making it possible to fabricate rectifiers and other switching devices with even higher breakdown voltages.

In order to fabricate a GaN-based switching device with a high breakdown voltage as described above, a thick low-doped GaN layer with the required thickness and background doping concentration is placed on top of the high-conductivity GaN base layer required for ohmic contact. It is necessary to adhere to.

However, due to the high coefficient of thermal expansion (TCE) mismatch and the formation of linear dislocations (TDs) and other defects, GaN is difficult to adhere to thicknesses greater than a few μm on heteroepitaxial substrates. Therefore, new growth methods, structures, and / or substrates need to be employed to coat the GaN layer to the appropriate thickness required for the fabrication of electronic devices. In addition, the epitaxial layer is on a substrate of suitable size with high uniformity and quality, and the suitable configuration (eg, horizontal or vertical) and direction (eg, c-plane, r-plane, m-plane, axis) of the epitaxial structure. Outer, axial, off-cut directions and angles) need to be adhered to meet the cost, yield and performance requirements of a particular device application.

Currently, Si, sapphire, SiC, HVPE / sapphire, and free-standing bulk GaN substrates are available in a variety of sizes and structures suitable for a variety of high voltage diode applications. Typically, low cost, low power (<lkV) devices employ heteroepitaxial substrates such as Si and sapphire. High-cost, high-power (> lkV) devices, on the other hand, employ more lattice-matched substrates such as SiC, HVPE / sapphire and free-standing bulk GaN substrates. Providing suitable epitaxy quality on a heteroepitaxial substrate is difficult due to the difference in coefficient of thermal expansion and the lattice mismatch between the heteroepitaxial substrate and the GaN layer grown on it. This results in high dislocation defect densities and severe cracks in the GaN epitaxial layer. Growth of the GaN layer on a GaN or HVPE / sapphire substrate is not significantly affected by the TCE and lattice mismatch, but other problems such as interfacial charge removal between the GaN substrate and the epitaxial layer still overcome. I need. In all cases, if the GaN epitaxial layer is doped with Si so as to form a high conductive n-type GaN layer in the high yield voltage element, the problem of cracking is exacerbated.

Therefore, it is an object of the present invention to provide a high quality, uniform, large diameter MOVPE epitaxial layer with low crack density, low pit density and high n-layer conductivity on a suitable heteroepitaxial or homoepitaxial substrate. is there. On it, a thick low-doped GaN layer can be formed to fabricate a GaN-based switching device with a high yield voltage.

<nplcit num="1"><text>Brandic et al., "High Voltage (450V) GaN Schottky Rectifier" Applied Phys Lett., Vol.74, No.9, pp.1266-1268 (March 1, 1999) )</text></nplcit><nplcit num="2"><text>Trivedi et al., "Performance Evaluation of High Power Wide Bandgap Semiconductor Rectifiers" Journal of Applied Physics (J. Appl. Phys.), Vol.85, No.9, pp.6889-6897 (1999) May 1st)</text></nplcit>

An object of the present invention is to provide a microelectronic device structure capable of solving the above-mentioned problems.

In one aspect, the microelectronic device structure of the present invention(a)About 1x1016/cm3The first GaN layer with the following dopant concentration and(b)A second conductive GaN layer overlaid on the first GaN layer,(c)Overlapping on the second conductive GaN layer and approximately 1 x 1016/cm3With a third GaN layer with a thickness of at least about 2.5 μm at the following dopant concentrations,(d)With at least one metal contact above the third GaN layer that forms a metal-to-semiconductor bond with that GaN layer.To be equipped.In the microelectronic device structure of one embodiment,In addition, it has a boardThe first GaN layer overlaps the substrate.In the microelectronic device structure of one embodiment,The above substrates include different types of substrates.Further, a nucleation buffer layer arranged between the first GaN layer and the dissimilar substrate is provided.In the microelectronic device structure of one embodiment, the dissimilar substrate comprises a material selected from the group consisting of sapphire, Si and SiC.In the microelectronic device structure of one embodiment, the dissimilar substrate comprises sapphire.In the microelectronic device structure of one embodiment, the thickness of the third GaN layer is less than 10 μm.In the microelectronic device structure of one embodiment, the thickness of the third GaN layer is less than 20 μm.In the microelectronic device structure of one embodiment, the thickness of the third GaN layer is less than 50 μm.In the microelectronic device structure of one embodiment, the second conductive GaN layer is doped with a tension reducing dopant.In the microelectronic device structure of one embodiment, the second conductive GaN layer is doped with germanium.In the microelectronic device structure of one embodiment,The first GaN layer has a thickness of about 0.6 μm and has a thickness of about 0.6 μm.The second conductive GaN layer has a thickness of about 2.0 μm and is about 1.5 × 10.19/cm3Has a dopant concentration of.In the microelectronic device structure of one embodiment,The first GaN layer has a thickness of about 0.6 μm and also has a thickness of about 0.6 μm.The second conductive GaN layer has a thickness of about 0.5 μm and is about 1.5 × 10.19/cm3Has a dopant concentration of.In the microelectronic device structure of one embodiment,The second conductive GaN layer includes a first conductive GaN sub-layer having a first dopant concentration and a second conductive GaN sub-layer having a second dopant concentration.The first conductive GaN sublayer is adjacent to the first GaN layer andThe second conductive GaN sublayer is adjacent to the third GaN layer and alsoThe first dopant concentration is lower than the second dopant concentration.In the microelectronic device structure of one embodiment,The first GaN layer has a thickness of about 0.6 μm and has a thickness of about 0.6 μm.The first conductive GaN sublayer has a thickness of about 1.9 μm and is about 2.0 × 10.18/cm3Has a dopant concentration ofThe second conductive GaN sublayer has a thickness of about 0.1 μm and is about 1.5 × 10.19/cm3Has a dopant concentration of.In one aspect, the microelectronic device structure of the present invention(a)5×106/cm2An n-type conductive first GaN layer with an upper surface characterized by the following dislocation defect densities,(b)Formed above the conductive GaN layer, 1 × 1015/cm3A second GaN layer with a thickness of more than 10 μm at the following dopant concentrations,(c)The p-type conductive third GaN layer formed above the second GaN layer and(d)With at least one metal contact overlaid on the third GaN layerTo be equipped.In the microelectronic device structure of one embodiment, the first GaN layer has a self-supporting GaN structure.In one aspect, the microelectronic device structure of the present invention(a)About 1x1016/cm3The first GaN layer with the following dopant concentration and(b)The n-type conductive second GaN layer that overlaps the first GaN layer,(c)Overlaid on the n-type conductive second GaN layer and approximately 1 × 1016/cm3With a third GaN layer with a thickness of at least about 2.5 μm at the following dopant concentrations,(d)The p-type conductive fourth GaN layer formed on the third GaN layer and(e)With at least one metal contact overlaid on the fourth GaN layerTo be equipped.In the microelectronic device structure of one embodiment,In addition, it has a boardThe first GaN layer overlaps the substrate.In the microelectronic device structure of one embodiment,The above substrates include different types of substrates.Further, a nucleation buffer layer arranged between the first GaN layer and the dissimilar substrate is provided.In the microelectronic device structure of one embodiment, the dissimilar substrate comprises a material selected from the group consisting of sapphire, Si and SiC.In the microelectronic device structure of one embodiment, the dissimilar substrate comprises sapphire.In the microelectronic device structure of one embodiment, the thickness of the third GaN layer is less than 10 μm.In the microelectronic device structure of one embodiment, the thickness of the third GaN layer is less than 20 μm.In the microelectronic device structure of one embodiment, the thickness of the third GaN layer is less than 50 μm.In the microelectronic device structure of one embodiment, the n-type conductive second GaN layer is doped with a tension reducing dopant.In the microelectronic device structure of one embodiment, the n-type conductive second GaN layer is doped with germanium.In the microelectronic device structure of one embodiment,The first GaN layer has a thickness of about 0.6 μm and also has a thickness of about 0.6 μm.The n-type conductive second GaN layer has a thickness of about 2.0 μm and is about 1.5 × 1019/cm3Has a dopant concentration of.In the microelectronic device structure of one embodiment,The first GaN layer has a thickness of about 0.6 μm and also has a thickness of about 0.6 μm.The n-type conductive second GaN layer has a thickness of about 0.5 μm and is about 1.5 × 1019/cm3Has a dopant concentration of.In the microelectronic device structure of one embodiment,The n-type conductive second GaN layer includes a first conductive GaN sub-layer having a first dopant concentration and a second conductive GaN sub-layer having a second dopant concentration .The first conductive GaN sublayer is adjacent to the first GaN layer andThe second conductive GaN sublayer is adjacent to the third GaN layer and alsoThe first dopant concentration is lower than the second dopant concentration.In the microelectronic device structure of one embodiment,The first GaN layer has a thickness of about 0.6 μm and has a thickness of about 0.6 μm.The first conductive GaN sublayer has a thickness of about 1.9 μm and is about 2.0 × 10.18/cm3Has a dopant concentration ofThe second conductive GaN sublayer has a thickness of about 0.1 μm and is about 1.5 × 10.19/cm3Has a dopant concentration of.The microelectronic device structure of one embodiment includes a Schottky diode selected from the group consisting of a mesa type Schottky diode and a planar type Schottky diode. In one aspect, the invention relates to a high voltage yield device with good current diffusivity made on a sapphire substrate or a heteroepitaxial substrate such as a SiC or Si substrate with high longitudinal conductivity. Severe cracks are commonly observed in epitaxial GaN layers made on such heteroepitaxial substrates. Cracks have high doping levels (> 5 × 10) in such heteroepitaxial substrates.18cm-3And <3 × 1019cm-3) Or by providing delta doping, but not completely removed. Therefore, one embodiment of the present invention employs two highly conductive GaN layers. One of them has a relatively high doping concentration and the other has a relatively low doping concentration, which is subsequently formed for further suppression of cracks in the undoped epitaxial GaN layer. Another embodiment of the present invention provides an undoped GaN layer beneath the highly conductive GaN layer. It improves the quality of the material and reduces pits and cracks in the undoped epitaxial GaN layer that is subsequently formed on the highly conductive GaN layer. Yet another embodiment of the present invention utilizes a tension reducing dopant such as germanium instead of the conventional Si dopant used for n-type doping of conductive GaN layers. Doping germanium into the conductive GaN layer significantly reduces cracks in it, as germanium fits the Ga site better than Si. In another aspect, the invention relates to high voltage yield devices made on a self-supporting homoepitaxial GaN substrate or on an HVPE / sapphire-based structure. The term "HVPE / sapphire base structure" in the present invention refers to a device quality, crack-free base layer about 10 μm thick, made on a sapphire substrate by the hydride vapor phase epitaxy (HVPE) method. It is a US patent issued on December 5, 2000 under the name of Robert P. Vaudo et al. For "GaN-based devices using a thick (Ga, Al, In) N base layer". It is described in No. 6,156,581, the contents of which are thereby combined by reference as a whole for all purposes. In one embodiment of the invention, the self-supporting GaN substrate or HVPE / sapphire base structure comprises an undoped GaN top layer, and the epitaxial growth of the GaN layer following it is the interface between the epitaxial GaN layer and the substrate or base structure. It is done uniformly by removing the dopant or conductivity in. The quality and performance of such epitaxial GaN layers is "improved epitaxy quality on self-contained nitride (aluminum, indium, gallium) ((AL, IN, GA) N) substrates for optelectronics and electronic devices. Described in US Pat. No. 6,447,604 issued September 10, 2002 under the name of Jeffrey S. Flynn et al. For "Methods for Obtaining (Surface Texture and Defect Density)" Further improvement can be achieved by adopting such alternating growth directions, off-cut angles and off-cut directions. Its contents are thereby combined by reference as a whole for all purposes. In a further aspect, the invention (a) Approximately 5 × 106/cm2A first conductive GaN interface layer with an upper surface characterized by the following dislocation defect densities, (b) Formed above the top layer of the conductive GaN base layer, approximately 1 × 1016/cm3A second GaN layer with the following dopant concentration and (c) With at least one metal contact above the first GaN layer that forms a metal-to-semiconductor bond with that GaN layer. The present invention relates to a microelectronic device equipped with. The term "GaN" as used in the present invention is broadly referred to as any Al, unless otherwise specified.xInyGa(1-xy)Also includes N. That is, GaN, AlxGa(1-x)N, AlxInyGa1-xyN, InyGa1-yIncluding, but not limited to, N and the like. The unit for dislocation defect density represents the number of dislocation defects measured per square centimeter. The unit for dopant concentration represents the number of dopant atoms measured per cubic centimeter. Such a microelectronic device is preferably a Schottky diode rectifier with Schottky and ohmic contacts. Another aspect of the invention is (a) Foreign substrates, (b) The nucleation buffer layer overlapping on the dissimilar substrate, (c) Overlapping on the nucleation buffer layer and approximately 1 × 1016/cm3The first GaN layer with the following dopant concentration and (d) The second conductive GaN layer overlaid on the first GaN layer, (e) Overlapping on the second conductive GaN layer and approximately 1 × 1016/cm3A third GaN layer with the following dopant concentration and (f) With at least one metal contact above the third GaN layer that forms a metal-to-semiconductor bond with that GaN layer. The present invention relates to a microelectronic device equipped with. Such microelectronic devices should also be Schottky diode rectifiers with Schottky and ohmic contacts. Yet another aspect of the invention is (a) Approximately 5 × 106/cm2An n-type conductive first GaN layer with an upper surface characterized by the following dislocation defect densities, (b) Approximately 1 × 10 formed above the conductive GaN layer15/cm3A second GaN layer with the following dopant concentration and (c) With the p-type conductive third GaN layer formed above the second GaN layer, (d) With at least one metal contact overlaid on the third GaN layer The present invention relates to a microelectronic device structure provided with. Such a microelectronic device structure is preferably a PIN diode with at least two ohmic contacts, including one p-type contact and one n-type contact. Other aspects and embodiments of the present invention will become more fully apparent from the following claims and claims.

<figref num="1">Figure 1 is a plot of the predicted doping and thickness requirements for a GaN-based rectifier.</figref><figref num="2A">FIG. 2A is a schematic diagram of a GaN-based mesa-Schottky diode rectifier according to an embodiment of the present invention.</figref><figref num="2B">FIG. 2B is a schematic diagram of a GaN-based planar Schottky diode rectifier according to an embodiment of the present invention.</figref><figref num="3">Figure 3 is the IV curve for the GaN-based Mesa-Schottky diode rectifier of Figure 2A.</figref><figref num="4">FIG. 4 is a scanning electron microscope view of the GaN-based mesa-Schottky diode rectifier of FIG. 2A after electrical yielding.</figref><figref num="5">FIG. 5 shows a self-contained GaN-based Schottky rectifier lacking a dissimilar substrate according to an embodiment of the present invention.</figref><figref num="6A">FIG. 6A is a general view of a group of GaN-based mesa-Schottky diode rectifiers according to an embodiment of the present invention.</figref><figref num="6B">FIG. 6B is a general view of a group of GaN-based planar Schottky diode rectifiers according to an embodiment of the present invention.</figref><figref num="7A">FIG. 7A shows a 32.5x Nomarski microscope view of the center of the nitride for forming a GaN-based Schottky diode rectifier according to one embodiment of the invention.</figref><figref num="7B">Figure 7B shows a 32.5x Nomalski microscope view of the edge of the nitride to form the GaN-based Schottky diode rectifier of Figure 7A.</figref><figref num="8A">FIG. 8A shows a 32.5x Nomarski microscope view of the center of the nitride for forming a GaN-based Schottky diode rectifier according to an embodiment of the invention.</figref><figref num="8B">Figure 8B shows a 32.5x Nomalski microscope view of the edge of the nitride to form the GaN-based Schottky diode rectifier of Figure 8A.</figref><figref num="9A">FIG. 9A shows a 32.5x Nomarski microscope view of the center of the nitride for forming a GaN-based Schottky diode rectifier according to one embodiment of the invention.</figref><figref num="9B">FIG. 9B shows a 32.5x Nomalski microscope view of the edge of the nitride for forming the GaN-based Schottky diode rectifier of FIG. 9A.</figref><figref num="10">FIG. 10 is a schematic view of a GaN-based mesa-Schottky rectifier according to an embodiment of the present invention.</figref><figref num="11">FIG. 11 is a schematic view of a GaN-based PIN diode according to an embodiment of the present invention.</figref><figref num="12">FIG. 12 shows the IV curve for the GaN-based PIN diode of FIG.</figref><figref num="13">FIG. 13 is a schematic view of a self-supporting GaN-based PIN diode according to an embodiment of the present invention.</figref>

To make microelectronics switching devices with relatively low breakdown voltage (ie, <2 kV), a thin GaN layer can be directly adhered by MOVPE on dissimilar substrates such as sapphire, Si and SiC. Despite the fact that such directly adhered dissimilar substrates are relatively thin (ie <10 μm), the strain in the GaN layer is caused by the difference in the coefficient of thermal expansion between the dissimilar substrate and the GaN layer. ) Consequent with significant cracks, pits and defect formation. Therefore, in order to make a Schottky rectifier with a yield voltage of less than about 2 kV, a low-doped GaN layer of this thickness (ie, <10 μm) is deposited on a thin conductive GaN layer on a dissimilar substrate. Is difficult. The following innovative and preferred embodiments specify these limitations.

Conductive GaN base layer formed on one or more MOVPE interface layers The present invention provides an n-type conductive conductive GaN base layer formed above a dissimilar substrate. Between them is one or more interfacial layers to reduce the defect density of such conductive GaN base layers.

Prior to the formation of the conductive GaN base layer, an Al-containing nucleation buffer layer is first provided on the dissimilar substrate. This is to ensure proper nucleation of such conductive GaN base layers, as silicon and other impurities used as n-type dopants interfere with the nucleation and bonding process during heteroepitaxial growth.

Thin (ie 0.1 μm), low dope (ie 1 × 10) prior to the formation of the conductive GaN base layer16/cm3A GaN layer of (dopant concentration below) can be deposited on top of such a nucleation buffer layer. This is to further improve the result of nucleation.

FIG. 6A shows a mesa-type Schottky diode structure comprising a conductive GaN base layer 34 formed above a dissimilar substrate 32 with a nucleation buffer layer 42 and a thin low-doped GaN layer 44 as interfacial layers between them. A comprehensive diagram of 30 is shown. A thick, low-doped GaN layer 36 is subsequently formed on the conductive GaN base layer 34. Schottky contacts 38 are made on it, and ohmic contacts 39A and 39B are made on the conductive GaN base layer 34.

FIG. 6B shows a general view of the planar Schottky diode structure 30'having a structure similar to that of the mesa-type Schottky diode structure 30 shown in FIG. 6A. The difference is that the ohmic contacts 39A'and 39B' of the planar Schottky diode 30'are formed directly on the conductive GaN base layer 36'.

Due to the Schottky diode structure with recessed contacts shown in Figure 6A, it is advantageous to have a thick conductive GaN layer 34 (Si-doped). It is also due to high lateral conductivity and current spread, low contact resistance and good ohmic contact, and ease of etching from the top of the structure, i.e. avoiding undershoot and overshoot of the conductive GaN layer 34 during the etching process. It is also for the sake of.

Improved ohmic contacts and conductive GaN layer 34 improve the IV characteristics of Schottky diodes. For example, the forward turn-on resistance (slope of the forward IV curve) is increased by a decrease in resistance or contact resistance within layer 34. Another advantage of the device is provided by modifying the region of the conductive GaN layer 34 to be closest to the low-doped GaN layer 36. For example, doping levels close to the low-doping GaN layer 36 can be designed to produce the desired depletion within the low-doping GaN layer 36. In addition, the quality, doping level and defect density of the low-doping layer can be modified to improve the IV characteristics of such Schottky diodes, including breakdown voltage and leakage current.

Schottky Diodes The following example includes the overall structure shown in Figure 6A, but with varying layer thicknesses and dopant concentrations, and the effect of layer thicknesses and dopant concentrations on the quality of such diodes. Shown.

Structure ALayer (1)-2.5 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (2)-2.0 μm Si-doped conductive GaN (3 × 10)19/cm3) Layer (3) --0.1 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (4)-Nucleation buffer Layer (5)-Sapphire substrate

This Schottky diode structure A exhibits high pit and crack densities.

Structure BLayer (1)-2.5 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (2)-1.0 μm Si-doped conductive GaN (1 × 10)19/cm3) Layer (3) --0.1 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (4)-Nucleation buffer Layer (5)-Sapphire substrate

This Schottky diode structure B has a conductive GaN layer with reduced thickness and dopant concentration as compared to that of structure A. Severe cracks and pits are still observed in this Schottky diode structure B, as shown in Figures 7A and 7B.

Structure CLayer (1)-2.5 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (2)-2.0 μm Si-doped conductive GaN (1.5 × 10)19/cm3) Layer (3)-0.6 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (4)-Nucleation buffer Layer (5)-Sapphire substrate

This Schottky diode structure C has an increased thickness of undoped or low-doped GaN interface layer directly below the conductive GaN layer as compared to that of structure A. As shown in FIGS. 8A and 8B, a reduced pit density is observed in this Schottky diode structure C.

Structure DLayer (1)-2.5 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (2)-0.5 μm Si-doped conductive GaN (1.5 × 10)19/cm3) Layer (3)-0.6 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (4)-Nucleation buffer Layer (5)-Sapphire substrate

This Schottky diode structure D has a conductive GaN layer with a reduced thickness and dopant concentration compared to that of structure A, and underneath the conductive GaN layer is an increased thickness of undoped or It has a low-doped GaN interface layer. As shown in FIGS. 9A and 9B, no significant cracks or pits are observed in such Schottky diode structure D.

Structure ELayer (1)-2.5 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (2) --0.1 μm Si-doped conductive GaN sublayer (1.5 × 10)19/cm3) Layer (3)-1.9 μm Si-doped conductive GaN sublayer (2 × 10)18/cm3) Layer (4)-0.6 μm undoped GaN (or 1 × 10)16/cm3The following light n-type dopant concentration) Layer (5)-Nucleation buffer Layer (6)-Sapphire substrate

This structure E is shown schematically in FIG. 10 (there as structure 50). This structure consists of a first conductive GaN sublayer 54A of smaller thickness and higher dopant concentration adjacent to the undoped or low-doped GaN layer 56 for contact formation, and the interface undoped or low-doped GaN layer 44. It has a second conductive GaN sublayer 54B with a larger thickness and a lower dopant concentration adjacent to it. Such a Schottky diode structure exhibits a sheet resistance of 36 ohm Ω / (ohm / square). It is close to the sheet resistance of structure A, 14Ω / . Further optimization of conductive GaN sublayers and interfacial undoped or low-doped GaN layers achieved to reach 14 Ω / with respect to their thickness and doping level, without significantly increasing the density of cracks or pits. Can be done.

In general, placing a thick undoped or low-doped GaN interface layer underneath the conductive GaN base layer reduces cracks and pits in the overall structure. Other interfacial layers or alloys are also used for tension relaxation or coefficient of thermal expansion (TCE) relaxation to further reduce cracks and pits within the formed Schottky diode structure and further improve device quality. obtain.

The n-type conductive conductive GaN base layer is doped with Si in the illustrated structures listed above. Instead, they can be doped with germanium (Ge) or other n-type dopants with similar atomic sizes to AlInGaN atoms. This is to allow for a modified elasticity, tension or TCE effect.

Delta doping can also be combined within the doped layer to provide a thick stack of average low resistance materials, as in the conductive GaN sublayers 54A and 54B of the Schottky diode structure 50 in FIG. For delta doping, Jeffrey S. Flynn and George Earl Brandes (for "doped III-V nitrides and their microelectronic devices and device precursors". It is fully described by the co-pending US Patent Application No. l0 / l07,001 filed on March 25, 2002 in the name of George R. Brandes), the disclosure of which is by reference in its entirety. Will be united.

Conductive GaN base layer formed by HVPE For example, we grew a GaN layer approximately 10 μm thick directly on a sapphire substrate by the hydride vapor phase epitaxy (HVPE) method. It was subsequently used to form GaN-based Schottky diodes, as schematically shown in Figures 2A and 2B. Compared to MOVPE, HVPE results in greater thickness due to reduced thermal expansion coefficient differences, very thick and heavier dislocation buffers and other interfacial defects attributed to overall low tension within the epilayer. can get.

The GaN-based mesa-type Schottky diode 10 in FIG. 2A includes a sapphire substrate 12, and an n-type conductive high-conductivity GaN layer 14 is provided at the GaN / sapphire interface. On top of that, low dopant concentration (about 1x10)16/cm3), A GaN layer 16 of approximately 10 μm has been prepared. Gold is used to form the Schottky contacts 18, and Ti / Al / Ni / Au is used to form the ohmic contacts 19A and 19B. The IV curve for this GaN-based mesa-type Schottky diode is shown in Figure 3. The reverse yield voltage of such a GaN-based mesa-type Schottky diode was measured, which was about 450V. FIG. 4 shows a scanning electron microscope view of the Schottky contact 18 of the GaN-based mesa-type Schottky diode in FIG. 2A after electrical yielding. Melted Au at the edge exhibits premature edge breakdown, which limits the overall reverse breakdown voltage of such Schottky diodes without the use of passivation or guard rings or similar steps.

FIG. 2B shows a GaN-based planar Schottky diode 10'having a structure similar to that of the mesa diode 10 shown in FIG. 2A. The difference is that the ohmic contacts 19A'and 19B'of such planar Schottky diodes 10'on the low dopant concentration 10 μm GaN layer 16'instead of the high conductive GaN layer 14'. It is being formed.

The GaN-based Schottky diodes shown in Figures 2A and 2B are therefore only suitable for relatively low voltage (ie <2kV) switching applications. However, many applications require switching elements that can operate at high voltages ( 2 kV). Therefore, it is another object of the present invention to provide a GaN-based Schottky diode with a switching voltage higher than about 2 kV.

In order to provide a high voltage GaN based switching device, it is necessary to provide a GaN layer with increased thickness and low dopant concentration, as shown by the prediction plot in FIG. For GaN layers grown on dissimilar substrates by MOVPE, the lattice mismatch and coefficient of thermal expansion difference between the dissimilar substrates and the GaN layers grown on them, along with high levels of tension, are high dislocations in the GaN layer. The result is defect density. When the thickness of such a GaN layer is substantially increased, tension causes severe cracks in the GaN layer, making it unsuitable for device fabrication.

Another object of the present invention is to provide a new Schottky diode structure. It has a very low dislocation defect density (ie 5 × 10)6/cm2) Has a conductive GaN base layer with an upper surface, on which approximately 1 × 1016/cm3A low-doped GaN layer with the following dopant concentrations can be grown. Since the conductive GaN base layer has an upper surface with a low dislocation defect density, a tension-relieved low-doped GaN layer on it can be grown to a sufficient thickness (ie, 10 μm) without cracks. It can subsequently be used to make high breakdown voltage switching devices.

Free-standing conductive GaN base layer Low dislocation defect density (ie 5 × 10)6/cm2) Thick conductive GaN layer first dissimilar substrates (such as sapphire, Si or SiC) at reduced growth temperatures (ie about 985 ° C to about 1010 ° C) by the hydride vapor phase epitaxy (HVPE) method. ) Can grow on. At such a reduced HVPE growth temperature, the GaN layer undergoes less tension induced by the difference in coefficient of thermal expansion between the dissimilar substrate and its GaN layer. That was on August 27, 2002 under the name of Robert P. Vaudo et al. For "Low Defect Density (Ga, Al, In) N and the HVPE Process for Making It". As described in U.S. Pat. No. 6,440,823 issued, it results in a reduced dislocation defect density. The disclosure is hereby incorporated by reference as a whole for all purposes. Such a reduced HVPE growth temperature is also used to increase the n-type conductivity of the GaN layer so formed and, therefore, to form an n-type conductive conductive GaN layer. obtain. The thick conductive GaN layer with low dislocation defect density can be separated from the dissimilar substrate to form a self-supporting conductive GaN base layer.

In addition, the epitaxy quality of such conductive GaN layers has been improved on "self-contained nitride (aluminum, indium, gallium) ((AL, IN, GA) N) substrates for optoelectronics and electronic devices. Described in US Pat. No. 6,447,604 issued September 10, 2002 under the name of Jeffrey S. Flynn et al. For "Methods for Obtaining Epitaxy Quality (Surface Texture and Defect Density)" It can be improved by various techniques made. The disclosure is thereby combined by reference as a whole for all purposes.

To further improve the epitaxial quality of such conductive GaN layers and the performance of high yield voltage devices, low temperature interface layers, alternating crystal directions (eg, m-plane, r-plane, c-plane), various off-cut angles. And directions, as described in Japanese Patent No. 6,447,604, correct crystal growth quality, eliminate defects, correct point defect density, correct impurity bonds, change crystal polarization, crystal mobility. It is desirable to use it to correct the mobility, increase the yield voltage, reduce the leakage current, and so on.

A free-standing GaN substrate can be usefully employed to provide the first undoped GaN layer. The undoped GaN layer growth is then continued in the MOVPE growth process for further thickness increase, reduction of dislocation density and improvement of yield voltage. For such continued growth of undoped GaN layers through MOVPE, properly control substrate cleaning, heating conditions and nucleation on the substrate, as described in Japanese Patent No. 6,447,604 above. By doing so, it is important that electrically active impurities and defects are reduced at the growth interface.

FIG. 5 shows a schematic view of a high voltage Schottky rectifier 20 according to an embodiment of the present invention. Such a Schottky rectifier 20 has a thickness greater than about 50 μm and 5 × 106/cm2It comprises a self-supporting conductive GaN base layer 22 with a top surface characterized by a low dislocation defect density. On top of that, about 1x1016/cm3A low-doped GaN layer 24 characterized by the following dopant concentrations and thickness greater than 10 μm has been grown. Such a Schottky rectifier 20 lacks any dissimilar substrate, therefore the Schottky contact 26 is formed on one side above the low-doped GaN layer 24 and the ohmic contact 28 is self-contained on the other side. It can be formed above the sex GaN base layer 22.

GaN-based PN and PIN diode structure GaN-based PN and PIN diodes with high yield voltages are also a concern for high power device applications. The ability to fabricate PN or PIN junctions with high breakdown voltages is a key step towards the development of power devices such as thyristors and IMPATTs.

In one aspect, the invention provides GaN-PIN diodes with yield voltages of about 320V and 450V. They were produced by growing GaN-based P and I layers with MOVPE on HVPE / GaN layers with a highly conductive n-type GaN layer near the epi-layer / substrate interface. Alternative PN and PIN structures, including AlGaN-PIN structures, and the use of GaN as substrate materials for epitaxies and devices are also realized by the present invention.

A schematic GaN / PIN diode structure is shown in Figure 11. It has an n-type conductive approximately 10 μm thick GaN layer grown by HVPE on a sapphire substrate 72. Such an n-type GaN layer further includes a more conductive 2 μm GaN sublayer 74 and approximately 1 × 10.16/cm3It is shown to have a lower conductive 8 μm GaN sublayer 76 with the conductivity of. It acts as an N junction. Subsequently, a low-doped GaN layer 77 of approximately 0.5 μm was subjected to 1 × 10 by MOVPE.15/cm3It grows on the GaN sublayer 76 under conditions attributable to the background dopant concentration below. It acts as an I junction. Approximately 0.5 μm p-type GaN layer 78 is 1 × 10 by MOVPE.17/cm3It grows on the low-doped GaN layer 77 under conditions attributed to the hole concentration of. It acts as a P-junction. Subsequently, p-type ohmic contacts 79A and n-type ohmic contacts 79B and 79C are formed to provide a complete PIN diode.

This type of PIN diode structure is formed by reactive ion etching to provide a mesa structure as shown in FIG. 11 and p-type and n-type ohmic contacts by standard metallization procedures. The IV curve for such a PIN diode structure is shown in Figure 12. A yield voltage of approximately 320V was measured with this PIN element. A yield voltage of 450V was obtained with another PIN diode of similar construction. In both cases, the device showed premature yielding at corners and edges, pointing to that the device was limited by device design rather than by material quality.

High yield voltage PN or PIN diodes can be made by using improved edge terminations and thicker I layers. The thickness of the GaN layer in the above PIN structure was limited by tension-inducing cracks. Tension-induced cracks occur when the thickness of the GaN layer grown on a dissimilar substrate such as sapphire is greater than approximately 10 μm, as described in the section on GaN-based Schottky diode structures above. It was observed in the GaN layer. Self-contained low dislocation defect density GaN layers as described for Schottky diode structures can also be used to make high voltage PN or PIN diode structures.

In particular, the technology for producing self-contained GaN substrates with low dislocation defect densities was published on August 27, 2002 for "Low Defect Density (Ga, Al, In) N and the HVPE Process for Making It". US Pat. No. 6,440,823, "Bulk Single Crystal Gallium Nitride and Methods for Making It," by Michael A. Tischler, Thomas F Kuech, and Simultaneously pending US Patent Application No. 08 / 955,168, filed October 21, 1997 in the name of Robert P. Vaudo, and Robert P. Vaudo, Joan M. Redwing, Michael A. Tischler and Duncan W. Brown) U.S. Patent No. 5,679,152 issued on October 21, 1997, U.S. Patent Application No. 08 / 984,473 filed on December 3, 1997, provisional filed on December 3, 1996. It is disclosed in Patent Application No. 60 / 031,555.

The high voltage PIN structure 80 of the present invention is shown in FIG. It's about 5x106/cm2It contains N junctions formed by an n-type conductive, self-contained conductive GaN base layer 86 characterized by the following dislocation defect densities and preferred thicknesses greater than 50 μm. A self-contained GaN base layer with such a low dislocation defect density is formed by a method similar to that described for the Schottky diode structure described above. 1x1015/cm3An I junction with a thick, low-doped GaN layer 87 with the following dopant concentration is formed on such a conductive GaN base layer 86. The GaN base layer 86 can be removed from the dissimilar substrate on which the GaN base layer is formed, either prior to or after the formation of the low-doped GaN layer 87. Since the conductive GaN base layer 86 has a low dislocation defect density, the low-doped GaN layer 87 formed on it is thick enough to increase the overall breakdown voltage of the PIN structure 80, That is, it can grow up to 10 μm. Subsequently, a P-junction with a p-type conductive, approximately 0.25 μm thick GaN layer 88 can be formed on the low-doped GaN layer 87.

A p-type ohmic contact 89A can be formed above the p-type GaN layer 88. On the other hand, n-type ohmic contact 89B can be formed above the n-type conductive GaN base layer 86. Also, the thickness of layer I 87 can be extended to more than 10 μm to increase the breakdown voltage. The vertical structure shown in FIG. 13 is advantageous over the horizontal element shown in FIG. 1 because it minimizes the current that collects in the n-type layer. The reduced dislocation defect density in the n-type conductive GaN base layer 86 also leads to a reduced leakage current in the device.

PIN diode structures containing (Al, Ga) N or (Al, Ga, In) N alloys can also be made. For example, (Al, Ga) N, which has a wider bandgap than GaN, leads to higher yield voltages, which leads to the ability to use thinner, lower-doped layers in the device structure.

The PN and PIN diode techniques described in this invention are thyristors (pnpn) and IMPATTs (n).+-pip+), Which can be used to fabricate more complex bipolar GaN-based power devices.

Although the present invention has been variously disclosed herein with respect to the illustrated embodiments and features, it is recognized that the embodiments and features described above do not limit the invention. Other modifications, modifications and other embodiments propose themselves to those skilled in the art. Therefore, the invention should be broadly construed in line with the claims.

32Heterogeneous substrate

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KR20040104683A	Republic of Korea	A	2004-12-10
EP1502303A1	European Patent Office (EPO)	A1	2005-02-02
US2005167697A1	United States of America	A1	2005-08-04
CN1656616A	China	A	2005-08-17
JP2005530334A	Japan	A	2005-10-06
EP1502303A4	European Patent Office (EPO)	A4	2008-02-27
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JP2010141351AThis record	Japan	A	2010-06-24
US7795707B2	United States of America	B2	2010-09-14
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EP2261988A2	European Patent Office (EPO)	A2	2010-12-15
EP2261989A2	European Patent Office (EPO)	A2	2010-12-15
EP2261988A3	European Patent Office (EPO)	A3	2011-02-16
EP2261989A3	European Patent Office (EPO)	A3	2011-02-16
KR101017657B1	Republic of Korea	B1	2011-02-25
EP1502303B1	European Patent Office (EPO)	B1	2011-12-21
AT538497T	Austria	T	2012-01-15
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