Method for manufacturing semiconductor device

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a field effect transistor.

In integrated circuits using SiMOS field effect transistors (Si-MOSFETs), power consumption has been reduced and speed has been increased by reducing device dimensions and operating voltage in accordance with the so-called scaling law. It was.

However, many problems have arisen, such as the problem of the short channel effect that occurs due to the size reduction, and the decrease in the operating margin due to the proximity of the drain voltage and the threshold voltage, which becomes noticeable when the voltage is lowered.

Also, looking at the mobility, which is an indicator of speedup, the various improvements mentioned above ironically result in the mobility of Si in the actual device being 100 or less, which is far below the bulk value. ing.

As described above, it has become extremely difficult to improve the performance of the conventional Si-MOSFET.

It should be noted that Patent Document 1 and Non-Patent Document 1 suggest that when strain is applied to Si or Ge, the mobility of carriers can be increased as compared with Si or Ge which is not subjected to strain.

<p><patcit num="1"><text>Japanese Patent Application Laid-Open No. 6-177375</text></patcit></p>

<p><nplcit num="1"><text>MVFischetti and SELaux: J.Appl.Phys.80 (1996) 2234</text></nplcit></p>

<p> In order to further improve the performance, it is necessary to improve the speed by improving the semiconductor material itself. Although using so-called compound semiconductors, which are essentially high-speed, is one solution, it is extremely difficult in terms of compatibility with Si integrated circuit manufacturing technology, and the manufacturing cost is enormous, so it is realistic. Not a good solution.</p><p> An object of the present invention is to provide a semiconductor device having a low power consumption and high-speed field-effect transistor by using a combination of Si and its cognate elements such as Ge and C.</p>

<p> The above object can be achieved by applying strain to the channel cambium on which the channel of the field effect transistor is formed by the strain-applied semiconductor layer, and making the mobility of carriers in the channel larger than that of the material of the strain-free channel cambium. .. For example, when the material of the channel cambium is Si, the in-plane lattice constant of the Si channel cambium is made larger than that of unstrained Si by applying strain.</p><p> Non-Patent Document 1 suggests that when strain is applied to Si or Ge, the mobility of carriers can be increased as compared with Si or Ge which is not subjected to strain. This has the same origin as the phenomenon that the mobility increases due to in-plane strain when Si is deposited on sapphire, and it has been known for a long time. The present invention applies this phenomenon to manufacture a semiconductor device such as a field effect transistor and an integrated circuit using the field effect transistor.</p><p> Further, the above object has a p-type field effect transistor in which the energy of the apex of the valence band at the interface between the channel forming layer and the layers adjacent to both sides of the channel forming layer is made larger on the gate insulating film side than on the other side. It can also be achieved by semiconductor devices.</p><p> Further, the above object is a semiconductor having an n-type field effect transistor in which the energy at the apex of the conduction band at the interface between the channel forming layer and the layers adjacent to both sides of the channel forming layer is smaller on the gate insulating film side than on the other side. It can also be achieved by the device.</p><p> Further, the above object is to have a structure in which the energy barrier for carriers in the channel of the field effect transistor exists on the opposite side of the gate insulating film with respect to the channel, and distorts the lattice of the channel cambium on which the channel is formed. It can also be achieved by increasing the mobility of carriers in the channel compared to the material of the strain-free cambium.</p>

<p> According to the present invention, a high-speed and low-power-consumption complementary field-effect transistor and a semiconductor device incorporating the complementary field-effect transistor can be realized.</p>

<figref num="1">SiO which is a specific example of the present invention₂Gate insulating film / strained Si layer / Si_1-xGe_xIt is a band diagram of a laminated structure called a strain application layer.</figref><figref num="2">It is a band diagram in the state where a positive bias is applied to the gate of the structure shown in FIG.</figref><figref num="3">It is a band diagram in the state where a negative bias is applied to the gate of the structure shown in FIG.</figref><figref num="4">Si with the structure shown in Fig. 1._1-xGe_xIt is a band diagram in a state where steep n-type doping is applied to the uppermost part of the strain application layer.</figref><figref num="5">It is a band diagram in the state where the substrate bias voltage is applied to the structure shown in FIG.</figref><figref num="6">SiO which is a specific example of the present invention₂Gate insulating film / strained Si layer / strained Si_1-yGe_yLayer / Si_1-xGe_xIt is a band diagram of a laminated structure called a strain application layer.</figref><figref num="7">It is sectional drawing of the complementary field effect transistor of Example 1 of this invention.</figref><figref num="8">It is sectional drawing of the complementary field effect transistor of Example 2 of this invention.</figref><figref num="9">It is sectional drawing of the complementary field effect transistor of Example 3 of this invention.</figref><figref num="10">It is sectional drawing of the complementary field effect transistor of Example 4 of this invention.</figref><figref num="11">It is sectional drawing of the complementary field effect transistor of Example 5 of this invention.</figref><figref num="12">It is sectional drawing of the complementary field effect transistor of Example 6 of this invention.</figref><figref num="13">It is sectional drawing of the complementary field effect transistor of Example 7 of this invention.</figref><figref num="14">It is sectional drawing of the SOI substrate of Example 8 of this invention.</figref><figref num="15">It is sectional drawing of the SOI substrate of Example 9 of this invention.</figref><figref num="16">It is sectional drawing of the manufacturing process of the SOI substrate of Example 10 of this invention.</figref>

First, the band structure and operating principle of a field-effect transistor whose channel is strained Si will be described. Si for the strain application layer that gives distortion to Si_1-xGe_xIt is appropriate to use (0 &lt;x &lt;1). Fig. 1 shows SiO₂Gate insulating film 3 / strained Si layer 1 / Si_1-xGe_xA band diagram of a laminated structure called a strain application layer 2 is shown. Bandgap 6 of strained Si layer 1 is Si_1-xGe_xIt is wider than the band gap 7 of the strain application layer 2, and both the valence band 5 and the conduction band 4 show a band discontinuity of a type in which the energy is lowered.

In the case of an n-type field effect transistor, when a positive voltage is applied to the gate, the band bends near the interface between the gate insulating film 3 and the strained Si layer 1 as shown in Fig. 2, and the strained Si formed in this part. Electrons are accumulated in the triangular well 10 of the conduction band in layer 1, and transistor operation can be performed. This is exactly the same as a normal MOS field effect transistor.

Further, in the case of a P-type field effect transistor, when a negative voltage is applied to the gate, the band bends near the interface between the gate insulating film 3 and the strained Si layer 1 as shown in FIG. However, the strained Si layer 1 and Si are more than the triangular well 11 in the valence band in the strained Si layer 1 formed in this part._1-xGe_xSi formed at the interface of strain application layer 2_1-xGe_xMany holes are accumulated in the triangular well 12 of the valence band in the strain application layer 2. However, Si compared to strained Si layer 1_1-xGe_xSince the mobility of holes in the strain application layer 2 is extremely small, there is a problem that the speed cannot be improved as compared with a normal MOS field effect transistor. Further, when a complementary field effect transistor is configured, there is a problem that it becomes difficult to balance between both pn channels.

In order to solve such a problem, it is sufficient to reduce the accumulation of holes in the triangular well 12, and there are the following methods. The first method is to make the junction depth of the source and drain sufficiently shallower than the thickness of the strained Si layer 1 so that Si_1-xGe_xPrevents holes from flowing out to the strain application layer 2. Specifically, when the thickness of the strained Si layer 1 is, for example, 70 nm, the bonding depth may be set to about 40 nm. This is a value that is not much different from the value used in short-channel devices with a channel length of 0.1 micron or less, and is therefore a sufficiently feasible value.

The second method is Si_1-xGe_xThis is a method of steeply performing n-type doping in the vicinity of the interface between the strain application layer 2 and the strained Si layer 1, preferably in a depth range of 0.1 to 30 nm. By this method, Si_1-xGe_xThe energy level of the apex 43 of the triangular well 12 in the valence band in the strain application layer 2 decreases. For example, it is lower than the energy level of the apex 42 of the triangular well 11 in the valence band in the strained Si layer 1. As a result, the accumulation of holes in the triangular well 12 is reduced. This method uses strained Si layer 1 or strained Si layer 1 and Si._1-xGe_xIt can also be realized by n-type doping of both strain application layers 2. In these cases as well, the doping depth is preferably in the range of 0.1 to 30 nm.

The third method is Si_1-xGe_xThis is a method of controlling the substrate bias voltage so that a positive voltage is applied to the strain application layer 2 side. By this method, Si_1-xGe_xIt has a downward-sloping band structure with the strain application layer 2 side lowered, and Si is higher than the energy level of the apex 42 of the triangular well 11 in the valence band in the strained Si layer 1._1-xGe_xThe energy level of the apex 43 of the triangular well 12 in the valence band in the strain application layer 2 is lower. As a result, the accumulation of holes in the triangular well 12 is reduced.

As described above, preventing the outflow of holes from the strained Si channel to the strained application layer is an indispensable factor for realizing a p-type field effect transistor or a complementary field effect transistor. Further, in order to increase the speed and decrease the voltage of the device, it is also effective to adopt the following configuration. That is, the material of the drain region in the case of a p-type field effect transistor and the material of the source region in the case of an n-type field effect transistor are Si._1-xGe_xThe same base material as the strain application layer, preferably the same composition ratio. In this way, the distribution of the electric field between the source and drain changes due to the band discontinuity between the strained Si and SiGe, and it becomes possible to accelerate the carriers more effectively. As a result, the speed can be further increased, and the pinch-off voltage can be lowered to enable operation at a lower voltage.

So far, we have described transistors that use strained Si as a channel for both electrons and holes, but for holes, strained Si has been described._1-yGe_yWhen (0 &lt;y 1) is used as a channel, higher mobility, that is, higher speed is realized. Si on the strain application layer_1-xGe_xWhen is used, the Si laminated on it has in-plane tensile strain, and Si_1-yGe_yIn-plane compression strain is applied to.

Si_1-xGe_xStrained Si on the strained layer 2_1-yGe_yWhen the layer 25, the strained Si layer 1, and the gate insulating film 3 are laminated in this order, the band diagram is as shown in FIG. 6, and the conduction band in the strained Si layer 1 near the interface between the strained Si layer 1 and the gate insulating film 3 is obtained. Electrons in the triangular well 10 of the strained Si layer 1 and strained Si_1-yGe_yStrained Si near the interface of layer 25_1-yGe_yHoles are accumulated in the triangular well 20 of the valence band in the layer 25. Unlike the case where the strained Si layer 1 is used for the hole channel, the outflow of holes to the strained application layer 2 is less likely to occur. Strained Si layer 1 and strained Si_1-yGe_yIt is possible to operate as a device regardless of the stacking order of the layers 25. However, strained Si_1-yGe_ySince the mobility of holes in layer 25 is higher than the mobility of electrons in strained Si layer 1, strained Si is considered when considering the balance of transconductance when a complementary field effect transistor is constructed._1-yGe_yIt is preferable that the layer 25 is farther than the gate electrode, that is, below the strained Si layer 1.

Also, strained Si layer 1 or strained Si_1-yGe_yA further SiGe layer may be sandwiched between the layer 25 and the gate insulating film 3. In this case, the electrons or holes are strained Si layer 1 or strained Si near the interface with this SiGe layer._1-yGe_ySince it is accumulated in the layer 25, it is not affected by the interface state and scattering of the gate insulating film 3.

Also, strained Si layer and strained Si_1-yGe_yStrained Si in the p-channel region using selective growth, etc., without stacking layers_1-yGe_yThe layer may grow a strained Si layer in the n-channel region.

Si for the strain application layer_1-xGe_xIt is desirable to use. In Si and Ge, the lattice constant of Ge is about 4% larger. Si_1-xGe_xThe lattice constant takes an interpolated value according to the Ge composition ratio x. Therefore, if an appropriate x is selected, a desired strain can be applied to Si or Ge laminated on it. For example, if x is 0.5, in-plane tensile strain and in-plane compressive strain of 2% can be applied to Si and Ge, respectively. Si and Si depending on how you choose x_1-yGe_yThe magnitude of the distortion of is appropriately controlled. That is, the in-plane lattice constant of the strained Si layer can be increased in the range of less than 4% with respect to the undistorted Si, and the strained Si can be increased._1-yGe_yThe in-plane lattice constant of the layer can be reduced to less than 4% of the undistorted Ge. As a result, the balance of electron mobility and hole mobility can be controlled, so that the transconductance of the complementary field effect transistors can be balanced. In the conventional complementary field effect transistor, adjustment is performed only by changing the dimensions of the element, but this method further increases the degree of freedom in design and is advantageous for high integration.

Strain control is Si_1-xGe_xIn addition to changing the Ge composition ratio x of, add C (Si)_1-xGe_x)_1-yC_yThe composition ratio y of the above may be changed. As a method of adding C, C may be added at the time of growth of the strain application layer, or may be added by a method such as ion implantation after the strain application layer is grown.

The strain application layer is Si with a constant composition_1-xGe_xA method of growing the silicon substrate, a method of gradually increasing the composition ratio x from the Si substrate in the growth direction, a so-called graded buffer layer may be used. In addition, a Si layer with a high defect density is grown on the Si substrate at a low temperature, or a defect layer is formed by a method such as ion implantation of hydrogen, Si, or Ge, and then Si._1-xGe_xAs it grows, Si directly on the Si substrate_1-xGe_xThis is preferable because the penetration transition density can be reduced and the surface flatness is improved as compared with the case of growing.

Further, if the substrate and the strain application layer portion have a so-called SOI (Silicon on insulator) structure, the stray capacitance can be reduced to further increase the speed. For SOI, a bonded SOI substrate and a SIMOX (Separation by Implanted Oxigen) substrate are commercially available, and Si is mounted on this substrate._1-xGe_xStrained Si (Si) that takes advantage of the features of SOI by growing a strained layer_1-yGe_y(0 &lt;y 1)) A field effect transistor can be manufactured.

Also, first Si on the Si substrate_1-xGe_xBy growing the strain application layer, and then driving oxygen ions and performing heat treatment, Si_1-xGe_xSiO in the strain application layer or Si immediately below it₂A method of embedding an insulating layer and then growing a strained Si layer, or first Si on a Si substrate_1-xGe_xBy growing the strained Si layer and the strained Si layer, and then performing heat treatment by driving oxygen ions, SiO is placed inside the strained Si layer.₂It is also possible to use a method of embedding an insulating layer. By using these methods, the thickness of the SOI active layer can be reduced, the element separation is excellent, and the well layer for pMOS and nMOS becomes unnecessary. In the latter case, SiO is directly below the strained Si layer.₂Since there is an insulating layer, the problem of holes flowing out to the strain application layer in pMOS as described above does not occur.

Alternatively, Si on a Si substrate_1-xGe_xAfter growing the strain application layer and further growing the Si layer, a substrate obtained by thermally oxidizing a part or all of the Si layer is prepared. Alternatively, instead of thermal oxidation of the Si layer, Si_1-xGe_xSiO on the strain application layer₂The layer may be grown by a vapor phase growth method or the like. And the support board and SiO prepared separately from this₂Facing each other, and then Si_1-xGe_xSi is cut by polishing the Si substrate on the side where the strain application layer is grown, or by driving hydrogen ions or inserting a porous Si layer in the middle._1-xGe_xWhen the strain application layer is exposed, Si_1-xGe_xA bonded SOI substrate with a strain application layer can be manufactured. According to this method, Si_1-xGe_xSince the portion of the strain application layer having a high defect density close to the Si substrate can be removed, the defect density can be reduced, and further polishing or etching makes it easy to secure the surface flatness. Further, by this method, the thickness of the SOI active layer can be reduced, the element separation is excellent, and the well layer for pMOS and nMOS becomes unnecessary.

When cutting the above-mentioned bonded SOI substrate, Si_1-xGe_xIt is not always necessary to leave the strain application layer. That is, Si on the Si substrate_1-xGe_xA support substrate and SiO in which a strain-applied layer is grown, a strained Si layer is further grown, and a substrate in which a part thereof is thermally oxidized is prepared separately is prepared.₂Are bonded face to face, cut or polished leaving the strained Si layer part, and SiO₂It is possible to manufacture a substrate in which a strained Si layer is placed on the layer. This board looks exactly the same as a conventional bonded SOI board, only the SOI layer is distorted. Therefore, it can be handled in exactly the same way as a conventional SOI substrate, has excellent element separation, eliminates the need for well layers for pMOS and nMOS, and has a light effective mass of the SOI active layer due to the effect of strain. It will have the characteristic of strained Si, which has high hole mobility. Also, just below the strained Si layer, SiO₂Since there is an insulating layer, the problem of holes flowing out to the strain application layer in pMOS as described above does not occur.

There is a certain limit to the thickness of the strained Si layer. This is because there is an upper limit on the film thickness of the strained Si layer that can grow without transition depending on the magnitude of the strain. This is called the critical film thickness, and Si_1-xGe_xWhen a strained Si layer is grown on the strain application layer, for example, when x = 0.2, the strain size is about 0.8%, the critical film thickness is about 100 nm, and when x = 0.5, the strain size is about 2. In%, the critical film thickness is around 10 nm. However, the magnitude of this critical film thickness depends on the growth conditions of the strained Si layer and cannot be uniquely determined. Further, the above limitation also differs in the case of a structure in which an oxide film layer is inserted between the SOI substrate and the strained Si layer, as in the case of a combination. However, the thickness of the strained Si layer is in the range of 1 nm to 200 nm, with x in the range of 0.2 to 0.8 and the strain in the range of 0.8 to 3.2%, which is a composition that realizes a practically significant strain magnitude. It is desirable to have. This is because if the thickness is less than 1 nm, the thickness of the active layer forming the channel in the field effect transistor is insufficient, and if it is thicker than 200 nm, transition starts to occur and the electrical characteristics begin to be adversely affected.

The selection of the plane orientation of the substrate crystal to be used and the selection of the relationship between the carrier traveling directions in the channel are necessary requirements for higher speed operation.

Using the {100} plane as the substrate plane orientation is advantageous in terms of coupling with conventional devices and the use of the same process because many conventional Si semiconductor devices use this plane orientation, and distortion. The mobility when is applied is also greatly increased, which is a desirable crystal orientation. In this case, it is advantageous to set the in-plane direction of the channel to the &lt;110&gt; or &lt;001&gt; direction in order to improve the controllability of processes such as epi-growth and etching.

It is also possible to use the {110} plane as the substrate plane orientation. In this case, it is advantageous to set the channel direction to &lt;110&gt; or &lt;001&gt; in terms of increasing the mobility due to the application of strain. Further, it is more desirable to use the &lt;110&gt; direction as the electron channel. However, this arrangement is not always necessary when considering the balance between nMOSFETs and pMOSFETs.

As described above, the field-effect transistor or complementary field-effect transistor in which the active layer forming the channel is distorted and the semiconductor device using the field-effect transistor have a lighter effective mass of carriers flowing through the channel than in the past. Therefore, its industrial value is extremely high because of its high mobility, high speed, high integration of elements, and high performance.

Hereinafter, the present invention will be described in detail with reference to Examples.

(Example 1) FIG. 7 is a cross-sectional view of the C MOSFET according to this embodiment. Immediately after cleaning the Si substrate 13, it was introduced into a chemical vapor deposition apparatus and Si._0.7Ge_0.3The strain application layer 2 is grown. The plane orientation of the Si substrate 13 is {100}. The film thickness is 500 nm. Si for raw material₂H₆And GeH₄It grows at a growth temperature of 700 ° C. Here, doping for determining the conductive type is not performed. Si_1-xGe_xThe Ge composition ratio x of the strain application layer 2 can be controlled in any way, but in order to optimize the strain applied to the strain Si layer 1, good results can be obtained by setting x to 0.2-0.4.

Next, Si_1-xGe_xA strained Si layer 1 is formed on the strained Si layer 2 by a chemical vapor deposition method. Here, doping for determining the conductive type is not performed. The film thickness was 60 nm. This layer is Si_1-xGe_xSince the lattice constant of the strain application layer 2 is larger than Si, it is subjected to in-plane tensile strain. As a result, the carrier (electron and hole) mobility in this is higher than that in undistorted Si. The growth of the Si layer and the SiGe layer is not limited to the chemical vapor deposition method.

Next, the device separation insulation region 19 is formed by the trench separation method, and the lower part of the strained Si layer 1 and Si are formed._1-xGe_xWell-forming ions are driven over the strain application layer 2. Group V elements such as P are injected into the lower part of the epitaxial region to form n-type, and group III elements such as B are injected into the lower part of the MIMO region to form p-type. Further, a group III element is injected into the PMOS region and a group V element is injected into the MIMO region above the strained Si layer 1 to adjust the threshold value.

Next, the surface of the strained Si layer 1 is thermally oxidized to determine SiO.₂The gate insulating film 3 is formed. Further, after forming the polysilicon gate electrode 16 on the polysilicon gate electrode 16, the area other than the gate region is removed by etching. Furthermore, the source / drain region is formed by self-alignment by the ion implantation method. At this time, if a group III element such as B is injected, a p-type source / drain region 17 can be formed, and if a group V element such as P is injected, an n-type source / drain region 18 can be formed. Can be made into. At this time, Si_1-xGe_xIn order to reduce the leakage current to the strain application layer 2, the ion implantation depth was set to 30 nm, which is less than half the thickness of the strain Si layer 1. Finally, an interlayer insulating film (not shown) is formed, contact holes are formed, a metal film such as Al is vapor-deposited, patterning is performed, and metal wiring is formed to complete a field effect transistor. This transistor has about 3 times the transconductance and 2.4 times the cutoff frequency compared to the undistorted Si field effect transistor manufactured directly on the Si substrate with the same dimensions.

(Example 2) FIG. 8 is a cross-sectional view of the C MOSFET according to this embodiment. In this example, instead of deepening the source / drain regions 17 and 18 in Example 1 to a depth of 30 nm to 50 nm in the normal case, Si_1-xGe_xIn the formation of the strain application layer 2, P doping gas is mixed in the upper 30 nm range, and 10¹⁸It is a steep n-type doping at a high concentration of every cubic centimeter. At that time, in order to dope only the pMOS region, the nMOS region is coated with an oxide film and removed after doping.

However, well-forming ions are not implanted in the steeply doped pMOS region.

In this example as well, the same effects as in Example 1 were obtained with respect to the transconductance and the cutoff frequency.

(Example 3) FIG. 9 is a cross-sectional view of the C MOSFET according to this embodiment. In this example, instead of the steep doping in Example 2, a positive bias is applied to the well region of pMOS.

Specifically, outside the device region, pMOS Si_1-xGe_xA contact hole is opened up to the strain application layer 2, an ohmic electrode is formed there, and the bias application electrode 22 is used.

By applying a voltage of + 1V to the bias application electrode 22, the punch-through current could be reduced to 5% or less as compared with the case where no bias was applied.

The methods of Examples 1 to 3 are methods that can be applied at the same time, and two or three types can be combined.

(Example 4) FIG. 10 is a cross-sectional view of the C MOSFET according to this embodiment. In this embodiment, the drain region 15 of the p-type MOSFET and the source region 14 of the n-type MOSFET of the strained Si layer 1 in the first embodiment are selectively etched, and the portions are Si._1-xGe_xLayer 23 is selectively grown and backfilled. The surface layer 5 nm of this part is Si, and Si by the subsequent process_1-xGe_xPrevent damage to layer 23.

The transistor of this embodiment can reduce the operating voltage of 3V, which is often used in conventional MOSFETs.

(Example 5) FIG. 11 is a cross-sectional view of the C MOSFET according to this embodiment. The feature of this embodiment is the strain Ge_yThe layer was used as a channel for PMOS.

A high defect density layer is formed on the Si substrate 13 in advance by implanting hydrogen ions over a region of 100 nm from the surface. Immediately after cleaning this substrate, it was introduced into a chemical vapor deposition apparatus, and x was changed from 0.3 to 0.5 in the growth direction._1-xGe_xThe lower layer 2 of the strain application layer composed of is grown. The film thickness is 300 nm. Si for raw material₂H₆And GeH₄It grows at a growth temperature of 700 ° C.

Furthermore, Si_0.5Ge_0.5The upper layer 24 of the strain application layer is formed in the same manner with a film thickness of 30 nm, the strain Ge layer 25 is formed with a film thickness of 10 nm, and the strained Si layer 1 is formed with a film thickness of 13 nm in this order. The growth of Si, Ge and SiGe layers is not limited to the chemical vapor deposition method, and any method capable of crystal growth having the above composition may be used. The strained Ge layer 25 receives in-plane compressive stress, and the strained Si layer 1 receives in-plane tensile stress. As a result, the effective mass of both the holes in the strained Ge layer 25 and the electrons in the strained Si layer 1 is reduced as compared with normal Si, and the mobility is increased.

Next, Si, which is the upper layer of the element separation insulation region 19 and the strain application layer, is formed by the same method as in Example 1._0.5Ge_0.5Layer 24 and the underlying Si_1-xGe_xWell-forming ions are implanted over the layer 2, and low-concentration ions for threshold adjustment are implanted in the upper part of the strained Si layer 1 and the upper part of the strained Ge layer 25. Then, SiO₂The gate oxide film 3 is formed, the gate electrode 16 is formed, and the source / drain regions 17 and 18 are formed. The ion implantation depth of the source / drain regions 17 and 18 was set to 10 nm, which is about the same as the thickness of the strained Si layer 1 for nMOS, and 20 nm, which reaches the strained Ge layer 25 for pMOS. Finally, the interlayer insulating film is formed, contact holes are formed, and metal wiring is formed to complete the CMOSFET.

In this embodiment, x = 0.5 Si_0.5Ge_0.5Since the layer 24 is grown as an upper layer of the strain application layer, the amount of strain applied to the strain Si layer 1 and the strain Ge layer 25 is large.

In this example, the channel is distorted Ge_yA layer was used, but strained Si mixed with Si_1-yGe_yLayers (0 &lt;y &lt;1) can also be used. In this case, the composition ratio y is Si_1-xGe_xMake the composition ratio of the strain application layer larger than x.

(Example 6) FIG. 12 is a cross-sectional view of the C MOSFET according to this embodiment. Si on the strained Si layer 1 in Examples and 5_0.5Ge_0.5The barrier layer 30 is formed at 2 nm.

Thus, Si_0.5Ge_0.5Since the barrier layer 30 is provided between the strained Si layer 1 and the gate insulating film 3, the electrons are not scattered at the interface between the strained Si layer 1 and the gate insulating film 3, and the Si_0.5Ge_0.5It is accumulated in the strained Si layer 1 near the interface between the barrier layer 30 and the strained Si layer 1.

Further, in this embodiment, the strained Si layer 1 is laminated on the strained Ge layer 25, but the order may be reversed. The ion implantation depth of the source / drain region 1718 is 12 nm, which is about the same as the thickness of the strained Si layer 1 for nMOS, and 22 nm, which reaches the strained Ge layer 25 for pMOS.

(Example 7) FIG. 13 is a cross-sectional view of the C MOSFET according to this embodiment. In this embodiment, the strained Si layer 1 and the strained Ge layer 25 in the fifth embodiment are arranged in parallel without being stacked.

Specifically, Si_0.5Ge_0.5A strained Ge layer 25 is selectively grown at 10 nm in the pMOS region and a strained Si layer 1 is selectively grown at 12 nm in the nMOS region on the strained layer 24. The strained Ge layer 25 is subjected to in-plane compressive stress, and the strained Si layer 1 is subjected to in-plane tensile stress. As a result, the effective mass of both the holes in the strained Ge layer 25 and the electrons in the strained Si layer 1 is reduced as compared with normal Si, and the mobility is increased.

(Example 8) FIG. 14 is a cross-sectional view of the SOI substrate according to this embodiment. After cleaning the Si substrate 13 having a high defect density epi layer with a thickness of 100 nm formed on the surface, it was immediately introduced into a chemical vapor deposition apparatus and Si._1-xGe_xThe strain application layer 2 is grown. The film thickness is 150 nm. Si for raw material₂H₆And GeH₄It grows at a growth temperature of 700 ° C. Si_1-xGe_xThe Ge composition ratio x of the strain applied layer 2 can be controlled in any way, but in order to optimize the strain applied to the strained Si layer 1 to be formed later, it is good to set x to 0.2-0.4. can get. In this example, it is set to 0.3. The growth of Si and SiGe layers is not limited to the chemical vapor deposition method, and any method capable of crystal growth having the above composition may be used.

Next, oxygen ions are accelerated with an acceleration voltage of 180 KeV and a dose amount of 4 x 10.¹⁷/cm²Si under the conditions of_1-xGe_xIt is injected from above the strain application layer 2 and annealed at 1350 ° C for 8 hours. This makes Si_1-xGe_xSiO just below the strain application layer 2₂The insulating layer 26 is formed. SiO₂The thickness of the insulating layer 26 is about 100 nm, and an insulating withstand voltage of 50 V or more is secured. Si by annealing treatment_1-xGe_xThe strain application layer 2 has an extremely low defect density, is flat, and has sufficient strain relaxation. Further, a strained Si layer 1 having a thickness of 60 nm is formed on the upper portion by a chemical vapor deposition method.

After that, the C MOSFET can be manufactured by using the same process as in Example 1 of the present invention. By using this substrate, ion implantation of the well layer becomes unnecessary.

In addition, since the stray capacitance is significantly reduced, the operating speed at the mounting level can be increased by about 40% compared to when using a normal Si substrate.

(Example 9) FIG. 15 is a cross-sectional view of another embodiment of the SOI substrate. Si in the same way as in Example 8_1-xGe_xAfter forming up to the strain application layer 2, Si_1-xGe_xA strained Si layer 1 having a thickness of 120 nm is formed on the strained silicon layer 2 by a chemical vapor deposition method. Next, oxygen ions are accelerated with an acceleration voltage of 50 KeV and a dose amount of 2 x 10.¹⁷/cm²It is injected from above the strained Si layer 1 under the conditions of 1300 ° C and annealed at 1300 ° C for 8 hours. As a result, SiO is contained inside the strained Si layer 1.₂The insulating layer 26 is formed. SiO₂The thickness of the insulating layer 26 is about 30 nm.

In this embodiment, ion implantation in the well layer is not required, and holes are unlikely to flow out to the SiGe strain application layer in pMOS. Therefore, it is necessary to particularly use measures to prevent hole outflow by doping or bias application. There is no.

(Example 10) FIG. 16 is a cross-sectional view of the manufacturing process of the SOI substrate according to this embodiment. First, as shown in FIG. 16 (a), the Si substrate 13 having a high defect density epi layer having a thickness of 100 nm formed on the surface was washed, and then immediately introduced into a chemical vapor deposition apparatus and Si._1-xGe_xThe strain application layer 2 is grown. The film thickness is 300 nm. Si for raw material₂H₆And GeH₄It grows at a growth temperature of 700 ° C. Si_1-xGe_xThe Ge composition ratio x of the strain applied layer 2 can be controlled in any way, but in order to optimize the strain applied to the strained Si layer 1, good results can be obtained by setting x to 0.2-0.4. In this example, it is set to 0.3. The growth of Si and SiGe layers is not limited to the chemical vapor deposition method, and any method capable of crystal growth having the above composition may be used. Further, a Ge substrate or a SiGe mixed crystal substrate may be used instead of the Si substrate 13. When the mixed crystal ratio x of Ge is large, it is better to use a Ge substrate or a SiGe substrate with a large Ge mixed crystal ratio._1-xGe_xThe strain application layer 2 grows easily or becomes unnecessary.

Next, the strained Si layer 1 is grown, the surface is thermally oxidized, and then hydrogen ions are injected to the depth of the cutting position 28 to form a damaged layer at this position. In this way, the state shown in FIG. 16 (a) is obtained. Cutting position 28 is Si_1-xGe_xIt may be the inside of the strain application layer 2 or the inside of the strain Si layer 1.

Further, the support substrate 29 prepared separately from the oxide film on the surface is joined at the joining position 27, and the state as shown in FIG. 16 (b) is obtained. Then, when annealed at 500 ° C, it is cut at the cutting position 28, and the cutting position 28 is Si._1-xGe_xThe inside of the strained silicon layer 2 is as shown in FIG. 16 (c), and the inside of the strained Si layer 1 is as shown in FIG. 16 (d). In the case shown in FIG. 16 (c), a 60 nm strained Si layer 1 is further epitaxially grown on the surface.

After that, the C MOSFET can be manufactured by using the same process as in Example 1 of the present invention. By using this substrate, ion implantation of the well layer becomes unnecessary. Further, in the case of the structure of FIG. 16 (d), since the holes do not flow out to the SiGe strain application layer in pMOS, it is not necessary to take measures to prevent the holes from flowing out by doping or bias application.

In addition, since the stray capacitance is significantly reduced, the operating speed at the mounting level can be increased by about 40% compared to when using a normal Si substrate.

(Example 11) By the method shown in Example 1, the complementary field effect transistor is Si using the Si substrate 13 on the {100} plane._1-xGe_xWhen the Ge composition ratio x of the strain applied layer 2 is variously changed and the mobility of electrons and holes in the strained Si channel is estimated from the transconductance of the devices, they are mixed as shown in Table 1. Even if the crystal ratio is about 0.2, the increase in mobility is quite large. The units are strain% (positive value is tensile strain) and mobility cm.²/ Vs. table 1 Ge composition ratio x strain electron mobility hole mobility 0 0 1300 400 0.1 0.4 2600 850 0.2 0.8 3300 2000 0.3 1.2 3550 3100 0.4 1.6 3500 4500 0.5 2.0 3450 5200 0.6 2.4 3400 6100 By the method shown in Example 7, the pMOSFET is Si using the Si substrate 13 on the {100} plane._1-xGe_xWhen the Ge composition ratio x of the strain application layer 2 is variously changed and the mobility of holes in the strain Ge channel in the &lt;001&gt; direction is estimated from the transconductance of the elements, in-plane compression is shown in Table 2. The mobility increases dramatically as it receives distortion. The units are strain% (positive value is tensile strain) and mobility cm.²/ Vs. Table 2 Ge composition ratio x strain hole mobility 1.0 0 1900 0.9 -0.4 2800 0.8 -0.8 4100 0.7 -1.2 7000 0.6 -1.6 9000 0.5 -2.0 12000 0.4 -2.4 13500 Complementary field-effect transistors are manufactured using the {110} -plane Si substrate 13 by the method shown in Example 1, and electrons in the &lt;001&gt; and &lt;110&gt; directions in the strained Si channel from the transconductance of the elements. Estimating the mobility of holes and holes, as shown in Table 3, the electron mobility is higher in the &lt;110&gt; direction. The units are strain% (positive value is tensile strain) and mobility cm.²/ Vs. Table 3 Ge composition ratio x strain direction electron mobility hole mobility 0.2 0.8 &lt;001&gt; 900 1800 0.2 0.8 &lt;110&gt; 3100 1800 0.3 1.2 &lt;001&gt; 900 2700 0.3 1.2 &lt;110&gt; 3300 2700

1 ... strained Si layer, 2 ... Si_1-xGe_xStrain application layer, 3 ... SiO₂Gate insulating layer, 4 ... conduction band, 5 ... valence band, 6 ... strained Si bandgap, 7 ... Si_1-xGe_xBand gap, 8 ... conduction band discontinuity, 9 ... valence band ... discontinuity, 10 ... gate insulating film / conduction band triangular well in the strained Si layer near the Si layer interface , 11 ... Gate insulating film / Triangular well of valence band in strained Si layer near interface, 12 ... Strained Si layer / Si_1-xGe_xSi near the strain application layer interface_1-xGe_xTriangular well of valence band in strain application layer 2, 13 ... Si substrate, 14 ... source electrode, 15 ... drain electrode, 16 ... gate, 17 ... p-type source / drain region, 18 ... n-type source / drain region, 19 ... element separation insulation region, 20 ... strain Si layer / strain Si_1-yGe_yStrained Si near the layer interface_1-yGe_yTriangular well of valence band in the layer, 21 ... steep n-type doping layer, 22 ... biased electrode, 23 ... Si_1-xGe_xDrain layer, 24 ... Si_0.5Ge_0.5Layer, 25 ... strained Si_1-yGe_yLayer (0 &lt;y 1), 26 ... SiO₂Insulation layer, 27 ... junction position, 28 ... cutting position, 29 ... support substrate, 30 ... Si_0.5Ge_0.5Barrier layer, 40, 41 ... the apex of the triangular well in the conduction band, 42, 43 ... the apex of the triangular well in the valence band.