Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, and the like.

Due to the miniaturization of electronic devices, the mounting space for electronic components such as semiconductor devices mounted inside the electronic devices is being limited. Therefore, there is a demand for miniaturization of electronic components such as semiconductor devices.

As a method for miniaturizing a semiconductor device, a method of stacking semiconductor substrates (semiconductor chips) to form a semiconductor device has been proposed. This method is a method for high-density mounting of semiconductor chips by laminating semiconductor chips having the same function or semiconductor chips having different functions and connecting the semiconductor chips with wiring.

Then, as a method for wiring-connecting between the semiconductor chips, a method of providing a through electrode (wiring electrode penetrating the semiconductor chip) on the semiconductor chip and thereby wiring and connecting each semiconductor chip has been proposed.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2007-49103</text></patcit>

<p> When the wiring connected to the power supply potential is electrically separated to supply different power supply voltages to multiple circuits, or when the wiring connected to the ground potential is electrically separated to suppress the influence of noise between circuits. May be separated into.</p><p> Similarly, when a plurality of semiconductor substrates are laminated to form a semiconductor device, the wiring connected to the power supply potential and the wiring connected to the ground potential can be electrically separated for each semiconductor substrate, or a plurality of wirings in the semiconductor substrate can be separated. It is conceivable that the wiring connected to the power supply potential and the wiring connected to the ground potential may be electrically separated for each circuit.</p><p> In such a case, since there is no discharge path when an electrostatic voltage is applied between the external terminals connected to the electrically separated potential wiring, the circuit element may be destroyed.</p><p> The present invention has been made in view of the above technical problems. According to some aspects of the present invention, it is possible to provide a semiconductor device using a through electrode and a method for manufacturing the semiconductor device, which can suppress electrostatic discharge destruction of a circuit element.</p>

<p> (1) The semiconductor device according to the present invention is A semiconductor device in which a plurality of semiconductor substrates are laminated and included. A through electrode that penetrates a given semiconductor substrate among the plurality of semiconductor substrates, Multiple circuits, including potential wiring to be connected to the first potential, Including electrostatic discharge protection circuit The plurality of circuits are provided on the semiconductor substrates that are different from each other. The potential wiring of one of the plurality of circuits and the potential wiring of the other circuit of the plurality of circuits are electrically connected to each other via the through electrode and the electrostatic discharge protection circuit. The feature is that they are connected to each other.</p><p> According to the present invention, when an electrostatic voltage is applied between electrically separated potential wires, the through electrode and the electrostatic discharge protection circuit serve as a discharge path. As a result, it is possible to suppress electrostatic discharge destruction of the circuit element.</p><p> (2) This semiconductor device is The plurality of electrostatic discharge protection circuits that form a part of an electrical path between the potential wiring of one of the plurality of circuits and the potential wiring of the other circuit of the plurality of circuits. The circuit may be provided on the semiconductor substrate on which one of the circuits of the above is provided.</p><p> (3) The semiconductor device according to the present invention is A semiconductor device in which a plurality of semiconductor substrates are laminated and included. A through electrode that penetrates a given semiconductor substrate among the plurality of semiconductor substrates, Multiple circuits, including potential wiring to be connected to the first potential, Including electrostatic discharge protection circuit The plurality of circuits and the electrostatic discharge protection circuit are provided on the semiconductor substrates that are different from each other. The potential wiring of one of the plurality of circuits and the potential wiring of the other circuit of the plurality of circuits are electrically connected to each other via the through electrode and the electrostatic discharge protection circuit. The feature is that they are connected to each other.</p><p> (4) This semiconductor device is The electrostatic discharge protection circuit may be provided on a semiconductor substrate manufactured by the least miniaturized manufacturing process among the plurality of semiconductor substrates.</p><p> (5) This semiconductor device is Includes multiple through silicon vias The potential wiring of one of the plurality of circuits and the potential wiring of the other circuit of the plurality of circuits are different from each other as a circuit element that is a part of the electrostatic discharge protection circuit. It may be connected by a plurality of electrical paths via a through electrode.</p><p> (6) This semiconductor device is Each electrical path of the plurality of electrical paths may be a part of the electrostatic discharge protection circuit and may include circuit elements provided on different semiconductor substrates.</p><p> (7) This semiconductor device is Includes three or more circuits, including potential wiring connected to the first potential, The three or more circuits are provided on the semiconductor substrates that are different from each other. The potential wiring of each of the three or more circuits may be electrically connected to the through electrode via the electrostatic discharge protection circuit corresponding to each of the three or more circuits.</p><p> (8) This semiconductor device is The electrostatic discharge protection circuit may be configured to include parallel diodes having different orientations from each other.</p><p> (9) This semiconductor device is The first potential may be the ground potential.</p><p> (10) The method for manufacturing a semiconductor device according to the present invention is as follows. Stacking multiple semiconductor substrates, A through electrode that penetrates a given semiconductor substrate among the plurality of semiconductor substrates, Multiple circuits, including potential wiring to be connected to the first potential, A method for manufacturing a semiconductor device including an electrostatic discharge protection circuit. The plurality of circuits are provided on the semiconductor substrates that are different from each other, and the potential wiring of one circuit of the plurality of circuits and the potential wiring of the other circuit of the plurality of circuits are connected to the through electrode. It is characterized in that it is electrically connected to each other via the electrostatic discharge protection circuit.</p><p> (11) The method for manufacturing a semiconductor device according to the present invention is as follows. Stacking multiple semiconductor substrates, A through electrode that penetrates a given semiconductor substrate among the plurality of semiconductor substrates, Multiple circuits, including potential wiring to be connected to the first potential, A method for manufacturing a semiconductor device including an electrostatic discharge protection circuit. The plurality of circuits and the electrostatic discharge protection circuit are provided on the semiconductor substrates that are different from each other, and the potential wiring of one circuit of the plurality of circuits and the other circuit of the plurality of circuits are provided. The potential wiring is electrically connected to each other via the through electrode and the electrostatic discharge protection circuit.</p>

Hereinafter, embodiments to which the present invention is applied will be described with reference to the drawings. However, the present invention is not limited to the following embodiments. Further, the present invention shall include a free combination of the following contents.

1. First embodiment FIG. 1 is a circuit diagram of a semiconductor device according to the first embodiment.

The semiconductor device 1 according to the first embodiment includes a circuit 10, a circuit 20, and an electrostatic discharge protection circuit 30. Further, the semiconductor device 1 is scheduled to receive the power supply potential from the external terminal VDD1 and the external terminal VDD2 and the ground potential from the external terminal VSS1 and the external terminal VSS2.

The circuit 10 includes an internal circuit 11. The internal circuit 11 is configured to include a circuit element such as a transistor, and functions during normal operation by being supplied with a power supply voltage.

The circuit 10 may include an electrostatic discharge protection circuit 12. The electrostatic discharge protection circuit 12 is a protection circuit that serves as a discharge path for electric charges due to the input static electricity between the external terminal VDD1 and the external terminal VSS1, and protects the circuit elements included in the internal circuit 11 from electrostatic discharge destruction. It is provided for protection.

Circuit 10 includes a potential wire 13 that will be connected to the first potential. In the example shown in FIG. 1, the first potential is the ground potential supplied from the external terminal VSS1.

The circuit 20 includes an internal circuit 21. The internal circuit 21 is configured to include a circuit element such as a transistor, and functions during normal operation by being supplied with a power supply voltage.

The circuit 20 may include an electrostatic discharge protection circuit 22. The electrostatic discharge protection circuit 22 is a protection circuit that serves as a discharge path for electric charges due to input static electricity between the external terminal VDD2 and the external terminal VSS2, and protects the circuit elements included in the internal circuit 21 from electrostatic discharge destruction. It is provided for protection.

The circuit 20 includes a potential wiring 23 that will be connected to the first potential. In the example shown in FIG. 1, the first potential is the ground potential supplied from the external terminal VSS2.

The electrostatic discharge protection circuit 30 is, for example, a protection circuit that serves as a discharge path for electric charges due to input static electricity between the external terminal VSS1 and the external terminal VSS2, and includes circuit elements included in the internal circuit 11 and the internal circuit 21. It is provided to protect from electrostatic discharge destruction. That is, when the circuit 10 and the circuit 20 are operating normally, it can be considered that the potential wiring 13 and the potential wiring 23 are electrically separated.

In the example shown in FIG. 1, the electrostatic discharge protection circuit 30 includes a diode 31 and a diode 32 having different orientations in parallel. In addition, one or a plurality of diodes may be further provided in series in the path on the diode 31 side and the path on the diode 32 side, respectively.

FIG. 2 is a schematic view for explaining the cross-sectional structure of the semiconductor device according to the first embodiment. Of the circuit elements shown in the circuit diagram of FIG. 1, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal VDD2 are not shown. There is. Further, FIG. 2 shows a cross-sectional structure of the laminated body 100 which is a part of the semiconductor device 1 according to the first embodiment.

The semiconductor device 1 according to the first embodiment is configured by laminating a semiconductor substrate 40 and a semiconductor substrate 50. The semiconductor substrate 40 electrically connects the semiconductor layer 41 on which the circuit elements (transistors, diodes, etc.) included in the circuit 10 and the electrostatic discharge protection circuit 30 are formed, and the circuit elements and through electrodes (details will be described later). It is configured to include a wiring layer 42 in which wiring for the purpose is formed. The semiconductor substrate 50 includes a semiconductor layer 51 on which circuit elements (transistors, diodes, etc.) included in the circuit 20 are formed, and a wiring layer 52 on which wiring is formed. The wiring is made of a metal such as aluminum or copper. Further, the wiring may be formed in a plurality of layers and electrically connected to each other via a via hole.

In the example shown in FIG. 2, the circuit elements of the electrostatic discharge protection circuit 30 and the circuit 10 (not shown) are formed on the semiconductor layer 41 of the semiconductor substrate 40, and the potential wiring 13 and the wiring 60 are formed on the wiring layer 42. There is. Further, a circuit element of the circuit 20 (not shown) is formed on the semiconductor layer 51 of the semiconductor substrate 50, and a potential wiring 23 is formed on the wiring layer 52.

Further, in the example shown in FIG. 2, the semiconductor device 1 includes an electrode 71 and an electrode 72 configured as a through electrode. The potential wiring 13 is electrically connected to the external terminal VSS1 via the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 via the electrode 72.

The semiconductor device 1 according to the first embodiment is configured to include a through electrode 61. The through silicon via 61 penetrates the semiconductor substrate 40 and functions as a part of the electrical path.

Through electrodes may be formed after laminating semiconductor substrates. Further, as shown in the schematic diagram for explaining an example of the configuration of the through electrode shown in FIG. 3, the through electrode is formed separately for each semiconductor substrate as in 61a and 61b, and the semiconductor substrates are laminated. It may be configured to be electrically connected.

The wiring layer 52 of the semiconductor substrate 50 and the semiconductor layer 41 of the semiconductor substrate 40 may be adhered with an adhesive 70.

In the semiconductor device 1 according to the first embodiment, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are electrically connected to each other via the through electrode 61 and the electrostatic discharge protection circuit 30. ing. In the example shown in FIG. 2, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are electrically connected to each other via the electrostatic discharge protection circuit 30, the wiring 60, and the through electrode 61. ..

According to the semiconductor device 1 according to the first embodiment, when an electrostatic voltage is applied between the electrically separated potential wiring 13 and the potential wiring 23, the through electrode 61 and the electrostatic discharge protection circuit 30 is the discharge path. As a result, it is possible to suppress electrostatic discharge destruction of the circuit elements included in the circuit 10 and the circuit 20.

Further, in the semiconductor device 1 according to the first embodiment, the electrostatic discharge protection circuit 30 which is a part of the electrical path between the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 is provided with the circuit 10. It is provided on the semiconductor substrate 40.

It is difficult to miniaturize the circuit elements constituting the electrostatic discharge protection circuit 30. Therefore, even if it is manufactured by a miniaturized manufacturing process, the influence on the area of the circuit element is small. Therefore, when the semiconductor substrate 40 is a semiconductor substrate manufactured by the least miniaturized manufacturing process among the plurality of semiconductor substrates constituting the semiconductor device 1, the electrostatic discharge protection circuit 30 is attached to the semiconductor substrate 40. By providing the above, the manufacturing cost can be suppressed.

Further, even when the semiconductor substrate 40 has a larger area than the semiconductor substrate 50, the electrostatic discharge protection circuit 30 can be provided on the semiconductor substrate 40.

4 (A) and 4 (B) are schematic views for explaining the cross-sectional structure of the semiconductor device according to the first embodiment. FIG. 4A is an example of a configuration in which the laminate 100 described with reference to FIG. 1 is placed face-up on the package substrate 80 and molded with the mold resin 81. FIG. 4B is an example of a configuration in which the laminate 100 described with reference to FIG. 2 is installed face-down on the package substrate 80 and molded with the mold resin 81.

In FIGS. 4 (A) and 4 (B), the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal are similar to those in FIG. Illustration 2 is omitted.

In the example shown in FIG. 4A, the package substrate 80 is provided with external terminals VDD1 and VSS2, and the electrode 71 and the external terminal VSS1 and the electrode 72 and the outside are provided via the wiring and the bonding wire inside the package substrate 80. Each terminal VSS2 is electrically connected.

In the example shown in FIG. 4B, the package substrate 80 is provided with external terminals VSS1 and VSS2, and the electrode 71 and the external terminal VSS1 and the electrode 72 and the external terminal VSS2 are provided via the wiring inside the package substrate 80. Are electrically connected to each other.

2. Second embodiment FIG. 5 is a schematic view for explaining the cross-sectional structure of the semiconductor device according to the second embodiment. The circuit diagram of the semiconductor device according to the second embodiment is the same circuit diagram shown in FIG. 1 as the semiconductor device according to the first embodiment. Of the circuit elements shown in the circuit diagram of FIG. 1, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal VDD2 are not shown. There is. Further, FIG. 5 shows a cross-sectional structure of the laminated body 200 which is a part of the semiconductor device 2 according to the second embodiment.

The semiconductor device 2 according to the second embodiment is configured by laminating a semiconductor substrate 40 and a semiconductor substrate 50. The semiconductor substrate 40 has a semiconductor layer 41 on which circuit elements (transistors, diodes, etc.) included in the circuit 10 and circuit 20 are formed, and a wiring layer on which wiring for electrically connecting the circuit elements and through electrodes is formed. It is composed of 42. The semiconductor substrate 50 includes a semiconductor layer 51 on which circuit elements (transistors, diodes, etc.) included in the electrostatic discharge protection circuit 30 are formed, and a wiring layer 52 on which wiring is formed.

In the example shown in FIG. 5, the circuit elements of the circuit 10 and the circuit 20 (both not shown) are formed on the semiconductor layer 41 of the semiconductor substrate 40, and the potential wiring 13 and the potential wiring 23 are formed on the wiring layer 42. Further, the circuit element of the electrostatic discharge protection circuit 30 is formed on the semiconductor layer 51 of the semiconductor substrate 50, and the wiring 60-1 and the wiring 60-2 are formed on the wiring layer 52.

Further, in the example shown in FIG. 5, the semiconductor device 2 includes electrodes 71 and 72. The potential wiring 13 is electrically connected to the external terminal VSS1 via the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 via the electrode 72.

The semiconductor device 2 according to the second embodiment includes through electrodes 61 and 62. Through electrodes 61, 62 penetrate the semiconductor substrate 40 and function as part of an electrical path.

In the semiconductor device 2 according to the second embodiment, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are electrically electrically connected to each other via the through electrodes 61 and 62 and the electrostatic discharge protection circuit 30. It is connected. In the example shown in FIG. 5, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 pass through the through electrode 61, the wiring 60-1, the electrostatic discharge protection circuit 30, the wiring 60-2, and the through electrode 62. Are electrically connected to each other.

According to the semiconductor device 2 according to the second embodiment, when an electrostatic voltage is applied between the electrically separated potential wiring 13 and the potential wiring 23, the through electrodes 61 and 62 and the electrostatic discharge are electrostatically discharged. The protection circuit 30 serves as a discharge path. As a result, it is possible to suppress electrostatic discharge destruction of the circuit elements included in the circuit 10 and the circuit 20.

Further, in the semiconductor device 2 according to the second embodiment, the electrostatic discharge protection circuit 30 which is a part of the electrical path between the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 is the circuit 10 or the circuit 20. Is provided on the semiconductor substrate 50 in which the above is not provided.

When the semiconductor substrate 50 is a semiconductor substrate manufactured by the least miniaturized manufacturing process among the plurality of semiconductor substrates constituting the semiconductor device 2, the semiconductor substrate 50 is provided with the electrostatic discharge protection circuit 30. As a result, the manufacturing cost can be suppressed.

Further, even when the semiconductor substrate 50 has a larger area than the semiconductor substrate 40, the electrostatic discharge protection circuit 30 can be provided on the semiconductor substrate 50.

The semiconductor device 2 according to the second embodiment has a configuration in which the laminated body 100 is replaced with the laminated body 200 in FIGS. 4 (A) and 4 (B).

3. Third embodiment FIG. 6 is a schematic view for explaining the cross-sectional structure of the semiconductor device according to the third embodiment. The circuit diagram of the semiconductor device according to the third embodiment is the same circuit diagram shown in FIG. 1 as the semiconductor device according to the first embodiment. Of the circuit elements shown in the circuit diagram of FIG. 1, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal VDD2 are not shown. There is. Further, FIG. 6 shows a cross-sectional structure of the laminated body 300 which is a part of the semiconductor device 3 according to the third embodiment.

The semiconductor device 3 according to the third embodiment is configured by laminating a semiconductor substrate 40 and a semiconductor substrate 50. In the semiconductor substrate 40, the semiconductor layer 41 on which the circuit elements (transistors, diodes, etc.) included in the circuit 10 and the electrostatic discharge protection circuit 30 are formed, and the wiring for electrically connecting the circuit elements and the through electrodes are formed. It is configured to include the wiring layer 42 to be formed. The semiconductor substrate 50 includes a semiconductor layer 51 on which circuit elements (transistors, diodes, etc.) included in the circuit 20 and the electrostatic discharge protection circuit 30 are formed, and a wiring layer 52 on which wiring is formed.

In the example shown in FIG. 6, a circuit element of circuit 10 (not shown) and a diode 31 which is a circuit element to be a part of the electrostatic discharge protection circuit 30 are formed on the semiconductor layer 41 of the semiconductor substrate 40, and a wiring layer is formed. The potential wiring 13 and the wiring 60-4 are formed on 42. Further, a circuit element of the circuit 20 (not shown) and a diode 32 which is a circuit element to be a part of the electrostatic discharge protection circuit 30 are formed on the semiconductor layer 51 of the semiconductor substrate 50, and the potential wiring 23 is formed on the wiring layer 52. And wiring 60-3 is formed.

Further, in the example shown in FIG. 6, the semiconductor device 3 includes an electrode 71 and an electrode 72 configured as a through electrode. The potential wiring 13 is electrically connected to the external terminal VSS1 via the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 via the electrode 72. In the example shown in FIG. 6, the electrode 71 and the electrode 72 are provided so as to be offset in the direction perpendicular to the plane of FIG. 6 (the electrode 71 is relatively on the front side and the electrode 72 is on the relatively back side). And are electrically separated.

The semiconductor device 3 according to the third embodiment includes through electrodes 61 and 62. Through electrodes 61, 62 penetrate the semiconductor substrate 40 and function as part of an electrical path.

In the semiconductor device 3 according to the third embodiment, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are circuit elements in which the potential wiring 23 of the circuit 20 is a part of the electrostatic discharge protection circuit 30, a diode 31 and a through electrode 61. The electrical path is electrically connected to each other via the diode 32 and the through electrode 62, which are circuit elements that are a part of the electrostatic discharge protection circuit 30. In the example shown in FIG. 6, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 have an electrical path via the diode 31, the wiring 60-4, and the through electrode 61, and the through electrode 62 and the wiring 60-. 3. They are electrically connected to each other through an electrical path via a diode 32.

According to the semiconductor device 3 according to the third embodiment, when an electrostatic voltage is applied between the electrically separated potential wiring 13 and the potential wiring 23, the through diodes 61 and 62 and the electrostatic discharge The diodes 31 and 32, which are part of the protection circuit 30, serve as the discharge path. As a result, it is possible to suppress electrostatic discharge destruction of the circuit elements included in the circuit 10 and the circuit 20.

The semiconductor device 3 according to the third embodiment has a configuration in which the laminated body 100 is replaced with the laminated body 300 in FIGS. 4 (A) and 4 (B).

4. Fourth embodiment FIG. 7 is a circuit diagram of the semiconductor device according to the fourth embodiment. Compared with the circuit diagram of the semiconductor device according to the first embodiment shown in FIG. 1, only the configuration of the electrostatic discharge protection circuit 30 is different. In the circuit diagram shown in FIG. 7, the electrostatic discharge protection circuit 30 is configured by connecting a set of diodes 31 and 33 in series and a set of diodes 32 and 34 connected in parallel in different directions. There is.

FIG. 8 is a schematic view for explaining the cross-sectional structure of the semiconductor device according to the fourth embodiment. Of the circuit elements shown in the circuit diagram of FIG. 7, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal VDD2 are not shown. There is. Further, FIG. 8 shows a cross-sectional structure of the laminated body 400 which is a part of the semiconductor device 4 according to the fourth embodiment.

The semiconductor device 4 according to the fourth embodiment is configured by laminating a semiconductor substrate 40 and a semiconductor substrate 50. In the semiconductor substrate 40, the semiconductor layer 41 on which the circuit elements (transistors, diodes, etc.) included in the circuit 10 and the electrostatic discharge protection circuit 30 are formed, and the wiring for electrically connecting the circuit elements and the through electrodes are formed. It is configured to include the wiring layer 42 to be formed. The semiconductor substrate 50 includes a semiconductor layer 51 on which circuit elements (transistors, diodes, etc.) included in the circuit 20 and the electrostatic discharge protection circuit 30 are formed, and a wiring layer 52 on which wiring is formed.

In the example shown in FIG. 8, a circuit element of circuit 10 (not shown) and diodes 31 and 34, which are circuit elements that are a part of the electrostatic discharge protection circuit 30, are formed on the semiconductor layer 41 of the semiconductor substrate 40. The potential wiring 13 and the wirings 60-5 and 60-7 are formed on the wiring layer 42. Further, a circuit element of the circuit 20 (not shown) and diodes 32 and 33 which are circuit elements to be a part of the electrostatic discharge protection circuit 30 are formed on the semiconductor layer 51 of the semiconductor substrate 50, and a potential is formed on the wiring layer 52. Wiring 23 and wirings 60-6 and 60-8 are formed.

Further, in the example shown in FIG. 8, the semiconductor device 4 includes an electrode 71 and an electrode 72 configured as a through electrode. The potential wiring 13 is electrically connected to the external terminal VSS1 via the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 via the electrode 72. In the example shown in FIG. 8, the electrode 71 and the electrode 72 are provided so as to be offset in the direction perpendicular to the plane of FIG. 8 (the electrode 71 is relatively on the front side and the electrode 72 is on the relatively back side). And are electrically separated.

The semiconductor device 4 according to the fourth embodiment includes through electrodes 61 and 62. Through electrodes 61, 62 penetrate the semiconductor substrate 40 and function as part of an electrical path.

In the semiconductor device 4 according to the fourth embodiment, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 penetrate through the diodes 31 and 33, which are circuit elements that are a part of the electrostatic discharge protection circuit 30. The electrical path via the electrode 61 and the electrical path via the diodes 32 and 34, which are circuit elements that are part of the electrostatic discharge protection circuit 30, and the through electrode 62 are electrically connected to each other. ing. Further, each electrical path is configured to be a part of the electrostatic discharge protection circuit 30 and include circuit elements provided on different semiconductor substrates.

In the example shown in FIG. 8, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are electrically pathed through the diode 31, the wiring 60-5, the through electrode 61, the wiring 60-6, and the diode 33 ( The first electrical path) and the electrical path (second electrical path) via the diode 34, wiring 60-7, through electrode 62, wiring 60-8, and diode 32 are electrically connected to each other. Has been done.

The first electrical path is configured to include diodes 31 and 34, which are circuit elements provided on different semiconductor substrates as part of the electrostatic discharge protection circuit 30, and the second electrical path is electrostatic. It is configured to include diodes 32 and 33, which are circuit elements that are part of the discharge protection circuit 30 and are provided on different semiconductor substrates.

According to the semiconductor device 4 according to the fourth embodiment, when an electrostatic voltage is applied between the electrically separated potential wiring 13 and the potential wiring 23, the through diodes 61 and 62 and the electrostatic discharge are electrostatically discharged. Diodes 31, 32, 33, and 34, which are part of the protection circuit 30, serve as discharge paths. As a result, it is possible to suppress electrostatic discharge destruction of the circuit elements included in the circuit 10 and the circuit 20.

Further, the layout of the diodes 31, 32, 33, and 34, which are a part of the electrostatic discharge protection circuit 30, can be made common between the semiconductor substrate 40 and the semiconductor substrate 50.

The semiconductor device 4 according to the fourth embodiment has a configuration in which the laminated body 100 is replaced with the laminated body 400 in FIGS. 4 (A) and 4 (B).

5. Fifth embodiment FIG. 9 is a circuit diagram of the semiconductor device according to the fifth embodiment.

The semiconductor device 5 according to the fifth embodiment includes circuits 10, 20, 90, and electrostatic discharge protection circuits 110, 120, and 130. Further, the semiconductor device 5 is scheduled to receive the power supply potential from the external terminals VDD1, VDD2 and VDD3 and the ground potential from the external terminals VSS1, VSS2, VSS3.

The circuit 10 includes an internal circuit 11. The internal circuit 11 is configured to include a circuit element such as a transistor, and functions during normal operation by being supplied with a power supply voltage.

The circuit 10 may include an electrostatic discharge protection circuit 12. The electrostatic discharge protection circuit 12 is a protection circuit that serves as a discharge path for electric charges due to the input static electricity between the external terminal VDD1 and the external terminal VSS1, and protects the circuit elements included in the internal circuit 11 from electrostatic discharge destruction. It is provided for protection.

Circuit 10 includes a potential wire 13 that will be connected to the first potential. In the example shown in FIG. 9, the first potential is the ground potential supplied from the external terminal VSS1.

The circuit 20 includes an internal circuit 21. The internal circuit 21 is configured to include a circuit element such as a transistor, and functions during normal operation by being supplied with a power supply voltage.

The circuit 20 may include an electrostatic discharge protection circuit 22. The electrostatic discharge protection circuit 22 is a protection circuit that serves as a discharge path for electric charges due to input static electricity between the external terminal VDD2 and the external terminal VSS2, and protects the circuit elements included in the internal circuit 21 from electrostatic discharge destruction. It is provided for protection.

The circuit 20 includes a potential wiring 23 that will be connected to the first potential. In the example shown in FIG. 9, the first potential is the ground potential supplied from the external terminal VSS2.

The circuit 90 includes an internal circuit 91. The internal circuit 91 is configured to include a circuit element such as a transistor, and is supplied with a power supply voltage to function during normal operation.

Circuit 90 may include electrostatic discharge protection circuit 92. The electrostatic discharge protection circuit 92 is a protection circuit that serves as a discharge path for electric charges due to input static electricity between the external terminal VDD3 and the external terminal VSS3, and protects the circuit elements included in the internal circuit 91 from electrostatic discharge destruction. It is provided for protection.

Circuit 90 includes a potential wire 93 that will be connected to the first potential. In the example shown in FIG. 9, the first potential is the ground potential supplied from the external terminal VSS3.

The electrostatic discharge protection circuits 110, 120, and 130 are input, for example, between the external terminal VSS1 and the external terminal VSS2, between the external terminal VSS1 and the external terminal VSS3, between the external terminal VSS2 and the external terminal VSS3, and the like. It is a protection circuit that serves as a discharge path for electric charges due to static electricity, and is provided to protect the circuit elements included in the internal circuits 11, 21, and 91 from electrostatic discharge destruction. That is, when the circuits 10, 20, and 90 are operating normally, the potential wirings 13, 23, and 93 can be considered to be electrically separated from each other.

In the example shown in FIG. 9, the electrostatic discharge protection circuit 110 includes diodes 111 and diodes 112 having different orientations in parallel. Similarly, the electrostatic discharge protection circuit 120 is configured to include diodes 121 and diodes 122 having different orientations in parallel, and the electrostatic discharge protection circuit 130 has diodes 131 and diodes 132 having different orientations in parallel. It is configured to include.

Further, one end of the electrostatic discharge protection circuit 110 is connected to the potential wiring 13, one end of the electrostatic discharge protection circuit 120 is connected to the potential wiring 23, and one end of the electrostatic discharge protection circuit 130 is connected to the potential wiring 93. There is. Further, the other ends of the electrostatic discharge protection circuits 110, 120, 130 are connected to each other via the common wiring 140.

In addition, one or a plurality of diodes may be further provided in series in the path on the diode 111 side and the path on the diode 112 side, respectively. Similarly, one or more diodes may be further provided in series in the diode 121 side path and the diode 122 side path, respectively, and one or more diodes may be provided in the diode 131 side path and the diode 132 side path, respectively. Diodes may be further provided in series.

FIG. 10 is a schematic view for explaining the cross-sectional structure of the semiconductor device according to the fifth embodiment. Among the circuit elements shown in the circuit diagram of FIG. 9, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the internal circuit 91, the electrostatic discharge protection circuit 92, and the external terminal VDD1 , External terminal VDD2 and external terminal VDD3 are not shown. Further, FIG. 10 shows a cross-sectional structure of the laminated body 500 which is a part of the semiconductor device 5 according to the fifth embodiment.

The semiconductor device 5 according to the fifth embodiment is configured by laminating a semiconductor substrate 40, a semiconductor substrate 50, and a semiconductor substrate 150. The semiconductor substrate 40 is formed with wiring for electrically connecting the semiconductor layer 41 on which the circuit elements (transistors, diodes, etc.) included in the circuit 10 and the electrostatic discharge protection circuit 110 are formed, and the circuit elements and the through electrodes. It is configured to include the wiring layer 42 to be formed. The semiconductor substrate 50 includes a semiconductor layer 51 on which circuit elements (transistors, diodes, etc.) included in the circuit 20 and the electrostatic discharge protection circuit 120 are formed, and a wiring layer 52 on which wiring is formed. The semiconductor substrate 150 includes a semiconductor layer 151 on which circuit elements (transistors, diodes, etc.) included in the circuit 90 and the electrostatic discharge protection circuit 130 are formed, and a wiring layer 152 on which wiring is formed.

In the example shown in FIG. 10, the circuit element of the circuit 10 (not shown) and the electrostatic discharge protection circuit 110 are formed on the semiconductor layer 41 of the semiconductor substrate 40, and the potential wiring 13 and the wiring 60-9 are formed on the wiring layer 42. Has been done. Further, a circuit 20 (not shown) and a circuit element of the electrostatic discharge protection circuit 120 are formed on the semiconductor layer 51 of the semiconductor substrate 50, and the potential wiring 23 and the wiring 60-10 are formed on the wiring layer 52. Further, the circuit 90 (not shown) and the circuit element of the electrostatic discharge protection circuit 130 are formed on the semiconductor layer 151 of the semiconductor substrate 150, and the potential wiring 93 and the wiring 60-11 are formed on the wiring layer 152.

Further, in the example shown in FIG. 10, the semiconductor device 5 includes an electrode 71 and electrodes 72 and 73 configured as through electrodes. The potential wiring 13 is electrically connected to the external terminal VSS1 via the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 via the electrode 72. The potential wiring 93 is electrically connected to the external terminal VSS3 via the electrode 73.

The semiconductor device 5 according to the fifth embodiment includes a through electrode 61. The through silicon via 61 penetrates the semiconductor substrate 40 and functions as a part of the electrical path. Further, the through electrode 61 functions as a part of the common wiring 140 in the circuit diagram of FIG.

In the semiconductor device 5 according to the fifth embodiment, the potential wiring 13 of the circuit 10 passes through the electrostatic discharge protection circuit 110, and the potential wiring 23 of the circuit 20 passes through the electrostatic discharge protection circuit 120, and the potential of the circuit 90. The wiring 93 is electrically connected to the through electrode 61 via the electrostatic discharge protection circuit 130.

In the example shown in FIG. 10, the potential wiring 13 of the circuit 10 is connected to the electrostatic discharge protection circuit 110 and the wiring 60-9, and the potential wiring 23 of the circuit 20 is connected to the electrostatic discharge protection circuit 120 and the wiring 60-10. The potential wiring 93 of the circuit 90 is electrically connected to the through electrode 61 via the electrostatic discharge protection circuit 130 and the wiring 60-11.

According to the semiconductor device 5 according to the fifth embodiment, when an electrostatic voltage is applied between any two of the electrically separated potential wiring 13, the potential wiring 23, and the potential wiring 93, The electrostatic discharge protection circuit corresponding to each potential wiring and the through electrode 61 serve as a discharge path. As a result, it is possible to suppress electrostatic discharge destruction of the circuit elements included in the circuits 10, 20, and 90.

Further, according to the semiconductor device 5 according to the fifth embodiment, even if the number of electrically separated circuits increases, only the same number of electrostatic discharge protection circuits as the number of circuits are prepared, and the circuit elements are static. It is possible to suppress electric discharge destruction.

11 (A) and 11 (B) are schematic views for explaining the cross-sectional structure of the semiconductor device according to the fifth embodiment. FIG. 11A is an example of a configuration in which the laminate 500 described with reference to FIG. 10 is installed face-up on the package substrate 80 and molded with the mold resin 81. FIG. 4B is an example of a configuration in which the laminate 500 described with reference to FIG. 10 is installed face-down on the package substrate 80 and molded with the mold resin 81.

In FIGS. 11 (A) and 11 (B), the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the internal circuit 91, and the electrostatic discharge are similar to those in FIG. The discharge protection circuit 92, the external terminal VDD1, the external terminal VDD2, and the external terminal VDD3 are not shown.

In the example shown in FIG. 4A, the package substrate 80 is provided with external terminals VSS1, VSS2, and VSS3, and the electrode 71 and the external terminals VSS1 and the electrode 72 are provided via the wiring and the bonding wire inside the package substrate 80. And the external terminal VSS2, and the electrode 73 and the external terminal VSS3 are electrically connected to each other.

In the example shown in FIG. 4B, the package substrate 80 is provided with external terminals VSS1, VSS2, and VSS3, and the electrode 71 and the external terminal VSS1, and the electrode 72 and the external terminal are provided via the wiring inside the package substrate 80. VSS2, electrode 73 and external terminal VSS3 are electrically connected to each other.

The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the gist of the present invention.

The present invention includes a configuration substantially the same as the configuration described in the embodiment (for example, a configuration having the same function, method and result, or a configuration having the same purpose and effect). The present invention also includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. The present invention also includes a configuration that exhibits the same effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the present invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

For example, in the description of each embodiment, only the external terminal connected to each potential wiring has been described, but other external terminals such as an input terminal, an output terminal, and a control terminal may be included.

Further, in each embodiment, it is possible to have three or more semiconductor substrates to be laminated.

<figref num="1">The circuit diagram of the semiconductor device which concerns on 1st Embodiment.</figref><figref num="2">The schematic diagram for demonstrating the cross-sectional structure of the semiconductor device which concerns on 1st Embodiment.</figref><figref num="3">The schematic diagram for demonstrating an example of the structure of a through electrode.</figref><figref num="4">4 (A) and 4 (B) are schematic views for explaining the cross-sectional structure of the semiconductor device according to the first embodiment.</figref><figref num="5">The schematic diagram for demonstrating the cross-sectional structure of the semiconductor device which concerns on 2nd Embodiment.</figref><figref num="6">The schematic diagram for demonstrating the cross-sectional structure of the semiconductor device which concerns on 3rd Embodiment.</figref><figref num="7">The circuit diagram of the semiconductor device which concerns on 4th Embodiment.</figref><figref num="8">The schematic diagram for demonstrating the cross-sectional structure of the semiconductor device which concerns on 4th Embodiment.</figref><figref num="9">The circuit diagram of the semiconductor device which concerns on 5th Embodiment.</figref><figref num="10">The schematic diagram for demonstrating the cross-sectional structure of the semiconductor device which concerns on 5th Embodiment.</figref><figref num="11">11 (A) and 11 (B) are schematic views for explaining the cross-sectional structure of the semiconductor device according to the fifth embodiment.</figref>

Code description

1,2 Semiconductor devices, 10 circuits, 11 internal circuits, 12 electrostatic discharge protection circuits, 13 potential wiring, 20 circuits, 21 internal circuits, 22 electrostatic discharge protection circuits, 23 potential wiring, 30 electrostatic discharge protection circuits, 31 , 32,33,34 Diode, 40 Semiconductor board, 41 Semiconductor layer, 42 Wiring layer, 50 Semiconductor board, 51 Semiconductor layer, 52 Wiring layer, 60,60-1,60-2,60-3,60-4, 60-5,60-6,60-7,60-8 Wiring, 61,62 Through Diode, 70 Adhesive, 71,72,73 Electrode, 80 Package Board, 81 Mold Resin, 90 Circuits, 91 Internal Circuits, 92 Electrostatic discharge protection circuit, 93 potential wiring, 100 laminate, 110 electrostatic discharge protection circuit, 111,112 diode, 120 electrostatic discharge protection circuit, 121,122 diode, 130 electrostatic discharge protection circuit, 131,132 diode, 140 common wiring, 151 semiconductor Layer, 152 wiring layer, 200,300,400,500 laminate, VDD1, VDD2, VDD3, VSS1, VSS2, VSS3 External terminal