Synchronisation method for two electronic devices over a wireless connection, in particular over a mobile telephone network, as well as a system to implement said procedure

The present invention also relates to a method of synchronizing two wireless electronic devices connected by an electrical signal transmission link and a system performing this method, especially in a mobile phone network.

Current standards for mobile phone networks only allow frequency errors of less than one millionth of the signal frequency. This means that the two devices are almost perfectly synchronized. Conventionally, it is known that synchronization is directly performed on a frame and the clock is recovered at the time of reception. However, the frequency of the signal thus obtained exceeds the permissible error and the stability is insufficient.

<p><patcit num="1"><text>European Patent Application Publication No. 2003/088524</text></patcit></p>

<p> Therefore, the present invention has been made in view of the problems in the above-mentioned conventional synchronization method, and an object of the present invention is to overcome the drawbacks of the conventional synchronization method having insufficient frequency stability described in the background art. To provide a synchronization method.</p>

<p> The synchronization method according to the present invention, which has been made to achieve the above object, is characterized in that a clock is transmitted directly from one device to the other, and after recovery, this clock is used for synchronization of a receiving device. ..</p><p> The method preferably transmits the clock signal in one form. It is preferable that the method establishes a digital value of the pilot signal in the transmitting device, modulates the digital value on the pilot signal, and transmits the latter modulated by the digital value to the receiving device. The method preferably modulates a frame of other information on the pilot signal in addition to the digital value of the pilot signal.</p><p> Also, a system that implements the synchronization method according to the invention, made to achieve the above object, produces a reference frequency in which the receiver is basically controlled by a clock signal comparison means received by the reference signal. It is characterized by having a local oscillator component.</p><p> In the system, the receiving device includes an analog-digital converter, the control component of the local oscillator component includes a counter for a digital clock signal and a reference signal, and a means for comparing the two counters, and the local oscillator component. Is preferably controlled by a signal established from the results of the comparison device.</p><p> For high pilot frequency signals, it is preferred that the receiver comprises a mixer and its oscillator is controlled by a transmitter that produces a reference signal. In the system, it is preferable that the transmitting device includes means for modulating the clock pilot signal by the digital value of the clock signal, and the receiving device includes means for demodulating. According to yet another feature of the present invention, it is preferred that the means for modulating the pilot signal is to modulate a frame consisting of other information in addition to the digital value of the clock signal on the latter. ..</p>

<p> The synchronization method and system according to the present invention have an advantage that the signal frequency does not exceed the margin of error and maintains sufficient stability.</p>

<figref num="1">It is a figure which shows the structure of the wireless communication system to which this invention is applied.</figref><figref num="2">It is a figure which shows the arrangement of the clock frequency in the frequency spectrum of the bidirectional link provided in the wireless communication system by this invention.</figref><figref num="3">It is a figure of the 1st Embodiment of the clock synchronization apparatus by this invention.</figref><figref num="4">It is a figure of the 2nd Embodiment of the clock synchronization apparatus by this invention.</figref><figref num="5">It is a figure of the 3rd Embodiment of the clock synchronization apparatus by this invention.</figref><figref num="6">It is a figure of the 4th Embodiment of the clock synchronization apparatus by this invention.</figref>

Next, a specific example of the embodiment for carrying out the synchronization method according to the present invention will be described with reference to the drawings. FIG. 1 shows a communication system between mobile phone 1 and fixed telephone 2 via mobile phone network 3 and fixed network 4. In mobile phone network 3, communication is intended for communication with mobile phone 1, relay antenna 5, wireless communication link 6, base control station 8 called BSC (base station control) and communication center called MSC (mobile switching center). It is one of the base stations equipped with 9, and is performed through a wireless communication bay 7 called BTS (base transceiver system). The radio link between the relay antenna 5 and the radio communication bay 7 called the BTS bay comprises a box-shaped electronic device 12 connected to the relay antenna 5 and a box-shaped electronic device 13 connected to the BTS bay. There is. The transmission of signals between these two electronic devices is carried out by radio frequency signals, i.e. radio, as indicated by reference numeral 14. This type of system is described in International Patent Application Publication WO 2005/05107.

The present invention relates to the synchronization of two electronic devices 12, 13 to ensure a high degree of stability of the exchanged signal frequencies.

As shown in FIG. 2, a bidirectional link type radio communication link 6 consists of at least one path including a transmit channel EX and a receive channel RX, and usually has two bidirectional links EX and RX. It has a route. As can be seen from the figure, the EX paths of these routes on the one hand and the RX paths of these routes on the other hand are grouped together. The figure shows a group of three channels EX1, EX2, EX3, and a group of three receive channels RX1, RX2, RX3.

According to the present invention, the synchronization of the electronic devices 12 and 13 of the mobile phone network 3 is performed by directly transmitting the clock pilot signal H from one device to the other device, for example, from the electronic device 13 to the electronic device 12, and on the transmitting device. It is done by recovering the clock at the time of reception to synchronize the receiving device of. Such direct transmission from the clock is the clock between two channels EX and RX on a single-path link, and in the case of links with several paths shown in Figure 2, between two adjacent transmit channels. This is done by arranging the pilot signal H.

3 to 6 show some possibilities or embodiments of the method according to the invention, the step of transmitting the clock pilot signal H directly from the transmitter to the receiver, and in the receiver in the receive channel RX, respectively. It consists of steps to recover this.

According to the first embodiment of the present invention shown in FIG. 3, the clock pilot signal H is transmitted, for example, by the electronic device 13 and placed on the transmission channel EX by the method shown in FIG. And then, if applicable, a spare splitter 16 designed to split the frequency if the frequency is too high, and its output terminal 18 have a reference signal RS available and synchronized by the clock pilot signal H. It is received in an electronic device 12 equipped with a phase lock loop 17 having a large spectral purity. For this purpose, the phase lock loop 17 is controlled by the phase lock loop component 20, each of which has two inputs connected to a spare splitter 16 and the output of the local oscillator component 19, i.e. the output terminal 18 of the reference signal RS. It also has a voltage-controlled crystal oscillator known as the VCXO.

The device according to FIG. 3 provides a spare splitter. This is because the reference frequency at the output terminal 18 must not exceed several hundred MHz.

A third embodiment, which is a mixture of digital and analog techniques, is based on a device for clock pilot signal H and frequency counting. The device performing this method converts the pilot signal coming from the electronic device 13 and the position filter 22 in the transmission band to the analog-to-digital pilot signal by the method described above, as shown in FIG. It is equipped with an analog-to-digital converter 23 to perform and a programmable logical component 24 called an FPGA. The FPGA is controlled by a control component 26 of the type known as the DAC and is part of a loop with a local oscillator component 25 voltage controlled by a crystal called the VCXO type. The control component receives an instruction from the microprocessor 30 and its input is connected to the output of the FPGA component 24. The microprocessor can also be integrated within the FPGA. As can be seen from the figure, this FPGA component counts the signals coming from the first counter 27, which is designed to count the digital signals coming from the analog-digital converter 23, and the VCXO type local oscillator component 25. A second counter 28 designed as described above and a comparison circuit 29 comparing the results of the two counters 27 and 28, the frequency lock loop type output signal of which is a local oscillator component via circuit 26. In addition to the microprocessor 30 that commands the 25, the synchronized reference signal RS is available at the output 30 of the VCXO type local oscillator component 25.

This embodiment demonstrates the advantage of separating the pilot and reference frequency domains. If the FPGA component 24 only allows operation at frequencies lower than GHz, it passes through intermediate frequencies to increase the operating frequency.

FIG. 5 shows a device that recovers the synchronized reference signal RS at higher frequencies, i.e. higher than the typical operating frequency of FPGA components. In addition to the device shown in FIG. 4, the configuration of this device is incorporated between the mixer 32, which lowers the frequency of the clock pilot signal H, and the VCXO type local oscillator component 25, upstream from the filter 22. It is equipped with a VCO type second oscillator and an oscillator 33 including a phase lock loop.

The mixer 32, on the one hand, allows for easier filtering of signals from pilots, and on the other hand, allows operation at frequencies compatible with FPGA components. This method makes it possible to obtain standards with extremely high spectral purity and extremely good stability.

Another embodiment shown in FIG. 6 proposes an architecture that allows synchronization of both electronic devices with extremely high spectral purity standards while transmitting different information.

FIG. 6 illustrates this method. Note that the device architecture of the receiver corresponds to that of the embodiment according to FIG. However, in the electronic device 13, which corresponds to the transmitter, the clock pilot signal H is added to the FPGA component marked by 35, counted by the counter 36, and this value of the counter is modulated on the pilot and thus the amplitude modulation of the pilot. Is digitally transmitted to the receiving device 12 in the form of.

Upon reception, the pilot is replaced by the mixer 32 at a lower frequency level, which is not compulsory in the case of extremely fast computers. The modulated signal is then recovered in the demodulator 38 and the synchronization reference, the pilot counter value, is compared between the reference counter 28 generated by the VCXO component 25 and the FPGA component. By this comparison, a control signal is established and added to this VCXO type local oscillator component to correct the frequency of the local oscillator component.

According to this embodiment of the present invention, a predetermined number of bits of other information is added to the number of bits stored for this count result, plus the FPGA of the electronic device 13 corresponding to the transmitter in the frame indicated by 37. By including it in the component, it is possible to transmit other information in addition to the counter information from the synchronous pilot reference. This communication information written in the IC is separated from the digital value of the clock pilot signal H at 39 and is available at terminal 40. In this way, it is possible to transmit information such as alarms, control data, communication protocols between base stations and antenna devices, or any other protocol within a communication frame.

This embodiment allows for the stability of the clock pilot signal and complete relief from some of the communication parasites, as long as the frequency of the clock pilot signal is not involved in synchronization. Only the value of the counter due to the communication frame is involved. It should be noted that some frame sync signals also do not adversely affect stability. Since this method is based on the characteristics of digital signals, it is possible to perform coding that is resistant to data interference and infringement.

The present invention is not limited to the above-described embodiment. Various changes can be made without departing from the technical scope of the present invention.

It is useful to apply the present invention to the field of mobile phone communication.

5 Relay antenna 6 Wireless communication link 7 Wireless bay 12,13 Electronic device 19,25 Local oscillator components 23 analog-to-digital converter 27,28 counter 29 Comparison circuit 32 mixer 33 oscillator 37 frames 38 Demodulation means EX transmit channel H clock pilot signal RX receive channel RS reference signal