Method fo growing nanofin transistors

[Cross-reference to related applications] "Nanowire Transistor With Surrounding Gate" USApplication Serial No. 11 / 397,527 (filed April 04, 2006), "Grown Nanofin Transistors" USApplication Serial No. 11 / 397,430 (filed April 04, 2006), "Etched Nanofin Transistors" Claim the benefit of the priority date of "USApplication Serial No. 11 / 397,358 (filed April 04, 2006)," DRAM With Nanofin Transistors "USApplication Serial No. 11 / 397,413 (filed April 04, 2006) here. To do. These applications are included in this disclosure by this reference.

This application is also related to US patent applications assigned to the assignees of the invention, which are listed below, and the entire of these applications are included in this disclosure by reference herein. "Vertical Tunneling Nano-Wire Transistor "US Application Serial No. 11 / 210,374 (filed August 25, 2004)," Ultra-Thin Body Vertical Tunneling Transistor "US Application Serial No. 11 / 215,468 (filed August 29, 2005), and "DRAM Tunneling Access Transistor" USApplication Serial No. 11 / 219,085 (filed August 29, 2005).

[Technical field] The present disclosure relates to semiconductor devices in general, and particularly to tunneling transistors with channels sublithographic.

The semiconductor industry market is being driven by the demand to reduce the size of devices such as transistors and increase the element density on the substrate. Product goals include reducing power consumption, improving performance, and downsizing. If the length of the transistor is shortened while allowing current to pass when the transistor is turned off, the amount of electricity stored will be deprived and the performance will be affected. When the gate-source voltage of a metal oxide semiconductor (MOS) transistor falls below the voltage threshold, it falls into the subthreshold region. Its characteristic is that the drain current with respect to the gate-source voltage changes exponentially. As the technique expands and contracts, the subthreshold leakage current increases exponentially, accounting for most of the total power dissipation. This is a major problem for designers of portable (handheld) devices, where battery life is important for portable devices. And the issue of minimizing the amount of power consumption while exhibiting sufficient performance is becoming more and more important. Also in DRAM, leakage current is a serious problem because it reduces the charge retention time in the capacitor cell.

Figure 1 shows the general tendency and correlation of various parameters of the device to be scaled by a coefficient k. As an example, in traditional transistor structures, the junction depth needs to be less than the channel length. Then, for the transistor 100 shown in Figure 1, the junction depth 101 should be in the order of hundreds of angstroms, given that the proper length of the channel length 102 is 1000 Å. Such shallow joints are difficult to make with traditional injection and diffusion methods. In addition, if the channels are heavily doped, the short-channel effect will inevitably be suppressed. These short-channel effects include drain-induced barrier lowering and threshold voltage roll. There are off (roll-off) and subthreshold transmission. When such ultra-high concentration doping is performed, leakage increases and carrier mobility decreases. Due to the low threshold voltage, sufficient overdrive and reasonable switching speed can be achieved. However, as shown in FIG. 2, when the threshold value is small, the subthreshold leakage current becomes considerably large. Therefore, the performance improvement that was sought from the shorter channels is offset by the low carrier mobility and the magnitude of leakage due to the high concentration doping.

Figure 3 shows the ideal down-threshold gradient of 60 mV / decade for traditional planar CMOS transistors and the digits of 120 mV / decade to 80 mV / decade for traditional planar CMOS transistor structures with short-channel effects. The comparison with the subthreshold gradient of is drawn. This figure shows how difficult it is to control and reduce subthreshold leakage current in traditional nanoscale planar CMOS transistor techniques. This problem is further exacerbated by the low power supply voltages used in nanoscale CMOS circuits-these low power supply voltages are now in the 2.5V digit, and will eventually be even lower, in the 1.2V range. Will go to. To obtain a good Ion / Ioff ratio, the subthreshold leakage current should be at least eight times (8 decades) lower than the transistor current when the transistor is turned on. That being said, the 1.2V power supply does not provide sufficient voltage amplitude to achieve both high current and low threshold leakage in traditional planar equipment. To turn on the transistor, the threshold voltage VT It is necessary to overdrive the voltage with sufficient voltage to exceed the above. And in order to cut off the leakage below the threshold value of the transistor, it is necessary to have several times the threshold voltage gradient (shown as about 100 mV / decade in Fig. 3).

In some designs proposed to address these issues, ultra-thin A transistor having bodies) or a transistor having the same size of the surface space charge region as the other dimensions of the transistor have been reduced is used. A dual-gate or double-gate transistor structure has also been proposed for the reduction of transistors. In the industry, a "dual gate" usually refers to a transistor with a front gate and a back gate that can be driven by separate, independent voltages. And "double gate" refers to a structure in which both gates are driven at the same potential. Since a dynamically fluctuating threshold voltage can be obtained in the transistor connected to the gate substrate, the threshold can be set to be low when the transistor is on and low when the transistor is off. FinFET is an example of a double gate device structure. A "Tri-gate" structure and a surrounding gate structure have also been proposed. In a "Tri-gate" structure, the gates are on three sides of the channel. In the sounding gate structure, the gate surrounds (surrounds) the transistor channel. With the sounding gate structure, desirable control can be performed over the entire transistor channel, but it has been difficult to actually create such a structure.

FIG. 4 shows a dual-gate MOSFET with a drain, a source, and front and back gates separated from the semiconductor substrate by a gate insulator. Furthermore, FIG. 3 also shows the electric field generated from the drain. The characteristic group of dual-gate MOSFETs and / or double-gate MOSFETs is superior to that of conventional bulk silicon MOSFETs. This is because, compared to a single gate, the two gates effectively shield the electric field generated from the source end of the channel of the drain electrode. The sounding gate can more effectively shield the electric field generated from the source side of the drain electrode. FIG. 5 roughly shows the improved subthreshold characteristics of a dual-gate MOSFET, a double-gate MOSFET, or a sounding gate MOSFET in comparison with the subthreshold characteristics of a conventional bulk silicon MOSFET. Subthreshold currents decrease faster when dual-gate and / or double-gate MOSFETs are turned off.

For MOSFETs with channel dimensions below the lithography reference dimensions (such as FinFETs), the subthreshold gradient can be set to 60 mV / decade, which is smaller than the subthreshold gradient associated with large and traditional planar MOSFETs. However, there is still a demand for new equipment structures that can further reduce subthreshold leaks.

The subthreshold gradient of the tunneling transistor can be near zero. This specification discloses a vertical tunneling transistor with a gate surrounding a transistor body having a width less than the photolithographic dimension. A thin tunneling transistor with such a sounding gate can be used to reduce subthreshold leakage in CMOS circuits. In various embodiments, whether the crystalline nanofin is grown from the amorphous structure formed on the substrate, or the crystalline substrate is etched so that the crystalline nanofin is defined from the crystalline substrate. Alternatively, a substrate having a lithography standard size or less is obtained by either a method of growing crystalline nanowires from an amorphous structure formed on the substrate. In various embodiments, the sidewall spacer method is used to achieve less than or equal to the lithography reference dimensions.

The various embodiments relate to transistors. Various embodiments of transistors have a cross-sectional width that is less than or equal to the lithographic reference dimension in the first direction and a minimum feature in the second direction that is orthogonal to the first direction. Nano Fins that have a cross-sectional width corresponding to size), the sounding gate insulator that surrounds the nano Fins, and the sounding that sandwiches the sounding gate insulator around the nano Fins. Includes gates and. The first source / drain region with the first conductive form at the bottom of the nanofin and the second source / drain region with the second conductive type at the top of the nanofin. A channel region running vertically between the first source / drain region and the second source / drain region is defined. Embodiments of various transistors include a crystalline column that is formed on the surface of the substrate and has a cross-sectional dimension that is less than or equal to the lithographic reference dimension in at least one direction, and a sounding gate that surrounds the crystalline column. Includes an insulator and a surrounding gate with the surrounding gate insulator sandwiched around a crystalline column. By using this crystalline column, a channel region running vertically between a first source / drain region having a first conductive type and a second source / drain region having a second conductive type. Is obtained.

Various embodiments relate to methods of forming transistors. Various embodiments of this method have a cross-sectional width that is less than or equal to the lithography reference dimension in the first direction and that corresponds to the smallest feature dimension in the second direction that is orthogonal to the first direction. Form such nanofins. Also, a salounding gate insulator is formed around the nanofin, and a salounding gate is formed around the nanofin with the salounding gate insulator sandwiched between them. By using this nanofin, a channel region running vertically between the first source / drain region having the first conductive type and the second source / drain region having the second conductive type can be created. can get. In various embodiments, nanofins are formed by forming amorphous semiconductor columns on a substrate and then recrystallizing them. In various embodiments, the crystalline substrate is etched with a plurality of grooves to form nanofins from the substrate.

In various embodiments according to the method, crystalline columns having cross-sectional dimensions that are less than or equal to the lithography reference dimensions in at least one direction are formed. This formation includes forming such crystalline columns by forming amorphous semiconductor columns on a substrate and then recrystallizing them. The salounding gate insulator is formed around the crystalline column, and then the salounding gate is formed around the crystalline column with the salounding gate insulator sandwiched between them. By using such a crystalline column, it runs vertically between the first source / drain region having the first conductive type and the second source / drain region having the second conductive type. The channel area is obtained.

These other aspects, embodiments, effects, and features will become apparent from subsequent descriptions and reference drawings on this subject.

In the following detailed description, reference is made to an accompanying drawing which shows as an example a specific group of embodiments and embodiments in which the subject can be implemented. These embodiments are described in sufficient detail to the extent that those skilled in the art can implement the subject matter. The various embodiments of the subject do not necessarily have to be exclusive to each other, and aspects of one embodiment may be combined with aspects of another embodiment. Other embodiments may be utilized, and structural, logical, and electrical changes can be made without departing from the scope of the subject matter. In the following description, the terms "wafer" and "substrate" are synonymous and generally refer to any structure in which an integrated circuit can be created, and an integrated circuit is being manufactured. It also refers to such structures at various stages of. Both terms include doped and non-doped semiconductors, epitaxial layers of semiconductors on supporting semiconductors or insulating materials, and thus include other structures known in the art. The term "horizontal" is defined in this application to mean a conventional plane or plane parallel to the surface of a wafer or substrate, with respect to the orientation of the wafer or substrate. It doesn't depend. The term "vertical" refers to the direction orthogonal to the "horizontal" defined above. "on" ("above", "attached"), "side" ("horizontal"), "higher" ("high"), "lower" ("low"), "over" ("above") "," Covered "), and" under " Prepositions such as ("below", "below") are defined for a conventional plane or surface located on the top surface of a wafer or substrate, depending on the orientation of the wafer or substrate. Absent. Therefore, the following detailed description should not be taken in a limited sense. And the scope of the present invention is defined only by the accompanying claims and the full range of equal features embodied by the claims.

The subject relates to tunneling transistors with sounding gates and channels that are less than or equal to the lithographic reference dimensions. Various embodiments relating to the tunneling transistor structure and the method for forming them will be described below. Examples of such a structure include a growth type nanowire tunneling transistor, a growth type nanofin tunneling transistor, and an etching type nanofin tunneling transistor. The following also describes the layout of nanofin arrays, examples of CMOS logic circuits, and high-level equipment and systems.

[Tunneling transistor] Figure 6 shows the transistor structure 603. The transistor structure 603 has a channel 604 that is vertical and less than or equal to the lithographic reference dimensions, a sounding gate 605, and the same conductive source / drain region 606 and source / drain region 607. There is. As such a transistor, nanofin transistors such as those described in US Application Nos. 11 / 397,430 (filed April 04, 2006) and 11 / 397,358 (filed April 04, 2006) may be used. Alternatively, as such a transistor, US Application No. Nanowire transistors such as those described on 11 / 397,527 (filed April 04, 2006) may be used. The sounding gate 605 is placed with the sounding gate insulator 608 sandwiched around the substrate or channel 604. By doping this substrate, a conductive wire 609 that electrically connects to the source / drain region 606 at the bottom can be formed on the substrate.

FIG. 7 shows a channel, a sounding gate, and a plurality of different conductive source / drain regions, which are vertical and less than or equal to the lithography reference dimensions, according to various embodiments of the subject. The transistor structure with it is drawn. The embodiments shown are in a silicon substrate or N.⁺It is formed in the well. In another embodiment, other conductive dope may be applied to the substrate.

Like the transistor shown in Fig. 6, the conventional N on the board⁺Formed the source area, but yes Instead, in the first source / drain area 706 of the subject, P⁺Dope. Furthermore, the source wiring 709 that connects the first source / drain region 706 to other elements in the circuit is also P.⁺Dope is applied.

A lightly doped thin p-type substrate 704 is formed on top of the first source / drain region 706. In some embodiments, a 0.1 micron technique is used in performing this formation so that the height of the transistor is in the range of about 100 nm and the thickness is in the range of 25 nm to 50 nm. In another class of embodiments, other heights and / or other thickness ranges may be used.

N⁺A second doped source / drain region 707 is formed on the top of the silicon substrate 704. By forming a contact 710 in the second source / drain region 707, the second source / drain region of the transistor can be connected to other elements of the electronic circuit. The site of this connection may be metal or some other material.

A gate insulation layer 708 is formed around the thin substrate 709. As the insulator, an oxide may be used, or some other kind of dielectric material may be used. In some embodiments, the oxidation of the semiconductor substrate produces such an insulator. For example, in one embodiment, a silicon oxide gate insulator is provided around the column by the step of thermally oxidizing the column.

The control gate 705 is formed around the insulation layer 708. As is well known in the art, the control gates can be properly biased to form N channels within the channel region between the first source / drain region 706 and the second source / drain region.

P⁺It is also possible to implement a first source / drain region of type. P⁺The amount to dope is N⁺There is no need to mask the top of the pillar as it will always be less, and the pillar will be N⁺Will remain. P under the side wall of the obtained pillar⁺There is an area, P at the top⁺There is an area. The pillars are thin, so P⁺The areas will diffuse and merge under the pillars. In certain embodiments, the transistor structure comprises a growth or deposition gate insulator and a salounding gate made by side wall etching.

8 and 9 are energy band diagrams for the behavior of the transistor in FIG. The upper line of each figure shows the energy of the conduction band, and the lower line shows the energy of the valence band. FIG. 8 is an energy band diagram showing the electrical behavior of the tunneling transistor of FIG. 7 when the transistor gate is not biased according to various embodiments of the present subject. In this figure, the channel and N⁺The second source / drain region 811 is, as well as P⁺The first source / drain region 812 is shown. Under non-conductive conditions, there is a large barrier 813 between the source / drain regions. FIG. 9 is an energy band diagram showing the electrical behavior of the tunneling transistor of FIG. 7 when biasing the transistor gate according to various embodiments of the subject. The electrical behavior of the transistor is based on a MOS gated pin diode. By biasing the gate, it is possible to create conductive conditions that induce the formation of electron channels once the electron concentration decreases. Tunnel junction 914, P of this channel⁺Form on the side. By biasing the drain, the band can be bent so that the N-type region conductive band is below the valence band crease in the source region. The electrons then tunnel from the source valence band to the induced n-type channel region, thus obtaining a drain current. Tunneling cannot occur until the creases in the conductive band of the channel are lowered below the valence band of the source. Therefore, the turn-on characteristic is very sharp, and as shown in FIG. 10, the subthreshold gradient approaches the ideal value for a tunneling transistor, that is, 0 mV / decade.

FIG. 10 is a plot of the drain current vs. tunneling transistor gate-source voltage for the tunneling transistor of FIG. 7 over various embodiments of the subject, showing subthreshold leakage current. In this plot, the subthreshold current 1015 shows a very tight gradient "S", which is due to biasing in the tunneling transistor embodiments. The vertical axis of FIG. 10 is the log scale, and the horizontal axis of VGS is linear.

[Method of forming channels that are vertical and less than or equal to the lithography standard dimensions] In the following description, a group of embodiments of silicon transistors will be referred to. Those skilled in the art can use other semiconductors to form tunneling transistors with channels that are less than or equal to the lithographic reference dimensions, after reading and understanding this disclosure. You will understand.

[Growth method of nanowire substrate] 11A-11H depict the process of growing a nanowire substrate to obtain vertical channels for tunneling transistors, according to various embodiments of the subject. In the steps shown, crystalline nanorods with salounding gates are formed. The steps shown are described in "Nanowire Transistor With Surrounding Gate" US Application No. 11 / 397,527 (filed April 04, 2006, incorporated herein by reference).

Figure 11A shows the first layer 1116 on board 1117. Multiple holes 1118 are made in the first layer 1116. The holes in this layer can be determined by etching the first layer. In various embodiments, when a plurality of holes 1118 are drilled into the silicon nitride layer 1116 on the silicon substrate 1117, the holes are made to penetrate the silicon nitride layer and reach the silicon substrate. In the embodiments shown, the dimensions of those holes are made to correspond to the minimum feature dimensions. The center of each hole corresponds to the desired position of the nanowire transistor. The center-to-center spacing for rows and columns of an array of nanowire transistors can be set to 2F.

After the holes are etched into the first layer and drilled, a layer of oxide is provided on top of the first layer. In various embodiments, silicon oxide is formed on the silicon nitride layer. In some class of embodiments, silicon oxide is deposited by a chemical vapor deposition (CVD) step.

FIG. 11B shows the structure after the oxide was anisotropically etched to leave the oxide side wall 1119 attached to the side of the pore. This oxide side wall 1119 has the effect of reducing the dimensions of the resulting pores. Flatten the resulting structure. In the 100 nm technique, for example, the oxide sidewalls reduce the pore size to about 30 nm. In this example, the thickness of the substrate region of the transistor is considered to be an order of one-third of the feature dimensions. In some class of embodiments, a chemical and mechanical polishing (CMP) step is used to flatten the structure.

Figure 11C shows a thick layer of amorphous semiconductor material 1120 overlaid on the resulting structure. This amorphous material fills the holes defined by the side wall 1119. In various embodiments, amorphous silicon is used as the amorphous material for deposition. Figure 11D depicts the resulting structure being flattened (eg with CMP), with the amorphous semiconductor material remaining only in the holes.

FIG. 11E shows the structure obtained after removing the side walls (such as the side walls made of silicon oxide). This structure is heat treated to crystallize an amorphous semiconductor 1120 (such as amorphous silicon) using known techniques such as solid phase epitaxy (SPE) and shake the crystalline nanorods (1120-C). Make a). Amorphous semiconductor columns 1120 are used with semiconductor wafers (such as silicon wafers). It is connected and therefore the crystal growth of the amorphous semiconductor column 1120 is seeded by the crystals in the wafer. Crystal formation by the SPE process is shown by arrow 1121 in Figure 11E.

Figure 11F depicts the structure after removing the first layer (such as silicon nitride), where crystalline nanorods 1120-C remain so as to rise from the substrate surface. After that, the gate insulator 1122 is put on the obtained structure. In some embodiments, a thermal oxidation step is used to form the gate insulator. That is, in the case of an embodiment in which the wafer is a silicon wafer and the nanorods are crystalline silicon nanorods, the gate insulator is silicon oxide. Other gate insulators, such as High K insulators, may be used.

The structure after the gate material 1123 is attached to the side wall of the crystalline nanorod 1120-C is shown in FIG. 11G as a side view and in FIG. 11H as a cross-sectional view taken along the line 11H-11H in FIG. 11G. .. In some embodiments, the gate material is deposited and then the resulting structure is etched to leave only the gate material attached to the side walls of the nanorods. In various embodiments, polysilicon is used as the gate material. The height of the column determines the channel length of the transistor, and the height of this column can be smaller than the minimum lithographic dimensions. In the various embodiments, the channel length is on the order of about 100 nm. Nanorods with such wraparound gates can be used to create nanowire transistors with surrounding gates. To form a single transistor or transistor array, "Nanowire Transistor With Surrounding Gate" US The method described in Application No. 11 / 397,527 (filed on April 04, 2006) may be followed.

[Growth method of nano Fin substrate] 12A-12L depict the process of growing a nanofin substrate to obtain vertical channels for tunneling transistors, according to various embodiments of the subject. The steps shown are described in "Grown Nanofin Transistors" US Application No. 11 / 397,430 (filed April 04, 2006, incorporated herein by reference).

What is disclosed here is a nano-Fin transistor and a construction method for producing a single-crystal silicon nano-Fin transistor by recrystallizing an amorphous silicon nano-Fin in the vertical direction on a substrate. Aspects of the subject provide nano-Fin transistors with vertical channels, which are the first source / drain region at the bottom of the Fin and the second source / drain at the top of the Fin. Has an area.

The top view of the semiconductor structure 1224 is shown in FIG. 12A, and the cross-sectional view along the line 12B-12B is shown in FIG. 12B. The semiconductor structure 1224 has a silicon nitride layer 1225, holes 1226 in the silicon nitride layer 122, and side wall spacers 1227 made of amorphous silicon along the walls of the holes. The holes are formed by etching the silicon nitride layer, and then the amorphous silicon is deposited and anisotropically etched to leave only the holes attached to the side walls. When etching the holes 1226, penetrate the silicon nitride layer 1225 to reach the silicon wafer or substrate 1228.

The top view of the structure 1224 after removing the silicon nitride layer is shown in FIG. 12C, and the cross-sectional view along the line 12D-12D is shown in FIG. 12D. As shown, after removing the silicon nitride layer, the side wall 1227 will remain as a self-supporting, narrow region of amorphous silicon. The resulting self-supporting silicon pattern is also called a "race track" pattern because it is roughly an elongated rectangle. The line width is determined not by the protection (masking) process / lithography process but by the thickness of amorphous silicon. In the various embodiments, for example, the thickness of amorphous silicon is about 20 nm to 50 nm. A solid phase epitaxial (SPE) growth process can be used to recrystallize these self-contained, narrow regions of amorphous silicon. SPE Growth Worker The process involves annealing, which triggers the crystallization of amorphous silicon in the structure from the interface with the silicon substrate 1228. This interface functions as a seed for crystal growth, and crystallization proceeds by crawling up the rest of the self-supporting narrow region of silicon.

FIG. 12E shows a top view of the structure 1224 after the mask layer has been applied. The shaded area is the etched part, and the self-supporting Fin made of crystalline silicon remains. Regarding the pattern formed by the self-supporting Fin 1229, Fig. 12F shows the top view, and Fig. 12G shows the cross-sectional view along the line 12G-12G. The embedded dope region 1230 serves as the primary source / drain region. In various embodiments, these embedded dope regions can be patterned to create conductive wires along the rows or columns of the Fin array.

Figure 12H shows a top view of the structure, where Fin is surrounded by gate insulator 1231 and gate 1232. This gate insulator may be made by depositing or by some other method. For example, silicon oxide can also be formed on silicon Fin using a thermal oxidation step. Any gate material can be used as the gate, for example polysilicon or metal can be used. By depositing and anisotropically etching the gate material, the gate material is left only on the side wall of the Fin structure with the gate insulator. The wiring can be oriented in either the "x direction" or the "y direction".

Structure in Figure 12H 1233 is backfilled with insulator 1233, and the gate wiring 1234 is made in the "x direction" (direction along the longitudinal side of Fin). The cross-sectional views along the above are shown respectively. In various embodiments, the structure is backfilled with silicon oxide. Make a groove in the backfilled insulator so that it runs along the side of the Fin. Then make a gate wire in the groove. In the various embodiments, one gate line runs along one side of the Fin and connects to the sounding gate of the Fin structure. In some embodiments, the first gate line is made on the first side of the Fin and the second gate line is made on the second side of the Fin. Gate wiring materials (such as polysilicon or metal) can be deposited and anisotropically etched to leave only on the sidewalls. The gate wiring material is preferably connected to the Fin's sounding gate. In various embodiments, the gate material and the gate wiring material are etched so that the gate and the gate wiring are recessed below the top of the fin. The entire structure can be backfilled with an insulator (such as silicon oxide) and then flattened so that only oxides remain on the surface. The tops of these columns or fins are exposed using etching. Traditional techniques can be used to create a second source / drain region by injecting it into the top of the Fin and also to create a metal contact to the drain region. For example, the metal wiring can be run in the "x direction" and the embedded source wiring can be run in the direction perpendicular to the paper in the figure.

Regarding the state where the structure is backfilled with insulator and the gate wiring is made in the "y direction" (direction along the short side of Fin), the top view is shown in Fig. 12K and the line 12L-12L is shown in Fig. 12L. The cross-sectional views are shown respectively. The groove opens the side of the Fin along the "y direction". Gate wiring material 1234 (such as polysilicon or metal) can be deposited and anisotropically etched to connect to the gate on the Fin, leaving only on the side walls. In various embodiments, the gate material and the gate wiring material are etched so that the gate and the gate wiring are recessed below the top of the fin. The entire structure can be backfilled with insulator 1233 (such as silicon oxide) and then flattened so that only the backfill insulation remains on the surface. It is also possible to then etch the contact openings and drain-doped regions to the top of the column and the metal contacts 1236 to the drain region 1235 and drain regions injected therein using traditional techniques. For example, run the metal wiring in the direction perpendicular to the paper in the figure, and the embedded source wiring 1230. Can be run in the "x direction". Implantable source / drain is patterned and injected prior to the deposition of amorphous silicon. FIG. 12L presents one of the finished Fin structures, which has a drain / source region, a recessed gate, and a source / drain region wiring. Since such a nanofin FET can have a large W / L ratio, it is possible to pass a large amount of current as compared with a nanowire FET.

[Nano Fin substrate etching method] What is disclosed here is a nano-Fin transistor and a construction method in which a substrate or a wafer is etched to obtain nano-Fin and the nano-Fin is used to produce a single crystal nano-Fin transistor. In the following detailed description, with reference to the accompanying drawings, specific embodiments and embodiments in which the subject can be implemented are shown as illustrations. Those skilled in the art will know how to make nanofins using other semiconductors after reading and understanding this disclosure. Aspects of the subject provide nano-Fin transistors with vertical channels, which are the first source / drain region at the bottom of the Fin and the second source / drain at the top of the Fin. Has an area.

In some embodiments, silicon nitride is deposited on a silicon wafer and then the silicon nitride is covered with a layer of amorphous silicon (a-silicon). FIG. 13A shows a side view of the structure 1337 after the holes 1338 have been defined in amorphous silicon 1339 to form the side wall spacers 1340. The holes 1338 extend within the silicon nitride layer 1341, and the silicon nitride layer 1341 is located on the substrate 1342 (such as a silicon wafer). In various embodiments, side wall spacers are made by oxidizing amorphous silicon. FIG. 13B shows a side view of structure 1337 after being covered with a thick layer of amorphous silicon 1339. Figure 13C shows structure 1337 after flattening at the point indicated by arrow 1344. Such flattening is performed at least to a height at which the oxide on top of the amorphous silicon can be removed. For example, a chemical / mechanical polishing (CMP) process can be used to flatten the structure. Thus, the surface-exposed oxide 1340 An elongated rectangular pattern made of remains. This pattern is also called the "race track" pattern. The line width of this pattern is determined not by the protection (masking) process / lithography process but by the thickness of the oxide. In the various embodiments, for example, the oxide thickness is from about 20 nm to 50 nm.

Figure 13D depicts a mask over the track pattern, which selectively covers the oxide portion and exposes the rest of the oxide. This exposed portion of the oxide is shaded and will be removed. Amorphous silicon is removed by performing an etching process (potassium hydroxide KOH etching, etc.). The oxide or part of the oxide remaining after the protection and etching steps shown in FIG. 13D will protect the nitride during the etching step. After removing the amorphous silicon, the nitride 1341 can be etched and the silicon anisotropic etching can be used to etch the wafer 1342 to a predetermined depth under the nitride layer. By protecting the local area of silicon from etching with a nitride pattern, silicon Fin 1343, made of silicon, can be obtained as if it were protruding from the now lowered surface of a silicon wafer (see Figure 13E). The top view of the structure after injecting the dopant into the top of Fin and the groove at the bottom of Fin is shown in FIG. 13F, and the side view is shown in FIG. 13G, respectively. As shown in Figure 13F, the dopant injected into the groove causes the conductive wire 1344. (Source line, etc.) is created. In addition, a source / drain region is formed by the dopant injected into the bottom or bottom of the Fin. Fins are so thin that if you dope the grooves, they will be completely diffused to the bottom of the fins. These pieces may be arranged in the row direction or in the column direction.

Figure 13H depicts structure 1337 after gate insulation 1345 is formed around Fin 1343 and gate material 1346 is formed around Fin 1343 with the gate insulation 1345 in between. .. In some embodiments, for example, a thermal oxidation step is used to oxidize silicon Fin. In various embodiments, polysilicon or metal can be used as the gate material 1346.

For the first embodiment of the array, FIG. 13I shows a top view and FIG. 13J shows a cross-sectional view along line 13J-13J. Backfill structure 1337 with insulator 1347 (such as oxide) and then make a groove beside the Fin. Gate wiring material 1348 (such as polysilicon or metal) can be deposited and anisotropically etched to connect to Fin's sounding gate 1346, leaving only where it attaches to the side wall. The gate material and gate wiring material can be etched and recessed below the top of the fin. The entire structure can be backfilled with oxides and then flattened so that only oxides remain on the surface. It is also possible to then etch the contact openings and drain-doped regions to the top of the column and the metal contacts to the drain and drain regions injected therein using traditional techniques. In this case, the metal wiring can be run in the "x direction" and the embedded source wiring 1349 can be run in the direction perpendicular to the paper in the figure.

For the second embodiment of the array, FIG. 13K shows a top view and FIG. 13L shows a cross-sectional view along the line 13L-13L. Structure 1337 is backfilled with insulator 1347 (such as oxide) with grooves along the "y direction" beside Fin 1343. Gate wiring material 1348 (such as polysilicon or metal) can be deposited and anisotropically etched to connect to the gate on the Fin, leaving only where it is attached to the side wall. The gate material and gate wiring material can be etched and recessed below the top of the fin. The entire structure can be backfilled with an insulator (such as an oxide) and then flattened so that only the oxide remains on the surface. It is also possible to then etch the contact openings and drain-doped regions to the top of the column and the metal contacts to the drain and drain regions injected therein using traditional techniques. In this case, the metal wiring can be run in the direction perpendicular to the paper in the figure, and the embedded source wiring can be run in the "x direction".

In both the first and second embodiments of the array, the implantable source / drain can be patterned and injected prior to the formation of the sounding gate insulator and the sounding gate. Figure 13L shows one of the finished Fin structures, which are drain / source area 1350 and drain / source area 1351, recessed gate 1346, and source / drain area wiring 1349. And have. Since such a nanofin FET can have a large W / L ratio, it is possible to pass a large amount of current as compared with a nanowire FET.

The processes shown in FIGS. 11A to 11H, 12A to 12L, and 13A to 13L can be roughly represented by a flow chart, and examples are shown in FIGS. 14 and 15. FIG. 14 shows a method of forming a tunneling nanoFin transistor according to various embodiments of the subject. In the embodiment shown, the nanofin is formed at 1452 so that the cross-sectional area of the nanofin is equal to or less than the lithographic reference dimension. A channel running in the vertical direction will be defined in the nanofin. The formation of the nanofins can be carried out by growing the crystalline nanofins as shown in FIGS. 12A to 12L, or as shown in FIGS. 13A to 13L. It may be done by etching the nanofin and determining the nanofin. In 1453, the first source / drain area is created at the bottom edge of the column. This first source / drain region has a first conductive type, eg P⁺Has an area. The formation of the first source / drain region can be performed prior to the formation of nanofins. It is also possible to create a first source / drain region after the formation of nanofins. The reason is that the nanoFin is so thin that the injected dopant can completely diffuse below the nanoFin. In 1454, a salounding gate insulator is built around the nanofin, and then the salounding gate is built around the nanofin with the sounding gate insulator in between. In 1455, a second source / drain region is formed at the apex of the nanofin. This second source / drain region is a second conductive type (eg N) that is different from the first conductive type.⁺). The first source / drain region is the second conductive type (N).⁺), And the second source / drain region is the first conductive type (P)⁺) May have.

FIG. 15 shows a method of growing a transistor body below the lithographic reference dimensions for a tunneling transistor according to various embodiments of the subject. In 1556, crystalline columns are grown from an amorphous semiconductor on a substrate so that their cross-sectional area is less than or equal to the lithographic reference dimensions. A channel running in the vertical direction will be defined in the crystalline column. This pillar may be a nanowire as shown in FIGS. 11A to 11H, or may be a nanofin as shown in FIGS. 12A to 12L. In 1557, the first source / drain area is created at the bottom edge of the column. This first source / drain region has a first conductive type, eg P⁺Has an area. The formation of the first source / drain region can be performed prior to the formation of crystalline columns. It is also possible to create a first source / drain region after the formation of crystalline columns. The reason is that the columns are so thin that the injected dopant can be completely diffused below the columns. In 1558, the sounding gate insulator is made around the pillar, and then the salounding gate is made by sandwiching the sounding gate insulator around the pillar. In 1559, a second source / drain region is formed at the apex of the column. This second source / drain region is a second conductive type (eg N) that is different from the first conductive type.⁺). The first source / drain region is the second conductive type (N).⁺), And the second source / drain region is the first conductive type (P)⁺) May have. A single transistor or transistor array is formed.

[Nano Fin Array] FIG. 16 is a top view layout of the nanofin for an array of tunneling nanofin transistors across various embodiments. In this figure, the side wall spacer 1660 It shows two "competition paths" made of, and also depicts a part of the side wall spacer removed by etching. Holes are used to make the side wall spacer competition path the minimum feature dimension (1F). The width of the mask piece 1661 is the minimum feature dimension (1F), and the mask piece 1661 The distance between them is also the minimum feature dimension (1F). In the layout shown, the distance between the centers of the rows of nanofins is approximately 2F, and the distance between the centers of the rows of nanofins is approximately 1F. Also, as shown in FIG. 16, since the nanofin is made from the side wall spacer attached to the wall of the hole, the distance between the centers of the first row and the second row is from 1F in length to nanofin. The length is slightly shrunk (1F-ΔT) by the amount corresponding to the thickness of. The distance between the centers of the second row and the third row is the length (1F + ΔT), which is the length 1F plus a small amount corresponding to the thickness of the nanofin. In general, the distance between the centers of the first row and the second row is a length (NF-ΔT) slightly reduced from the minimum feature spacing (NF) by an amount corresponding to the thickness of the nanofin, and the second row. The distance between the centers of the row and the third row is the length (NF + ΔT), which is the minimum feature spacing (NF) plus a small amount corresponding to the thickness of the nanofin.

[Logic circuit] FIG. 17 depicts a NOR gate logic circuit with tunneling transistors that spans various embodiments of the subject. Introduce logic levels from inputs A, B, C into the CMOS logic shown. A logical low input signal from any of these inputs turns on one of the corresponding ones of the MIMO transistor 1772-1774 and turns it off of one of the tunneling transistors 1775-1777. The logical high input signal has the opposite effect. When any of the tunneling transistors 1775-1777 is turned on, the action of bringing the output to the ground (that is, logic 0) is obtained. When all of the photoresist transistors 1772-1774 are turned on, the action of connecting the output to VDD (that is, logic 1) is obtained.

FIG. 18 depicts a NAND gate logic circuit with tunneling transistors according to various embodiments of the subject. In this application, a tunneling transistor is incorporated in a NAND gate CMOS logic circuit so that the NMOS transistor is in close contact with Vss. A logical low input signal from any of the three inputs A, B, C turns on one of the corresponding ones of the PMOS device 1878-1880 and pushes the output to logical high. When all inputs are logically high, each of the NMOS transistors 1881-1882 is turned on, and the tunneling transistor 1883 is also turned on, pushing the output to logical low.

The tunneling transistor in this subject makes it possible to substantially reduce the sub-threshold leakage current, and thus the operation of CMOS circuits (such as the NOR gate logic circuit shown in FIG. 17 and the NAND gate logic circuit shown in FIG. 18). Power can also be reduced. Since the tunneling transistors of this subject can be used in any transistor circuit, these embodiments are for illustration purposes only.

[High-level equipment / system] FIG. 19 is a highly organized, simplified block diagram of various embodiments of the memory device according to the various embodiments of the subject. The memory device 1984 shown includes a memory array 1985 and a read / write control circuit 1986 for operating on the memory array via a communication line or channel 1987 (s). There is. As the memory device 1954 shown, a memory card or a memory module can be used, and for example, SIMM (single inline memory module) or DIMM (dual inline memory module) can be used. Those skilled in the art will appreciate that, upon reading and understanding this disclosure, semiconductor components in memory arrays and / or control circuits can be assembled using tunneling transistors as described above. The structure and the method of manufacturing these devices are described above.

The memory array 1985 has a large number of memory cells 1988. The memory cells in an array are arranged so as to form rows and columns. In various embodiments, the word line 1989 is connected to a row of memory cells and the bit line 1990 is connected to a row of memory cells. The read / write control circuit 1986 includes a word line selection circuit 1991 that has the function of selecting the desired row, a bit line selection circuit 1992 that has the function of selecting the desired column, and a selected memory cell in the memory array 1985. Includes a read circuit 1993, which has the ability to detect the memory state of.

FIG. 20 shows a schematic diagram of an electronic system with tunneling transistors (s) for various embodiments. The electronic system 2094 includes a control means 2095, a bus 2096, and an electronic device 2097, which is the communication line between the control means 2095 and the electronic device 2097. In various embodiments, the control means and / or electronics include tunneling transistors as described above. The electronic systems 2094 shown include, but are not limited to, information processing devices, wireless devices, telecommunications devices, optical fiber systems, electro-optical systems, and computers.

FIG. 21 is a schematic diagram of an embodiment of system 2101 having control means 2102 and memory 2103. The control means 2102 and / or memory 2103 may have tunneling transistors for various embodiments. The system 2101 shown also includes the electronic device 2104 and the bus 2105, which is the communication line (s) between the control means and the electronic device and between the control means and the memory. As such a bus, an address, a data bus, and a control bus, each of which is configured independently, are used. Alternatively, a common communication line that provides addresses, data, and / or controls may be used. And its use is controlled by the control means. In certain embodiments, the electronic device 2104 may be an additional memory configured similar to the memory 2103. In some embodiments, peripherals (s) connected to bus 2105 (s) 2106 May include. Such peripherals include displays, additional storage memory, or other control devices that can work with control means and / or memory. In some embodiments, a processor is used as the control means. Any of the control means 2102, the memory 2103, the electronic device 2104, and the peripheral device 2106 may include tunneling transistors formed according to various embodiments. Such systems 2101 include, but are not limited to, information processing devices, remote communication systems, and computers. Applications for tunneling transistors described in this disclosure include memory modules, device drivers, power modules, communication modems, processor modules, and electronic systems for use in special purpose modules, which in turn include multiple layers and multiple chips. The module to be included may be included. Such circuits may be subordinate components of various electronic systems such as watches, televisions, mobile phones, PCs, automobiles, industrial control systems, airplanes, and the like.

Such a memory can be realized as a memory device including a tunneling transistor according to various embodiments. The group of embodiments has the same effect as a memory circuit of any size and type, and is not intended to be limited to a particular type of memory device. The types of memory include DRAM, SRAM (Static Random Access Memory), and flash memory. Furthermore, it is considered that synchronous DRAM may be used as DRAM. Such synchronous DRAM is also called SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM). Transistors with tunneling transistors can also be used with various emerging memory technologies.

The present disclosure includes various processes, schematics, and cell structures. The subject is not limited to a particular process sequence or logical arrangement. Although illustrated herein for a particular group of embodiments, one of ordinary skill in the art will appreciate that any arrangement devised to achieve the same objective can be used in place of the particular embodiments shown. You can understand it correctly. This application is intended to include application examples or variations of the subject matter. It should be understood that the above description is for illustrative purposes only and is not intended to be limiting. Those skilled in the art will be self-evident if the above description is read through the combination of the above-described embodiment groups and other embodiment groups. The scope of the subject matter should be defined by reference to the accompanying claims, along with the full range of equal features that the claims embody.

<figref num="1">It roughly shows the tendency and correlation of various device parameters scaled by the coefficient k.</figref><figref num="2">Shows subthreshold leakage in traditional silicon MOSFETs.</figref><figref num="3">The ideal 60 mV / decade down-threshold for traditional planar CMOS transistors and the approximately 120 mV / decade to 80 mV / decade down-threshold for traditional planar CMOS transistor structures with short-channel effects. , The comparison is drawn.</figref><figref num="4">It depicts a dual-gate MOSFET with a drain, a source, front and back gates separated from the semiconductor substrate by a gate insulator, and an electric field generated from the drain.</figref><figref num="5">The improved subthreshold characteristics of dual-gate MOSFETs, double-gate MOSFETs, and sounding gate MOSFETs are roughly shown in comparison with the subthreshold characteristics of conventional bulk silicon MOSFETs.</figref><figref num="6">A transistor structure is depicted that includes a channel that is vertical and less than or equal to the lithographic reference dimensions, a salounding gate, and multiple source / drain regions that are of the same conductivity.</figref><figref num="7">Transistor structure with vertical and less than or equal to lithographic reference dimensions, a sounding gate, and multiple source / drain regions of different conductivity, according to various embodiments of the subject. The body is drawn.</figref><figref num="8">An energy band diagram shows the electrical behavior of the tunneling transistor of FIG. 7 when the transistor gate is not biased according to various embodiments of the present subject.</figref><figref num="9">The electrical behavior of the tunneling transistor of FIG. 7 when biasing the transistor gate according to various embodiments of the present subject is shown in an energy band diagram.</figref><figref num="10">The drain current vs. tunneling transistor gate-source voltage for the tunneling transistor in FIG. 7 is plotted according to various embodiments of the subject, showing subthreshold leakage current.</figref><figref num="11A">It depicts the process of growing a nanowire substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="11B">It depicts the process of growing a nanowire substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="11C">It depicts the process of growing a nanowire substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="11D">It depicts the process of growing a nanowire substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="11E">It depicts the process of growing a nanowire substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="11F">It depicts the process of growing a nanowire substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="11G">It depicts the process of growing a nanowire substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="11H">It depicts the process of growing a nanowire substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12A">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12B">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12C">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12D">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12E">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12F">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12G">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12H">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12I">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12J">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12K">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="12L">It depicts the process of growing a nanofin substrate to obtain a vertical channel for a tunneling transistor according to various embodiments of the subject.</figref><figref num="13A">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13B">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13C">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13D">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13E">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13F">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13G">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13H">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13I">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13J">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13K">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="13L">It depicts the process of obtaining a vertical channel for a tunneling transistor by etching the substrate and defining the nanoFin substrate according to various embodiments of the subject.</figref><figref num="14">Demonstrates how to form tunneling nanoFin transistors according to various embodiments of the subject.</figref><figref num="15">Demonstrates how to grow a transistor body below the lithographic reference dimensions for a tunneling transistor according to various embodiments of the subject.</figref><figref num="16">A top-top layout of nanofins for an array of tunneling nanofin transistors according to various embodiments of the subject.</figref><figref num="17">NOR gate logic circuits with tunneling transistors are drawn for various embodiments of the subject.</figref><figref num="18">A NAND gate logic circuit with a tunneling transistor is drawn for various embodiments of the subject.</figref><figref num="19">FIG. 5 is a highly organized, simplified block diagram of various embodiments of a memory device according to various embodiments of the subject.</figref><figref num="20">FIG. 5 is a schematic diagram of an electronic system with one or more tunneling transistors for various embodiments.</figref><figref num="21">It is a figure of the embodiment of the system which has a control means and a memory.</figref>