Cache memory, vector processor and vector data alignment method

The present invention relates to a vector processing device including a vector processing unit, a scalar processing unit, a vector load buffer, and a cache memory. In particular, by providing the cache memory with a vector load buffer function, the amount of hardware of the vector processing device and Related to technology for reducing power consumption.

In the conventional vector processing apparatus, as shown in FIG. 7, the data is returned from the memory unit 220 at an irregular timing into, for example, the memory control unit 210 between the vector register 201 in the vector processing unit 200 and the memory unit 220. The series of vector data to be processed is aligned and supplied to the vector processing unit 200, and even if the vector register 201 is in use (busy) in the calculation, the vector data is read from the memory unit 220 in advance and the memory latency is A dedicated Vector Load Buffer (VLDB) 212 is provided for the two purposes of concealing the data (see, for example, Patent Document 1). The alignment determination circuit 211 is a circuit that notifies the vector processing unit 200 that all the requested vector data are aligned in the vector load buffer 212.

On the other hand, the cache memory adopted by the scalar processor is configured to return the requested data one by one (one element) to the register of the scalar processor each time the data is requested from the scalar processor.

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2-101576</text></patcit>

<p> By the way, in recent years, the improvement of the memory latency cannot keep up with the improvement of the operating frequency of the vector processor, and the capacity (number) of the vector load buffer tends to increase in order to hide the memory latency. Although the memory latency can be concealed by increasing the capacity of the vector load buffer, increasing the capacity of the vector load buffer causes a problem that the hardware and power consumption increase.</p><p> In order to solve such a problem, it is conceivable to use the cache memory as a vector load buffer. However, the cache memory is configured to return the requested data to the scalar processor each time one element of data is requested from the scalar processor, and continuously sends the requested data after all the elements of the vector data are prepared. Since it does not have an alignment function, it cannot be used as a vector load buffer.</p><p>[Purpose of Invention] Therefore, an object of the present invention is to reduce the amount of hardware and power consumption of the vector processing apparatus by making the cache memory also available as a vector load buffer.</p>

<p> The first cache memory according to the present invention is A data array with multiple cache lines that stores a copy of some of the data stored in main memory, and For each divided data obtained by dividing the vector data requested from the vector processing unit at the cache line boundary of the data array, it is determined whether or not the divided data is stored in the data array, and the divided data is stored. For the divided data that is not provided, a cache control unit is provided which reads the corresponding data from the main storage device, stores the data in the data array, stores all the vector data in the data array, and then transmits the data to the vector processing unit. It is characterized by that.</p><p> The first vector processing apparatus according to the present invention is The cache memory according to any one of claims 1 to 4 and A vector processing unit that issues a memory request that requests vector data from the cache memory, and It is characterized by including a scalar processing unit that issues a scalar instruction to the cache memory.</p><p> The first vector data alignment method according to the present invention is The first step in which the vector processing unit requests vector data from the cache memory, Among the components of the vector data requested by the vector processing unit, the cache memory reads a component that does not exist in the own memory from the main storage device, and arranges the vector data after all the components are arranged in the own memory. It is characterized by including a second step of causing the data to be transmitted to the vector processing unit.</p>

<p> According to the present invention, the amount of hardware and power consumption of the vector processing apparatus can be reduced.</p>

Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

[Embodiment of the present invention] Referring to FIG. 1, the present embodiment includes a vector processing unit 100, a cache memory 110, a memory unit (main storage device) 120, and a scalar processing unit 130.

The vector processing unit 100 includes a plurality of vector registers 101 and a request control unit 102. The vector processing unit 100 also includes an arithmetic processing unit that performs vector operations, an instruction register that stores vector instructions, and the like, but the illustration is omitted because it is not directly related to the present invention.

The vector register 101 is a group of registers that stores the vector data stored in the memory unit 120 and the operation results of the operation processing unit (not shown). Generally, one vector register contains n (n is plural). ) Data is stored. These n pieces of data are called vector data.

When the vector load instruction is stored in the instruction register (not shown), the request control unit 102 issues a memory request corresponding to the vector load instruction to the cache memory 110. This memory request includes the start address and the number of elements of the vector data requested by the vector load instruction. Further, the request control unit 102 manages the usage status of the vector register 101, and a storage completion notification indicating that all the vector data requested by the memory request from the cache memory 110 is available on the cache memory 110 is sent. When it is sent, a transfer enable notification is sent to the cache memory 110 on condition that the vector register specified by the above vector load instruction is available.

The cache memory 110 includes a cache control unit 111, a data array 112, a reservation flag 113, and an alignment flag 114.

The data array 112 is composed of a plurality of cache lines L0 to Ln, and each cache line L0 to Ln stores a copy of a part of the data stored in the memory unit 120.

The reservation flag 113 is provided for each cache line L0 to Ln, and is set when the corresponding cache line is a cache line used for storing vector data. The reservation flag 113 functions as a guard flag for preventing the data in the cache line from being replaced by the scalar instruction before transmitting the vector data to the vector processing unit 100.

The alignment flag 114 is provided for each cache line L0 to Ln, and is used to determine whether or not vector data is stored in the corresponding cache line. In the present embodiment, the valid bit (bit indicating whether or not the cache line is valid) for each cache line provided in the cache memory is used as the alignment flag 114.

The cache control unit 111 has the following functions (a) to (f).

(a) For each divided data obtained by dividing the vector data requested by the memory request from the vector processing unit 100 at the cache line boundary of the data array 112, the divided data is stored in the data array 112. Judge whether or not. Dividing the vector data at the cache line boundary of the data array 112 means that the vector data is divided by separating the data at the address (nk-1) when the size of the cache lines L0 to Ln is k bytes. Where n is a positive integer.

(b) For the divided data determined to be stored in the data array 112, the reservation flag 113 corresponding to the cache line in which the divided data is stored is set.

(c) For the divided data determined not to be stored in the data array 112, a cache line for storing the divided data is determined, and the reservation flag 113 corresponding to the cache line is set. Further, the corresponding data is read from the memory unit 120, stored in the cache line determined above, and the alignment flag 114 of the cache line is set.

(d) Whether or not all the vector data requested by the memory request is stored in the data array 112 is determined based on the alignment flag 114, and if it is determined that all the vector data is stored, the vector processing unit 100 is notified. And send a storage completion notification.

(e) When a transfer enable notification is sent from the vector processing unit 100, the vector data stored in the data array 112 and requested by the memory request are aligned and transmitted to the vector processing unit 100, and then the above Resets the reservation flag 113 of the cache line where the vector data was stored.

(f) A function to process scalar commands from the scalar processing unit 130. Regarding the processing of the scalar instruction, the cache control unit 111 of the present embodiment performs the same processing as the cache control unit of the normal cache memory except for the following (f-1) and (f-2). (f-1) When replacing the cache line data because the data accessed by the scalar instruction from the scalar processing unit 130 does not exist on the data array 112, the cache line in which the reservation flag 113 is not set is selected. Replace the data with the target. (f-2) If the data to be rewritten according to the scalar command from the scalar processing unit 130 is stored in the cache line in which the reservation flag 113 is set, the above data is rewritten until the reservation flag 114 is reset. Suppress.

The scalar processing unit 130 issues a scalar instruction (load instruction, store instruction) to the cache memory 110.

[Explanation of operation of the embodiment] Next, the operation of this embodiment will be described.

When the vector load instruction is stored in the instruction register, the request control unit 102 in the vector processing unit 100 issues a memory request corresponding to the vector load instruction to the cache memory 110. This memory request contains the start address and the number of elements of the vector data requested by the vector load instruction.

When the cache control unit 111 receives the memory request, the cache control unit 111 divides the vector data indicated by the start address and the number of elements included in the memory request at the cache line boundary of the data array 112 to obtain the divided data. After that, for each divided data, it is checked whether or not the divided data is stored in the cache line in which the alignment flag 114 is set.

Then, for the divided data stored in the data array 112, the reservation flag 113 corresponding to the cache line in which the divided data is stored is set. On the other hand, for the divided data that is not stored in the data array 112, the cache line that stores the divided data is determined, and the reservation flag 113 of the cache line is set. Further, a load request for requesting the data of the block including the divided data is issued to the memory unit 120, and the arrival of the data is waited for. When the data from the memory unit 120 arrives, the data is stored in the cache line that has already been determined, and the alignment flag 114 of the cache line is set.

After that, when the cache control unit 111 detects that all the alignment flags 114 of the cache line for storing the divided data of the vector data are set, the cache control unit 111 sends a storage completion notification to notify that all the vector data are complete. Send to 100.

Upon receiving the storage completion notification, the request control unit 102 in the vector processing unit 100 notifies the cache memory 110 that transfer is possible, provided that the vector register 101 specified by the vector load instruction is available. To send. As a result, the cache control unit 111 in the cache memory 110 aligns the vector data stored in the cache line in which the reservation flag 113 and the alignment flag 114 are set and transmits the vector data to the vector processing unit 100, and the transmission is completed. Reset the reservation flag 113 of the cache line. As a result, each cache line used to store the vector data is also replaced by the scalar instruction.

In the present embodiment, the alignment flag 114 is realized by using the effective bit, but the alignment flag 114 may be newly provided separately from the effective bit.

[Effect of Embodiment] According to this embodiment, the amount of hardware and power consumption of the vector processing apparatus can be reduced. The reason is that the cache memory 110 can be used as a substitute for the vector load buffer. The reason why the cache memory 110 can be used as a substitute for the vector load buffer is that the divided data obtained by dividing the vector data requested by the vector processing unit 100 at the cache line boundary of the data array 112 is divided. Is stored in the data array 112, and for the divided data that is not stored, the corresponding data is read from the memory unit 120 and stored in the data array 112, and all the vector data is stored in the data array 112. This is because the cache control unit 110 is provided for aligning and transmitting the data to the vector processing unit 100.

Further, according to the present embodiment, the cache memory 110 can be used as a substitute for the vector load buffer without stopping the scalar processing unit 130. The reason is that when the cache control unit 111 replaces the cache line data at the time of a miss hit, the data is replaced for the cache line for which the reservation flag 113 is not set, and the data is rewritten according to the scalar instruction. This is because when is stored in the cache line in which the reservation flag 113 is set, the rewriting of data is suppressed until the reservation flag 113 is reset.

[Example] Next, an example of this embodiment will be described.

Referring to FIG. 2, the cache control unit 111 used in this embodiment includes a cache hit determination unit 1111, a management table storage unit 1112, an alignment determination unit 1113, and a storage unit 1114.

The cache hit determination means 1111 has the following functions (g) to (k).

(g) A plurality of divided data are generated by dividing the vector data requested by the memory request from the request control unit 102 at the cache line boundary of the data array 112. For example, the start address of the vector data included in the memory request, the number of elements are "192" and "256", respectively, one element is "1 byte" (1 byte for convenience), cache line L0. Assuming that the size of each of ~ Ln is "128 bytes", there are three types of data: divided data with addresses "192 to 255", divided data with addresses "256 to 383", and divided data with addresses "384 to 447". Divided data will be generated. In this embodiment, the memory request from the request control unit 102 includes a vector load instruction that specifies the vector load instruction that triggered the request control unit 102 to issue the memory request, in addition to the start address and the number of elements. The ID is also included.

(h) A management table for each memory request sent from the request control unit 102, and a management table for managing the address information and cache line ID of each divided data related to the memory request is generated and stored in the management table. Store in part 1112 and update its contents as needed. The address information of the divided data is information indicating the address on the memory unit 120 of the divided data, and the cache line ID is information indicating the cache line in which the divided data is stored or stored. Figure 3 shows an example of the management table. This example is a management table corresponding to the vector load instruction of the vector load instruction ID "VLn", and the vector data required by the vector load instruction is the divided data of the addresses "192 to 255" and the address "256". It is divided into divided data of ~ 383 "and divided data of addresses" 384 ~ 447 ", and each divided data is stored or stored in the cache line of cache line IDs" ID1 "," ID10 ", and" ID3 ", respectively. It is shown that. In this embodiment, "ID1 to IDn" are assigned as cache line IDs to each cache line L0 to Ln. Further, in the following description, the vector load instruction with the vector load instruction ID VLn may be simply referred to as the vector load instruction VLn.

(i) For each divided data, it is determined whether or not the divided data is stored in the data array 112.

(j) For the divided data determined to be stored in the data array 112, the reservation flag 113 corresponding to the cache line in which the divided data is stored is set (in this embodiment, 1 is set). ..

(k) For the divided data determined not to be stored in the data array 112, a load request requesting the data of the block including the divided data is issued to the memory unit 120, and the divided data is further stored. The cache line to be used is determined and the reservation flag 113 corresponding to the cache line is set.

The alignment determination means 1113 determines whether or not all the alignment flags corresponding to the cache line IDs registered in the management table are set for each management table registered in the management table storage unit 1112. , It is determined whether or not all the vector data requested by the memory request managed by the management table exists on the data array 112, and if it is determined that all the vector data exists, the storage is completed in the vector processing unit 100. Send a notification (including the vector load instruction ID registered in the management table). After that, on condition that the transfer enable notification (including the vector load instruction ID) is sent from the vector processing unit 100, the corresponding vector data is input based on the address information and the cache line ID stored in the management table. Align and send to the vector processing unit 100.

The storage means 1114 stores the data sent from the memory unit 120 in the data array 112, and sets the alignment flag 114 of the cache line in which the data is stored.

Although description is omitted here, the cache control unit 111 has a function of processing a scalar instruction from the scalar processing unit 130. This function is as in the above-described embodiment. Further, also in this embodiment, the effective bit provided in the cache memory is used as the alignment flag 114.

[Explanation of operation of the embodiment] Next, the operation of this embodiment will be described in detail.

When the vector load instruction is set in the instruction register, the request control unit 102 in the vector processing unit 100 issues a memory request corresponding to the vector load instruction to the cache memory 110. This memory request includes the start address and the number of elements of the vector data requested by the vector load instruction, and the vector load instruction ID.

When a memory request is sent from the request control unit 102, the cache hit determination means 1111 in the cache memory 110 performs the process shown in the flow chart of FIG. Now, for example, the start address, the number of elements, and the vector load instruction ID included in the memory request are "192", "256", and "VLn", respectively, one element is "1 byte", and the size of the cache line L0 to Ln. Assuming that each is "128 bytes", the cache hit determination means 1111 performs the following processing.

First, the cache hit determination means 1111 generates a plurality of divided data by dividing the vector data (data of addresses "192 to 447") requested by the memory request at the cache line boundary of the data array 112. .. In this example, three divided data are generated: the divided data D1 of the addresses "192 to 255", the divided data D2 of the addresses "256 to 383", and the divided data D3 of the addresses "384 to 447".

Next, a management table as shown in FIG. 3 is generated and stored in the management table storage unit 1112 (step S41). However, at this point, only the vector load instruction ID "VLn" and the address information of each of the divided data D1 to D3 are registered, and the cache line ID is not registered.

After that, the cache hit determination means 1111 pays attention to the first divided data D1 and determines whether or not it is stored in the data array 112 (steps S42 and S43). This determination is performed by determining whether or not any one of the addresses indicated by the address information of the divided data D1 is stored in the cache line in which the alignment flag 114 is set.

Then, when the divided data D1 is stored in the data array 112, the reservation flag 113 corresponding to the cache line in which the divided data D1 is stored is set, and then the cache line ID of the divided data D1 is set in the management table. Register the ID of the above cache line (YES in step S43, S44, S45).

On the other hand, when the divided data D1 is not stored in the data array 112, one cache line for storing the divided data D1 is determined from the cache lines in which the reservation flag 113 is not set, and the memory is further determined. Issue a memory request to unit 120 requesting the data of the block including the divided data D1 (steps S43 are NO, S48). After that, the reservation flag 113 corresponding to the determined cache line is set, and the ID of the determined cache line is registered in the management table as the cache line ID of the divided data D1 (steps S44 and S45).

Then, when the process of step S45 is completed, attention is paid to the next divided data D2 (step S47), and the same process as the above-described process is performed. When the above processing is performed up to the divided data D3 and there is no unfocused divided data (YES in step S46), the cache hit determination means 1111 ends the processing.

On the other hand, the storage means 1114 stores the data in the corresponding cache line of the data array 112 every time data is sent from the memory unit 120, and sets the alignment flag 114 of the cache line. (Steps S60, S61 in Figure 6).

Further, the alignment determination means 1113 performs the processing shown in the flow chart of FIG. 5 for each management table stored in the management table storage unit 1112.

For example, when the management table shown in FIG. 3 is registered in the management table storage unit 1112, the alignment determination means 1113 has a cache line L1 corresponding to the cache line IDs ID1, ID10, ID3 registered in the management table. By waiting for all the alignment flags 114 of ", L10, L3" to be set, it waits for all the vector data requested by the vector load instruction "VLn" to be aligned on the data array 112 (step S50).

Then, when all the vector data is prepared, the storage completion notification is sent to the request control unit 102 in the vector processing unit 100, and the transfer enable notification is sent from the request control unit 102 (step S50 is YES). , S51, S52). The storage completion notification includes the vector load instruction ID "VLn" registered in the management table.

The request control unit 102 transmits a transfer enable notification to the alignment determination means 1113 on condition that the vector register specified by the vector load instruction VLn is available. This transfer enable notification includes the vector load instruction ID "VLn".

When the alignment determination means 1113 receives the transfer enable notification including the vector load instruction ID VLn, the alignment determination means 1113 transmits the vector data requested by the vector load instruction VLn to the vector processing unit 100 (step S53). At that time, the alignment determination means 1113 refers to the management table shown in FIG. 3, and is first registered in the cache line L1 with the data of the youngest address "192 to 255" registered in the cache line L1 and then in the cache line L10. The data of the addresses "256 to 383" and the data of the addresses "384 to 447" registered in the cache line L3 are finally transmitted to the vector processing unit 100. That is, the vector data is aligned and transmitted to the vector processing unit 100.

After that, the alignment determination means 1113 deletes the management table of FIG. 3 that has been processed, resets the reservation flag corresponding to the cache line ID registered in the management table (step S54), and sets the management table to the above. End the process.

[Effect of Examples] According to this embodiment, the amount of hardware and power consumption of the vector processing apparatus can be reduced. The reason is that the cache memory 110 can be used as a substitute for the vector load buffer. The reason why the cache memory 110 can be used as a substitute for the vector load buffer is that the divided data obtained by dividing the vector data requested by the vector processing unit 100 at the cache line boundary of the data array 112 is divided. The cache hit determination means 1111 that determines whether or not is stored in the data array 112, and the divided data that is not stored in the data array 112 is read from the memory unit 120 and stored in the data array 112. This is because it includes an alignment determination means 1113 that aligns all the vector data in the data array 112 and then transmits the alignment to the vector processing unit 100.

The present invention is suitable for application to supercomputers and the like.

<figref num="1">It is a block diagram which shows the structural example of embodiment of the vector processing apparatus which concerns on this invention.</figref><figref num="2">It is a block diagram which shows the configuration example of the cache memory 110 used in the Example of Embodiment.</figref><figref num="3">It is a figure which shows an example of the management table.</figref><figref num="4">It is a flow chart which shows the processing example of the cache hit determination means 1111.</figref><figref num="5">It is a flow chart which shows the processing example of the alignment determination means 1113.</figref><figref num="6">It is a flow chart which shows the processing example of the storage means 1114.</figref><figref num="7">It is a block diagram which shows the structural example of the conventional vector processing apparatus.</figref>

Code description

100 ... Vector processing unit 101 ... vector register 102 ... Request control unit 110 ... cache memory 111 ... Cache control unit 1111 ... Cache hit judgment means 1112 ... Management table storage 1113 ... Alignment judgment means 1114 ... Storage means 112 ... data array 113 ... Reservation flag 114 ... alignment flag 120 ... Memory section 130 ... Scalar processing unit