Computer system provided with power management function of hardware control

The present invention relates to integrated circuits, especially to computer systems with hardware controlled power management functions.

Electronic circuit manufacturers are increasingly under pressure to reduce the power consumption of their circuit boards. Power storage is especially important in portable electronic devices such as laptop and notebook computers whose products are specially designed for use in the absence of electrical outlets . Preserving battery power is important because laptop and notebook computers must operate on internal or rechargeable batteries for extended periods of time.

On laptop or notebook computers, it is the display that uses the most power. The percentage of power consumed by the display depends on the technology used. Thus, laptop and notebook computer manufacturers have turned off their displays while they are not working. Decoupling the display from the power supply can be achieved with a fairly simple circuit.

In laptop or notebook computers, it is the CPU master microprocessor that consumes the next most power. Traditionally, computer manufacturers have used one or two techniques to reduce the power consumption of microprocessors when they are not in operation. One technique reduces the speed of the system clock to a fraction of the normal operating frequency when inactive. Since the power consumption of the microprocessor is proportional to the frequency, reducing the frequency of the system clock also reduces the power consumption of the microprocessor. For Intel 80386DX microprocessors (manufactured by Intel in Santa Clara, California), the typical operating current of the microprocessor is reduced from 400mA to about 100mA by reducing the operating frequency from 33MHz to 4MHz. Is reduced to. Nevertheless, the operating current of 100mA still forces the battery to leak a lot of power.

A second technique to reduce power is to turn off the system clock when inactive. Turning off the system clock affects all circuits on the master plate. As a result, the circuit that renders the system clock inoperable stores all relevant information in the microprocessor and associated board logic, and at the time of resumption of operation, the state of the computer after the resumption of the system clock is before the system clock is stopped. The data must be restored so that it is the same as the state of the computer. As a result, this technique for consuming power is costly due to the complexity of the circuit and is also slow due to the need to save and restore the state of the computer.

<p> Therefore, there is a need to provide methods and devices for storing power in electronic devices that significantly reduce microprocessor power leakage without the need for complex external circuits.</p>

<p> The computer system of the present invention includes one or more power control signals including at least one power control signal including a BIOS circuit and each having a first combination of assertion states and deassertion states corresponding to a power management mode of operation. A system control circuit that supplies processor control signals and</p><p> A memory circuit that stores and supplies at least a portion of a plurality of data and at least a portion of a plurality of data instructions for data processing.</p><p> An interface circuit that sends at least other parts of multiple data and at least other parts of multiple data instructions.</p><p> The one or more processor control signals, the plurality of data, the plurality of data commands, and the one or more coupled to the system control circuit, the memory circuit, and the interface circuit at least partially. It is equipped with an integrated processor circuit that receives the user command of the above and supplies the plurality of display data.</p><p> The integrated processor circuit has the respective assertion states after the first processor control signal state combination, and is associated with the assertion state and the deassertion state of the one or more processor control signals, respectively. And a processor control circuit that at least partially responds to the one or more processor control signals and the first clock signal by supplying at least one clock control signal having a deassertion state.</p><p> The first clock signal coupled to the processor control signal and having active and active states substantially independent of the assertion and deassertion states of the at least one clock control signal, and the at least one clock control signal. A clock circuit that at least partially responds to the at least one clock control signal by supplying a second clock signal having active and inactive states corresponding to the deassertion state and the assertion state, respectively.</p><p> Memory control that responds at least partially to at least one of the first and second clock signals by being connected to the clock circuit and controlling reception by an integrated processor circuit of multiple data and multiple data instructions. Circuit and</p><p> A plurality of pipeline subcircuits, which are at least partially coupled to the processor control circuit and the clock circuit and respond to at least the second clock signal by selectively operating on the plurality of data instructions. Including sub-circuits</p><p> A plurality of fetch operations and a plurality of fetch operations for the plurality of data instructions in which the first part of the plurality of subcircuits supplies a plurality of processing control signals and also supplies a plurality of corresponding decode instructions. Responding to at least the active second clock signal according to the execution of the decoding operation,</p><p> A second portion of the plurality of subcircuits, including at least the first portion of the pipeline subcircuit, is coupled to the first portion of the plurality of subcircuits to provide corresponding plurality of executable instructions. By doing so, it responds to the active second clock signal, at least the plurality of processing control signals, and the plurality of decoding instructions.</p><p> A third portion of the plurality of subcircuits, including at least a second portion of the pipeline subcircuit, is coupled to the second portion of the plurality of subcircuits and each portion of the plurality of executable instructions. Is a system characterized in that it responds to at least the active second clock signal by executing.</p><p> Other computer systems of the invention include one or one containing at least one power control signal comprising a BIOS circuit and each having a first combination of assertion and deassertion states corresponding to a power management mode of operation. The system control means for supplying the above processor control signals and</p><p> At least one of the above by supplying a memory means for storing and supplying a plurality of data and a plurality of data instructions for data processing, and an enable visual display and a disable visual display corresponding to the plurality of display data, respectively. Display means that respond to the first and second states of the power control signal,</p><p> An interface means for sending one or more user commands and the plurality of display data, and</p><p> The integrated processor means for receiving the one or more processor control signals, the plurality of data, the plurality of data instructions, and the one or more user commands and supplying the plurality of display data. ,</p><p> The integrated processor means has the respective assertion states after the first processor control signal state combination, and the assertion states associated with the assertion state and the deassertion state of the one or more processor control signals, respectively. And a processor control means that at least partially responds to the one or more processor control signals and the first clock signal by supplying at least one clock control signal having a deassertion state.</p><p> The first clock signal having active and inactive states substantially independent of the assertion and assertion states of the at least one clock control signal, and the deassertion and assertion states of the at least one clock control signal, respectively. A clock means that at least partially responds to said at least one clock control signal by supplying a second clock signal with corresponding active and inactive states.</p><p> It includes a pipeline subcircuit and includes a plurality of sub-means that respond to at least the second clock signal by selectively operating on the plurality of data instructions.</p><p> A plurality of fetch operations and a plurality of fetch operations for the plurality of data instructions in which the first portion of the plurality of sub-means supplies a plurality of processing control signals and also supplies a plurality of corresponding decoding instructions. Responding to at least the active second clock signal according to the execution of the decoding operation,</p><p> A second portion of the plurality of sub-means, including at least the first portion of the pipeline sub-means, comprises the active second clock signal and at least the plurality of said active second clock signals by supplying corresponding plurality of executable instructions. In response to the processing control signal and the plurality of decoding instructions,</p><p> A third portion of the plurality of sub-means, including at least a second portion of the pipeline sub-means, executes at least the active second clock signal by executing each portion of the plurality of executable instructions. It is a system characterized by responding to.</p>

<p> This feature of the present invention provides significant advantages. Enhanced features can be added to microprocessors that require pins not found in other x86 compatible microprocessors. Its enhanced feature pins can be selectively disabled by the three-state device to ensure compatibility with the x86 microprocessor architecture. The pin may be selectively activated (enabled) through software in such a way that its enhanced features are assisted.</p>

In order to gain a more complete understanding of the present invention and its advantages, the present invention will be described with reference to the accompanying drawings.

Preferred examples of the present invention and their advantages can be best understood by referring to FIGS. 1 to 6. Similar numbers are used for similar and corresponding parts of the various figures.

Figure 1 is a block diagram of a computer system. The computer system 10 consists of a microprocessor CPU chip 12 coupled to a memory subsystem 14, a BIOS ROM 16, and a logic circuit chip 18 (commonly referred to as a "chipset"). The microprocessor 12 is connected to the bus 20. Bus 20 is used to communicate with several peripherals shown as keyboard controller 22, video controller 24, I / O circuit 26 and disk controller 28 in Figure 1.

The keyboard controller 22 is connected to the keyboard 29. The disk controller 28 is connected to the hard disk 30 and the flexible disk 32. The video controller 24 is connected to the display 34. The optional coprocessor 35 is connected to microprocessor 12 and BIOS ROM 16.

The computer system 10 shown in FIG. 1 is a general-purpose architecture common to personal computers such as IBM personal computers and compatible personal computers. The BIOS 16 (basic input / output system) is typically a read-only memory containing a set of programs for performing basic control and management operations for computer system 10. The BIOS 16 acts as an interface between the computer circuit and the application software executed by the CPU 12.

Importantly, for power consumption purposes, the BIOS 16 and logic 18 monitor selected circuits to determine if a power consumption reduction procedure can be performed. For example, BIOS 16 and / or Logic 18 can monitor display 34 to determine if its output has changed over a predetermined time. If not, BIOS 16 can take steps to disable the power supply to the display 34 to save energy (assuming the computer system 10 is a portable computer).

In addition, BIOS 16 monitors microprocessor 12 to determine if it can be idle without affecting the operation of computer system 10. For example, microprocessor 12 may be running a routine that waits for characters from the keyboard. In this case, the operation of the microprocessor can be suspended until a key is pressed.

FIG. 2 is a detailed block diagram of various subcircuits of a preferred embodiment of microprocessor 12. For purposes of illustration, micros that are pin- and instruction-compatible with Intel's 80x86 family of processors (especially the 80386 microprocessor, but the invention can also be used with other processors). The microprocessor 12 will be described in relation to the processor.

The microprocessor 12 consists of three main functional groups: the core circuit 36, the memory circuit 38 and the bus controller 40. The core circuit 36 includes an instruction queue 42 connected to the internal data bus 44. The output of the instruction queue 42 is connected to the decoder 46 of the decode / sequence circuit 47. The decoding / sequencing circuit 47 also includes the sequencer 50 and the exception handling device 86. The decoder 46 is connected to the microcode ROM 48, the exception handling device 86, and the sequencer 50. The sequencer 50 is also connected to the microcode ROM 48 and the executor 52.

The executing device includes a limit device 54, a multiplication device 56, an addition device 58, a shift device 60, and a register file 62. The execution device 52 is connected to the microcode ROM 48 and the multiplexer and I / O register circuit 64. The memory circuit 38 consists of a memory management device 66 connected to the linear address bus 68, which bus is also connected to the execution device 52 and the instruction / data cache memory 70. The memory management device 66 is further connected to the internal data bus 44.

The pre-emption device 72 is connected between the memory management device 66 and the cache 70. The bus controller 40 includes a data buffer 74, an address buffer 76 and a control circuit 78. Data buffer 74 is connected to data I / O pins D31-D0, and address buffer 76 is connected to address pins A31-A2 and BE3 # -BE0 #. The data address bus 80 connects the memory management device 66, the cache 70, and the address buffer 76. The instruction address bus 82 connects the preemptive device 72, the cache 70, and the address buffer 76. The data buffer 74 is connected to the internal data bus 44.

The clock module 84 receives an external clock signal (CLK2) and generates a CLKA (connected to the bus controller 40) and a CLKB (connected to the memory circuit 38 and the core circuit 36). Both CLKA and CLKB are clock signals having a frequency that is half the frequency of CLK2. The clock module 84 receives a control signal from the bus controller 40.

During operation, instructions are received from external memory by the microprocessor 12 under the control of memory management device 66. To improve performance, the instruction / data cache 70 stores instructions and data received through the bus controller 40. The instruction is stored in the instruction queue 42 and later converted into microcode by the decoder 46. The sequencer 50 points to the next address in the microcode ROM 48 under the control of the decoder 46 and the executor 52. The executor 52 processes the information under the control of the microcode ROM 48.

In a preferred embodiment, the microprocessor 12 has a static design, i.e., the maintenance of data in the internal memory and the registers of the microprocessor 12 does not depend on the clock signal. As will be described in detail later, the clock module 84, under the control of the bus controller 40, makes the clocks to the subcircuits of the core circuit 36 and the memory circuit 38 inoperable while continuously generating the clock signal to the bus controller 40. Can be done. Therefore, when inactive, most of the microprocessor circuit can be paused, which can significantly reduce the power consumed by the microprocessor 12.

Figures 3 and 4 show the power reduction circuit in detail. FIG. 3 is a block diagram showing control signals between various parts of the microprocessor. The bus controller 40 controls the signal from the external pin of the microprocessor 12. A pause (SUSP) signal is input to the bus controller 40, and a pause confirmation (SUSPACK) is output from the bus controller 40. Busy is received from the coprocessor 35 by the bus controller 40. The bus controller 40 also receives a non-maskable interrupt (INTR) signal and a non-maskable interrupt (NMI) signal.

Interrupt (or "exception") signal F<u style="single"></u>Output SUSP to exception handling device 86 and control signal D<u style="single"></u>Receive SUSPACK. The exception handling device 86 monitors the microcode ROM 48, the bus controller 40, and the executing device 52 to determine whether or not the instruction is being executed. Exception handling device 86 is signal D<u style="single"></u>Output EXCEPTION to sequencer 50 and control signal U from microcode ROM 48<u style="single"></u>Receive AHALT. The bus controller 40 has a control signal F.<u style="single"></u>Output IDLE to clock module 84.

When activated, an external circuit (typically BIOS 16 associated with logic 18) may suspend the operation of the microprocessor, for example, when the microprocessor is executing a routine that waits for characters from the keyboard. Detect the state. When such a condition is detected, the external circuit asserts the SUSP pin (eg, by driving the SUSP pin at a logically low voltage). Depending on the assertion of the SUSP signal, the bus controller 40 is associated with the exception handling device 86.<u style="single"></u>Assert the IDLE control signal to clock module 84. F<u style="single"></u>In response to the IDLE signal assertion, the clock module 84 activates the CLKB clock signal (by holding the disabled clock signal at a logical high voltage or a logical low voltage) while continuing to generate the CLKA clock signal. Disable.

Since the microprocessor design is static, the memory does not require a refresh operation, so pausing the clock does not lose any data in the microprocessor 12. A SUSPACK signal is asserted to inform the external circuit that the microprocessor 12 is in a paused state. To resume the operation of the microprocessor 12, for example, the assertion of the SUSP signal is stopped when the signal from the keyboard is detected by the BIOS 16 and the logic circuit 18 (that is, by applying a logical low voltage to the SUSP pin). ).

By suspending the clocks to the core circuit 36 and the memory circuit 38, the power consumed by the microprocessor 12 can be significantly reduced. The bus controller 40 remains active to observe and control the I / O signals between the microprocessor 12 and the external circuitry.

FIG. 4 is a flowchart showing the details of the operation in the pause mode. In the determination block 88, a loop is formed that waits for the SUSP signal to be asserted. At block 90, after the SUSP signal is asserted, the bus controller 40 is F.<u style="single"></u>The SUSP signal is asserted, which is relayed to the exception handling device 86. In block 92, F<u style="single"></u>In response to the assertion of the SUSP signal, the instruction queue 42 is prohibited from advancing new instructions. At block 94, the decoder 46 stops advancing new instructions to the microcode ROM 48 and includes activity by the bus controller 40 for the instructions in the pipeline to the microcode ROM 48 or the executor 52 (collectively, The "pipeline") completes the instruction currently being processed.

After all the instructions in the pipeline have been executed, the exception handler 86 controls signal D in block 96.<u style="single"></u>EXCEPTION is output. D<u style="single"></u>EXCEPTION is received by sequencer 50, which is D<u style="single"></u>Start the power-down microcode routine (block 98) in response to EXCEPTION.

This power-down microcode routine prepares the microprocessor for pause mode. In block 100, the microcode ROM 48 sends the control signal U to the exception handling device 86.<u style="single"></u>Assert AHALT. U<u style="single"></u>In response to the reception of AHALT, the exception handling device 86 is D in block 102.<u style="single"></u>Assert SUSPACK to bus controller 40. In the determination block 104, the bus controller 40 is D from the exception handling device.<u style="single"></u>After receiving the SUSPACK, check the busy signal received from the coprocessor.

While the busy signal is asserted by the coprocessor, the SUSPACK signal to the external circuit is not asserted and the CLKB is not disabled. When the coprocessor stops the busy signal assertion, the microprocessor 12 is in a paused state, and the coprocessor is currently not doing any calculations and can be paused. A SUSPACK signal is asserted by the bus controller 40 to alert.

In block 108, F<u style="single"></u>IDLE is asserted to clock module 84 by bus controller 40. F<u style="single"></u>In response to the output of the IDLE signal, the clock module 84 renders the CLKB inoperable at block 109, thereby suspending the operation of core circuit 36 and memory circuit 38. Then, the bus controller 40 waits until the assertion of the SUSP signal is stopped in the determination block 110. When the SUSP signal assertion is stopped, CLKB is restarted.

Most microprocessors, including the 80386, do not use all the available pins on the chip package. Therefore, the SUSP signal and the SUSPACK signal can be exchanged with the microprocessor 12 by using the unused pins, and thus compatibility with the existing technology can be maintained. Nevertheless, in a preferred embodiment, the pins for the SUSP and SUSPACK signals can be selectively actuated or inoperable.

In a preferred embodiment, the SUSP and SUSPACK pins are initially disabled and BIOS 16 must be configured to make the pins operational in its starting routine. Control bits that can be read and written through preselected I / O ports are provided to enable and disable the SUSP and SUSPACK pins.

Preferred examples of this feature are illustrated in detail in connection with FIGS. 5 (a) and 5 (b). In FIG. 5 (a), the plurality of control registers in the microprocessor 12 (FIG. 1) are accessible using the INDEX and DATA signals input to the control register 120. The majority of the registers (and their bits) are used to form the cache memory subsystem. For example, defining a non-cacheable area of main memory 14, selecting a caching method (direct mapping or aggregate association), and setting a control register to allow flushing of cache memory 70 via an external pin. You can use it.

Each control register is accessible by writing the address of that register (referred to here as INDEX) to the I / O port shown as I / O port 22h in Figure (a). The other I / O ports shown here as I / O ports 23h are used to read and write data from the specified control registers. In a preferred embodiment, the operation of each I / O port 23h is preceded by the operation of the I / O port 22h, otherwise the operation of the second and subsequent I / O port 23h is directed off-chip. become. In the embodiment shown in FIG. 5 (a), the control registers each have an index between C0h and CFh.

In FIG. 5 (b), the register 122 with the index of C0h uses its least significant bit to display the three-state devices 124 and 126, each of which contains a high impedance state in addition to the high and low states. Control. A bit equal to logic high (ie, logic "1") allows both three-state devices 124 and 125 to provide transmission of SUSP and SUSPACK signals. Logic "0" renders the three-state devices 124 and 126 inoperable, thereby isolating the SUSP and SUSPACK pins from the circuit of microprocessor 12.

This feature of the preferred embodiment ensures compatibility with the pin structure of existing microprocessors. FIG. 6 shows another feature of the present invention, in which the operation of the microprocessor 12 can be paused in response to a software command. The 80x86 device supports a "pause (HALT)" operation (opcode F4) that suspends the execution of all instructions and puts the 80x86 in a pause (HALT) state. A non-maskable interrupt (NMI pin) relayed to the bus controller that resumes execution in response to an unmasked interrupt (on the INTR pin relayed to the bus controller 40) or a reset. Usually, this instruction is used as the last instruction in the sequence to stop the system.

However, in the present invention, the HALT instruction has essentially the same result as producing an output from the SUSP pin. Therefore, BIOS 16 can issue a HALT instruction to microprocessor 12 to disable CLKB. Also, disabling CLKB can significantly reduce the power consumed by the microprocessor 12.

FIG. 6 is a flowchart showing the operation of the HALT instruction in the preferred embodiment. When the HALT instruction to the microprocessor 12 is received in the determination block 130, the U in the block 132 is U by the microcode ROM 48.<u style="single"></u>AHALT is output. U from microcode ROM<u style="single"></u>In response to the AHALT signal, the exception handling device 86 is D<u style="single"></u>Output SUSPACK. After checking the busy signal from the coprocessor in the determination block 136, the SUSPACK signal is output by the bus controller 40 in the block 140 and the internal CLKB clock is disabled in the block 142. In the determination block 144, the determination block 144 remains in the paused state until an interrupt is output. When the interrupt is output, the CLKB clock is activated and processing continues.

The HALT instruction allows BIOS 16 to suspend the microprocessor 12 without any additional hardware connections to the microprocessor. The present invention provides significant advantages over prior art. By pausing the clocks to the core and memory circuits, less than 10mA of current consumption was demonstrated. Additional coding to support SUSP and SUSPACK signals is relatively simple, as most BIOS programs support power storage means. Alternatively, the chipset logic 18 can be modified to assist in the generation of SUSP and SUSPACK signals.

Moreover, in a preferred embodiment, the SUSPACK is not asserted until the coprocessor has completed its operation, so the BIOS does not have to provide additional circuitry or code to monitor the coprocessor. In addition, power saving circuitry can be provided on the microprocessor chip without sacrificing pin compatibility. Also, by using the enhanced HALT command, the microprocessor can be operated in the paused state without any hardware interaction other than outputting an interrupt that causes the microprocessor 12 to escape from the paused state.

Although the present invention and its advantages have been described in detail, it is understood that various modifications, substitutions and modifications can be made to it without departing from the scope of the invention as defined by the content of the claims column. There must be.

<figref num="1">A block diagram of a computer system is shown.</figref><figref num="2">FIG. 5 is a block diagram of a preferred embodiment of a microprocessor used in the computer system of FIG.</figref><figref num="3">It is a detailed block diagram of the part related to the power management circuit of the microprocessor of FIG.</figref><figref num="4">It is a flowchart explaining the preferable embodiment of the operation which reduces the power consumption of a microprocessor.</figref><figref num="5">(a) and (b) show circuits for enabling and disabling the pins that provide the power management control signal.</figref><figref num="6">It is a flowchart of the operation of the software-controlled embodiment for maintaining the power consumption of a microprocessor.</figref>