Wafer level package structure and sensor element

The present invention relates to, for example, a wafer level package structure and a sensor element in which a plurality of sensor elements such as an acceleration sensor element and a gyro sensor element are formed.

In recent years, as a sensor element having a chip size package (CSP), a sensor element formed by using wafer level packaging technology has been researched and developed in various places (see, for example, Patent Document 1).

Here, in Patent Document 1, as shown in FIG. 21 (a), a plurality of MEMS (Micro Electro Mechanical System) elements 211 and sensing units (not shown) of the MEMS elements 211 are electrically connected to each other. A package in which a sensor wafer 210 on which a metal wiring (leading electrode) 217 is formed and a recess 221 for forming a space for airtightly sealing a through-hole wiring 224 electrically connected to the metal wiring 217 and a MEMS element 211 are formed. After facing the wafer 220, the sensor wafer 210 and the package wafer 220 are bonded together at the wafer level as shown in FIG. 21 (b) to form the wafer level package structure 200, and the wafer level package structure 200 is formed from the wafer level package structure 200. A technique for dividing into individual sensor elements is disclosed. In the sensor element manufactured in this manner, a portion cut out from the sensor wafer 210 constitutes a sensor substrate (sensor main body), and a portion cut out from the package wafer 220 constitutes a package substrate.

Here, on the surface of the sensor wafer 210 facing the package wafer 220, a first seal surrounding the MEMS element 211 and the metal wiring 217 electrically connected to the MEMS element 211 for each region corresponding to each sensor element. A bonding metal layer for fastening (base metal film for sealing) 218 is formed, and a recess 221 is surrounded on the facing surface of the package wafer 220 with the sensor wafer 210 for each region corresponding to each sensor element, and a first seal is provided. A second sealing metal layer (sealing base metal film) 228 is formed so as to face the fastening metal layer 218.

Further, in the sensor wafer 210, the first connecting metal layer 219 electrically connected to the metal wiring 217 is formed inside the first sealing metal layer 218, and the package wafer 220 is the second. A second connecting metal layer 229 electrically connected to the through-hole wiring 224 is formed inside the sealing metal layer 228 of the above.

In the wafer level package structure 200 described above, the first sealing metal layer 218 of the sensor wafer 210 and the second sealing metal layer 228 of the package wafer 220 are made of solder such as AuSn. The first connecting metal layer 219 and the second connecting metal layer 229 are joined via the second soldering portion 239, while being joined via the solder portion 238 of 1.

By the way, as a MEMS, an acceleration sensor, a gyro sensor, etc. are widely known, and as an acceleration sensor, a piezo that detects an acceleration by a change in a resistance value due to a strain of a gauge resistance consisting of a piezo resistance when the acceleration is applied. Resistant-type acceleration sensors and capacitive-type acceleration sensors that detect acceleration by changing the capacitance between a fixed electrode and a movable electrode when acceleration is applied are known.

The piezoresistive acceleration sensor is a cantilever type in which the weight portion arranged inside the rectangular frame-shaped frame portion is swingably supported by the frame portion via a flexible portion extending in one direction. Alternatively, a double-sided type in which the weight portion arranged inside the frame-shaped frame portion is swingably supported by the frame portion via a pair of flexible portions extending in opposite directions has been proposed. In recent years, the weight portion arranged inside the frame-shaped frame portion is swingably supported by the frame portion via four flexible portions extending in all directions, and acceleration in each of the three directions orthogonal to each other is achieved. Has also been proposed so that each can be detected separately (see, for example, Patent Documents 2 and 3).

In the above-mentioned piezoresistive acceleration sensor, the weight portion and the flexible portion form a movable portion, and the piezoresistive portion constitutes a sensing portion. Further, in a capacitive acceleration sensor (for example, see Patent Document 4) and a gyro sensor (for example, see Patent Document 5), a weight portion provided with a movable electrode, a weight portion that also serves as a movable electrode, and the like constitute the movable portion. The sensing unit is composed of a fixed electrode and a movable electrode.<patcit num="1"><text>Japanese Patent Application Laid-Open No. 2005-251898</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2004-109114</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2004-233072</text></patcit><patcit num="4"><text>Japanese Unexamined Patent Publication No. 2004-028912</text></patcit><patcit num="5"><text>Japanese Unexamined Patent Publication No. 2005-292117</text></patcit>

<p> However, in the wafer level package structure 200 and the sensor element described above, the second connecting metal layer 229 for connection and the second metal bonding metal layer 228 for sealing formed on the package wafer 220 side are on the same plane. While formed at substantially the same height, on the sensor wafer 210 side, the first connecting metal layer 219 and the first sealing metal layer 219 are sealed with respect to the plane including the forming surface of the first connecting metal layer 219. Since the height is different from that of the bonding metal layer 228, the distance between the second connecting metal layer 229 and the first connecting metal layer 219 and the second sealing metal layer 228 are different. In order to absorb the difference in distance from the distance between the first sealing metal layer 218 and the first sealing metal layer 218 and join the connecting metal layers 229,219 and the sealing metal layers 228,218 to each other, A predetermined amount of solder is supplied to the joints of the second connection metal layer 229 and the second sealing metal layer 228 by the solder chute method, and then the sensor wafer 210 and the package wafer 220 are overlapped with each other. Reflow had to be done, complicating the manufacturing process. Further, in the technique described in Patent Document 1, when AuSn is used as the solder, the reflow process temperature becomes 280 ° C or higher, and the residual stress near the bonding interface becomes large due to the residual stress. The sensor characteristics vary.</p><p> The present invention has been made in view of the above reasons, and an object thereof is a wafer level package structure and a sensor capable of simplifying the manufacturing process, lowering the process temperature, and improving the yield of the joining process. To provide the element.</p>

<p> The invention of claim 1 is a wafer-level package structure in which one sensor wafer having a plurality of sensor bodies having a sensing unit and at least one package wafer bonded at the wafer level, and at least one package wafer. A through-hole wiring that is electrically connected to the sensing portion of the sensor body is formed in each region corresponding to the sensor body, and the sensor wafer has a frame shape in which a first insulating film is formed on one surface side. The first sealing metal layer and the first connecting metal layer electrically connected to the sensing unit, which are located inside the first sealing metal layer, are the first for each sensor body. A second insulating film is formed on the surface of the sensor wafer side of the package wafer formed on the insulating film of the above and the through-hole wiring is formed, and the package wafer is bonded to the first sealing metal layer over the entire circumference. The frame-shaped second sealing metal layer and the second sealing metal layer located inside the second sealing metal layer and electrically connected to the through-hole wiring are the sensor body. The package wafer formed on the second insulating film for each region corresponding to the above, and the sensor wafer and the through-hole wiring are formed, includes a first sealing metal layer and a second sealing metal layer. The first connecting metal layer and the second connecting metal layer are directly joined, and each sealing metal layer and each connecting metal layer are of the lower layer. It is characterized by being composed of a laminated film of a Ti film and an upper Au film.</p><p> According to the present invention, when joining a sensor wafer and a package wafer in which through-hole wiring is formed, the bonding metal layers for sealing and the metal layers for connection are directly bonded by a room temperature bonding method or the like without inclusions. The manufacturing process can be simplified, and the manufacturing process can be simplified and the process can be simplified compared to the conventional manufacturing process in which solder is supplied to each joint and then heat treatment such as reflow is adopted. Since the temperature can be lowered and each sealing metal layer and each connecting metal layer are composed of a laminated film of a lower Ti film and an upper Au film, each sealing metal is formed. Adhesion between the sealing metal layers and the connecting metal layers is higher than when the layers and the connecting metal layers are composed of a laminated film of the lower TiW film and the upper Au film. It becomes higher and the yield of the joining process can be improved.</p><p> The invention of claim 2 is a wafer-level package structure in which one sensor wafer having a plurality of sensor bodies having a sensing unit and at least one package wafer bonded at the wafer level, and at least one package wafer. A through-hole wiring that is electrically connected to the sensing portion of the sensor body is formed in each region corresponding to the sensor body, and the sensor wafer has a frame shape in which a first insulating film is formed on one surface side. The first sealing metal layer and the first connecting metal layer electrically connected to the sensing unit, which are located inside the first sealing metal layer, are the first for each sensor body. A second insulating film is formed on the surface of the sensor wafer side of the package wafer formed on the insulating film of the above and the through-hole wiring is formed, and the package wafer is bonded to the first sealing metal layer over the entire circumference. The frame-shaped second sealing metal layer for sealing and the second connecting metal layer for connecting that is located inside the second sealing metal layer and electrically connected to the through-hole wiring are the sensor body. The package wafer formed on the second insulating film for each region corresponding to the above, and the sensor wafer and the through-hole wiring are formed, includes a first sealing metal layer and a second sealing metal layer. The first connecting metal layer and the second connecting metal layer are directly joined, and each sealing metal layer and each connecting metal layer are of the lower layer. It is characterized by being composed of a laminated film of a Cr film and an upper Au film.</p><p> According to the present invention, when joining a sensor wafer and a package wafer in which through-hole wiring is formed, the bonding metal layers for sealing and the metal layers for connection are directly bonded by a room temperature bonding method or the like without inclusions. The manufacturing process can be simplified, and the manufacturing process can be simplified and the process can be simplified compared to the conventional manufacturing process in which solder is supplied to each joint and then heat treatment such as reflow is adopted. Since the temperature can be lowered and each sealing metal layer and each connecting metal layer are composed of a laminated film of a lower Cr film and an upper Au film, each sealing metal is formed. Adhesion between the sealing metal layers and the connecting metal layers is higher than when the layers and the connecting metal layers are composed of a laminated film of the lower TiW film and the upper Au film. It becomes higher and the yield of the joining process can be improved. Further, since each sealing metal layer and each connecting metal layer are composed of a laminated film of a lower Cr film and an upper Au film, the lower layer is a Ti film as in the invention of claim 1. In comparison with the case where, the etching process for patterning the first sealing metal layer and the first connecting metal layer in the sensor wafer, and the second sealing bonding in the package wafer in which the through-hole wiring is formed. The side etching of the lower layer in each of the etching steps of patterning the metal layer and the second connecting metal layer for connection can be suppressed, and the yield of each etching step can be improved.</p><p> The invention of claim 3 is characterized in that, in the invention of claim 1 or 2, the sensor body is formed with an integrated circuit that cooperates with the sensing unit.</p><p> According to the present invention, the wiring length between the sensing unit and the integrated circuit can be shortened, and the sensor performance can be improved.</p><p> The invention of claim 4 is characterized in that the wafer level package structure according to any one of claims 1 to 3 is divided into a desired size defined based on the size of the sensor body. ..</p><p> According to the present invention, the manufacturing process can be simplified, the process temperature can be lowered, and the yield of the joining process can be improved.</p>

<p> The inventions of claims 1 and 2 have the effects of simplifying the manufacturing process, lowering the process temperature, and improving the yield of the joining process.</p>

(Embodiment 1) Hereinafter, the sensor element of this embodiment will be described with reference to FIGS. 1 to 12.

The sensor element of this embodiment is an acceleration sensor element, and is formed on a sensor substrate (sensor body) 1 on which a sensing portion described later is formed as shown in FIGS. 1 (c) and 2 and a sensing portion of the sensor substrate 1. Through-hole wiring forming substrate (first package substrate portion) 2 having a through-hole wiring 24 electrically connected and sealed on one surface side (upper surface side of FIG. 1C) of the sensor substrate 1. And a cover substrate (second package substrate portion) 3 sealed on the other surface side (lower surface side of FIG. 1C) of the sensor substrate 1. Here, the outer peripheral shapes of the sensor substrate 1, the through-hole wiring forming substrate 2 and the cover substrate 3 are rectangular, and the through-hole wiring forming substrate 2 and the cover substrate 3 are formed to have the same external dimensions as the sensor substrate 1. Note that FIG. 1 (c) is a diagram corresponding to the schematic cross section of FIG. 2A-A'.

The above-mentioned sensor substrate 1 is formed by processing an SOI wafer having an n-shaped silicon layer (active layer) 10c on an insulating layer (embedded oxide film) 10b made of a silicon oxide film on a support substrate 10a made of a silicon substrate. The through-hole wiring forming substrate 2 is formed by processing a first silicon wafer, and the cover substrate 3 is formed by processing a second silicon wafer. In the present embodiment, the thickness of the support substrate 10a in the SOI wafer is about 300 μm to 500 μm, the thickness of the insulating layer 10b is about 0.3 μm to 1.5 μm, the thickness of the silicon layer 10c is about 4 μm to 10 μm, and the thickness is about 4 μm to 10 μm. The thickness of the first silicon wafer is about 200 μm to 300 μm, and the thickness of the second silicon wafer is about 100 to 300 μm, but these values are not particularly limited. The surface of the silicon layer 10c, which is the main surface of the SOI wafer, is the (100) surface.

As shown in FIGS. 5 to 7, the sensor substrate 1 includes a frame-shaped (rectangular frame-shaped in this embodiment) frame portion 11, and the weight portion 12 arranged inside the frame portion 11 is on one surface side. It is swingably supported by the frame portion 11 via four flexible strip-shaped flexible portions 13 (on the upper surface side of FIGS. 1 (c) and 5 (b)). In other words, in the sensor substrate 1, the weight portion 12 arranged inside the frame-shaped frame portion 11 is swingably supported by the frame portion 11 via four flexible portions 13 extending from the weight portion 12 in all directions. Has been done. Here, the frame portion 11 is formed by using each of the support substrate 10a, the insulating layer 10b, and the silicon layer 10c of the above-mentioned SOI wafer. On the other hand, the flexible portion 13 is formed by utilizing the silicon layer 10c in the above-mentioned SOI wafer, and is sufficiently thinner than the frame portion 11.

The weight portion 12 is continuously integrated with the rectangular parallelepiped core portion 12a supported by the frame portion 11 via the above-mentioned four bending portions 13 and the four corners of the core portion 12a when viewed from the one surface side of the sensor substrate 1. It has four rectangular parallelepiped attachments 12b connected to. In other words, the weight portion 12 is formed integrally with the core portion 12a in which the other end of each bending portion 13 in which one end is connected to the inner surface of the frame portion 11 is connected to the outer surface, and the core portion 12a. It has four ancillary portions 12b arranged in the space between the portion 12a and the frame portion 11. That is, each ancillary portion 12b is arranged in a space surrounded by the frame portion 11 and the core portion 12a and the two flexible portions 13 and 13 extending in the direction orthogonal to each other when viewed from the one surface side of the sensor substrate 1. A slit 14 is formed between each of the incidental portions 12b and the frame portion 11, and the distance between the adjacent incidental portions 12b sandwiching the flexible portion 13 is longer than the width dimension of the flexible portion 13. There is. Here, the core portion 12a is formed by using the support substrate 10a, the insulating layer 10b, and the silicon layer 10c of the SOI wafer described above, and each ancillary portion 12b is formed by using the support substrate 10a of the SOI wafer. There is. Thus, on the one surface side of the sensor substrate 1, the surface of each incidental portion 12b is from the plane including the surface of the core portion 12a to the other surface side of the sensor substrate 1 (FIGS. 1 (c) and 5 (b). It is located apart from the lower surface side). The frame portion 11, the weight portion 12, and the flexible portions 13 of the sensor substrate 1 may be formed by using a lithography technique and an etching technique.

By the way, as shown in the lower right of each of FIGS. 5A and 5B, one direction along one side of the frame portion 11 in a plane parallel to the above one surface of the sensor substrate 1 is the positive direction of the x-axis. If one direction along the side orthogonal to this one side is defined as the positive direction of the y-axis and one direction of the thickness direction of the sensor substrate 1 is defined as the positive direction of the z-axis, the weight portion 12 is extended in the x-axis direction. pairwise deflection sandwich the core portion 12a Te supporting a body portion 13, the frame portion 11 via the two pair of flexures 13 and 13 sandwich the core portion 12a is extended in the y-axis direction It will be done. In the Cartesian coordinates defined by the above-mentioned three axes of x-axis, y-axis, and z-axis, the origin is the center position of the weight portion 12 on the surface of the portion of the sensor substrate 1 formed by the silicon layer 10c.

The flexible portion 13 extending in the positive direction of the x-axis from the core portion 12a of the weight portion 12 (the flexible portion 13 on the right side of FIG. 5 (a)) is a pair of piezoresistive resistors Rx2, Rx4 in the vicinity of the core portion 12a. Is formed, and one piezoresistive Rz2 is formed in the vicinity of the frame portion 11. On the other hand, the flexible portion 13 extending in the negative direction of the x-axis from the core portion 12a of the weight portion 12 (the flexible portion 13 on the left side of FIG. 5 (a)) is a pair of piezoresistive Rx1 in the vicinity of the core portion 12a. , Rx3 is formed, and one piezoresistive Rz3 is formed in the vicinity of the frame portion 11. Here, the four piezo resistors Rx1, Rx2, Rx3, and Rx4 formed in the vicinity of the core portion 12a are formed to detect the acceleration in the x-axis direction, and the planar shape is an elongated rectangular shape. , The longitudinal direction is formed so as to coincide with the longitudinal direction of the flexible portion 13, and the wiring (diffusion layer wiring formed on the sensor substrate 1, metal wiring 17) constitutes the bridge circuit Bx on the left side in FIG. Etc.). The piezoresistives Rx1 to Rx4 are formed in a stress concentration region where stress is concentrated in the flexed portion 13 when acceleration in the x-axis direction is applied.

Further, the flexible portion 13 (the upper flexible portion 13 in FIG. 5 (a)) extending in the positive direction of the y-axis from the core portion 12a of the weight portion 12 is a pair of piezoresistive Ry1 in the vicinity of the core portion 12a. Along with the formation of Ry3, one piezoresistive Rz1 is formed in the vicinity of the frame portion 11. On the other hand, the flexible portion 13 extending in the negative direction of the y-axis from the core portion 12a of the weight portion 12 (the lower flexible portion 13 in FIG. 5 (a)) is a pair of piezoresistive Ry2 in the vicinity of the core portion 12a. , Ry4 is formed, and one piezoresistive Rz4 is formed at the end on the frame portion 11 side. Here, the four piezoresistives Ry1, Ry2, Ry3, and Ry4 formed in the vicinity of the core portion 12a are formed to detect the acceleration in the y-axis direction, and the planar shape is an elongated rectangular shape. , The longitudinal direction is formed so as to coincide with the longitudinal direction of the flexible portion 13, and the wiring (diffusion layer wiring formed on the sensor substrate 1, metal wiring 17) constitutes the central bridge circuit By in FIG. Etc.). The piezoresistives Ry1 to Ry4 are formed in a stress concentration region where stress is concentrated in the flexed portion 13 when acceleration in the y-axis direction is applied.

The four piezoresistives Rz1, Rz2, Rz3, and Rz4 formed in the vicinity of the frame portion 11 are formed to detect acceleration in the z-axis direction, and constitute the bridge circuit Bz on the right side in FIG. It is connected by wiring (diffusion layer wiring formed on the sensor substrate 1, metal wiring 17, etc.) so as to be used. However, the piezoresistive resistors Rz1 and Rz4 formed in one of the two sets of flexible portions 13, 13 are formed so that the longitudinal direction coincides with the longitudinal direction of the flexible portions 13, 13. On the other hand, the piezoresistive resistances Rz2 and Rz3 formed in the flexing portions 13 and 13 of the other set are formed so that the longitudinal direction coincides with the width direction (short direction) of the flexing portions 13 and 13. There is.

Note that, in FIGS. 1 to 3 and 5, only the portion of the metal wiring 17 in the sensor substrate 1 near the first connecting metal layer 19 for connection is shown, and the diffusion layer wiring is not shown. ..

Here, an example of the operation of the sensor substrate 1 will be described.

Now, if acceleration is applied to the sensor substrate 1 in the positive direction of the x-axis while the sensor substrate 1 is not accelerated, the frame portion 11 is caused by the inertial force of the weight portion 12 acting in the negative direction of the x-axis. The weight portion 12 is displaced with respect to the above, and as a result, the bending portions 13 and 13 having the longitudinal direction in the x-axis direction are deflected and the resistance values of the piezo resistances Rx1 to Rx4 formed in the bending portions 13 and 13 change. Will be done. In this case, the piezoresistives Rx1 and Rx3 receive tensile stress, and the piezoresistives Rx2 and Rx4 receive compressive stress. In general, the piezoresistive effect has the property that the resistance value (resistive effect) increases when it receives tensile stress and the resistance value (resistive effect) decreases when it receives compressive stress. The value increases, and the resistance values of the piezoresistive Rx2 and Rx4 decrease. Therefore, if a constant DC voltage is applied from the external power supply between the pair of input terminals VDD and GND shown in FIG. 8, the potential difference between the output terminals X1 and X2 of the bridge circuit Bx on the left side shown in FIG. 8 will increase. It changes according to the magnitude of acceleration in the x-axis direction. Similarly, when acceleration in the y-axis direction is applied, the potential difference between the output terminals Y1 and Y2 of the central bridge circuit By shown in Fig. 8 changes according to the magnitude of the acceleration in the y-axis direction, and the z-axis When acceleration in the direction is applied, the potential difference between the output terminals Z1 and Z2 of the bridge circuit Bz on the right side shown in FIG. 8 changes according to the magnitude of the acceleration in the z-axis direction. By detecting the change in the output voltage of each of the bridge circuits Bx to Bz, the sensor board 1 described above detects the acceleration in the x-axis direction, the y-axis direction, and the z-axis direction acting on the sensor board 1. Can be detected. In the present embodiment, the weight portion 12 and each bending portion 13 form a movable portion, and each of the piezoresistive resistances Rx1 to Rx4, Ry1 to Ry4, and Rz1 to Rz4 constitutes a sensing portion on the sensor substrate 1. There is.

By the way, as shown in FIG. 8, the sensor board 1 has two input terminals VDD and GND common to the above-mentioned three bridge circuits Bx, By and Bz, and two output terminals X1 and X2 of the bridge circuit Bx. It has two output terminals Y1 and Y2 of the bridge circuit By and two output terminals Z1 and Z2 of the bridge circuit Bz, and each of these input terminals VDD, GND and each output terminal X1, X2, Y1, Y2, Z1 and Z2 are provided as the first connection metal layer 19 on the one surface side (that is, the through hole wiring forming substrate 2 side), and the through hole wiring 24 formed on the through hole wiring forming substrate 2 is provided. Is electrically connected to. That is, eight first connection metal layers 19 are formed on the sensor substrate 1, and eight through-hole wirings 24 are formed on the through-hole wiring forming substrate 2. The eight first connecting metal layers 19 for connection have a rectangular outer peripheral shape (square shape in the present embodiment), and are arranged apart from each other in the circumferential direction of the frame portion 11 (rectangular frame shape). Two are placed on each of the four sides of the frame part 11 of.)

Further, on the frame portion 11 of the sensor substrate 1, a frame-shaped (rectangular frame-shaped) first sealing metal layer 18 having a larger opening area than the frame portion 11 is formed, and the above eight bonding metal layers 18 are formed. The first connecting metal layer 19 for connection is arranged inside the first sealing metal layer 18 for sealing in the frame portion 11. In short, in the sensor substrate 1, the width dimension of the first sealing metal layer 18 is set smaller than the width dimension of the frame portion 11, and the first sealing metal layer 18 and the joint metal for each connection are set. The layer 19 is formed on the same plane.

Here, in the sensor substrate 1, an insulating film 16 composed of a laminated film of a silicon oxide film and a silicon nitride film is formed on the silicon layer 10c on the one surface side thereof, and the first connecting metal layer 19 for connection is formed. The first sealing metal layer 18 and the metal wiring 17 are formed on the same level surface of the insulating film 16 with the same thickness. The insulating film 16 is not limited to a laminated film of a silicon oxide film and a silicon nitride film, and may be formed of, for example, a silicon oxide film or a BPSG film.

Further, in the first sealing metal layer 18 and the first connecting metal layer 19, a Ti film for improving adhesion is interposed between the Au film for bonding and the insulating film 16. In other words, the first sealing metal layer 18 and the first connecting metal layer 19 are formed on the lower Ti film formed on the same level surface of the insulating film 16 and the Ti film. It is composed of a laminated film with an upper Au film. In short, since the first connecting metal layer 19 and the first sealing metal layer 18 are formed of the same metal material, the first connecting metal layer 19 and the first sealing The joint metal layer 18 for connection can be formed at the same time, and the first metal joint for connection 19 and the first metal joint for sealing 18 can be formed to have the same thickness. Here, in the first sealing metal layer 18 and the first connecting metal layer 19, the film thickness of the Ti film is set to 30 nm and the film thickness of the Au film is set to 200 nm, and the metal wiring 17 has a film thickness of 200 nm. The film thickness is set to 1 μm, but these values are examples. Here, the material of each Au film is not limited to pure gold, and may be one to which impurities are added.

Each of the above-mentioned piezo resistors Rx1 to Rx4, Ry1 to Ry4, Rz1 to Rz4 and each of the above diffusion layer wirings are formed by doping each formation site of the above silicon layer 10c with an appropriate concentration of p-type impurities. The above-mentioned metal wiring 17 is formed by patterning a metal film (for example, Al film, Al alloy film, etc.) formed on the insulating film 16 by a sputtering method or a vapor deposition method by using lithography technology and etching technology. The metal wiring 17 is electrically connected to the diffusion layer wiring through a contact hole provided in the insulating film 16. Further, in the first connection metal layer 19 and the metal wiring 17, the connection portion 19b (see FIG. 3B) with the metal wiring 17 in the first connection metal layer 19 forms a through-hole wiring. The substrate 2 is electrically connected so as to be located in a displacement space forming recess 21 formed on a surface facing the sensor substrate 1 which will be described later.

As shown in FIGS. 9 to 11, the through-hole wiring forming substrate 2 has a weight portion 12 of the sensor substrate 1 and each bending portion 13 on the surface of the sensor substrate 1 side (lower surface side in FIG. 1 (c)). A plurality of the above-mentioned displacement space forming recesses 21 for securing the displacement space of the movable portion to be formed are formed, and a plurality of the above-mentioned displacement space forming recesses 21 penetrate in the thickness direction in the peripheral portion (8 in the present embodiment). The through hole 22 is formed, and an insulating film 23 made of a silicon oxide film (thermal insulating film) is formed so as to straddle both sides in the thickness direction and the inner surface of the through hole 22. A part of the insulating film 23 is interposed between the inner surface and the inner surface. Here, the eight through-hole wirings 24 of the through-hole wiring forming substrate 2 are formed so as to be separated from each other in the circumferential direction of the through-hole wiring forming substrate 2. Further, although Cu is used as the material for the through-hole wiring 24, the material is not limited to Cu, and for example, Ni or the like may be used.

Further, a plurality of through-hole wiring forming substrates 2 are electrically connected to each of the through-hole wirings 24 on the peripheral portion of the displacement space forming recess 21 on the surface on the sensor substrate 1 side (8 in this embodiment). ), A second connecting metal layer 29 for connection is formed. The through-hole wiring forming substrate 2 has a frame-shaped (rectangular frame-shaped) second sealing metal layer 28 formed on the peripheral portion of the surface on the sensor substrate 1 side over the entire circumference. The eight second connecting metal layers 29 of No. 2 have an elongated rectangular outer shape, and are arranged inside the second sealing metal layer 28 for sealing. Here, in the second connection metal layer 29, one end in the longitudinal direction is joined to the through-hole wiring 24 and electrically connected, and the other end is from the metal wiring 17 of the sensor substrate 1. Is also arranged so as to be joined to the first connection metal layer 19 of the sensor substrate 1 and electrically connected to the outside. In short, the positions of the through-hole wiring 24 and the first connecting metal layer 19 corresponding to the through-hole wiring 24 are shifted in the circumferential direction of the through-hole wiring forming substrate 2, and the second connecting metal layer for connecting is shifted. 29 is arranged so that the longitudinal direction coincides with the circumferential direction of the second sealing metal layer 28 and straddles the through-hole wiring 24 and the first connecting metal layer 19.

Further, the second sealing metal layer 28 and the second connecting metal layer 29 have a Ti film for improving adhesion interposed between the Au film for bonding and the insulating film 23. In other words, the second sealing metal layer 28 and the second connecting metal layer 29 are formed on the lower Ti film formed on the same level surface of the insulating film 23 and the Ti film. It is composed of a laminated film with an upper Au film. In short, since the second connecting metal layer 29 and the second sealing metal layer 28 are formed of the same metal material, the second connecting metal layer 29 and the second sealing are made of the same metal material. The joint metal layer 28 for connection can be formed at the same time, and the second metal joint metal layer 29 for connection and the second metal joint metal layer 28 for sealing can be formed to have the same thickness. Here, in the second sealing metal layer 28 and the second connecting metal layer 29, the film thickness of the Ti film is set to 30 nm and the film thickness of the Au film is set to 200 nm. Is an example. Here, the material of each Au film is not limited to pure gold, and may be one to which impurities are added.

Further, on the surface of the through-hole wiring forming substrate 2 opposite to the sensor substrate 1 side, a plurality of external connection electrodes 25 electrically connected to each of the through-hole wiring 24 are formed. The outer peripheral shape of each external connection electrode 25 is rectangular.

As shown in FIG. 12, the cover substrate 3 has a recess 31 having a predetermined depth (for example, about 5 μm to 10 μm) forming a displacement space of the weight portion 12 on the surface facing the sensor substrate 1. Here, the recess 31 is formed by using a lithography technique and an etching technique. In the present embodiment, the recess 31 forming the displacement space of the weight portion 12 is formed on the surface of the cover substrate 3 facing the sensor substrate 1, but the core portion 12a of the weight portion 12 and each accompanying portion 12b are formed. The thickness of the portion formed by using the support substrate 10a is compared with the thickness of the portion formed by using the support substrate 10a in the frame portion 11 in the thickness direction of the sensor substrate 1. By thinning the weight portion 12 by the allowable displacement amount, the weight portion on the other surface side of the sensor substrate 1 in the direction intersecting the other surface without forming the recess 31 in the cover substrate 3 A gap that allows the displacement of 12 is formed between the weight portion 12 and the cover substrate 3.

By the way, in the above-mentioned acceleration sensor element, the sensor substrate 1 and the through-hole wiring forming substrate 2 are joined together with the first sealing metal layer 18 for sealing and the second sealing metal layer 28 for sealing. The connection metal layer 19 of 1 and the second connection metal layer 29 are bonded, and the peripheral portions of the facing surfaces of the sensor substrate 1 and the cover substrate 3 are bonded to each other. Further, as shown in FIGS. 1 (a) to 1 (c), the acceleration sensor element of the present embodiment penetrates through the sensor wafer 10 in which a plurality of sensor substrates 1 are formed on the above-mentioned SOI wafer and the above-mentioned first silicon wafer. Wafer level package by joining the first package wafer 20 on which a plurality of hole wiring forming substrates 2 are formed and the second package wafer 30 on which a plurality of cover substrates 3 are formed on the above-mentioned second silicon wafer at the wafer level. After the structure 100 is formed, it is divided into a desired size defined based on the size of the sensor substrate 1 by a dicing step (the acceleration sensor element of FIG. 1 (c) is at the wafer level shown in FIG. 1 (a). Corresponds to the cross section of the part of the package structure 100 circled A). Therefore, the through-hole wiring forming substrate 2 and the cover substrate 3 have the same outer size as the sensor substrate 1, and a small chip size package can be realized and manufacturing becomes easy. As can be seen from the above description, the first package wafer 20 is formed with through-hole wiring 24 electrically connected to the sensing portion of the sensor substrate 1 for each region corresponding to the sensor substrate 1. In the present embodiment, the insulating film 16 of the sensor substrate 1, that is, the insulating film 16 formed on the sensor wafer 10 constitutes the first insulating film, and the insulating film 23 formed on the through-hole wiring forming substrate 2 is formed. It constitutes the second insulating film.

Here, in the present embodiment, as a joining method between the sensor wafer 10 and the first package wafer and the second package wafer 30, a room temperature joining method capable of joining at a lower temperature in order to reduce the residual stress of the sensor substrate 1 is possible. Is adopted. In the room temperature bonding method, before bonding, argon plasma, an ion beam, or an atomic beam is irradiated to the bonding surfaces in a vacuum to cleanse and activate each bonding surface, and then the bonding surfaces are brought into contact with each other. Join at room temperature. In the present embodiment, the first sealing metal layer 18 and the second sealing metal layer 28 are directly bonded by applying an appropriate load at room temperature by the above-mentioned normal temperature bonding method. At the same time, the first connection metal layer 19 and the second connection metal layer 29 are directly bonded, and by the above-mentioned normal temperature bonding method, the frame portion 11 of the sensor substrate 1 is bonded at room temperature. It is directly joined to the peripheral portion of the cover substrate 3.

Thus, in the wafer level package structure 100 of the present embodiment, the sealing metal layers 18, 28 and the connecting metal layers 19, 29 of the sensor wafer 10 and the first package wafer 20 are directly bonded to each other. The sensor wafer 10 and the second package wafer 30 are directly bonded by a low temperature process such as a room temperature bonding method, and the sensor wafer 10 and the first package wafer 20 and the second package wafer 30 are solder reflowed. Compared with the case of joining by a method requiring such heat treatment, there is an advantage that the piezo resistors Rx1 to Rx4, Ry1 to Ry4, and Rz1 to Rz4 constituting the sensing portion are less affected by thermal stress. Further, in the present embodiment, since the sensor substrate 1, the through-hole wiring forming substrate 2 and the cover substrate 3 are formed of Si, which is the same semiconductor material, the sensor substrate 1, the through-hole wiring forming substrate 2 and the cover substrate 3 are formed. The influence of the stress (residual stress on the sensor substrate 1) caused by the difference in linear expansion rate with and on the output signal of the bridge circuit can be reduced, and the through-hole wiring forming substrate 2 and the cover substrate 3 are made of different materials from the sensor substrate 1. It is possible to reduce variations in sensor characteristics as compared with the case where they are formed. Although the sensor substrate 1 is formed by processing an SOI wafer, it is not limited to the SOI wafer and may be formed by processing, for example, a silicon wafer.

In the wafer level package structure 100 and the acceleration sensor element in the present embodiment described above, when the sensor wafer 10 and the first package wafer 20 on which the through-hole wiring 24 is formed are joined, the sensor wafer 10 and the first package are joined. It is possible to adopt a manufacturing process in which the bonding metal layers 18, 28 for sealing and the bonding metal layers 19, 29 for connection with the wafer 20 are directly bonded to each other without inclusions, and soldering is performed at each bonding site as in the conventional case. Compared with the case of adopting a manufacturing process in which heat treatment such as reflow is performed after supplying the wafer, the manufacturing process can be simplified, and the sealing metal layers 18, 28 are connected to each other and the connecting metal layers 19, As a method of directly joining 29 to each other, a low temperature process such as a normal temperature joining method can be adopted, and the process temperature can be lowered.

Further, in the present embodiment, the first sealing metal layer 18 and the first connecting metal layer 19 are on the same level surface of the sensor wafer 10 (the same level surface orthogonal to the thickness direction of the sensor wafer 10). The second sealing metal layer 28 and the second connecting metal layer 29 are at the same level as the first package wafer 20 on which the through-hole wiring 24 is formed. Since it is formed with the same thickness on the surface (the same level surface orthogonal to the thickness direction of the first package wafer 20), the bonding reliability between the sealing metal layers 18 and 28 and the connecting metal layer for connection are formed. It is possible to improve the joining reliability between 19,29 and 29, and it is easy to control the load at the time of joining the sensor wafer 10 and the first package wafer 20.

Here, in order to improve the yield of the joining process of joining the sealing metal layers 18, 28 to each other and the connecting metal layers 19, 29 to each other, the inventors of the present application, the sealing metal layers 18, The film thickness of the upper Au film and the material of the lower layer in 28 and the bonding metal layers 19 and 29 for connection were examined.

Regarding the examination of the thickness of the Au film, specifically, the insulating film (insulating film 16 of the sensor substrate 1, that is, the sensor wafer) covers the entire surface side of the SOI wafer having the same specifications as the SOI wafer that is the basis of the sensor wafer 10. The SOI wafer for bonding test, in which the insulating film formed under the same conditions as the insulating film 16 of 10), the Ti film of the lower layer, and the Au film of the upper layer are laminated, and the silicon wafer that is the basis of the first package wafer 20 are the same. An insulating film (insulating film 23 of the through-hole wiring forming substrate 2, that is, an insulating film formed under the same conditions as the insulating film 23 of the first package wafer 20) and a lower layer on the entire surface side of the silicon wafer of the specifications. After preparing various Au film thicknesses with the same Au film thickness (Au film film thickness) for the silicon wafer for bonding test in which the Ti film and the upper Au film are laminated, the bonding process is performed by the room temperature bonding method. , The ratio of the bonding area between the SOI wafer for bonding test and the silicon wafer for bonding test to the wafer area was evaluated as the bonding area ratio by ultrasonic microscopy (the Ti film and Au film were formed by the sputtering method). ..

As a result, as shown in FIG. 4, it was found that the joint area ratio decreases as the Au film thickness increases, and if the Au film thickness is 500 nm or less, a value larger than 90% can be obtained as the joint area ratio. It was. By the way, in order to improve the total yield in manufacturing the sensor element, it is necessary to improve the yield in each process, and it is desirable to set the yield in each process to a value of 90% or more. From the results, in order to make the yield of the joining process of joining the sealing metal layers 18,28 and the connecting metal layers 19,29 to 90% or more, the Au film thickness should be set to 500 nm or less. It turns out to be good. In the results of FIG. 4, it is presumed that the reason why the bonding area ratio decreases as the Au film thickness increases is that the surface of the Au film becomes rough and bonding defects are likely to occur. Regarding the lower limit of Au film thickness, if the Au film thickness becomes too thin, the film continuity of the Au film will decrease and the resistance will increase, or conduction failure will occur between the bonding metal layers 19 and 29 for connection. It is desirable to set it to 10 nm or more because it will be easier.

Next, Ti, TiW, and Cr were examined for the materials of the lower layers of the sealing metal layers 18 and 28 and the connecting metal layers 19 and 29. Specifically, the basic condition is that a value of approximately 100% is obtained as the bonding area ratio from the result of FIG. 4 above (the film thickness of the Au film in the upper layer is 200 nm, and the film thickness of the Ti film in the lower layer is 30 nm. ), A SOI wafer for bonding test and a silicon wafer for bonding test in which the materials of the lower layer were different with Ti, TiW, and Cr were prepared, and the surface roughness, the bonding area ratio, and the workability were evaluated (Note that the Ti film, The TiW film, Cr film, and Au film were all formed by the sputtering method). The results are shown in Table 1 below.

<tables num="1"><img file="JP2007194574A_D0001.tif" /></tables>

Here, in Table 1, the RMS roughness value of the Au film surface of the upper layer measured by using an AFM (atomic force microscope) is shown as the surface roughness, and the workability of the laminated film of the lower layer and the upper layer is shown. "" is described for materials with high corrosion resistance to the hydrofluoric acid-based solution to be patterned (materials with less side etching), and "" is described for materials with slightly more side etching than materials with "". ..

From the results in Table 1, if Ti or Cr is used as the material of the lower layer, the bonding metal layers 18 and 28 for sealing and the bonding metal layers 19 and 29 for each connection are the lower TiW film and the upper Au film. It can be seen that the adhesion between the sealing metal layers 18, 28 and the connecting metal layers 19, 29 is higher than in the case of being composed of the laminated film of the above, and the yield of the joining process can be improved. ..

Further, from the results in Table 1, if the sealing metal layers 18 and 28 and the connecting metal layers 19 and 29 are composed of a laminated film of a lower Cr film and an upper Au film, the lower layer is Ti. Although the bonding area ratio is slightly lower than that of the film, the etching process for patterning the first sealing metal layer 18 and the first connecting metal layer 19 in the sensor wafer 10, the through-hole wiring 24 Etching step of patterning the second sealing metal layer 28 and the second connecting metal layer 29 in the first package wafer 20 in which the above is formed It is possible to suppress the side etching of the lower layer in each step. , It can be seen that the yield of each etching process can be improved.

Further, in the present embodiment, the second package wafer 30 is bonded to the other surface side (lower surface side of FIG. 1 (c)) opposite to the one surface side (upper surface side of FIG. 1 (c)) of the sensor wafer 10. Is directly bonded by a low temperature process such as a room temperature bonding method, so that it is not necessary to form a metal layer for bonding between the sensor wafer 10 and the second package wafer 30, which simplifies the manufacturing process. It can be planned.

(Embodiment 2) Hereinafter, the sensor element of this embodiment will be described with reference to FIGS. 13 to 19.

The basic configuration of the acceleration sensor element, which is the sensor element of this embodiment, is substantially the same as that of the first embodiment. The sensor substrate 1 which is the sensor body is an integrated circuit (CMOS IC) using CMOS and cooperates with the sensing unit. It differs from the first embodiment in that an IC region portion E2 in which a working integrated circuit is formed is provided. Here, the integrated circuit is a signal processing circuit or a signal that performs signal processing such as amplification, offset adjustment, and temperature compensation on the output signal of the bridge circuit Bx, By, Bz described in the first embodiment and outputs the signal. The EEPROM and the like that store the data used in the processing circuit are integrated. The same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIGS. 13 and 15, the sensor substrate 1 in the present embodiment includes a part of the frame portion 11, the weight portion 12, each bending portion 13, and the piezoresistive Rx1 to Rx4, Ry1 to described in the first embodiment. The sensor region E1 in which Ry4, Rz1 to Rz4, etc. are formed, the IC region E2 in which the integrated circuit is formed, the first sealing metal layer 18 described in the first embodiment, and the like are formed. Each region portion E1 to E3 is provided with the formed junction region portion E3 so that the sensor region portion E1 located at the center in a plan view is surrounded by the IC region portion E2 and the IC region portion E2 is surrounded by the joint region portion E3. Layout is designed. Here, in the present embodiment, the external dimensions of the frame portion 11 of the sensor substrate 1 in the first embodiment are increased (in other words, the width dimension of the frame portion 11 is increased), and the above integration is performed in the frame portion 11. A circuit is formed.

By the way, the sensor substrate 1 is formed by using the SOI wafer as in the first embodiment, and the IC region portion E2 uses the multilayer wiring technology to reduce the occupied area of the IC region portion E2 in the sensor substrate 1. I am trying to make it. Therefore, in the IC region portion E2 of the sensor substrate 1, an interlayer insulating film or passivation is provided on the surface side of the insulating film 16 composed of a laminated film of the silicon oxide film on the silicon layer 10c and the silicon nitride film on the silicon oxide film. A multilayer structure 41 made of a film or the like is formed, and a plurality of pads 42 are exposed by removing appropriate parts of the passivation film, and each pad 42 is a lead-out wiring 43 made of a metal material (for example, Au). It is electrically connected to the first connecting metal layer 19 on the insulating film 16 of the bonding region E3 via the (see FIG. 16). Here, in the present embodiment, the material of the lead-out wiring 43 and the material of the first connection metal layer 19 are the same, and the lead-out wiring 43 and the first connection metal layer 19 are formed in a continuous manner. Has been done. The plurality of pads 42 formed in the IC region portion E2 are electrically connected to the sensing unit through a signal processing circuit and are electrically connected to the sensing unit without passing through the signal processing circuit. However, in any case, the through-hole wiring 24 of the through-hole wiring forming substrate 2 and the sensing portion are electrically connected.

Further, in the present embodiment, as in the first embodiment, the through-hole wiring forming substrate 2 (see FIGS. 13, 17, and 18) and the second silicon wafer formed by using the first silicon wafer are used. The cover substrate 3 (see FIGS. 13 and 19) formed in the above is formed to have the same external dimensions as the sensor substrate 1, and the through-hole wiring forming substrate 2 in the present embodiment is the displacement space described in the first embodiment. The opening area of the displacement space forming recess 21 is larger than that of the first embodiment so that the sensor region E1 and the IC region E2 fit within the projected area of the opening surface of the forming recess 21. The multilayer structure portion 41 of the above is arranged in the recess 21 for forming the displacement space (see FIGS. 13 and 14).

Hereinafter, a method for manufacturing the sensor wafer 10 in which a plurality of sensor substrates 1 are formed on the above-mentioned SOI wafer will be briefly described with reference to FIG. 20, but FIGS. 20 (a) to 20 (d) show A- in FIG. 15 (a). The cross section of the part corresponding to the A'cross section is shown.

First, on the main surface side of the SOI wafer (the surface side of the silicon layer 10c), each piezoresistive Rx1 to Rx4, Ry1 to Ry4, Rz1 to Rz4, the diffusion layer wiring for forming the bridge circuit Bx, By, Bz, the above integrated circuit, etc. Circuit elements are formed using CMOS process technology. Here, at the stage where the step of exposing each pad 42 of the IC region portion E2 is completed, the above-mentioned multi-layer structure portion 41 is also formed in the sensor region portion E1 and the joint region portion E3, but the multi-layer structure portion 41 No metal wiring is provided in the portion formed in the portion corresponding to the sensor region portion E1 and the joint region portion E3.

After the above-mentioned steps of exposing each pad 42 are completed, a resist layer patterned so as to expose the portions of the multilayer structure portion 41 corresponding to the sensor region portion E1 and the bonding region portion E3. The resist layer is used as an etching mask, the exposed portion of the multilayer structure portion 41 is removed by etching using the silicon nitride film of the insulating film 16 on the silicon layer 10c as an etching stopper layer, and then the resist layer is removed. By removing, the structure shown in FIG. 20 (a) is obtained.

After that, on the main surface side of the SOI wafer, the first encapsulating bonded metal layer 18, each connecting bonded metal layer 19, and each lead-out wiring 43 are subjected to a thin film forming technique such as a sputtering method, a photolithographic technique, and an etching technique. After forming by using, on the main surface side of the SOI wafer, the parts corresponding to the frame part 11, the core part 12a of the weight part 12, and each bending part 13 are covered with the above-mentioned insulating film 16 to expose the other parts. A resist layer patterned so as to be formed is formed, and the insulating film 16 is patterned by etching the exposed portion of the insulating film 16 using the resist layer as an etching mask, and the SOI wafer reaches the insulating layer 10b from the main surface side. A surface-side patterning step of etching the insulating layer 10b to a depth as an etching stopper layer is performed, and then the resist layer is removed to obtain the structure shown in FIG. 20 (b). By performing this surface-side patterning step, the silicon layer 10c in the SOI wafer has a portion corresponding to the frame portion 11, a portion corresponding to the core portion 12a, and a portion corresponding to each of the bending portions 13. In the etching in this surface side patterning step, for example, dry etching may be performed using an inductively coupled plasma (ICP) type dry etching apparatus, and as an etching condition, the insulating layer 10b functions as an etching stopper layer. Set such conditions.

After removing the resist layer following the surface patterning step described above, a portion corresponding to the frame portion 11 and a portion corresponding to the core portion 12a in the silicon oxide film 10d laminated on the support substrate 10a on the back surface side of the SOI wafer. A resist layer patterned so as to cover and each accompanying portion 12b and expose other portions is formed, and the exposed portion of the silicon oxide film 10d is etched using the resist layer as an etching mask. After patterning the silicon oxide film 10d with, and removing the resist layer, the silicon oxide film 10d is used as an etching mask, and the SOI wafer is used as an etching stopper layer from the back surface side to a depth reaching the insulating layer 10b. The structure shown in FIG. 20 (c) is obtained by performing a backside patterning step of dry etching. By performing this back surface side patterning step, the support substrate 10a in the SOI wafer has a portion corresponding to the frame portion 11, a portion corresponding to the core portion 12a, and a portion corresponding to each of the accompanying portions 12b. As the etching apparatus in this back surface side patterning step, for example, an inductively coupled plasma (ICP) type dry etching apparatus may be used, and the etching conditions are such that the insulating layer 10b functions as an etching stopper layer. Set.

After the back surface side patterning step, the frame portion 11, each of the flexible portions 13, and the bending portion 13 are removed by etching the unnecessary portion of the insulating layer 10b, leaving the portion corresponding to the frame portion 11 and the portion corresponding to the core portion 12a by wet etching. By performing the separation step of forming the weight portion 12, the structure shown in FIG. 20 (d) is obtained. In this separation step, the silicon oxide film 10d on the back surface side of the SOI wafer is also removed by etching.

Similar to the first embodiment, the acceleration sensor element of the present embodiment is a first sensor wafer 10 in which a plurality of sensor substrates 1 are formed on an SOI wafer and a first in which a plurality of through-hole wiring forming substrates 2 are formed on the above-mentioned first silicon wafer. The wafer level package structure 100 is formed by joining the package wafer 20 of the above and the second package wafer 30 in which a plurality of cover substrates 3 are formed on the above-mentioned second silicon wafer at the wafer level at room temperature, and then the sensor. The acceleration sensor element shown in FIG. 13 (c) is divided into a desired size defined based on the size of the substrate 1 by a dying step (the acceleration sensor element shown in FIG. 13 (c) is a circle A of the wafer level package structure 100 shown in FIG. Corresponds to the cross section of the part surrounded by). Therefore, the through-hole wiring forming substrate 2 and the cover substrate 3 have the same outer size as the sensor substrate 1, and a small chip size package can be realized and manufacturing becomes easy. Here, also in the present embodiment, as in the first embodiment, Ti or Cr may be adopted as the material of the lower layers of the sealing metal layers 18, 28 and the connecting metal layers 19, 29, respectively. ..

Further, in the acceleration sensor element of the present embodiment, a sensor in which the acceleration sensor element of the first embodiment and an IC chip forming an integrated circuit that cooperates with the sensing unit of the acceleration sensor element of the first embodiment are housed in one package. Compared to a module, the size and cost can be reduced, and the wiring length between the sensing unit and the integrated circuit can be shortened, so that the sensor performance can be improved.

In each of the above-described embodiments, the piezo resistance type acceleration sensor element has been exemplified as the sensor element, but the technical idea of the present invention is not limited to the piezo resistance type acceleration sensor element, for example, a capacitive acceleration sensor element or a gyro. It can also be applied to other sensor elements such as sensor elements and thermal infrared sensor elements. In capacitive acceleration sensor elements and gyro sensor elements, weights provided with movable electrodes and weights that also serve as movable electrodes serve as movable parts. It is configured, and the sensing unit is composed of the fixed electrode and the movable electrode.

Further, in each of the above-described embodiments, two package wafers 20 and 30 are bonded at the wafer level to one sensor wafer 10, but the number of wafers to be bonded at the wafer level is not particularly limited. Depending on the structure of the sensor substrate 1 which is the sensor body, only one package wafer may be bonded to one sensor wafer at the wafer level and then divided into desired sizes.

<figref num="1">The wafer level package structure in Embodiment 1 is shown, (a) is a schematic plan view, (b) is a schematic side view, and (c) is a schematic cross-sectional view of an acceleration sensor element.</figref><figref num="2">It is the schematic plan view of the acceleration sensor element in the same as above.</figref><figref num="3">The acceleration sensor element in the above is shown, (a) is an enlarged view of a main part of FIG. 1 (c), and (b) is a schematic cross-sectional view of C-C'of FIG.</figref><figref num="4">It is explanatory drawing of Au film thickness and the joint area ratio in the same as above.</figref><figref num="5">The sensor substrate in the above is shown, (a) is a schematic plan view, and (b) is a schematic cross-sectional view of B-A'of (a).</figref><figref num="6">The sensor substrate in the above is shown, FIG. 5 (a) is a schematic cross-sectional view taken along the line A-A'of FIG. 5 (a), and FIG. 5 (b) is a schematic cross-sectional view taken along the line C-C'of FIG.</figref><figref num="7">It is a schematic bottom view which shows the sensor substrate in the same above.</figref><figref num="8">It is a circuit diagram of the sensor board in the same as above.</figref><figref num="9">The through-hole wiring forming substrate in the above is shown, (a) is a schematic plan view, and (b) is a schematic cross-sectional view of A-A'in (a).</figref><figref num="10">The through-hole wiring forming substrate in the same as above is shown, and is an enlarged view of a main part of FIG. 9 (b).</figref><figref num="11">It is the bottom view of the through hole wiring formation substrate in the same as above.</figref><figref num="12">The cover substrate in the above is shown, (a) is a schematic plan view, and (b) is a schematic cross-sectional view of A-A'in (a).</figref><figref num="13">The wafer level package structure in Embodiment 2 is shown, (a) is a schematic plan view, (b) is a schematic side view, and (c) is a schematic cross-sectional view of an acceleration sensor element.</figref><figref num="14">The acceleration sensor element in the above is shown, (a) is a schematic cross-sectional view of a main part, and (b) is a schematic cross-sectional view of another main part.</figref><figref num="15">The sensor substrate in the above is shown, (a) is a schematic plan view, and (b) is a schematic cross-sectional view.</figref><figref num="16">It is the schematic sectional drawing of the main part of the sensor substrate in the same as above.</figref><figref num="17">The through-hole wiring forming substrate in the above is shown, (a) is a schematic plan view, and (b) is a schematic cross-sectional view of A-A'in (a).</figref><figref num="18">It is the bottom view of the through hole wiring formation substrate in the same as above.</figref><figref num="19">The cover substrate in the above is shown, (a) is a schematic plan view, and (b) is a schematic cross-sectional view.</figref><figref num="20">It is a main process sectional view for demonstrating the manufacturing method of the sensor wafer in the same wafer level package structure.</figref><figref num="21">It is explanatory drawing of the manufacturing method of the wafer level package structure of the conventional example.</figref>

Code description

1 Sensor board (sensor body) 2 Through-hole wiring forming board 3 Cover board 10 Sensor wafer 16 Insulating film 18 First sealing metal bonding metal layer 19 First connecting metal bonding metal layer 20 First package wafer 23 Insulating film 28 Second Encapsulating Bonded Metal Layer 29 Second Connecting Bonded Metal Layer 30 Second Package Wafer 100 Wafer Level Package Structure