Solid imaging apparatus, and its driving method

The present invention relates to a solid-state image sensor and a method for driving the same, and more particularly to an amplified solid-state image sensor and a method for driving the same.

In recent years, as one of the solid-state image pickup devices, an amplification type solid-state image pickup device using a MOS type image sensor has attracted attention. This solid-state image sensor is provided for each cell representing a pixel, includes an amplification transistor that amplifies a signal detected by a photodiode, and has a feature of high sensitivity. In this solid-state image sensor, there is a demand for higher image quality by increasing the number of pixels (megapixels).

Regarding such a solid-state image sensor, in a solid-state image sensor having pixels arranged in two dimensions, a solid-state image sensor capable of selecting / not selecting pixels without providing a transfer selection switch is, for example, a patent. It is proposed in Reference 1.

The solid-state image sensor described in Patent Document 1 will be described below. FIG. 12 is a diagram showing a circuit configuration of the solid-state image sensor described in Patent Document 1.

This solid-state imaging device is composed of a plurality of floating diffusion sections (hereinafter referred to as FD sections) 25 which are directly connected to the gate of the photodiode 21, the readout transistor 22, the reset transistor 23, the amplification transistor 24, the vertical selection transistor 26, and the amplification transistor 24. An image area 504 in which unit cells 20 are arranged in a matrix, a row selection circuit 510 that selects unit cells 20 in row units, and a first unit that transmits the signal voltage of unit cells 20 to the signal processing unit 511 in column units. The vertical signal line 509 of the above, the signal processing unit 511 that holds the signal voltage transmitted through the first vertical signal line 509 and cuts noise, and the column selection circuit 512 that selects the unit cell 20 in column units. It is composed of a horizontal signal line 513 that transmits the signal voltage output from the signal processing unit 511 to the output amplifier 514, an output amplifier 514, and a load transistor group 515.

FIG. 13 is a diagram showing a circuit configuration of the signal processing unit 511. In FIG. 13, vertical signal lines connected to two rows of pixels are shown corresponding to the image area 504 of the solid-state image sensor shown in FIG.

The signal processing unit 511 has a sample hold transistor 601 connected to the first vertical signal line 509, a clamp capacity 602 connected to the first vertical signal line 509 via the sample hold transistor 601 and a clamp capacity 602. A second vertical signal line 603 connected to the first vertical signal line 509 via, a sampling transistor 604 connected to the second vertical signal line 603, and a second vertical signal line via the sampling transistor 604. The sampling capacitance 605 connected to the 603, the clamp transistor 606 connected to the clamp capacitance 602 and the sampling transistor 604, the column selection transistor 607 connected to the second vertical signal line 603, and the horizontal signal line 513 are connected. It is composed of a horizontal signal line capacity of 608.

The sample hold transistor 601 is turned on in response to the application of the sampling pulse that raises the SP line to a high level, and transmits the signal voltage transmitted by the first vertical signal line 509 to the clamp capacitance 602.

The second vertical signal line 603 transmits the signal voltage transmitted from the first vertical signal line 509 via the clamp capacitance 602.

The sampling transistor 604 is turned on in response to the application of the capacitance selection pulse that raises the SW line to a high level, and transfers the signal voltage transmitted by the second vertical signal line 603 to the sampling capacitance 605.

The clamp transistor 606 is turned on in response to the application of the clamp pulse that raises the CP line to a high level, and resets the second vertical signal line 603, the clamp capacitance 602, and the sampling capacitance 605 to the potential of the CLD NC line. To do. The clamp capacitance 602 retains the voltage between terminals A and B at the time of reset, thereby removing fixed pattern noise that differs for each unit cell 20.

The column selection transistor 607 is sequentially turned on in response to the application of the column selection pulse that raises the CSEL line to a high level, and transfers the signal voltage accumulated in the sampling capacitance 605 to the horizontal signal line 513.

The sampling capacity 605 holds the signal voltage read for each row. The operation of the conventional solid-state image sensor as described above will be described with reference to the drive timing chart shown in FIG. 14 (a).

When the unit cell 20 in the m-th row is selected, a row selection pulse (m) that raises the LSET (m) line to a high level is applied to the vertical selection transistor 26 in the unit cell 20 in the m-th row. The vertical selection transistor 26 is turned on, a source follower circuit is formed by the amplification transistor 24 and the load transistor group 515, and the voltage following the pixel power supply of the unit cell 20 is output from the source follower circuit to the first vertical signal line 509. Will be done.

Next, a sampling pulse that raises the SP line to a high level is applied to the sample hold transistor 601. The sample hold transistor 601 is turned on, and the voltage output from the source follower circuit to the first vertical signal line 509 is held in the clamp capacitance 602. At this time, a clamp pulse that raises the CP line to a high level is applied to the clamp transistor 606. The clamp transistor 606 is turned on, and the second vertical signal line 603 side of the clamp capacitance 602 is reset to the potential of the CLD NC line. At the same time, a capacitance selection pulse that raises the SW line to a high level is applied, so that the sampling transistor 604 is turned on and the sampling capacitance 605 is reset to the potential of the CLD NC line.

Next, a reset pulse (m) that raises the RESET (m) line to a high level is applied to the reset transistor 23. The reset transistor 23 is turned on, and the potential of the FD unit 25 is reset. The gate voltage of the amplification transistor 24 connected to the FD section 25 becomes the potential of the FD section 25, and the voltage corresponding to this voltage, specifically, the voltage given by (potential of the FD section -Vt) × α is the first. It is output to the vertical signal line 509 of. Here, Vt is the threshold voltage of the amplification transistor 24, and α is the voltage amplification factor.

Next, a clamp pulse that lowers the CP line to a low level is applied to the clamp transistor 606, the clamp transistor 606 is turned off, and the potential of the second vertical signal line 603 is in a floating state.

Next, a read pulse (m) that raises the READ (m) line to a high level is applied to the read transistor 22. The read transistor 22 is turned on, and the signal charge accumulated in the photodiode 21 is transferred to the FD unit 25. The gate voltage of the amplification transistor 24 connected to the FD section 25 becomes the potential of the FD section 25, and the voltage corresponding to this voltage, specifically, the voltage given by (potential of the FD section -Vt) × α is the first. It is output to the vertical signal line 509 of. At this time, since the clamp pulse that lowers the CP line to the low level is applied to the clamp transistor 606, the clamp transistor 606 is turned off, and the sampling capacitance 605 is set to the first when the potential of the FD section 25 is reset. Voltage corresponding to the difference between the voltage output to the vertical signal line 509 and the voltage output to the first vertical signal line 509 when the signal charge stored in the photodiode 21 is transferred to the FD unit 25. The change is accumulated as the signal voltage of the unit cell 20 in the mth row.

Next, a column selection pulse (m) that raises the CSEL (m) line to a high level, a column selection pulse (m + 1) that raises the CSEL (m + 1) line to a high level, ... Sequentially applied, each column selection transistor 607 is sequentially turned ON, and the signal voltage accumulated in the sampling capacitance 605 is sequentially output to the horizontal signal line 513.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2004-304771</text></patcit>

<p> By the way, in the drive timing of the conventional amplification type solid-state image sensor, coupling to the FD unit occurs in the operation when the readout transistor is ON and OFF. That is, the image quality is deteriorated due to the influence of the coupling of the readout transistor on the vertical signal line.</p><p> The details of the image defect will be described below. FIG. 14 (b) shows that the read pulse applied to the read transistor 22 of the solid-state image sensor shown in FIG. 12 changes from low level to high level or high level in the dark when the signal charge is not accumulated in the photodiode 21. It is a figure which shows the state of the potential change of the FD part 25 and the state of the potential change of the 1st vertical signal line 509 when it changes to a low level.</p><p> As shown in FIG. 14 (b), when the read pulse changes from low level to high level and the read transistor 22 is in the ON state (t in FIG. 14).₁), The potential of the FD section 25 rises due to the coupling to the FD section 25 via the capacitance between the gate and the source of the read transistor 22. As a result, the potential of the first vertical signal line 509 rises through the source follower, and since the sampling pulse is in the high level state in this state, the potential of the second vertical signal line 603 is also changed.</p><p> Further, as shown in FIG. 14 (b), when the read pulse changes from high level to low level and the read transistor 22 is in the OFF state (t in FIG. 14).₂), The potential of the FD section 25 is lowered by the coupling to the FD section 25 via the gate and the source of the read transistor 22. As a result, the potential of the first vertical signal line 509 rises through the source follower, and since the sampling pulse is in the high level state in this state, the potential of the second vertical signal line 603 is also changed.</p><p> That is, in the conventional amplification type solid-state image sensor, the potential of the second vertical signal line 603 changes due to the coupling of the potential change for operating the readout transistor 22. Since the coupling amount of the readout transistor 22 varies in each row, the potential change of the second vertical signal line 603 in each row also varies. Therefore, when the signal components of each column are taken out and output by the column selection circuit 512, the output of each column varies, and as a result, the conventional amplification type solid-state image sensor has a problem of image failure.</p><p> Therefore, in view of such a problem, the present invention is a solid-state image sensor capable of suppressing image defects caused by coupling that occurs during operation of a readout transistor that controls readout of a signal charge from a photodiode, and a method for driving the same. The purpose is to provide.</p>

<p> In order to achieve the above object, the solid-state imaging device of the present invention is an amplification type solid-state imaging device, which includes a photodiode that converts light into a signal charge and stores it, and a readout transistor that reads out the signal charge of the photodiode. A unit cell that outputs an amplified signal corresponding to a signal charge, a signal line connected to the unit cell, a storage element that stores the amplified signal transmitted via the signal line, and the readout. Provided is a transmission prevention means for preventing transmission of the amplified signal of the unit cell to the storage element at either the start of reading the signal charge by the transistor and the end of reading of the signal charge by the read transistor. It is characterized by. Here, the transmission prevention means is a first transmission prevention inserted between the constant voltage source connected to the signal line between the unit cell and the storage element and the constant voltage source and the signal line. It may be a transistor and a first control means for controlling the first transmission prevention transistor.</p><p> Further, the present invention includes a photodiode that converts light into a signal charge and stores it, a readout transistor that reads out the signal charge of the photodiode, and a unit cell that outputs an amplified signal corresponding to the signal charge, and the above-mentioned unit cell. A signal line connected to the unit cell, a storage element that stores the amplified signal transmitted via the signal line, and a constant voltage source connected to the signal line between the unit cell and the storage element. A method for driving an amplification type solid-state imaging device including a first transmission prevention transistor inserted between the constant voltage source and the signal line and a first control means for controlling the first transmission prevention transistor. The first control means is such that the first transmission prevention transistor is turned off at either the start of reading the signal charge by the read transistor and the end of reading of the signal charge by the read transistor. It can also be a driving method of a solid-state imaging device characterized by being controlled.</p><p> As a result, it is possible to suppress the voltage change of the gate of the read transistor from being transmitted to the signal line, and to suppress the influence of the coupling that occurs during the operation of the read transistor from being transmitted to the signal line. Image defects caused by the ring can be suppressed.</p>

<p> According to the present invention, it is possible to suppress image defects caused by coupling that occur during the operation of the readout transistor with a simple circuit configuration. As a result, a low-cost and high-performance solid-state image sensor can be realized, which is particularly useful in a solid-state image sensor that amplifies a signal from a photodiode in a circuit by miniaturizing wiring.</p>

(First Embodiment) Hereinafter, the solid-state image sensor and the driving method thereof according to the first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of an amplification type solid-state image sensor according to the present embodiment. This solid-state imaging device converts light into a signal charge and stores it, a photodiode 11, a readout transistor 12 that reads out the signal charge of the photodiode 11, a reset transistor 13, an amplification transistor 14, and a floating transistor that is directly connected to the gate of the amplification transistor 14. An image consisting of a diffusion section (hereinafter referred to as the FD section) 15 and a vertical selection transistor 16 in which a plurality of unit cells 10-m ... 10-n that output an amplified signal corresponding to a signal charge are arranged in a matrix. A first vertical signal line 109 that is connected to the area 104, the row selection circuit 110 that selects the unit cell 10 in row units, and the unit cell 10, and transmits the signal voltage of the unit cell 10 to the signal processing unit 111 in column units. And a bias current source 116 which is provided for each column of the unit cell 10 and is connected to the first vertical signal line 109 between the unit cell 10 and the signal processing unit 111, and is provided for each column of the unit cell 10. , The coupling control transistor 115 inserted between the bias current source 116 and the first vertical signal line 109, the coupling control circuit 117 that controls the coupling control transistor 115, and the first vertical signal line. The signal processing unit 111 that holds the signal voltage transmitted via 109 and cuts noise, the column selection circuit 112 that selects the unit cell 10 in column units, and the signal voltage output from the signal processing unit 111 are output. It is composed of a horizontal signal line 113 transmitted to the amplifier 114 and an output amplifier 114.

In the image area 104, only two columns of the first pixel row and the second pixel row are shown for convenience. Further, each unit cell 10 is connected to a pixel power supply via a signal line 101.

The coupling control transistor 115 is turned off in response to the application of the coupling control pulse that lowers the CONT line, and the amplification of the row of the corresponding unit cells 10 transmitted by the first vertical signal line 109. Prevents the signal from being transmitted to the signal processing unit 111.

The coupling control circuit 117 prevents transmission of the amplified signal of the unit cell 10 to the signal processing unit 111 at both the start of reading the signal charge by the read transistor 12 and the end of reading the signal charge by the read transistor 12. As a result, the on / off of the coupling control transistor 115 is controlled. That is, the coupling control circuit 117 turns off the coupling control transistor 115 at the start and end of reading the signal charge by the read transistor 12.

The bias current source 116, the coupling control transistor 115, and the coupling control circuit 117 are examples of a constant voltage source, a first transmission prevention transistor, and a first control means, respectively, and constitute a transmission prevention means.

As described above, the solid-state image pickup device according to the first embodiment of the present invention is characterized in that it includes a coupling control circuit 117 as a transmission prevention means in terms of device configuration.

FIG. 2 is a diagram showing a circuit configuration of the signal processing unit 111. In FIG. 2, a vertical signal line connected to two rows of pixels is shown corresponding to the image area 104 of the solid-state image sensor shown in FIG.

The signal processing unit 111 includes a sample hold transistor 201 inserted between the unit cell 10 and the sampling capacitance 205, that is, the first vertical signal line 109 and the second vertical signal line 203, and a sample. A clamp capacitance 202 connected to the first vertical signal line 109 via the hold transistor 201, a second vertical signal line 203 connected to the first vertical signal line 109 via the clamp capacitance 202, and a second. The sampling transistor 204 connected to the vertical signal line 203 of the above is connected to the second vertical signal line 203 via the sampling transistor 204, and is transmitted via the first vertical signal line 109 and the second vertical signal line 203. The sampling capacitance 205 as a storage element for accumulating the amplified signal, the clamp transistor 206 connected to the clamp capacitance 202 and the sampling transistor 204, the column selection transistor 207 connected to the second vertical signal line 203, and the horizontal It is composed of a horizontal signal line capacitance 208 connected to the signal line 113 and a signal processing circuit 209.

The sample hold transistor 201 is turned on in response to the application of the sampling pulse that raises the SP line to a high level, and transmits the signal voltage transmitted by the first vertical signal line 109 to the clamp capacitance 202.

The second vertical signal line 203 transmits the signal voltage transmitted from the first vertical signal line 109 via the clamp capacitance 202.

The sampling transistor 204 is turned on in response to the application of the capacitance selection pulse that raises the SW line to a high level, and transfers the signal voltage transmitted by the second vertical signal line 203 to the sampling capacitance 205.

The clamp transistor 206 is turned on in response to the application of the clamp pulse that raises the CP line to a high level, and resets the second vertical signal line 203, the clamp capacitance 202, and the sampling capacitance 205 to the potential of the CLD NC line. To do. The clamp capacitance 202 retains the voltage between terminals A and B at the time of reset, thereby removing fixed pattern noise that differs for each unit cell 10.

The column selection transistor 207 is sequentially turned on in response to the application of the column selection pulse that raises the CSEL line to a high level, and transfers the signal voltage accumulated in the sampling capacitance 205 to the horizontal signal line 113.

The sampling capacity 205 is provided for each column of the unit cell 10 and stores the signal voltage of the corresponding column of the unit cell 10.

The signal processing circuit 209 applies a pulse to the SP line, the SW line, and the CP line. The operation of the solid-state image sensor according to the first embodiment as described above will be described with reference to the drive timing chart shown in FIG. 3 (a).

When the unit cell 10-m in the mth row is selected, the row selection pulse (m) that raises the LSET (m) line to the high level is the vertical selection transistor 16 in the time domain indicated by A in FIG. 3 (a). The vertical selection transistor 16 is turned on. At this time, since a coupling control pulse that raises the CONT line to a high level is applied to the coupling control transistor 115, a source follower circuit is formed by the amplification transistor 14 and the bias current source 116, and the pixels of the unit cell 10 are formed. The voltage following the power supply is output from the source follower circuit to the first vertical signal line 109.

Further, a sampling pulse that raises the SP line to a high level is applied to the sample hold transistor 201. The sample hold transistor 201 is turned on, and the voltage output from the source follower circuit to the first vertical signal line 109 is held in the clamp capacitance 202. At this time, a clamp pulse that raises the CP line to a high level is applied to the clamp transistor 206. The clamp transistor 206 is turned on, and the second vertical signal line 203 side of the clamp capacitance 202 is reset to the potential of the CLD NC line. At the same time, a capacitance selection pulse that raises the SW line to a high level is applied, so that the sampling transistor 204 is turned on and the sampling capacitance 205 is reset to the potential of the CLD NC line.

Further, a reset pulse (m) that raises the RESET (m) line to a high level is applied to the reset transistor 13. The reset transistor 13 is turned on, and the potential of the FD unit 15 is reset. The gate voltage of the amplification transistor 14 connected to the FD section 15 becomes the potential of the FD section 15, and the voltage corresponding to this voltage, specifically, the voltage given by (potential of the FD section -Vt) × α is the first. It is output to the vertical signal line 109 of. Here, Vt is the threshold voltage of the amplification transistor 14, and α is the voltage amplification factor.

Next, a clamp pulse that lowers the CP line to a low level is applied to the clamp transistor 206, the clamp transistor 206 is turned off, and the potential of the second vertical signal line 203 is in a floating state.

Next, in the time domain indicated by B in FIG. 3 (a), a read pulse (m) that raises the READ (m) line to a high level is applied to the read transistor 12. The readout transistor 12 is turned on, and the signal charge stored in the photodiode 11 is transferred to the FD unit 15. The gate voltage of the amplification transistor 14 connected to the FD section 15 becomes the potential of the FD section 15, and the voltage corresponding to this voltage, specifically, the voltage given by (potential of the FD section -Vt) × α is the first. It is output to the vertical signal line 109 of. At this time, since the clamp pulse that lowers the CP line to the low level is applied to the clamp transistor 206, the clamp transistor 206 is in the OFF state, and the sampling capacitance 205 is the first when the potential of the FD unit 15 is reset. Voltage corresponding to the difference between the voltage output to the vertical signal line 109 and the voltage output to the first vertical signal line 109 when the signal charge stored in the photodiode 11 is transferred to the FD unit 15. The change is accumulated as the signal voltage of the unit cell 10-m in the mth row.

Here, when the read transistor 12 changes from the OFF state to the ON state (t in FIG. 3).₁) And when changing from the ON state to the OFF state (t in Fig. 3)₂), The coupling control pulse is set to a low level and the coupling control transistor 115 is temporarily turned off. Therefore, as shown in FIG. 3 (b), when the read transistor 12 changes from the OFF state to the ON state, the voltage coupling to the FD section 15 that occurs via the parasitic capacitance between the gate and the source of the read transistor 12 Is transmitted to the first vertical signal line 109, but not to the second vertical signal line 203. Further, when the read transistor 12 changes from the ON state to the OFF state, the influence of the voltage coupling on the FD section 15 that occurs via the parasitic capacitance between the gate and the source of the read transistor 12 is also the first vertical signal line 109. Is transmitted to, but is not transmitted to the second vertical signal line 203.

Next, in the time domain indicated by C in FIG. 3 (a), the column selection pulse (m) that makes the CSEL (m) line high level and the column selection pulse (m) that makes the CSEL (m + 1) line high level ( m-1), ... Are sequentially applied to the column selection transistors 207, each column selection transistor 207 is sequentially turned ON, and the signal voltage accumulated in the sampling capacitance 205 is sequentially output to the horizontal signal line 113.

As described above, according to the solid-state image sensor according to the present embodiment, the coupling control pulse is temporarily set to a low level when the readout transistor 12 changes from the OFF state to the ON state and from the ON state to the OFF state. By setting, the coupling control transistor 108 is turned off. Therefore, the voltage change of the gate of the readout transistor 12 is coupled to the FD section 15 via the capacitance between the source and the gate, the potential of the FD section 15 changes, and the potential change passes through the source follower of the FD section 15. It is possible to suppress transmission to the vertical signal line 203 of 2. That is, the influence of the coupling of the FD section 15 is suppressed from being transmitted to the second vertical signal line 203, and the coupling variation of the FD section 15 in each row affects the second vertical signal line 203. Since it can be suppressed, image defects due to coupling can be suppressed. In addition, even when noise reduction is achieved by adding an amplification function such as an amplifier on the vertical signal line to reduce noise, the effect of coupling is not transmitted, so the amplification factor of the signal from the photodiode is higher than before. Can also be increased, which can greatly contribute to noise reduction.

In the solid-state image sensor of the present embodiment, both the start of reading the signal charge by the read transistor 12 and the end of reading the signal charge by the read transistor 12 are sent to the signal processing unit 111 of the amplified signal of the unit cell 10. It is said that the on / off of the coupling control transistor 115 is controlled so as to prevent the transmission of the electric charge. However, the coupling control transistor 115 is turned on / off so that the amplification signal of the unit cell 10 is prevented from being transmitted to the signal processing unit 111 at either the start or the end of the signal charge read by the read transistor 12. May be controlled.

That is, as shown in FIG. 4A, the coupling control transistor 115 is set to the low level temporarily only when the read transistor 12 changes from the OFF state to the ON state. It may be turned off. As a result, as shown in FIG. 4 (b), when the read transistor 12 changes from the OFF state to the ON state, the influence of the coupling of the FD unit 15 is transmitted to the second vertical signal line 203. Since it can be suppressed and the coupling variation of the FD unit 15 can be suppressed from affecting the second vertical signal line 203, image defects due to the coupling can be suppressed.

Further, as shown in FIG. 5A, the coupling control transistor 115 is set to the low level temporarily by temporarily lowering the coupling control pulse only when the read transistor 12 changes from the ON state to the OFF state. It may be turned off. As a result, as shown in FIG. 5 (b), when the read transistor 12 changes from the ON state to the OFF state, the influence of the coupling of the FD unit 15 is transmitted to the second vertical signal line 203. Since it can be suppressed and the coupling variation of the FD unit 15 can be suppressed from affecting the second vertical signal line 203, image defects due to the coupling can be suppressed.

Further, in the solid-state imaging device of the present embodiment, the coupling control transistor 115 is provided on the first vertical signal line 109 between the image area 104 and the signal processing unit 111, but the present invention is not limited to this. It may be provided anywhere on the first vertical signal line 109.

(Second Embodiment) Hereinafter, the solid-state image sensor and the driving method thereof according to the second embodiment of the present invention will be referred to with reference to the drawings, focusing on the differences from the solid-state image sensor of the first embodiment. I will explain while.

FIG. 6 is a diagram showing a circuit configuration of the amplification type solid-state image sensor according to the second embodiment. By controlling the sample hold transistor instead of the coupling control transistor, this solid-state image sensor controls the amplified signal of the unit cell at the start of reading the signal charge by the read transistor and the end of reading the signal charge by the read transistor. It differs from the solid-state image sensor of the first embodiment in that it prevents transmission to the sampling capacitance.

This solid-state imaging device includes an image area 104 in which a plurality of unit cells 10-m ... 10-n are arranged in a matrix, a row selection circuit 110, a first vertical signal line 109, and a first. It consists of a signal processing unit 311 that holds the signal voltage transmitted via the vertical signal line 109 and cuts noise, a column selection circuit 112, a horizontal signal line 113, an output amplifier 114, and a load transistor group 315. Will be done.

FIG. 7 is a diagram showing a circuit configuration of the signal processing unit 311. In FIG. 7, a vertical signal line connected to two rows of pixels is shown corresponding to the image area 104 of the solid-state image sensor shown in FIG.

The signal processing unit 311 is provided for each row of the unit cell 10, and is provided between the signal line between the unit cell 10 and the sampling capacity 205, that is, between the first vertical signal line 109 and the second vertical signal line 203. The inserted sample hold transistor 401, clamp capacitance 202, second vertical signal line 203, sampling transistor 204, sampling capacitance 205, clamp transistor 206, column selection transistor 207, and horizontal signal line capacitance 208. , Signal processing circuit 409.

The sample hold transistor 401 is turned on in response to the application of the sampling pulse that raises the SP line to a high level, and transmits the signal voltage transmitted by the first vertical signal line 109 to the clamp capacitance 202. In addition, it is turned off in response to the application of the sampling pulse that lowers the SP line to the low level, and the amplification signal of the row of the corresponding unit cell 10 transmitted by the first vertical signal line 109 is transmitted to the sampling capacitance 205. To prevent.

The signal processing circuit 409 applies pulses to the SP line, SW line, and CP line. Further, sample hold is performed so that transmission of the amplified signal of the unit cell 10 to the sampling capacitance 205 is prevented at both the start of reading the signal charge by the read transistor 12 and the end of reading the signal charge by the read transistor 12. Controls the on / off of the transistor 401. That is, the signal processing circuit 409 turns off the sample hold transistor 401 at the start and end of reading the signal charge by the read transistor 12.

The sample hold transistor 401 and the signal processing circuit 409 are examples of the second transmission prevention transistor and the second control means, respectively, and constitute the transmission prevention means.

As described above, the solid-state imaging device according to the second embodiment of the present invention is characterized in that it includes a signal processing circuit 409 connected to the sample hold transistor 401 as a transmission prevention means. ..

The operation of the solid-state image sensor according to the second embodiment as described above will be described with reference to the drive timing chart shown in FIG. 3 (a).

When the unit cell 10-m in the mth row is selected, the row selection pulse (m) that raises the LSET (m) line to the high level is the vertical selection transistor 16 in the time domain indicated by A in FIG. 8 (a). Is applied to. The vertical selection transistor 16 is turned on, a source follower circuit is formed by the amplification transistor 14 and the load transistor group 315, and the voltage following the pixel power supply of the unit cell 10 is output from the source follower circuit to the first vertical signal line 109. Will be done.

Further, a sampling pulse that raises the SP line to a high level is applied to the sample hold transistor 401. The sample hold transistor 401 is turned on, and the voltage output from the source follower circuit to the first vertical signal line 109 is held in the clamp capacitance 202. At this time, a clamp pulse that raises the CP line to a high level is applied to the clamp transistor 206. The clamp transistor 206 is turned on, and the second vertical signal line 203 side of the clamp capacitance 202 is reset to the potential of the CLD NC line. At the same time, a capacitance selection pulse that raises the SW line to a high level is applied, so that the sampling transistor 204 is turned on and the sampling capacitance 205 is reset to the potential of the CLD NC line.

Further, a reset pulse (m) that raises the RESET (m) line to a high level is applied to the reset transistor 13. The reset transistor 13 is turned on, and the potential of the FD unit 15 is reset. The gate voltage of the amplification transistor 14 connected to the FD section 15 becomes the potential of the FD section 15, and the voltage corresponding to this voltage is output to the first vertical signal line 109.

Next, a clamp pulse that lowers the CP line to a low level is applied to the clamp transistor 206, the clamp transistor 206 is turned off, and the potential of the second vertical signal line 203 is in a floating state.

Next, in the time domain indicated by B in FIG. 8 (a), a read pulse (m) that raises the READ (m) line to a high level is applied to the read transistor 12. The readout transistor 12 is turned on, and the signal charge stored in the photodiode 11 is transferred to the FD unit 15. The gate voltage of the amplification transistor 14 connected to the FD section 15 becomes the potential of the FD section 15, and the voltage corresponding to this voltage is output to the first vertical signal line 109. At this time, since the clamp pulse that lowers the CP line to the low level is applied to the clamp transistor 206, the clamp transistor 206 is in the OFF state, and the sampling capacitance 205 is the first when the potential of the FD unit 15 is reset. Voltage corresponding to the difference between the voltage output to the vertical signal line 109 and the voltage output to the first vertical signal line 109 when the signal charge stored in the photodiode 11 is transferred to the FD unit 15. The change is accumulated as the signal voltage of the unit cell 10-m in the mth row.

Here, when the read transistor 12 changes from the OFF state to the ON state (t in FIG. 8).₁) And when changing from the ON state to the OFF state (t in Fig. 8)₂), The sunring pulse is set to a low level and the sample hold transistor 401 is temporarily turned off. Therefore, as shown in FIG. 8 (b), when the read transistor 12 changes from the OFF state to the ON state, the voltage coupling to the FD unit 15 that occurs via the parasitic capacitance between the gate and the source of the read transistor 12 Is transmitted to the first vertical signal line 109, but not to the second vertical signal line 203. Further, when the read transistor 12 changes from the ON state to the OFF state, the influence of the voltage coupling on the FD section 15 that occurs via the parasitic capacitance between the gate and the source of the read transistor 12 is also the first vertical signal line 109. Is transmitted to, but is not transmitted to the second vertical signal line 203.

Next, in the time domain indicated by C in FIG. 8 (a), the column selection pulse (m) that makes the CSEL (m) line high level and the column selection pulse (m) that makes the CSEL (m + 1) line high level ( m-1), ... Are sequentially applied to the column selection transistors 207, each column selection transistor 207 is sequentially turned ON, and the signal voltage accumulated in the sampling capacitance 205 is sequentially output to the horizontal signal line 113.

As described above, according to the solid-state image sensor according to the present embodiment, the sampling pulse is temporarily set to a low level when the readout transistor 12 changes from the OFF state to the ON state and from the ON state to the OFF state. As a result, the sample hold transistor 401 is turned off. Therefore, the voltage change of the gate of the readout transistor 12 is coupled to the FD section 15 via the capacitance between the source and the gate, the potential of the FD section 15 changes, and the potential change passes through the source follower of the FD section 15. It is possible to suppress transmission to the vertical signal line 203 of 2. That is, the influence of the coupling of the FD section 15 in each row is suppressed from being transmitted to the second vertical signal line 203, and the coupling variation of the FD section 15 is suppressed from affecting the second vertical signal line 203. Therefore, image defects caused by coupling can be suppressed.

Further, according to the solid-state image sensor according to the present embodiment, the influence of the coupling of the FD unit 15 is transmitted to the second vertical signal line 203 as in the solid-state image sensor of the first embodiment. Since it is not necessary to provide a new transistor for suppression, a low-cost and high-performance solid-state image sensor can be realized.

In the solid-state image sensor of the present embodiment, at both the start of reading the signal charge by the read transistor 12 and the end of reading the signal charge by the read transistor 12, the sampling capacity 205 of the amplified signal of the unit cell 10 is reached. The on / off of the sample hold transistor 401 is controlled so as to prevent transmission. However, the on / off of the sample hold transistor 401 is controlled so that the amplification signal of the unit cell 10 is prevented from being transmitted to the sampling capacitance 205 at either the start or the end of the signal charge read by the read transistor 12. You may.

That is, as shown in FIG. 9A, the sample hold transistor 401 is turned off by temporarily lowering the sampling pulse only when the read transistor 12 changes from the OFF state to the ON state. May be good. As a result, as shown in FIG. 9B, when the read transistor 12 changes from the OFF state to the ON state, the influence of the coupling of the FD unit 15 is transmitted to the second vertical signal line 203. Since it can be suppressed and the coupling variation of the FD unit 15 can be suppressed from affecting the second vertical signal line 203, image defects due to the coupling can be suppressed.

Further, as shown in FIG. 10A, the sample hold transistor 401 is turned off by temporarily lowering the sampling pulse only when the read transistor 12 changes from the ON state to the OFF state. May be good. As a result, as shown in FIG. 10B, when the read transistor 12 changes from the ON state to the OFF state, the influence of the coupling of the FD unit 15 is transmitted to the second vertical signal line 203. Since it can be suppressed and the coupling variation of the FD unit 15 can be suppressed from affecting the second vertical signal line 203, image defects due to the coupling can be suppressed.

(Third Embodiment) Hereinafter, the camera according to the third embodiment of the present invention will be described with reference to the drawings.

FIG. 11 is a block diagram of the camera according to the third embodiment. This camera is a camera using the amplification type solid-state image sensor 1010 of the first and second embodiments, and includes a lens 1000, a solid-state image sensor 1010, a drive circuit 1020, a signal processing unit 1030, and an external device. It consists of an interface section 1040.

In the camera having the above configuration, the processing until the signal is output to the outside is performed in the following order. (1) Light passes through the lens 1000 and enters the solid-state image sensor 1010. (2) The signal processing unit 1030 drives the solid-state image sensor 1010 through the drive circuit 1020, and captures the output signal from the solid-state image sensor 1010. (3) The signal processed by the signal processing unit 1030 is output to the outside through the external interface unit 1040.

As described above, according to the camera of the present embodiment, it is possible to realize a camera provided with a solid-state image sensor capable of suppressing image defects caused by coupling. Therefore, it is possible to realize a camera having excellent image quality.

Although the solid-state image sensor and the driving method thereof of the present invention have been described above based on the embodiments, the present invention is not limited to the embodiments. The scope of the present invention also includes various modifications that can be conceived by those skilled in the art within the scope of the present invention.

For example, the drive timing of the solid-state image sensor may be a combination of the drive timings shown in the first embodiment and the second embodiment.

The present invention can be used for a method for driving a solid-state image sensor, and can be particularly used for an amplified solid-state image sensor and a method for driving the same.

<figref num="1">It is a figure which shows the circuit structure of the amplification type solid-state image sensor which concerns on the 1st practical form of this invention.</figref><figref num="2">It is a figure which shows the circuit structure of a signal processing part.</figref><figref num="3">(a) It is a timing chart for demonstrating the operation of the solid-state image sensor in the same embodiment. (b) It is a figure which shows the state of the potential change of the FD part and the state of the potential change of a vertical signal line.</figref><figref num="4">(a) It is a timing chart for demonstrating the operation of the modification of the solid-state image sensor in the same embodiment. (b) It is a figure which shows the state of the potential change of the FD part and the state of the potential change of a vertical signal line.</figref><figref num="5">(a) It is a timing chart for demonstrating the operation of the modification of the solid-state image sensor in the same embodiment. (b) It is a figure which shows the state of the potential change of the FD part and the state of the potential change of a vertical signal line.</figref><figref num="6">It is a figure which shows the circuit structure of the amplification type solid-state image sensor which concerns on the 2nd practical form of this invention.</figref><figref num="7">It is a figure which shows the circuit structure of a signal processing part.</figref><figref num="8">(a) It is a timing chart for demonstrating the operation of the solid-state image sensor in the same embodiment. (b) It is a figure which shows the state of the potential change of the FD part and the state of the potential change of a vertical signal line.</figref><figref num="9">(a) It is a timing chart for demonstrating the operation of the modification of the solid-state image sensor in the same embodiment. (b) It is a figure which shows the state of the potential change of the FD part and the state of the potential change of a vertical signal line.</figref><figref num="10">(a) It is a timing chart for demonstrating the operation of the modification of the solid-state image sensor in the same embodiment. (b) It is a figure which shows the state of the potential change of the FD part and the state of the potential change of a vertical signal line.</figref><figref num="11">It is a block diagram of the camera which concerns on 3rd Embodiment of this invention.</figref><figref num="12">It is a figure which shows the circuit structure of the conventional solid-state image sensor.</figref><figref num="13">It is a figure which shows the circuit structure of a signal processing part.</figref><figref num="14">(a) It is a timing chart for demonstrating the operation of the conventional solid-state image sensor. (b) It is a figure which shows the state of the potential change of the FD part, and the state of the potential change of the 1st vertical signal line.</figref>

Code description

10, 20 Unit cell 11, 21 Photodiode 12, 22 Read transistor 13, 23 Reset transistor 14, 24 Amplification transistor 15, 25 Floating diffusion section 104, 504 Image area 109, 509 First vertical signal line 110, 510 line selection Circuit 111, 311, 511, 1030 Signal processing unit 112, 512 Column selection circuit 113, 513 Horizontal signal line 114, 514 Output amplifier 115 Coupling control transistor 116 Bias current source 117 Coupling control circuit 201, 401, 601 Sample hold Transistor 202, 602 Clamp capacity 203, 603 Second vertical signal line 204, 604 Sampling transistor 205, 605 Sampling capacity 206, 606 Clamp Transistors 207, 607 Column Selection Transistors 208, 608 Horizontal Signal Line Capacities 315, 515 Load Transistors 209, 409 Signal Processing Circuit 1000 Lens 1010 Solid State Image Sensor 1020 Drive Circuit 1040 External Interface