Solid-state imaging device, method of driving solid-state imaging device and imaging apparatus

The present invention relates to a solid-state image pickup device, a method for driving the solid-state image pickup device, and an image pickup device.

In recent years, CCD (Charge Coupled Device) image sensors and amplification type image sensors, which are known as solid-state image sensors suitable for applications such as video cameras and digital still cameras, are due to an increase in the number of pixels and a reduction in image size with high sensitivity. Pixel size is becoming finer. On the other hand, in general, solid-state image sensors such as CCD image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors tend to be used in various environments such as indoors and outdoors, daytime and nighttime, and changes in outside light. In many cases, it is necessary to perform an electronic shutter operation for adjusting the exposure time by controlling the charge accumulation period in the photoelectric conversion element to optimize the sensitivity.

By the way, in the CMOS image sensor, as a method of expanding the dynamic range, a method of adjusting the exposure time by releasing the electronic shutter at high speed, a method of photographing and superimposing a plurality of frames at high speed, and a photoelectric conversion characteristic of the light receiving part are described. A method of making a logarithmic response is known.

However, for high-contrast shooting scenes where bright and dark areas are mixed, the method of releasing the electronic shutter at high speed does not allow sufficient exposure time, especially in dark areas, that is, in low-light scenes. N deteriorates and the image quality deteriorates. The method of shooting multiple frames at high speed and superimposing them can improve the S / N by superimposing the images compared to the method of simply releasing the electronic shutter, but only the number of readings corresponding to multiple frames Since the reading noise is accumulated, the S / N deteriorates in low light.

Although the method of expanding the dynamic range by the logarithmic response characteristic is effective, the fixed pattern noise due to the variation of the threshold value of the transistor operating in the subthreshold region becomes remarkable especially in the low illuminance region. For example, when shooting a person near a window from a room, if the sensitivity is adjusted to match the person, the view of the window becomes saturated with white and cannot be reproduced. When the sensitivity is adjusted to match the scenery of the window, the person is photographed in a dark state, the signal level cannot be sufficiently secured, and the S / N is lowered. Even if the image is amplified after the image is photographed, high image quality cannot be obtained.

That is, in a certain shooting, it is necessary to realize a high S / N with a long exposure time for a pixel having a small amount of incident light on the image sensor, and to have a wide dynamic range avoiding saturation for a pixel having a large amount of incident light.

Conventionally, the technique described in Non-Patent Document 1 is known as a method of realizing an S / N almost equivalent to a normal operation in a low-light pixel and expanding a dynamic range in a high-light pixel. Specifically, as shown in FIG. 40, transfer is performed in an amplification type image sensor in which pixels 100 having a photodiode 101, a transfer transistor 102, a reset transistor 103, an amplification transistor 104, and a selection transistor 105 are arranged in a matrix. When the transistor 102 is turned off, the voltage applied to the control electrode is not the level at which it is completely turned off as usual, but the level Vtrg that overflows the surplus to the FD section 106 if electrons are accumulated above a certain level. Set to.

When electrons accumulate in the photodiode 101 and exceed the level Vtrg, leakage to the FD section 106 begins in the subthreshold region. Since this leak operates in the subthreshold region, the number of electrons remaining in the photodiode 101 is a logarithmic response.

As shown in FIG. 41, after the reset operation in the period t0, the accumulation is executed while the voltage Vtrg is applied to the control electrode of the transfer transistor 102. In the state of the period t1 where the number of stored electrons is small, all the electrons are retained in the photodiode 101, but when the number of stored electrons exceeds the level of Vtrg, the electrons start leaking to the FD section 106 as in the period t2.

Since there is a leak in the subthreshold region, electrons are accumulated with logarithmic characteristics with respect to the incident light intensity even if the accumulation is continued (t3). In the period t4, the electrons overflowing to the FD unit 106 are reset, and all the electrons held in the photodiode 101 are read out by complete transfer. The relationship between the incident light intensity and the number of output electrons at this time is shown in FIG. For incident light with an intensity that exceeds the upper limit Qlinear of the linear region set by the voltage Vtrg, the number of output electrons is determined by the logarithmic response.

<nplcit num="1"><text>IEEE International Solid-State Circuits Conference (ISSCC) 2005, pp.354, Feb.2005</text></nplcit>

<p> However, in the prior art described in Non-Patent Document 1, it is reported that a dynamic range of 124 dB is realized, but the saturation level in the linear region that can realize a high S / N is reported to be the normal saturation level Qs. It is less than half. In addition, although a very wide dynamic range is realized by logarithmic response, since it is a logarithmic response circuit that is susceptible to threshold variation, etc., a threshold variation canceling operation is executed for a fixed pattern noise of 0.8 mV in the linear region. However, a large fixed pattern noise of 5 mV in the logarithmic region remains in the wide dynamic range region.</p><p> Therefore, the present invention enables linear and high S / N signal acquisition without narrowing the normal saturation level in low illuminance, and is good in the linear region even for incident light above the normal saturation level. It is an object of the present invention to provide a solid-state image sensor capable of expanding the dynamic range while realizing S / N, a driving method of the solid-state image sensor, and an image pickup device.</p>

<p> In order to achieve the above object, in the present invention, unit pixels including a photoelectric conversion element that converts an optical signal into a signal charge and a transfer gate that transfers the signal charge photoelectrically converted by the photoelectric conversion element are arranged in a matrix. In a dimensionally arranged solid-state imaging device, a plurality of control voltages are sequentially supplied to the control electrodes of the transfer gate, and when the plurality of control voltages are sequentially supplied, the signal charge transferred by the transfer gate is supplied twice or more. It has a read-out configuration.</p><p> A plurality of control voltages are sequentially supplied to the control electrodes of the transfer gate, and at that time, the signal charges transferred by the transfer gate are read out twice or more, and the signal based on these read signal charges is read in advance in, for example, in the signal processing system in the subsequent stage. By clipping and adding at the set saturation level, it is possible to acquire signals linearly and at high S / N without narrowing the normal saturation level in low light, and for incident light above the normal saturation level. The dynamic range can be expanded while achieving good S / N in the linear region.</p>

<p> According to the present invention, it is possible to acquire a signal linearly and at a high S / N without narrowing the normal saturation level in low illuminance, and it is also good in the linear region even for incident light above the normal saturation level. Since the dynamic range can be expanded while achieving S / N, it is possible to acquire high-quality images with high S / N in low-light scenes against changes in external light under various environments. At the same time, it is possible to acquire images with low saturation in high-light scenes with high image quality by linear response, and even in high-contrast scenes where low-light and high-light are mixed, high-light while maintaining high S / N in low-light areas. Partial saturation can be avoided.</p>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system configuration diagram showing a configuration of a solid-state image sensor, for example, a CMOS image sensor according to an embodiment of the present invention.

As shown in FIG. 1, in the CMOS image sensor 10 according to the present embodiment, unit pixels (hereinafter, may be simply referred to as pixels) 20 including a photoelectric conversion element are two-dimensionally arranged in a matrix shape. In addition to the pixel array unit 11, the peripheral circuits include a vertical scanning circuit 12, a supply voltage control circuit 13, a voltage supply circuit 14, a timing generation circuit (TG) 15, a plurality of column circuits 16, a horizontal scanning circuit 17, and the like. It has a configuration having a column signal selection circuit 18.

A vertical signal line 111 is wired for each column with respect to the matrix array of pixels 20 of the pixel array unit 11, and a drive control line, for example, a transfer control line 112, a reset control line 113, and a selection control line 114 are wired for each row. Has been done. Further, a reset line 115 for supplying a reset voltage Vrst is wired to each of the unit pixels 20.

(Unit Pixel) FIG. 1 shows an example of the circuit configuration of the unit pixel 20. The unit pixel 20 according to this circuit example is a pixel circuit having four transistors, for example, a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25, in addition to a photoelectric conversion element, for example, a photodiode 21. .. Here, for example, N-channel MOS transistors are used as the transistors 22 to 25.

The transfer transistor 22 corresponds to a transfer gate within the scope of the patent claim, is connected between the cathode electrode of the photodiode 21 and the FD unit (floating diffusion unit) 26 which is a charge-voltage conversion unit, and is photoelectrically converted by the photodiode 21. Then, the signal charge (electrons in this case) accumulated here is transferred to the FD unit 26 by applying the transfer pulse TRG to the gate electrode (control electrode).

The reset transistor 23 has a drain electrode connected to the reset line 115 and a source electrode connected to the FD section 26, and a reset pulse RST is given to the gate electrode prior to the transfer of the signal charge from the photodiode 21 to the FD section 26. This resets the potential of the FD unit 26 to the reset voltage Vrst.

The amplification transistor 24 has a gate electrode connected to the FD section 26 and a drain electrode connected to the pixel power supply Vdd, and outputs the potential of the FD section 26 after being reset by the reset transistor 23 as a reset level, and is further output by the transfer transistor 22. The potential of the FD unit 26 after the signal charge is transferred is output as the signal level.

The selection transistor 25 is turned on by, for example, the drain electrode is connected to the source electrode of the amplification transistor 24 and the source electrode is connected to the vertical signal line 111, and the selection pulse SEL is given to the gate electrode, and the pixel 20 is selected. The signal output from the amplification transistor 24 is output to the vertical signal line 111.

The selection transistor 25 may be configured to be connected between the pixel power supply Vdd and the drain electrode of the amplification transistor 24.

The vertical scanning circuit 12 is composed of a shift register, an address decoder, or the like, and by appropriately generating a reset pulse RST, a transfer pulse TRG, a selection pulse SEL, or the like, each pixel 20 of the pixel array unit 11 is read out as an electronic shutter line. While scanning each row in the vertical direction (vertical direction), the electronic shutter operation is performed for the electronic shutter row to sweep out the signal of the pixel 20 of the row, and the read row is subjected to the electronic shutter operation. The read operation for reading the signal of the pixel 20 of the row is performed.

Although not shown here, the vertical scanning circuit 12 includes a read scanning system for performing a read operation for reading the signal of each pixel 20 in the read row while sequentially selecting the pixels 20 in line units, and the read scan. It is configured to have an electronic shutter scanning system for performing an electronic shutter operation on the same row (electronic shutter row) by a time corresponding to the shutter speed before the readout scanning by the system.

The period from the timing when the unnecessary charge of the photodiode 21 is reset by the shutter scanning by the electronic shutter scanning system to the timing when the signal of the pixel 20 is read by the readout scanning by the readout scanning system is the period of the signal charge in the pixel 20. It becomes the accumulation period (exposure period). That is, the electronic shutter operation is an operation in which the signal charge accumulated in the photodiode 21 is reset (swept away), and after the reset, the accumulation of the signal charge is newly started.

The supply voltage control circuit 13 controls the control voltage supplied (applied) to the gate electrode (control electrode) of the transfer transistor 22 in the unit pixel 20. The specific configuration of the supply voltage control circuit 13 will be described later.

The voltage supply circuit 14 has a plurality of voltages (control voltages) having different voltage values with respect to the supply voltage control circuit 13, specifically, a high level (hereinafter, "" H level) which is the voltage level of the pixel power supply Vdd. It supplies an intermediate voltage (hereinafter sometimes referred to as "intermediate voltage") between the low level (hereinafter referred to as "L" level ") which is the ground level (hereinafter referred to as" L "level"). Here, the intermediate voltage (intermediate voltage) is a voltage that can partially transfer the remaining accumulated charge to the FD unit 26 while retaining a part of the charge accumulated in the photodiode 21.

The timing generation circuit (TG) 15 generates timing signals PTRG1, PTRG2, PTRG3 (see FIG. 2) that determine the timing when the supply voltage control circuit 13 supplies the control voltage to the gate electrode of the transfer transistor 22.

The column circuit 16 is arranged in the pixel array unit 11, for example, for each pixel row, that is, in a one-to-one correspondence with respect to the pixel row, and from each pixel 20 of the read row selected by vertical scanning by the vertical scanning circuit 12. A predetermined signal processing is performed on the signal output through the vertical signal line 111, and the pixel signal after the signal processing is temporarily held.

The column circuit 16 includes a circuit configuration including a sample hold circuit for sample-holding a signal output through the vertical signal line 111 and a sample-hold circuit, and is subjected to CDS (Correlated Double Sampling) processing. , A circuit configuration including a noise removing circuit for removing fixed pattern noise peculiar to a pixel such as reset noise and threshold variation of the amplification transistor 24 is used. However, these are only examples, and are not limited to these. For example, it is possible to provide the column circuit 16 with an A / D (analog / digital) conversion function and adopt a configuration in which the signal level is output as a digital signal.

The horizontal scanning circuit 17 is composed of a shift register, an address decoder, or the like, and horizontally scans the column circuits 16 arranged for each pixel row of the pixel array unit 11 in order. The column signal selection circuit 18 is composed of a horizontal selection switch, a horizontal signal line, and the like, and sequentially outputs the signals of the pixels temporarily held in the column circuit 16 in synchronization with the horizontal scanning by the horizontal scanning circuit 17.

A constant current source 19 is connected to each end of the vertical signal line 111. It is also possible to use, for example, a biased transistor instead of the constant current source 19. Further, timing signals and control signals that serve as reference for the operation of the vertical scanning circuit 12, the timing generation circuit 15, the column circuit 16, the horizontal scanning circuit 17, and the like are generated by a timing control circuit (not shown).

(Supply voltage control circuit) The supply voltage control circuit 13 receives an address signal ADR that drives a row selected and scanned by the vertical scanning circuit 12 as an input, and a plurality of first control voltages supplied from the voltage supply circuit 14, for example, 4 One of the two voltages Vtrg1, Vtrg2, Vtrg3, Vtrg4 (Vtrg1&gt; Vtrg2&gt; Vtrg3&gt; Vtrg4) is selected based on the timing signals PTRG1, PTRG2, PTRG3 supplied from the timing generation circuit 15 and within the unit pixel 20. It is supplied to the gate electrode of the transfer transistor 22 of.

FIG. 2 is a circuit diagram showing an example of the configuration of the supply voltage control circuit 13. As shown in FIG. 2, the supply voltage control circuit 13 according to this example includes four circuit blocks 131 to 134 corresponding to four voltages (intermediate voltages) Vtrg1, Vtrg2, Vtrg3, and Vtrg4, and a three-input NOR circuit 135. It has a structure having and. The address signal ADR is commonly given to the circuit blocks 131 to 134 from the vertical scanning circuit 12. Timing signals PTRG1, PTRG2, and PTRG3 are given to the NOR circuit 135 as three inputs from the voltage supply circuit 14.

The circuit block 131 is composed of a NAND circuit 1311, which has two inputs of an address signal ADR and a timing signal PTRG1, a level shifter 1312, and a P-channel drive transistor 1313, and selects a voltage Vtrg1 higher than the power supply voltage of the logic circuit section. It is supplied to the gate electrode of the transfer transistor 22.

The circuit block 132 is composed of an AND circuit 1321 having two inputs of an address signal ADR and a timing signal PTRG2 and a drive transistor 1322 of a P channel, and is equal to or lower than the power supply voltage of the logic circuit section and higher than the ground voltage. A voltage Vtrg2 higher than the threshold of the facsimile transistor is selected and supplied to the gate electrode of the transfer transistor 22.

The circuit block 133 is composed of a NAND circuit 1331 having two inputs of an address signal ADR and a timing signal PTRG3 and an N channel drive transistor 1332, and is equal to or higher than the ground voltage of the logic circuit section and higher than the power supply voltage. A voltage Vtrg4, which is lower than the threshold of the NMOS transistor, is selected and supplied to the gate electrode of the transfer transistor 22.

The circuit block 134 has an AND circuit 1341 having two inputs of the address signal ADR and the output signal of the NOR circuit 135, and an OR having the address signal ADR as one (negative) input and the output signal of the AND circuit 1341 as the other input. It consists of a circuit 1342, a level shifter 1343 and an N-channel drive transistor 1344, and selects a voltage Vtrg4 lower than the ground voltage to supply to the gate electrode of the transfer transistor 22.

In this circuit block 134, in order to supply a voltage lower than the ground voltage, for example, -1.0V as a voltage for turning off the transfer transistor 22, the NOR circuit 135 acts exclusively from the other circuit blocks 131, 132, 133. It has a circuit configuration that works.

FIG. 3 shows the input / output timing relationship of the supply voltage control circuit 13. When the voltage supplied to the gate electrode of the transfer transistor 22 is Vtrg1, Vtrg2, Vtrg3, Vtrg4, when a row is selected by the address signal ADR, the corresponding voltage Vtrg1 is used by the timing signals PTRG1, PTRG2, PTRG3. , Vtrg2, Vtrg3 are supplied, and the voltage Vtrg4 is supplied otherwise.

Subsequently, the operation of the CMOS image sensor 10 according to the present embodiment having the above configuration will be described with reference to the timing chart of FIG. In FIG. 4, (A) shows the timing relationship of each operation in the case of normal reading, and (B) shows the timing relationship of each operation in the case of high S / N and wide dynamic range.

In the CMOS image sensor 10 in which the unit pixels 20 of the pixel circuit configuration shown in FIG. 1 are arranged in a matrix, generally, as shown in FIG. 4 (A), the transfer pulse TRG and the reset pulse RST are generated in the period t1. When both reach the "H" level, the photodiode 21 and the FD unit 26 are reset, and the light received in the period t2 is photoelectrically converted into electrons and stored in the photodiode 21. In addition, the reset pulse RST resets the FD section 26 when it reaches the H level in the latter half of the period t2, and then the potential of the FD section 26 resets when the selection pulse SEL reaches the H level. Read as a level, and then transfer the electrons stored in the photodiode 21 to the FD section 26 when the transfer pulse TRG becomes H level at t3, and then the selection pulse SEL becomes H level. The potential of the FD unit 26 is read out as a signal level in the period t5.

In contrast to this normal readout operation, the present invention applies a plurality of control voltages during the storage period (exposure period) in which electrons are accumulated by photoelectric conversion for the purpose of achieving high S / N and wide dynamic range. The control electrode (gate electrode) of the transfer transistor 22 is sequentially supplied, and at that time, the signal charge transferred by the transfer transistor 22 is read out twice or more.

Specifically, as shown in FIG. 4 (B), the photodiode 21 and the FD section 26 are reset when the transfer pulse TRG and the reset pulse RST both reach the H level in the period t10, and the light is received in the period t11. The generated light is photoelectrically converted into electrons and stored in the photodiode 21. Then, in the latter half of the period t11, the reset pulse RST resets the FD section 26 when it reaches the H level, and then the selection pulse SEL resets the potential of the FD section 26 when it reaches the H level. Read as a level.

Next, in the period t13, the voltage Vtrg1 is supplied to the control electrode of the transfer transistor 22, and the voltage Vtrg1 is partially transferred to the FD unit 26 according to the amount of stored electrons of the photodiode 21 determined by the incident light intensity. In the period t14, the potential of the FD unit 26 corresponding to the amount of electrons transferred when the selected pulse SEL becomes the H level is read out as a signal level, and if necessary, the reset level read out in the period t12 is used. Therefore, for example, noise canceling processing is performed in the column circuit 16.

In the period t15, the accumulation operation is continuously executed, and in the period t16, the FD section 26 is reset again when the reset pulse RST becomes the H level, and then the reset level when the selected pulse SEL becomes the H level. Is read. Further, the voltage Vtrg2 is supplied to the control electrode of the transfer transistor 22 in the period t17, and the sum of the electrons remaining in the photodiode 21 without being transferred in the period t13 and the electrons accumulated in the period t15 is transferred by the voltage Vtrg2. The portion exceeding the potential of the transistor 22 is transferred to the FD unit 26, and the potential of the FD unit 26 is read out as a signal level when the selected pulse SEL becomes the H level in the period t18.

From the period t19 to the period t22, the supply voltage to the control electrode of the transfer transistor 22 is set to Vtrg3, and the same operation is repeated. Further, the operation from the period t11 to the period t14 is executed once or a plurality of times while changing the supply voltage to the transfer transistor 22. Then, after the exposure in the period t23, the reset operation is performed again when the reset pulse RST becomes the H level in the period t24, the reset level is read out when the selected pulse SEL becomes the H level, and then the reset level is read out in the period t25. Then, when the transfer pulse TRG becomes H level, the transfer transistor 22 is completely turned on to execute complete transfer to the FD unit 26, and when the selected pulse SEL becomes H level in the period t26, the signal level Is read.

Here, FIG. 5 shows an example of the potential in the pixel when the voltages Vtrg1, Vtrg2, and Vtrg3 are supplied to the control electrode of the transfer transistor 22. When the number of electrons stored in the photodiode 21 is large and exceeds the potential Φtrgi due to the voltage Vtrg1, the electrons stored in the photodiode 21 are partially transferred to the FD unit 26.

FIG. 6 is a potential diagram showing an example of a potential change when a voltage Vtrg is gradually supplied when the incident light is weak. When the number of electrons stored in the photodiode 21 is small, the potential Φtrgi of the transfer transistor 22 is not exceeded, so the electrons generated by the photoelectric conversion are held in the photodiode 21 and transferred to the FD unit 26 in the final complete transfer. And read out as a signal level.

On the other hand, as shown in FIG. 7, when the incident light is strong, the electrons exceeding the potential Φtrgi are transferred to the FD unit 26 and sequentially read out as a signal level. As a result, in low illuminance, it is possible to read out by complete transfer after a sufficient exposure time without signal deterioration, and in high illuminance, by reading out the surplus step by step, a composite image with a wide dynamic range is finally created. can do.

The operation periods t10 to t26 in FIGS. 6 and 7 correspond to the operation periods t10 to t26 in the timing chart of FIG. 4 (A), respectively.

In this way, when a plurality of voltages Vtrg1, Vtrg2, Vtrg3 are supplied stepwise to the control electrode of the transfer transistor 22 and surplus electrons are transferred to the FD unit 26 multiple times, the threshold variation is canceled in the second and subsequent transfers. To. This is due to the following reasons.

As shown in FIG. 8, the potential of the transfer transistor 22 when the voltage Vtrg1 is applied to the control electrode of the transfer transistor 22 in the first transfer is φ._trg1, The potential of the photodiode 21 before charge accumulation is φ_had0, Q the number of electrons held in the photodiode 21_HAD1, Q the number of electrons overflowing to FD section 26_FD1, Number of electrons Q_HAD1The potential of the photodiode 21 when holding_had1And. Assuming that the photocurrent generated by the photodiode 21 in proportion to the incident light intensity is Ipd, the exposure time until the first transfer is ΔT, and the capacitance of the photodiode 21 is Cpd, Q_HAD1And Q_FD1Is expressed by the following formula.

Q_HAD1= Cpd φ_had1 Q_FD1= Ipd ΔT-Q_HAD1 φ_had1= φ_had0-φ_trg1 φ_trg1= Vtrg1-(Vth + ΔVth) where Vth is the threshold value of the transfer transistor 22, and ΔVth is the threshold variation of the transfer transistor 22.

In the second transfer in which a different voltage Vtrg2 was applied after further exposure for ΔT time and accumulating photocurrent, the potential of the transfer transistor 22 was similarly set to φ._trg2, Q the number of electrons held in the photodiode 21_HAD2, Q the number of electrons overflowing to FD section 26_FD2, Number of electrons Q_HAD2The potential of the photodiode 21 when holding_had2Then, it is expressed by the following formula.

Q_HAD2= Cpd φ_had2 φ_had2= φ_had0-φ_trg2 φ_trg2= Vtrg2-(Vth + ΔVth) Q_FD2= (Q_HAD1+ Ipd ΔT) -Q_HAD2 = Cpd φ_had1+ Ipd ΔT-Cpd φ_had2 = Cpd (φ_had0-φ_trg1) + Ipd ΔT -Cpd (φ_had0-φ_trg2) = Cpd φ_trg1+ Ipd ΔT-Cpd φ_trg2 = Cpd {Vtrg1-(Vth + ΔVth)} + Ipd ΔT -Cpd {Vtrg2- (Vth + ΔVth)} = Ipd ΔT-Cpd (Vtrg2-Vtrg1)

In this way, after the second transfer, the number of electrons intermediately transferred to the FD unit 26 is applied immediately before the incident light intensity, that is, the generated photoelectric flow rate and the voltage Vtrg2 applied to the control electrode of the transfer transistor 22. It is determined by the difference from the obtained voltage Vtrg1, and it is possible to reduce the influence of the threshold variation ΔVth of the transfer transistor 22. Further, since the number of electrons transferred via the transfer transistor 22 at each timing has a phase, the number of residual electrons that cannot be transferred within the transfer period due to the number of electrons exceeding the potential also has a phase. After the second time, the variation due to residual electrons is also reduced.

Here, the level of the voltage Vtrg supplied to the control electrode of the transfer transistor 22 is determined as follows.

As shown in FIG. 9, the number of stored electrons in the photodiode 21 increases in proportion to the exposure time when the amount of incident light is constant. For example, assuming an incident light intensity that reaches saturated electron count Qs at a reference exposure time Ts such as 1/30 seconds for 30 frames per second and 1/60 seconds for 60 frames per second, the control electrode of the transfer transistor 22 Estimate the number of stored electrons Nei at the timing Ti when the voltage Vtrg is supplied to. The supply voltage Vtrgi at the timing Ti is set as a voltage that can hold the stored electron number Nei in the photodiode 21.

FIG. 10 shows the experimental results of the supply voltage Vtrg to the control electrode of the transfer transistor 22 in the photodiode 21 having a saturated electron number Qs of 8800e- and the number of electrons held by the photodiode 21 when the voltage Vtrg is supplied. Is shown.

In this case, the supply voltage at the timings T1, T2, and T3 becomes the voltage Vtrg1, Vtrg2, Vtrg3 from the number of stored electrons Ne1, Ne2, Ne3 in FIG. The voltage actually supplied is several hundred mV lower if the transfer transistor 22 is an N-channel MOS transistor, and the number if it is a P-channel MOS transistor, as a margin to prevent leakage due to thermal diffusion from the photodiode 21 to the FD section 26. It is more preferable to apply a voltage 100 mV higher.

FIG. 11 shows another example of the supply timing of the voltage supplied to the control electrode of the transfer transistor 22.

In this other example, the voltage Vtrg1 is supplied at the timing of 1/4 of the exposure time until the complete transfer, and the voltage Vtrg3 is supplied at the timing of 3/4. The method of determining the respective voltages Vtrg1 and Vtrg3 is the same as in the above case.

By controlling the supply interval of the voltages Vtrg1 and Vtrg3 in this way, the relationship between the number of electrons in the intermediate transfer with respect to the incident light intensity, that is, the sensitivity can be controlled. That is, by setting each intermediate transfer execution interval to a plurality of intervals, a wide dynamic range can be achieved with a plurality of sensitivities, and the S / N is relatively high even in a wide dynamic range region where the light intensity is relatively weak. Can be set.

For example, as shown in FIG. 11, the exposure time (t31) from the first intermediate transfer to the second intermediate transfer is one-fourth of the total, and the exposure time (t35) from the first intermediate transfer to the second intermediate transfer is the total. If it is halved, the sensitivity of the number of read electrons to the incident light intensity is halved in the first transfer, which contributes to the expansion of the dynamic range.

On the other hand, in the second transfer, the sensitivity is halved and the dynamic range is narrower than in the first transfer, but the S / N is higher than in the area due to the first transfer up to about twice the normal area. realizable. In the final complete transfer, the sensitivity and dynamic range are one times higher than usual, that is, the same sensitivity and dynamic range as the incident light intensity, and the deterioration of image quality in the low illuminance region due to the wide dynamic range is avoided.

FIG. 12 shows yet another example of the supply timing of the voltage supplied to the control electrode of the transfer transistor 22.

In this example, at any one or more times of the voltage Vtrgi supplied multiple times, the reset operation is performed without reading the transferred signal level. This operation can be realized by moving to the reset operation immediately after the transfer without activating the selection signal. By this operation, when a signal in which the variation in the number of transferred electrons due to the threshold variation is reduced is obtained as described above, the read operation in the first transfer with a large variation can be omitted.

Further, by not executing the read operation, the transfer interval can be shorter than the frame rate of the CMOS image sensor 10, which can contribute to the expansion of the dynamic range. For example, in FIG. 12, the voltage Vtrg1 is supplied at a timing of 1/8 of the exposure time until the complete transfer, and is reset without being read. The voltage Vtrg2 is supplied at the timing of 1/4, and the signal level is read out. Next, the voltage Vtrg3 is supplied at the timing of 3/4, the signal level is read, and finally the signal level is read by complete transfer.

Of the three read operations performed in total, the first read transferred by the voltage Vtrg2 has an output equivalent to 1/8 of the exposure time, so it has a dynamic range of up to about 8 times. It can be secured, and the threshold variation is reduced by the transfer by the voltage Vtrg1 immediately before. In the second read with the voltage Vtrg3, since the transfer interval is 1/2, a signal with a higher S / N than the first read can be obtained with a dynamic range of about twice the saturation level.

In this example, the dynamic range is expanded about 8 times, but the read speed is 4 times faster than usual. Similarly, the dynamic range can be expanded by bringing the supply timing of the voltage Vtrg1 closer to the supply timing of the voltage Vtrg2. Further, as in the example of FIG. 12, in addition to the operation of FIG. 4A, it is possible to reset the electrons of the FD unit 26 in advance by executing the reset operation immediately after the transfer or the reading of the signal level. ..

Here, as shown in FIG. 13, the signal obtained by the plurality of intermediate transfers is clipped and added at a preset saturation level to obtain continuous input / output characteristics. For example, in FIG. 13, the result of the complete transfer in the normal exposure, which is the i-th readout, is output at a high S / N up to the normal saturation level, and the exposure time is halved in the previous i-1th transfer. The dynamic range of about 2 times is possible by the intermediate transfer with, and the dynamic range of about 8 times is possible by the intermediate transfer of the exposure time at 1/8 in the i-2nd transfer. By clipping and adding together, continuous characteristics can be obtained.

The processing of high S / N and wide dynamic range by performing such clipping and addition was read out a plurality of times in, for example, a signal processing circuit (not shown) provided in the subsequent stage of the CMOS image sensor 10. It will be executed by using the frame memory that stores the image.

However, this processing example is only an example, and if the image read multiple times is saved, it can be processed by a personal computer or the like, and the frame memory should be mounted on the CMOS image sensor 10. Therefore, it is also possible to adopt a configuration in which only the final image is output by processing on the image sensor 10.

Figure 14 shows the experimental results. In this experiment, in the timing chart of FIG. 12, the voltage Vtrg1 was set to 0.6V, the voltage Vtrg2 was set to 1.1V, and the voltage Vtrg3 was set to 1.3V, and the voltage was supplied to the control electrode of the transfer transistor 22.

In FIG. 14, assuming that the exposure time from the reset of the photodiode 21 to the complete transfer is about 16 ms, the intermediate transfer by the first voltage Vtrg1 is performed 2 ms after the reset of the photodiode 21, and the intermediate transfer by the second voltage Vtrg2 is performed 4 ms later. It shows the number of electrons remaining in the photodiode 21 when the third intermediate transfer is executed after 12 ms.

In FIG. 14, t1, t3, t5, t7 are the exposure period, and t2, t4, t6 are the transfer period. The time during which the voltage Vtrg is applied to the control electrode of the transfer transistor 22 is 100 ns. Graphs 40 to 51 show that the total number of electrons generated by the photodiode 21 during 16 ms is 350e-, 1200e-, 2200e-, 4400e-, 6600e-, 8800e-, 11000e-, 17500e-, 25000e-, 35000e-. It is a condition that light having an intensity of, 44000e-, 53000e- is incident on the photodiode 21. The transfer period is preferably a sufficient time so that the transfer approaches an equilibrium state, and more preferably 100 ns or more.

FIG. 15 is a diagram showing the relationship between the total number of generated electrons indicating the incident light intensity in the experiment and the number of electrons transferred as an output in each intermediate transfer and the final complete transfer. In FIG. 15, graph 60 is the number of electrons transferred by the voltage Vtrg1, and the error bar is the value when the threshold value of the transfer transistor 22 is varied by ± 50 mV.

In the first transfer, the variation in the number of transferred electrons is large due to the variation in the threshold value, but in the transfer result 61 by the second voltage Vtrg2, the variation in the number of electrons is reduced. The third transfer result 62 by the voltage Vtrg3 has a higher sensitivity and a larger gradient because the transfer period is longer than the transfer by the voltage Vtrg2. Result 63 with full transfer has the same S / N as normal transfer without intermediate transfer in low light. Results 61 and 62 have gradients of 1/2 times and 1/8 times that of results 63, respectively, and it can be confirmed that sensitivity control and wide dynamic range can be realized by controlling the transfer timing. Result 63 is a wide dynamic range characteristic obtained by the method of characteristic synthesis. It achieves high S / N in low illuminance and wide dynamic range with linear characteristics.

As described above, for example, in the CMOS image sensor 10 in which the unit pixels 20 including the photodiode 21 and the transfer transistor 22 for transferring the signal charge photoelectrically converted by the photodiode 21 are two-dimensionally arranged in a matrix, the transfer is performed. A plurality of first control voltages are sequentially supplied to the control electrodes of the transistor 22 from the supply voltage control circuit 13, and the signal charge transferred by the transfer transistor 22 at that time is read out twice or more by the vertical scanning circuit 12. In addition to enabling linear and high S / N signal acquisition in low light without narrowing the normal saturation level, it also achieves good S / N in the linear region even for incident light above the normal saturation level. While expanding the dynamic range.

This makes it possible to acquire high-quality images with high S / N in low-light scenes against changes in outside light in various environments such as indoors and outdoors, daytime and nighttime, and also high-lightness. Images with low saturation can be acquired with high image quality by linear response, and even in high-contrast scenes where low-light and high-light are mixed, saturation of high-light parts is maintained in low-light areas while maintaining high S / N. It can be avoided.

In addition, even when highly sensitive pixels are arranged in a normal pixel array for the purpose of increasing sensitivity, it is not necessary to adjust the exposure time to the high sensitivity pixels to deteriorate the S / N of the normal pixels, which is usually the case. A high S / N image of high-sensitivity pixels can be obtained according to the proper exposure of the pixels, which is advantageous for the processing of high image quality in the subsequent stage.

In the above embodiment, the case where the unit pixels 20 including the selection transistor 25 (see FIG. 1) are arranged in a matrix has been described, but the present invention is limited to this application example. is not it.

That is, in the CMOS image sensor 10 according to the present invention, the electrons transferred to the FD unit 26 can be reset before the next exposure period regardless of whether or not there is a read operation immediately after the selection transistor 25. The same applies to a CMOS image sensor in which unit pixels that are not included are arranged in a matrix.

Specifically, as shown in FIG. 16 (A), in addition to the photodiode 21, it has three transistors, a transfer transistor 22, a reset transistor 23, and an amplification transistor 24, and the FD unit 26 is passed through the reset transistor 23. Is also applicable to a CMOS image sensor having a unit pixel of a pixel circuit in which the potential of is set to a potential lower than the threshold value of the amplification transistor 24, that is, the selective power supply potential SEL VDD and the unit pixel is not selected.

Further, as shown in FIG. 16B, similarly, in a pixel circuit having three transistors of a transfer transistor 22, a reset transistor 23 and an amplification transistor 24, and one switch transistor 27 in addition to the photodiode 21. Applicable. In this pixel circuit, since the reset voltage Vrst is selectively supplied from the vertical signal line 111, the reset transistor 23 is located between the FD section 26 (gate electrode of the amplification transistor 24) and the vertical signal line 111. The vertical signal line 111 is selectively supplied with the reset voltage Vrst via the switch transistor 27 which is turned on by the switch pulse SW.

Further, it can be applied to a pixel structure in which the amplification transistor 24 is shared among a plurality of unit pixels for the same reason.

Here, the operation in the case of a CMOS image sensor having a unit pixel of a pixel circuit having a three-transistor configuration shown in FIG. 16A will be described with reference to the timing chart of FIG.

After the period T4 of complete transfer and reading of the previous frame, the signal charges of the photodiode 21 and the FD unit 26 are emptied by the electronic shutter in the period T1. Then, the electric charge (here, an electron) generated by the exposure and the photoelectric conversion is accumulated in the photodiode 21. Before the intermediate readout, an intermediate voltage (corresponding to the voltage Vtrg1 in FIG. 4) is applied to the control electrode of the transfer transistor 22 during the period T2, and the signal charge generated by the pixel with a large amount of incident light is partially transferred to the FD unit 26. To do. Here, the electric charge transferred to the FD unit 26 is reset without being read.

By applying the same or different intermediate voltage as the period T2 to the control electrode of the transfer transistor 22 in the period T3, the signal charge generated in the pixel having a large amount of incident light is partially transferred to the FD unit 26 again. Here, the signal charge transferred to the FD unit 26 is read out. The exposure is continued, and in the period T4, the transfer transistor 22 is completely turned on, so that all the signal charges accumulated in the photodiode 21 are transferred to the FD unit 26 and read out from the FD unit 26.

In the period T4, in a pixel with a small amount of incident light in which transfer does not occur due to the application of an intermediate voltage, the signal charge is accumulated without decreasing, so that the signal can be read out with a high S / N. On the other hand, in a pixel with a large amount of incident light, the signal charge is saturated, but it is read out as a signal by intermediate transfer by applying an intermediate voltage.

FIG. 18 shows the potential relationship between the photodiode (PD) 21 and the FD unit 26 during the complete transfer period T4 and the electronic shutter period T1, and the detailed timing relationship between the selective power supply potential SELVDD, the reset pulse RST, and the transfer pulse TRG.

When the selected power supply potential SEL VDD is in the H level state, the reset pulse RST becomes the H level in the period t0, the reset transistor 23 is turned on, and the FD section 26 is reset. The potential of unit 26 is set as the reset level and read out via the amplification transistor 24. In the period t2, the signal charge of the photodiode 21 is transferred to the FD unit 26 when the transfer pulse TRG becomes H level, and in the period t3, the potential of the FD unit 26 is read out through the amplification transistor 24 as the signal level.

When the reset pulse RST becomes H level in the period t4 and the reset transistor 23 is turned on, the FD unit 26 is reset and the electronic shutter is operated. In the period t5, the selective power supply potential SEL VDD becomes L level, and the potential of the FD unit 26 is set to a potential lower than the threshold value of the amplification transistor 24, so that the amplification transistor 24 is turned off and the pixel is not selected. To do.

FIG. 19 shows the potential relationship between the photodiode 21 and the FD section 26 and the detailed timing relationship between the selective power supply potential SELVDD, the reset pulse RST, and the transfer pulse TRG during the intermediate transfer periods T2 and T3.

At period t0, the reset pulse RST becomes H level, and the reset transistor 23 is turned on to reset the FD section 26. In the case of the period T3, the potential of the FD unit 26 is set as the reset level in the period t1 and read out via the amplification transistor 24. In the case of period T2, it is not necessary to execute the read operation. An arbitrary voltage Vfg is applied to the control electrode of the transfer transistor 22 in the period t2, and intermediate transfer is executed. For any voltage Vfg, the period T2 is Vfg0 and the period T3 is Vfg1.

When the amount of incident light is small, the voltage of the photodiode 21 is high as shown by the broken line, and transfer to the FD unit 26 does not occur. On the other hand, when the amount of incident light is large, the voltage of the photodiode 21 becomes low as shown by the solid line, and the signal charge exceeding the potential under the gate of the transfer transistor 22 is partially transferred to the FD unit 26. In the case of the period T3, the potential of the FD unit 26 is read out via the amplification transistor 24 as a signal level in the period t3. In the case of period T2, the read operation does not have to be executed.

In the period t4, the reset pulse RST becomes the H level, and when the reset transistor 23 is turned on, only the FD section 26 is reset. In the period t5, the selected power supply potential SELVDD becomes the L level, and the FD section 26 By setting the potential to a potential lower than the threshold value of the amplification transistor 24, the amplification transistor 24 is turned off and the pixel is deselected.

Figure 20 shows the potential relationship at each timing. FIG. 20A is a potential diagram of the electronic shutter operation in the period t4 in the period T4 of complete transfer and reading. In this electronic shutter operation, the electric charges accumulated in the photodiode 21 and the FD unit 26 are swept out to the selective power supply potential SEL VDD side.

FIG. 20 (b) is a potential diagram after the reset operation in the period t0 in the periods T2, T3, and T4. After this reset operation, charge accumulation occurs due to exposure depending on the magnitude of the incident light intensity.

FIG. 20 (c) is a potential diagram during the intermediate transfer operation in the period t2 in the intermediate transfer periods T2 and T3. In this intermediate transfer operation, when a voltage is applied to the control electrode of the transfer transistor 22 so that the potential under the gate of the transfer transistor 22 is in an intermediate state between the on state and the off state of the transfer transistor 22, the incident light intensity is small. In this case, transfer does not occur because the accumulated charge is small, and the potential of the photodiode 21 exceeds the potential under the gate of the transfer transistor 22 only when the incident light intensity is strong, so that charge transfer occurs to the FD unit 26.

FIG. 20 (d) is a potential diagram in the period t2 in the period T4, that is, when the transfer transistor 22 is turned on in order to perform a complete transfer to read out all the charges accumulated in the photodiode 21. FIG. 20 (e) is a potential diagram in the period t3 in the periods T3 and T4, that is, when the transfer transistor 22 is turned off after complete transfer to read the signal. FIG. 20 (f) is a potential diagram when the pixel non-selection operation is executed so that the period t5 in the periods T1, T2, and T3, that is, the potential of the FD unit 26 is equal to or less than the threshold value of the amplification transistor 24.

By the way, in the pixel array unit, when the potential shape of the photodiode 21 which is the light receiving unit is not uniform for each pixel, the number of electrons held in the photodiode 21 differs depending on the application of the intermediate voltage. As a result, the output signal in the high illuminance region obtained by reading with the application of an intermediate voltage has fixed pattern noise depending on the variation in the potential shape of the photodiode 21, and there is a concern that the image quality may be deteriorated.

Here, for example, as shown in FIG. 21, one of the charges Qi0 is applied by applying the voltage Vfg0 to the control electrode of the transfer transistor 22 from the state (a) in which the charge Qi0 is accumulated in the photodiode (PD) 21. Consider the case (b) in which only the charge Q0 remains in the photodiode 21 when the part is swept out.

By applying the voltage Vfg1 to the control electrode of the transfer transistor 22 for the state (c) in which the charge Qi1 is further accumulated from the state (b), the charge Q0 + Q1 is left in the photodiode 21 and the charge Qfg1 is FD. It can be transferred to unit 26 and read out as a signal (state (c)).

As shown in FIG. 22, the charge Qi1 accumulated from the state (b) to the state (c) is proportional to the incident light intensity. In order to obtain the incident light intensity, that is, the brightness, from the signal charge Qfg1 transferred in the state (d), it is necessary to obtain the charge Q1 determined by the voltage Vfg0 and the voltage Vfg1. However, if the potential shape of the photodiode 21 is not the same for each pixel, the charge Q1 varies from pixel to pixel, so that the image obtained from the charge Qfg1 contains fixed pattern noise.

[Application example]

An application example described below is used to correct the fixed pattern noise that depends on the variation in the potential shape of the photodiode 21 described above.

(Operation Example 1) FIG. 23 is a timing chart showing an operation example 1 according to an application example of the present invention. This operation example 1 is an operation example in the case of a CMOS image sensor having a unit pixel of a pixel circuit having a three-transistor configuration shown in FIG. 16 (A).

First, after reading in the previous frame, the photodiode 21 is filled with electric charges (electrons or holes) in the period S1. Next, the voltage Vfg1 is applied to the control electrode of the transfer transistor 22 in the period S2, intermediate transfer is performed, and then reset is performed. Next, the voltage Vfg0 is applied to the control electrode of the transfer transistor 22 in the period S3, intermediate transfer is performed, and then the signal is read out. Finally, complete transfer is performed in period S4 to read the signal, and shutter operation is performed in period S5.

FIG. 24 shows the potential relationship between the photodiode 21 and the FD section 26 and the detailed timing relationship between the selective power supply potential SEL VDD, the reset pulse RST, and the transfer pulse TRG during the intermediate transfer periods S2 and S3.

At period t0, the reset pulse RST becomes H level, and the reset transistor 23 is turned on to reset the FD section 26. In the case of the period S3, the potential of the FD unit 26 is set as the reset level in the period t1 and read out via the amplification transistor 24. In the case of period S2, it is not necessary to execute the read operation. An arbitrary voltage Vfg is applied to the control electrode of the transfer transistor 22 in the period t2, and intermediate transfer is executed. For any voltage Vfg, let Vfg1 be for period S2 and Vfg0 for period S3. Here, Vfg0 and Vfg1 may have the same voltage value.

When the amount of incident light is small, the voltage of the photodiode 21 is high as shown by the broken line, and transfer to the FD unit 26 does not occur. On the other hand, when the amount of incident light is large, the voltage of the photodiode 21 becomes low as shown by the solid line, and the signal charge exceeding the potential under the gate of the transfer transistor 22 is partially transferred to the FD unit 26. In the case of the period S3, the potential of the FD unit 26 is read out via the amplification transistor 24 as a signal level in the period t3. In the case of period S2, the read operation does not have to be executed.

In the period t4, the reset pulse RST becomes the H level, and when the reset transistor 23 is turned on, only the FD section 26 is reset. In the period t5, the selected power supply potential SELVDD becomes the L level, and the FD section 26 By setting the potential to a potential lower than the threshold value of the amplification transistor 24, the amplification transistor 24 is turned off and the pixel is deselected.

FIG. 25 shows the potential relationship between the photodiode 21 and the FD unit 26 during the complete transfer period S4 and the electronic shutter period S5, and the detailed timing relationship between the selective power supply potential SEL VDD, the reset pulse RST, and the transfer pulse TRG.

When the selected power supply potential SEL VDD is in the H level state, the reset pulse RST becomes the H level in the period t0, the reset transistor 23 is turned on, and the FD section 26 is reset. The potential of unit 26 is set as the reset level and read out via the amplification transistor 24. In the period t2, the signal charge of the photodiode 21 is transferred to the FD unit 26 when the transfer pulse TRG becomes H level, and in the period t3, the potential of the FD unit 26 is read out through the amplification transistor 24 as the signal level.

When the reset pulse RST becomes H level in the period t4 and the reset transistor 23 is turned on, the FD unit 26 is reset and the electronic shutter is operated. In the period t5, the selective power supply potential SEL VDD becomes L level, and the potential of the FD unit 26 is set to a potential lower than the threshold value of the amplification transistor 24, so that the amplification transistor 24 is turned off and the pixel is not selected. To do.

(Operation Example 2) FIG. 26 is a timing chart showing an operation example 2 according to an application example of the present invention. This operation example 2 is also an operation example in the case of a CMOS image sensor having a unit pixel of a pixel circuit having a three-transistor configuration.

The operation example 2 is an operation example in which the reading of the last complete transfer in the operation example 1 is omitted. By omitting the reading of the last complete transfer, the photodiode 21 is compared with the case of the operation example 1. It is possible to shorten the time required for a series of processes for obtaining a correction signal for correcting the fixed pattern noise that depends on the variation of the potential shape. By setting any or all of the plurality of voltages to a voltage other than the voltage that completely turns off the transfer transistor 22, the reading of the complete transfer can be omitted.

FIG. 27 shows the potential relationship between the photodiode 21 and the FD section 26 in the intermediate transfer period S3'and the electronic shutter period S5 in the case of operation example 2, and the detailed timing relationship of the selective power supply potential SEL VDD, reset pulse RST, and transfer pulse TRG. Shown. In operation example 2, as shown in the timing chart of FIG. 27, the shutter operation and the deselection operation of the electronic shutter period S5 are executed after the intermediate readout.

(Operation Example 3) FIG. 28 is a timing chart showing an operation example 3 according to an application example of the present invention. This operation example 3 is also an operation example in the case of a CMOS image sensor having a unit pixel of a pixel circuit having a three-transistor configuration.

Operation example 3 is an operation example in which the intervals between the forced saturation operation in the period S1, the intermediate transfer operation in the period S2, and the intermediate transfer and read operations in the period S3 are shortened. By shortening the length, the influence of incident light and dark current can be reduced as compared with the case of operation example 1.

(Operation Example 4) FIG. 29 is a timing chart showing an operation example 4 according to an application example of the present invention. This operation example 4 is also an operation example in the case of a CMOS image sensor having a unit pixel of a pixel circuit having a three-transistor configuration.

Operation example 4 is an operation example in which the reading of the signal by the intermediate transfer is continuously executed a plurality of times, and each voltage is supported by applying a plurality of voltages to the control electrodes of the transfer transistor 22 in order from the lowest voltage. A correction signal of the corrected amount can be obtained.

FIG. 30 shows the timing relationship of the forced saturation operation of the photodiode 21 in the operation examples 1 to 4 described above. In FIG. 30, the period S1 shows the timing relationship of the forced saturation operation.

Transfer by setting the reset voltage (here, the selective power supply potential SELVDD), which is the initial voltage of the FD section 26, to the voltage of the photodiode 21 at saturation, and setting the transfer pulse TRG and reset pulse TRS to the H level. Turn on the transistor 22 and the reset transistor 23. As a result, the photodiode 21 is in a state in which the charge is retained as in the saturated state. That is, by turning on the transfer transistor 22 with the potential of the FD unit (transfer capacitance) 26 as the potential of the photodiode 21 in the saturated state, the photodiode 21 can be satisfied with the potential or holes.

As described above, after the photodiode 21 is filled with electric charges (electrons or holes), a plurality of intermediate voltages (second control voltages) are sequentially applied to the control electrodes of the transfer transistor 22 to perform partial transfer. That is, by partially transferring the remaining stored charge to the FD unit 26 while retaining a part of the charge stored in the photodiode 21, the signal charge transferred by any or all of the intermediate voltages is voltageed. It can be acquired as a signal. This voltage signal includes a variation component of the potential shape of the photodiode 21, and thus serves as a correction signal for correcting fixed pattern noise depending on the variation of the potential shape.

As is clear from the explanation of the operation example 4 described above, the application order of the plurality of intermediate voltages (second control voltage) is the reverse of the application order of the plurality of control voltages (second control voltage) at the time of image acquisition. It becomes. That is, when a plurality of control voltages are applied in order from the highest voltage at the time of image acquisition, by applying a plurality of intermediate voltages in order from the lowest voltage, fixed pattern noise depending on the variation in the potential shape of the photodiode 21 It is possible to acquire a correction signal for correcting the voltage.

(Principle for obtaining correction signal) Next, the principle for obtaining a correction signal for correcting fixed pattern noise depending on the variation in the potential shape of the photodiode 21 will be described.

FIG. 31 is a potential diagram in reading with intermediate transfer. In FIG. 31, (a) is the potential of the period t1 in the intermediate transfer period S2, (b) is the potential of the period t2 in the intermediate transfer period S2, and (c) is the potential of the period t1 in the intermediate transfer period S3. c) shows the potential of period t2 in the intermediate transfer period S3, respectively.

The charge Qi0 stored in the photodiode 21 during the S2-t1 period (a) is partially transferred to the FD section 26 by applying the voltage Vfg0 to the transfer transistor 22 during the S2-t2 period (b). Only the charge Q0 remains in the photodiode 21. The charge Qfg0 transferred to the FD unit 26 is reset.

Here, the charge Q0 is controlled by the applied voltage Vfg0, and the charge Q0 has a variation in the number of charges due to the characteristic variation (threshold variation) of the transfer transistor 22 and a variation in the number of charges due to the variation in the potential shape ΔQpot0. Is included as a fixed pattern noise for each pixel. Then, the electric charge Q0 is expressed by the following equation (1), where the average value of the electric charges Q0 is Qhad0. Q0 = Qhad0 + ΔQvth + ΔQpot0 ...... (1)

In the reading of the period S3, the charge Qi1 generated by the photoelectric conversion is added to the photodiode 21 during the exposure period from the period S2, and the photodiode 21 holds the charge (Qi1 + Q0). In this state, by applying the intermediate voltage Vfg1 to the control electrode of the transfer transistor 22, a part of the charge Qi1 is transferred to the FD unit 26. At this time, assuming that the remaining charge of the charge Qi1 is Q1, the photodiode 21 holds a charge of (Q0 + Q1).

The charge (Q0 + Q1) also includes the variation ΔQvth in the number of charges due to the variation in the threshold value of the transfer transistor 22, and also includes the variation ΔQpot1 in the number of charges due to the variation in the potential shape with respect to the charge Q1. Here, assuming that the average value of the electric charge Q1 is Qhad1, it can be expressed as Q0 + Q1 = (Qhad0 + ΔQpot0) + (Qhad1 + ΔQpot1) + ΔQvth ...... (2). Here, the charge Q1 is Q1 = Qhad1 + ΔQpot1 ...... (3).

The read signal, that is, the charge Qfg1 transferred to the FD unit 26, is Qfg1 = Qi1-Q1 = Qi1- (Qhad1 + ΔQpot1) ... (4). As can be seen from this equation (4), it is necessary to cancel the variation in the number of charges due to the variation in the potential shape ΔQpot1 as the variation in the characteristics of the pixels.

FIG. 32 is a potential diagram in forced saturation operation and intermediate transfer. In FIG. 32, (a) is the potential of period t4 in the forced saturation period S1, (b) is the potential of period t5 in the forced saturation period S1, and (c) is the potential of period t2 in the intermediate transfer period S2. c) shows the potential of period t2 in the intermediate transfer period S3, and (d) shows the potential of period t2 in the intermediate transfer period S4.

The photodiode 21 is forcibly saturated in the S2-t4 period (a), and the saturated electron number Qs0 is held in the photodiode 21 in the S1-t5 period (b). In the S2-t2 period (c), the electric charge (Q0 + Q1) represented by the equation (2) can be held in the photodiode 21 by applying the voltage Vfg1 to the control electrode of the transfer transistor 22. The charge transferred to the FD unit 26 is reset.

In the S3-t3 period, when the voltage Vfg0 is applied to the control electrode of the transfer transistor 22, the charge Q0 represented by the equation (1) is held by the photodiode 21, and the remaining charge Q1 is transferred to the FD section 26 to signal. Is read as. Since the charge Q1 is expressed by Eq. (3), fixed pattern noise is generated as a variation in pixel characteristics, and an offset value due to the term ΔQpot1 that deteriorates image quality can be obtained.

When the complete transfer is subsequently executed in the S4-t2 period, the charge Q0 in Eq. (1) is read out as a signal, so that the offset value of (ΔQpot0 + ΔQvth) can also be obtained. By reading this signal, it is possible to remove the fixed pattern noise due to the threshold variation of the transfer transistor 22.

(Correction of Fixed Pattern Noise) From the CMOS image sensor 10 shown in FIG. 1, the charge Qfg1 including the charge (quantity) Qi1 depending on the amount of incident light is read out as a signal. The average value Qhad1 of the charges Q1 remaining by the intermediate transfer is a value that can be controlled by the intermediate voltage Vfg1, but the variation in the number of charges due to the variation in the potential shape ΔQpot1 deteriorates the image quality as the fixed pattern noise of the pixels.

Therefore, the charge Q1 of the equation (3) is obtained by the method of acquiring the correction signal (correction value) described above. Then, when the arithmetic processing that takes the sum of the electric charge Q1 and the electric charge Qfg1 is performed, the arithmetic result of the following equation (5) is obtained. Qfg1 + Q1 = Qi1- (Qhad1 + ΔQpot1) + Qhad1 + ΔQpot1 = Qi1 ...... (5) The variation in the number of charges due to the variation in the potential shape is removed, and only the charge Qi1 that depends on the amount of incident light is removed. Will be obtained.

That is, by performing the addition process of Eq. (5), the variation in the number of charges due to the variation in the potential shape of the photodiode 21 is canceled by using the correction signal obtained by the acquisition method described above, and the amount of incident light is shown. Since the charge Qi1 is obtained, the image quality of the captured image can be improved by reducing the fixed pattern noise.

As shown in FIG. 33, the addition process of the equation (5) is executed in the digital signal processing circuit 50 provided after the CMOS image sensor 10. Here, it is assumed that the imaging signal is output as a digital signal from the CMOS image sensor 10. The digital signal processing circuit 50 has, for example, a frame memory, stores correction signals acquired for each pixel by the acquisition method described above in the frame memory for each pixel, and stores the correction signal in the frame memory during normal imaging. The addition process of Eq. (5) is executed in order to correct the fixed pattern noise that depends on the variation in the potential shape of the light receiving unit (photodiode) for each pixel using the correction signal.

Regarding the acquisition of the correction signal, the acquisition process is executed once at the manufacturing stage and the correction signal of each pixel is stored as a fixed value in the non-volatile memory, or the acquisition process is executed once when the system power is turned on. A method of storing the pixel correction signal as a fixed value in the frame memory, or a method of repeatedly executing the acquisition process at regular intervals such as several frame periods or several tens of frame periods, and the correction signal stored in the frame memory each time. A method of updating, a method of repeatedly executing the acquisition process for each frame, and a method of updating the correction signal stored in the frame memory can be considered. As the number of correction signals acquired increases, there is an advantage that fixed pattern noise due to changes over time can be reliably corrected.

As described above, after the photodiode 21 is filled with electric charge, a plurality of intermediate voltages (second control voltages) are sequentially applied to the control electrodes of the transfer transistor 22 to perform partial transfer, and any or all of them. The fixed pattern noise of the image obtained by reading out the signal charge obtained by the transfer by the intermediate voltage and sequentially applying a plurality of control voltages to the control electrodes of the transfer transistor 22 at the time of normal imaging with the signal charge as a correction term. By using it for removal, the following effects can be obtained. That is, it is possible to remove the fixed pattern noise of the image generated by the variation in the potential shape of the photodiode 21 and / or the variation in the threshold value of the transfer transistor 22 in the output signal at high illuminance when the dynamic range is widened. In addition, the image quality of the captured image can be improved.

In this embodiment, a case where the correction signal obtained by the above-mentioned acquisition method is applied to an image pickup signal obtained by sequentially applying a plurality of control voltages to the control electrodes of the transfer transistor 22 is given as an example. However, the present invention is not limited to this application example.

In the above-described embodiment and its application example, the case where it is applied to a CMOS image sensor has been described as an example, but the present invention is not limited to the application to a CMOS image sensor, and the amplification type solid-state image sensor in general. Furthermore, since the invention relates to a portion for reading a signal charge from a photoelectric conversion element, it can be similarly applied to a charge transfer type solid-state image pickup device represented by a CCD image sensor.

Figure 34 shows an example when applied to a CCD image sensor. In the CCD image sensor, photoelectric conversion is performed by the photodiode (light receiving unit) 31 which is a photoelectric conversion element, and the signal charge accumulated here is transferred to the vertical CCD (vertical transfer unit) 33 by the transfer gate (read gate) 32. , It will be read by the vertical transfer by the vertical CCD33. In this CCD image sensor, the amount of electrons transferred to the vertical CCD 33 can be controlled by applying the above-mentioned control voltage Vtrg to the transfer gate 32.

When the incident light is weak (A), the amount of photoelectrically converted electrons is small, so even if the control voltage Vtrg is applied to the transfer gate 32, the stored electrons of the photodiode 31 have the potential under the transfer gate 32. It cannot be exceeded and is held in the photodiode 31. On the other hand, when the incident light is strong (B), since the amount of photoelectrically converted electrons is large, by applying the control voltage Vtrg to the transfer gate 32, the stored electrons of the photodiode 31 are transferred under the transfer gate 32. Partially transferred to vertical CCD33 beyond potential.

Then, by applying the control voltage Vtrg at the same control timing as in the case of the CMOS image sensor, the signal is acquired by intermediate transfer in the high illuminance while maintaining the signal charge in the low illuminance as in the case of the CMOS image sensor. Can be executed.

[Modification example]

In the embodiment described above, a plurality of control voltages are sequentially supplied to the control electrodes of the transfer transistor 22 for all the pixels 20 of the pixel array unit 11, and the signal charges transferred by the transfer transistor 22 at that time are twice. Although the drive for reading is performed as described above, the present invention is not limited to the application example in which the drive is performed for all the pixels 20. Other application examples will be described below as modified examples 1, 2, and 3.

(Modification 1) FIG. 35 is a conceptual diagram of Modification 1 of the present invention. In this modification 1, color transmission filters such as R (red), G (green), and B (blue) primary color filters and Cy (cyan), Mg (magenta), and Ye (yellow) complementary color filters are applied on the pixels. In a solid-state imaging device that acquires a color image by arranging in, a pixel 36 that does not have a color transmission filter and has a higher sensitivity than the pixel 35 that has a color transmission filter is partially provided, and the pixel 36 having a higher sensitivity is provided. It is characterized in that a plurality of control voltages are sequentially supplied to the control electrodes of the transfer transistor, and at this time, the signal charge transferred by the transfer transistor is read out twice or more.

FIG. 36 is a diagram showing an example of the spectrum of an incandescent lamp. In general, an incandescent lamp contains a large amount of infrared light and has a wide wavelength range as shown in the characteristic W of FIG. 20, and when it passes through a blue, green, and red color transmission filters, it has characteristics B, G, and R. The strength is attenuated. Therefore, the high-sensitivity pixel 36 having no color transmission filter has several times the sensitivity of the pixel 35 having a color transmission filter in order to receive light in a wide wavelength range.

In this way, in a solid-state imaging device in which a low-sensitivity pixel 35 having a color transmission filter and a high-sensitivity pixel 36 having no color transmission filter coexist, the high-sensitivity pixel 36 can be used as a control electrode of a transfer transistor. By sequentially supplying a plurality of control voltages and driving the signal charge transferred by the transfer transistor to be read out twice or more, high sensitivity is maintained while maintaining high S / N in pixel 35 having a color transmission filter. The signal can be acquired even when the normal level is exceeded in the pixel 36 of.

Here, the signal acquired in the high-sensitivity pixel 36 having no color transmission filter has a sharp edge. Therefore, as an example, by reflecting the signal acquired in the high-sensitivity pixel 36 having no color transmission filter in the signal acquired in the low-sensitivity pixel 35 having a color transmission filter, a captured image with clear edges can be obtained. be able to.

(Modification 2) FIG. 37 is a conceptual diagram of Modification 2 of the present invention. This modification 2 is similar to the modification 1 in that the low-sensitivity pixel 35 having a color transmission filter and the high-sensitivity pixel 36 having no color transmission filter are mixed, but the modification 1 has a high sensitivity. The difference is that the pixel 36 is partially provided, whereas the high-sensitivity pixel 36 is provided in line units.

In the modified example 1 in which the high-sensitivity pixels 36 are scattered, it is not possible to distinguish between the low-sensitivity pixel 35 and the high-sensitivity pixel 36 by performing selective scanning on a line-by-line basis. On the other hand, in the modification 2 in which the high-sensitivity pixel 36 exists in line units, the low-sensitivity pixel 35 and the high-sensitivity pixel 36 can be distinguished and selectively driven in line units. In other words, the rows of highly sensitive pixels 36 can be selectively driven independently.

In order to selectively drive the row of the high-sensitivity pixel 36 independently, the vertical scanning circuit 12 of FIG. 1 has a scanning system for selectively scanning the row of the low-sensitivity pixel 35 having a color transmission filter and a color transmission filter. A scanning system for selectively scanning the rows of the high-sensitivity pixels 36 may be provided, and scanning may be performed separately for each scanning system.

In this way, since the rows of the high-sensitivity pixels 36 can be selectively driven independently, a plurality of control voltages are sequentially supplied to the control electrodes of the transfer transistor for the high-sensitivity pixels 36, and at that time. While the drive to read the signal charge transferred by the transfer transistor twice or more is performed at high speed, the normal read operation can be performed at low speed for the low-sensitivity pixel 35, so the low-sensitivity pixel 35 is used. On the other hand, as compared with the modified example 1, which has no choice but to perform high-speed operation like the high-sensitivity pixel 36, there is an advantage that the power consumption can be reduced by the amount that the low-sensitivity pixel 35 can be driven at a low speed.

(Modification 3) FIG. 38 is a conceptual diagram of Modification 3 of the present invention. In the third modification, for example, in the pixel arrangement of the second modification, the infrared light cut filter 37 is placed on a pixel other than the high-sensitivity pixel 36 having no color transmission filter, that is, on a low-sensitivity pixel 35 having a color transmission filter. It is characterized by being arranged in pixel units.

In order to arrange the infrared light cut filter 37 on the low-sensitivity pixel 35 in pixel units, for example, it can be formed by laminating a dielectric multilayer film on the low-sensitivity pixel 35. Further, by removing the infrared light cut filter generally arranged in front of the image pickup apparatus for the high-sensitivity pixel 36 or by using a filter that blocks infrared light having a longer wavelength, the low-sensitivity pixel An infrared light cut filter 37 can be placed on the 35.

By arranging the infrared light cut filter 37 on the low-sensitivity pixel 35 in this way, the high-sensitivity pixel 36 can also receive infrared light and further increase the sensitivity of the pixel 36. It is possible to acquire a signal equal to or higher than the normal saturation level of the high-sensitivity pixel 36 without degrading the signal of the low-sensitivity pixel 35 having a normal color transmission filter.

[Application example]

The CMOS image sensor according to the above-described embodiment (including modifications 1 to 3) is suitable for use as an image pickup device (image input device) in an image pickup device such as a digital still camera or a video camera.

Here, the image pickup device includes a solid-state image pickup device as an image pickup device, an optical system for forming an image light of a subject on an image pickup surface (light receiving surface) of the solid-state image pickup device, and a signal processing circuit of the solid-state image pickup device. It refers to a camera module (for example, used by being mounted on an electronic device such as a mobile phone), a camera system such as a digital still camera or a video camera equipped with the camera module.

FIG. 39 is a block diagram showing an example of the configuration of the image pickup apparatus according to the present invention. As shown in FIG. 39, the image pickup apparatus according to this example includes an optical system including a lens 41, an image pickup device 42, a camera signal processing circuit 43, and the like.

The lens 41 forms an image of the image light from the subject on the image pickup surface of the image pickup device 42. The image pickup device 42 outputs an image signal obtained by converting the image light imaged on the image pickup surface by the lens 41 into an electric signal in pixel units. As the image pickup device 42, the CMOS image sensor 10 according to the above-described embodiment is used. The camera signal processing unit 43 performs various signal processing on the image signal output from the image pickup device 42.

As described above, in an imaging device such as a video camera, an electronic still camera, or a camera module for a mobile device such as a mobile phone, the CMOS image sensor 10 according to the above-described embodiment is used as the imaging device 42. The CMOS image sensor 10 enables linear and high S / N signal acquisition in low light without narrowing the normal saturation level, and is good in the linear region even for incident light above the normal saturation level. Since the dynamic range can be expanded while achieving S / N, there is an advantage that the image quality of the captured image can be further improved.

<figref num="1">It is a system block diagram which shows the structure of the CMOS image sensor which concerns on one Embodiment of this invention.</figref><figref num="2">It is a circuit diagram which shows an example of the circuit structure of the supply voltage control circuit.</figref><figref num="3">It is a timing chart which shows the input / output timing relation of the supply voltage control circuit.</figref><figref num="4">It is a timing chart for explaining each operation in the case of normal reading (A) and the case of aiming for high S / N and wide dynamic range (B).</figref><figref num="5">It is a potential figure which shows an example of the potential in a pixel when a plurality of voltages are selectively supplied to the control electrode of a transfer transistor.</figref><figref num="6">It is a potential figure which shows the example of the potential change when the incident light is weak.</figref><figref num="7">It is a potential figure which shows the example of the potential change when the incident light is weak.</figref><figref num="8">It is explanatory drawing of the reason why the threshold variation is canceled in the second and subsequent transfers.</figref><figref num="9">It is a figure which shows the relationship between the exposure time and the number of stored electrons of a light receiving part.</figref><figref num="10">It is a figure which shows the experimental result of the supply voltage Vtrg to the control electrode of a transfer transistor in a photodiode having a saturated electron number Qs of 8800e-, and the number of electrons held by the photodiode when the voltage Vtrg is supplied.</figref><figref num="11">It is a timing chart which shows another example about the supply timing of the voltage supplied to the control electrode of a transfer transistor.</figref><figref num="12">It is a timing chart which shows still another example about the supply timing of the voltage supplied to the control electrode of a transfer transistor.</figref><figref num="13">It is explanatory drawing of high S / N and wide dynamic range.</figref><figref num="14">It is a figure which shows the experimental result under a predetermined condition.</figref><figref num="15">It is a figure which shows the relationship between the total number of generated electrons which show the incident light intensity in the said experiment, and the number of electrons transferred as an output in each intermediate transfer and the last complete transfer.</figref><figref num="16">It is a circuit diagram which shows the other circuit example of a unit pixel.</figref><figref num="17">It is a timing chart which shows the operation example when the pixel circuit of 3 transistor composition is used.</figref><figref num="18">It is a timing chart which shows the potential relation and the detailed timing relation in a complete transfer period and an electronic shutter period.</figref><figref num="19">It is a timing chart which shows the potential relation and the detailed timing relation in the intermediate transfer period.</figref><figref num="20">It is a potential diagram which shows the potential relation at each timing.</figref><figref num="21">It is a potential diagram in the intermediate transfer.</figref><figref num="22">It is a figure which shows the correspondence relationship between the incident light intensity and a signal charge in an intermediate transfer.</figref><figref num="23">It is a timing chart which shows operation example 1 which concerns on application example of this invention.</figref><figref num="24">It is a timing chart which shows the potential relation and the detailed timing relation in the intermediate transfer period in the case of operation example 1. FIG.</figref><figref num="25">It is a timing chart which shows the potential relation and the detailed timing relation in the complete transfer period and the electronic shutter period in the case of operation example 1.</figref><figref num="26">It is a timing chart which shows operation example 2 which concerns on application example of this invention.</figref><figref num="27">It is a timing chart which shows the potential relation and the detailed timing relation in the intermediate transfer period and the electronic shutter period in the case of operation example 2.</figref><figref num="28">It is a timing chart which shows operation example 3 which concerns on application example of this invention.</figref><figref num="29">It is a timing chart which shows operation example 4 which concerns on application example of this invention.</figref><figref num="30">It is a timing chart of the forced saturation operation.</figref><figref num="31">It is a potential diagram in reading with intermediate transfer.</figref><figref num="32">It is a potential figure in a forced saturation operation and an intermediate transfer.</figref><figref num="33">It is a block diagram which shows the system structure which has the correction function of the fixed pattern noise of a pixel.</figref><figref num="34">It is a potential figure which shows the example when it is applied to a CCD image sensor.</figref><figref num="35">It is a conceptual diagram of the modification 1 of this invention.</figref><figref num="36">It is a figure which shows the example of the spectrum of an incandescent lamp.</figref><figref num="37">It is a conceptual diagram of the modification 2 of this invention.</figref><figref num="38">It is a conceptual diagram of the modification 3 of this invention.</figref><figref num="39">It is a block diagram which shows an example of the structure of the image pickup apparatus which concerns on this invention.</figref><figref num="40">It is a circuit diagram which shows an example of the circuit structure of a pixel.</figref><figref num="41">It is a potential diagram in the prior art described in Non-Patent Document 1.</figref><figref num="42">It is a figure which shows the relationship between the incident light intensity and the number of output electrons in the prior art described in Non-Patent Document 1.</figref>

Code description

10 ... CMOS image sensor, 11 ... pixel array section, 12 ... vertical scanning circuit, 13 ... supply voltage control circuit, 14 ... voltage supply circuit, 15 ... timing generation circuit, 16 ... column circuit, 17 ... horizontal scanning circuit, 18 ... column signal selection circuit, 20 ... unit pixel, 21,31 ... photodiode, 22 ... transfer transistor, 23 ... Reset transistor, 24 ... amplification transistor, 25 ... selection transistor, 26 ... FD (floating diffusion) section, 32 ... transfer gate, 33 ... vertical CCD, 35 ... low-sensitivity pixels , 36 ... High-sensitivity pixels, 37 ... Infrared light cut filter, 50 ... Digital signal processing circuit