Error correction device, program and method

The present invention relates to an error correction device, an error correction program, and an error correction method for correcting an error generated in received data.

Since the data transmitted and received between the devices may become error data due to the mixing of noise and the like, error correction is performed using an error correction code. At this time, the error correction performed by the error correction device is divided into a case where the error is not included and a case where the error is included.

Here, as an example of the error correction device, an error correction device in a disk device will be described. Loss information is TA (Thermal Asperity: error signal caused by temperature) or Code Vio1ation (non-regular code) information from RDC (lead channel), or information arbitrarily given by MPU (Micro Processing Unit). And so on. This lost information is given before error correction is started, and if there is loss, software such as MPU intervenes to correct the error. At this time, for a certain error correction code, if there is no loss, error correction of maximum t is possible, and if there is loss, there are error correction and loss correction, so correction up to t × 2 is possible. It becomes.

First, error correction when the loss is not included will be described. FIG. 4 is a conceptual diagram showing the configuration and operation flow of the conventional error correction device that does not include loss. As shown in FIG. 4, in the error correction device that does not include loss, the RDC 22 converts the analog signal from the data storage disk 21 into a 10-bit digital signal to generate a received word. Further, the RDC 22 inputs this received word into the error correction circuit 23a that does not include the loss of the hard disk controller 23, and corrects the error. Here, the error correction circuit 23a that does not include loss is composed of hardware.

At this time, the error correction circuit 23a, which does not include loss, executes error correction according to the following procedure. First, the error correcting circuit 23a that do not involve erasure generates a syndrome which is a clue of the error correction from the received word received from RDC22 (step flop S21). Next, the error correction circuit 23a, which does not include loss, calculates the error position polynomial and the error evaluation polynomial based on the generated syndrome (step S22). Then, the error correction circuit 23a, which does not include loss, calculates the error position and the error value by the chain search using two polynomials, the error position polynomial and the error evaluation polynomial (step S23).

Further, the error correction circuit 23a, which does not include loss, corrects the received word based on the calculated error position and error value, and writes the result in RAM (Random Access Memory) 23b (step S24). At this time, all the processes from step S21 to step S24 described above are performed by the hardware. By performing the error correction processing by the hardware in this way, the processing time for performing the error correction is short.

Next, error correction in the case of including disappearance will be described. FIG. 5 is a conceptual diagram showing the configuration and operation flow of the conventional error correction device including loss. As shown in FIG. 5, the RDC 22 converts the analog signal from the data storage disk 21 into a 10-bit digital signal to generate a received word, detects the loss in the received word, and generates the lost information, and this reception The words and the loss information are input to the error correction circuit 23a that does not include the loss of the hard disk controller 23. That is, even in the error correction device including the loss in FIG. 5, the same circuit as the error correction circuit 23a which does not include the loss in the error correction device which does not include the loss shown in FIG. 4 is used.

However, in the error correction device including the loss in FIG. 5, the error correction circuit 23a, which does not include the loss of the hard disk controller 23, receives the loss information and the received word from the RDC 22 to generate a syndrome and retain the loss information. (Step S31), calculation of error position polynomial and error evaluation polynomial (corresponding to step S22 in FIG. 4), calculation of error position and error value by chain search (corresponding to step S23 in FIG. 4), and for received words The function of each step of error correction (corresponding to step S24 in FIG. 4) is not executed. In other words, if an attempt is made to realize error correction including loss by hardware, the circuit scale will be enormous. Therefore, as shown in FIG. 5, the error correction device including loss executes a program only for error correction processing including loss. Prepare MPU24 separately.

Therefore, when the error correction device including loss performs error correction including loss, the following procedure is performed. First, as described above, the error correction circuit 23a, which does not include the loss of the hard disk controller 23, receives the loss information and the received word from the RDC 22 to generate a syndrome and hold the loss information (step S31). Then, the MPU24 dedicated to the disappearance process acquires the syndrome and the disappearance information from the error correction circuit 23a that does not include the disappearance (step S32), and calculates the error position polynomial and the error evaluation polynomial from the syndrome and the disappearance information (step S33). .. In addition, the MPU24 uses these two polynomials (ie, the error position polynomial and the error evaluation polynomial) to calculate the error position and error value including disappearance by chain search for the error including disappearance (step). S34). Then, MPU24 executes error correction for the received word and writes the result to RAM 13b (step S35). In step S34 (calculation of error position and error value including disappearance by chain search) and step S35 (error correction), processing for errors other than disappearance and disappearance is not distinguished, and processing for all errors is performed. I do.

Here, in the error correction including loss, the process of only generating the syndrome and holding the loss information in step S31 is performed by the error correction circuit 23a (that is, hardware) not including loss, and in step S32 above. The process from acquisition of syndrome and loss information to error correction in step S35 is performed by MPU24 (that is, software). In this way, in error correction including loss, sharing processing is performed by hardware and software.

As a prior art related to the present invention, for example, Patent Document 1 shown below is disclosed. According to this technique, by performing error correction of lost data using MPU, it is possible to speed up the loss correction while minimizing the increase in the circuit scale of the hardware.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2001-101020 (see paragraph numbers 0137 to 0138 and FIG. 1)</text></patcit>

<p> However, when performing error correction including loss, in step S34 of FIG. 5, when the software MPU24 performs error correction including loss by chain search, it is applied to all data positions where errors can occur. It takes a long processing time because it is necessary to check whether or not the position is an error. That is, since the software performs a brute force chain search for all data positions, it takes a considerably long time to calculate the error position and the error value including the chain search and loss. As a result, the processing time for performing error correction including loss becomes considerably long.</p><p> The present invention has been made to solve the above-mentioned problems, and is an error correction device and an error correction program that shortens the processing time for error correction of received words including loss by effectively using software and hardware. , And an error correction method.</p>

<p> In order to solve the above-mentioned problems, the present invention is an error correction device that corrects an error of the codeword based on the acquired codeword and the lost information, and is there a loss of the codeword based on the lost information? It is generated by the disappearance judgment unit that executes the software that determines whether or not it is present, the syndrome generation unit that is the hardware that generates the codeword syndrome, and the syndrome generation unit when the disappearance judgment unit determines that there is loss. An erasure correction section that executes software that corrects the disappearance of a codeword based on the existing syndrome and the disappearance information and causes the syndrome generator to generate the codeword syndrome with the corrected disappearance, and the codeword generated by the syndrome generator. It is equipped with a non-erasure error correction section, which is hardware that corrects errors that do not include erasure, based on the syndrome.</p><p> Further, according to the present invention, in the error correction device of the above invention, when the disappearance determination unit determines that there is no disappearance, the syndrome generation unit generates a codeword syndrome of the acquired codeword and outputs the result as a non-erasure error correction unit. When the disappearance judgment unit determines that there is a loss, first, the acquired codeword syndrome is generated, the result is passed to the disappearance correction unit, and then the codeword syndrome corrected by the disappearance correction unit is passed. It is generated and the result is passed to the error correction section without loss.</p><p> Further, according to the present invention, in the error correction device of each of the above inventions, the error correction unit without disappearance performs calculation of an error position polynomial, calculation of an error evaluation polynomial, and chain search based on the syndrome generated by the syndrome generation unit. I tried to do it.</p><p> Further, according to the present invention, in the error correction device of each of the above inventions, the erasure correction unit calculates the error position polynomial and the error evaluation polynomial based on the syndrome generated by the syndrome generation unit and the erasure information. It is the one that was made.</p><p> Further, in order to solve the above-mentioned problems, the present invention is an error correction program that causes a computer to correct a code word error based on the acquired code word and disappearance information, and is a hardware that generates a syndrome. A codeword generation step for generating a codeword syndrome, a disappearance determination step for determining whether or not a codeword has disappearance based on disappearance information, and an error determination step for determining whether or not the codeword has disappeared. An error correction step that corrects the disappearance based on the syndrome generated from the word and the disappearance information, and an error-corrected syndrome that causes the hardware that generates the syndrome to generate the codeword syndrome corrected by the disappearance correction step. Loss correction that causes the generation step and the hardware that corrects the error not including loss to correct the codeword error corrected by the disappearance correction step based on the syndrome generated by the disappearance correction post-syndrome generation step. It causes the computer to perform a post-error correction step.</p><p> Further, the present invention is generated by the syndrome generation step in the hardware that corrects the error not including the disappearance when it is further determined by the disappearance determination step that there is no disappearance in the error correction program of the above invention. Based on the syndrome, the computer is made to perform an error-free error correction step without loss, which causes the correction of codeword errors.</p><p> Further, according to the present invention, in the error correction program of each of the above inventions, the hardware that corrects an error that does not include loss in the error correction step after erasure correction is an error position polypoly based on the syndrome generated by the syndrome generation step. Calculation, error evaluation polynomial calculation, and chain search.</p><p> Further, in the error correction program of each of the above inventions, the hardware for correcting an error not including loss in the error correction step without loss is based on the syndrome generated by the syndrome generation step or the syndrome regeneration step. , Calculation of error position polynomial, calculation of error evaluation polynomial, and chain search.</p><p> Further, according to the present invention, in the error correction program of each of the above inventions, the erasure correction step calculates an error position polynomial and an error evaluation polynomial based on the syndrome generated by the syndrome generator and the erasure information. Is.</p><p> Further, in order to solve the above-mentioned problems, the present invention is an error correction method that corrects an error in a codeword based on the acquired codeword and disappearance information, and is a code for hardware that generates a syndrome. From the codeword when it is determined that there is a disappearance by the syndrome generation step that generates the syndrome of the word, the disappearance judgment step that determines whether or not the codeword has disappearance based on the disappearance information, and the disappearance judgment step. An error correction step that corrects disappearance based on the generated syndrome and disappearance information, and an error correction post-syndrome generation step that causes the hardware that generates the syndrome to generate the codeword syndrome corrected by the disappearance correction step. And, the error after loss correction is made to perform the correction of the codeword error corrected by the disappearance correction step based on the syndrome generated by the syndrome generation step after loss correction by the hardware that corrects the error not including the loss. It executes a correction step.</p><p> Further, in the error correction method of the above invention, the present invention is further generated by a syndrome generation step on hardware that corrects an error that does not include disappearance when it is determined by the disappearance determination step that there is no disappearance. Based on the syndrome, a non-loss error correction step is performed to perform codeword error correction.</p><p> Further, according to the present invention, in the error correction method of each of the above inventions, the hardware that corrects an error that does not include loss in the error correction step after erasure correction is an error position polynomial based on the syndrome generated by the syndrome generation step. Calculation, error evaluation polynomial calculation, and chain search.</p><p> Further, in the error correction method of each of the above inventions, the hardware for correcting an error not including loss in the error correction step without loss is based on the syndrome generated by the syndrome generation step or the syndrome regeneration step. , Error position polynomial calculation, error evaluation polynomial calculation, and chain search.</p><p> Further, according to the present invention, in the error correction method of each of the above inventions, the erasure correction step calculates an error position polynomial and an error evaluation polynomial based on the syndrome generated by the syndrome generator and the erasure information. Is.</p>

<p> While maintaining the same circuit scale as the conventional error correction circuit, it is possible to significantly reduce the processing time for error correction including loss.</p>

Hereinafter, embodiments of the error correction device according to the present invention will be described in detail with reference to the drawings. First, an outline of the error correction device according to the present invention will be described. In the error correction device of the present invention, when performing error correction of a received word (codeword) including loss, only calculation related to loss and correction of loss are performed by software, and calculation and error correction related to errors not including loss are performed. Is implemented in hardware. In other words, error correction including loss is performed by a sharing method based on a hybrid configuration of hardware and software. As a result, since all the chain search of the error data is performed by the hardware, it is possible to significantly reduce the processing time of the error correction including the loss performed by the software.

Hereinafter, preferred embodiments of the error correction device according to the present invention will be described in detail. FIG. 1 is a block diagram showing a configuration of an error correction device of the present invention. As shown in FIG. 1, the error correction device in the present invention has a configuration including a data storage disk 1, an RDC (read channel) 2, and a hard disk controller 3. Further, the hard disk controller 3 is configured to include an error correction circuit 3a that does not include loss, RAM 3b, MPU 4, a switch 5, and a data bus 6 peculiar to the present invention.

In the error correction circuit 3a that does not include loss, the lost information holding unit 3a1 that holds the lost information of the received word, the syndrome generator 3a2 that generates and holds the syndrome of the received word, and the received word that is lost based on the lost information. The disappearance judgment unit 3a3 that determines whether or not it is present, the polynomial calculation unit 3a4 that calculates the error position polynomial and the error evaluation polynomial, the chain search unit 3a5 that searches for the error position by chain search and calculates the error value, and the error position. It is equipped with an error correction section 3a6 that corrects errors in RAM3b based on the results of the error values.

Here, the error correction circuit 3a that does not include loss corrects the error by using the functions of all the above means 3a1 to 3a6 when performing error correction that does not include loss. However, when performing error correction including loss, the loss information and syndrome are converted to MPU4 from the error correction circuit 3a that does not include loss without using the functions of the polynomial calculation unit 3a4, the chain search unit 3a5, and the error correction unit 3a6. hand over. Then, the MPU4 only corrects the disappearance based on the disappearance information and the syndrome, stores it in the RAM3b, and transmits it to the error correction circuit 3a which does not include the disappearance again as a received word which does not include the disappearance. As a result, the error correction circuit 3a that does not include loss can be treated as a received word that does not include loss, and error correction processing is performed using the functions of the polynomial calculation unit 3a4, the chain search unit 3a5, and the error correction unit 3a6. To execute.

RAM3b stores the received word and can be accessed from the error correction circuit 3a and MPU4 which do not include loss. Further, the RAM 3b and the switch 5 are connected by the data bus 6, and the received word output from the RAM 3b that does not include the loss is transmitted to the switch 5.

The switch 5 appropriately switches between the received word transmitted from the data storage disk 1 via RDC2 and the received word retransmitted from RAM 3b that does not include loss, and the error correction circuit 3a that does not include loss is used. It has a function to send to the syndrome generator 3a2.

The MPU4 has a function of acquiring the syndrome and the loss information from the error correction circuit 3a that does not include the loss, correcting the loss, and reading / writing to the RAM 3b. That is, the MPU4 calculates the error position polynomial and the error evaluation polynomial from the disappearance information / syndrome acquisition unit 4a1 that acquires the syndrome and the disappearance information of the received word from the error correction circuit 3a that does not include the disappearance, and the syndrome and the disappearance information. It is equipped with a polynomial calculation unit 4a2, an erasure error value calculation unit 4a3 that calculates the erasure error value from the calculation results of the error position polynomial and the error evaluation polynomial, and an erasure correction unit 4a4 that corrects the erasure in RAM3b.

Next, the operation of the error correction device of the present invention shown in FIG. 1 will be described with reference to the flowchart. FIG. 2 is a conceptual diagram showing the configuration and operation flow of the error correction device of the present invention. Since the error correction process including loss is executed across each element of the error correction device of FIG. 1, a flowchart is drawn in each element in FIG. 2 for easy understanding. ..

That is, error correction including loss is performed by the following procedure according to the division method of hardware processing and software processing by MPU4. First, the error correction circuit 3a that does not include loss holds the loss information of the received word transmitted from RDC2 (step S1). Further, the error correction circuit 3a, which does not include loss, receives the received word transmitted from the RDC 2 via the switch 5 and generates and holds the syndrome (step S2).

Next, the error correction circuit 3a that does not include loss determines whether or not to perform error correction including loss based on the loss information (step S3), and does not perform error correction including loss (step S3, No.). ), The error position polynomial and the error evaluation polynomial are calculated (step S4), and the error position and the error value are calculated by the chain search (step S5). Then, the error correction data is stored in the RAM 3b from the calculation result of the error position and the error value.

On the other hand, when performing error correction including loss in step S3 (step S3, Yes), when there is loss information when the received word is received or when correction is performed by arbitrarily adding the loss information of the MPU. Therefore, the software MPU4 obtains the loss information and syndrome of the received word from the error correction circuit 3a that does not include the loss of hardware (step S7), and the error position polynomial and error evaluation polynomial from the loss information and syndrome. Perform the calculation (step S8).

In addition, the error value of disappearance is calculated using the calculated error evaluation polynomial and error position polynomial and disappearance. The number of lost error values that must be calculated at this time shall be equal to or greater than the total number of errors minus the number of errors t that can be corrected by the hardware (error correction circuit 3a that does not include loss) (step S9). .. Then, the received data is corrected using the lost value obtained in step S9, and the lost error is corrected for the data stored in RAM3b (step S10).

Next, the received word stored in RAM 3b (that is, the received word for which the loss error has been corrected) is transmitted to the switch 5 via the data bus 6. Then, the system of the switch 5 is switched, and the received word from the RAM 3b (that is, the received word for which the loss error correction has been performed) is transmitted to the error correction circuit 3a that does not include the loss. As a result, the error correction circuit 3a that does not include loss performs error correction that does not include loss for the received data (that is, the received word for which the error correction of loss has been performed).

In this way, the error correction circuit 3a that does not include loss determines that the error correction does not include loss in step S3 by receiving the received word that does not include loss from RAM3b (steps S3, No). Therefore, the error correction circuit 3a that does not include loss calculates the error position polynomial and the error evaluation polynomial in the same manner as the received word that does not include loss previously received from RDC2 (step S4), and performs the error position and the error position and the error evaluation polynomial by chain search. Calculate the error value (step S5). Then, error correction is performed on RAM3b from the calculation result of the error position and the error value (step S6).

That is, even when error correction including loss is performed, only loss is corrected by MPU4, and then the error is transmitted to the error correction circuit 3a which does not include loss again via RAM 3b and data bus 6, so that loss is not included. It can be treated as an error correction process.

As a result, only the loss correction is performed by MPU4 (software), and the error correction that does not include loss is performed by the error correction unit 3a (hardware) that does not include loss. As a result, all chain searches are performed by the error correction unit 3a, which does not include the loss of hardware. Therefore, the time for error correction including chain search and disappearance is shortened.

FIG. 3 is a data conceptual diagram showing an example of data error correction performed by the error correction device of the present invention shown in FIG. This data conceptual diagram shows an example of data error correction when the correction capability without loss is 3 bits.

First, when the correct data 11 is transmitted from RDC2, the received word 12 containing four error data at the positions of data ranks 4, 6, 10 and 11 is input to the error correction circuit 3a which does not include loss. Further, the loss information 13 is input to the error correction circuit 3a which does not include the loss. 1 in the disappearance information 13 indicates disappearance, and in this example, the data ranks 10 and 11 indicate disappearance.

Here, only the disappearance is corrected by MPU4, and only the data at the positions of the data ranks 10 and 11 is corrected for the data 14 for the loss only correction, and the two data of the data ranks 4 and 6 remain as error data. Become. Then, the loss-only correction data 14 is stored in RAM3b from MPU4. Further, the loss-only correction data 14 is transmitted from the RAM 3b to the error correction circuit 3a that does not include the loss via the data bus 6 and the switch 5.

Therefore, the error correction circuit 3a that does not include loss corrects only the loss correction data 14 (that is, the data that does not include loss), and corrects the error correction data 15 in which the two data of the data ranks 4 and 6 are corrected. It will be stored in RAM3b. At this time, since the correction capability of the error correction circuit 3a that does not include loss is 3 bits, the error correction circuit 3a that does not include loss corrects only the loss correction data 14 in which the error data is 2 bits, and the result is incorrect. It can be output as correction data 15. Therefore, it can be seen that the error correction data 15 is the same data as the correct data 11.

According to the error correction device of the present invention, the software (MPU) re-receives the data corrected for loss by hardware (error correction circuit not including loss) to correct the error. That is, when performing error correction including loss, the software (MPU) does not perform a chain search, but calculates the loss value based on the loss information and corrects only the loss. Then, after converting to error data that does not include loss, the hardware (error correction circuit that does not include loss) searches for the error position by chain search and calculates the error value. This eliminates the need for software (MPU) to perform chain searches, significantly reducing error correction time.

In this way, by using the error correction device of the present invention, it is possible to significantly reduce the processing time of error correction including loss by the circuit scale equivalent to that of the conventional error correction circuit. Specifically, when the code length is N and the error correction capability of the code word is t, the time required for error position search should be reduced to about t / N times the time required by conventional software. Is possible.

In the above-described embodiment, the error correction device in the disk device has been described as a preferable example, but the present invention is not limited to this, and can be easily applied as an error correction means of various information devices and communication devices. can do.

Further, a program for executing each of the above steps in the computer constituting the error correction device can be provided as an error correction program. By storing such an error correction program in a recording medium that can be read by a computer, it is possible to execute the error correction program by a computer constituting the error correction device. Here, as the recording medium that can be read by the computer, an internal storage device such as ROM or RAM internally mounted on the computer, a portable storage such as a CD-ROM, a flexible disk, a DVD disk, a magneto-optical disk, or an IC card. It includes a medium, a database that holds a computer program, another computer, the database, and a transmission medium on a line.

Next, the correspondence between the constituent means and the embodiments in each claim will be described. The disappearance determination unit in claim 1 corresponds to the disappearance determination unit 3a3 built in the error correction circuit 3a that does not include the disappearance in FIG. 1 in the embodiment, and the syndrome generation unit in claim 1 is the diagram in the embodiment. Corresponds to the syndrome generator 3a2 built into the error correction circuit 3a that does not include the loss of 1. Further, the erasure correction unit in claim 1 corresponds to the erasure information / syndrome acquisition unit 4a1 of MPU4 in FIG. 1, the MPU polynomial calculation unit 4a2, the erasure error value calculation unit 4a3, and the erasure correction unit 4a4 in the embodiment. Further, the error correction unit without loss in claim 1 corresponds to the polynomial calculation unit 3a4, the chain search unit 3a5, and the error correction unit 3a6 built in the error correction circuit 3a not including the loss in FIG. 1 in the embodiment. ..

Further, the syndrome generation step in claims 3 and 5 corresponds to step S2 in which the syndrome is generated and held by the error correction circuit 3a that does not include the disappearance of FIG. 2 in the embodiment, and claims 3 and 5. The disappearance determination step in 5 corresponds to step S3 of determining "is it an error correction including disappearance?" Performed by the error correction circuit 3a not including disappearance in FIG. 2 in the embodiment. Further, the erasure correction steps in claims 3 and 5 correspond to steps S7 to S10 performed by MPU4 in FIG. 2 in the embodiment. Further, the erasure-corrected syndrome generation step in claims 3 and 5 corresponds to step S2 in which the error correction circuit 3a of FIG. 2 in the embodiment generates and holds the syndrome, which does not include the erasure correction. The error correction step after erasure correction in claim 5 corresponds to steps S4 to S6 performed by the error correction circuit 3a that does not include the erasure in FIG. 2 in the embodiment.

(Appendix 1) An error correction device that corrects an error in the codeword based on the acquired codeword and the lost information, and software that determines whether or not the codeword has lost based on the lost information. The disappearance determination unit that executes the above, the syndrome generation unit that is the hardware that generates the codeword syndrome, and the syndrome generated by the syndrome generation unit when the disappearance determination unit determines that there is disappearance. An error correction section that executes software that corrects the disappearance of the codeword based on the disappearance information and causes the codeword generation unit to generate a syndrome of the codeword for which the disappearance has been corrected, and a codeword generation unit that generates the codeword. An error correction device including a non-loss error correction section, which is hardware that corrects errors that do not include loss based on the syndrome. (Appendix 2) In the error correction device described in Appendix 1, When the disappearance determination unit determines that there is no disappearance, the syndrome generation unit generates a syndrome of the acquired codeword, passes the result to the no disappearance error correction unit, and the disappearance determination unit eliminates the disappearance. When it is determined that there is, first, the syndrome of the acquired codeword is generated, the result is passed to the erasure correction unit, and further, the syndrome of the codeword corrected by the erasure correction unit is generated, and the result is obtained as described above. An error correction device characterized in that it is passed to an error correction unit without loss. (Appendix 3) In the error correction device described in Appendix 1 or Appendix 2, the error correction unit without disappearance calculates an error position polynomial and an error evaluation polynomial based on the syndrome generated by the syndrome generation unit. And an error correction device characterized by performing a chain search. (Appendix 4) In the error correction device according to any one of Appendix 1 to Appendix 3, the disappearance correction unit calculates an error position polynomial and calculates an error position polynomial based on the syndrome generated by the syndrome generation unit and the disappearance information. Error evaluation An error correction device characterized by performing polynomial calculations. (Appendix 5) An error correction program that causes a computer to correct an error in the codeword based on the acquired codeword and disappearance information, and a syndrome generation step that causes the hardware that generates the codeword to generate the codeword syndrome. , The disappearance determination step for determining whether or not the codeword has disappearance based on the disappearance information, and the syndrome generated from the codeword when it is determined that there is disappearance by the disappearance determination step. An error correction step that corrects the disappearance based on the disappearance information, an error correction post-syndrome generation step that causes the hardware that generates the syndrome to generate the codeword syndrome corrected by the disappearance correction step, and the disappearance. Error correction after loss correction that causes hardware that corrects errors that do not include the above to perform correction of codeword errors corrected by the disappearance correction step based on the syndrome generated by the disappearance correction post-syndrome generation step. An error correction program that causes the computer to perform steps and. (Appendix 6) In the error correction program described in Appendix 5, Further, when it is determined by the disappearance determination step that there is no disappearance, the hardware for correcting the error not including the disappearance is based on the syndrome generated by the syndrome generation step, and the codeword error is found. An error correction program characterized by having a computer perform a non-loss-free error correction step that causes correction to be performed. (Appendix 7) In the error correction program described in Appendix 5 or Appendix 6, the hardware that corrects an error that does not include the disappearance in the error correction step after erasure correction is based on the syndrome generated by the syndrome generation step. An error correction program characterized by calculating an error position polypoly, calculating an error evaluation polypoly, and performing a chain search. (Appendix 8) In the error correction program described in any of Appendix 5 to Appendix 7, The hardware that corrects the error that does not include the loss in the error correction step without loss is the calculation of the error position polynomial and the error evaluation polynomial based on the syndrome generated by the syndrome generation step or the syndrome regeneration step. An error correction program characterized by performing calculations and chain searches. (Appendix 9) In the error correction program described in any of Appendix 5 to Appendix 8, the disappearance correction step calculates an error position polynomial and calculates an error position polynomial based on the syndrome generated by the syndrome generator and the disappearance information. Error evaluation An error correction program characterized by performing polynomial calculations. (Appendix 10) An error correction method that corrects an error in a codeword based on the acquired codeword and disappearance information, and causes the hardware that generates the codeword to generate the codeword syndrome. A step, a disappearance determination step for determining whether or not the codeword has disappearance based on the disappearance information, and When it is determined by the disappearance determination step that there is disappearance, the disappearance correction step that corrects the disappearance based on the syndrome generated from the code word and the disappearance information, and the hardware that generates the syndrome , The erasure correction post-syndrome generation step that generates the code word syndrome corrected by the erasure correction step, the hardware that corrects the error that does not include erasure, and the syndrome generated by the erasure correction post-syndrome generation step. Based on this, an error correction method for executing an error correction step after erasure correction for executing correction of an error of a code word corrected by the erasure correction step. (Appendix 11) In the error correction method described in Appendix 10, further, when it is determined by the disappearance determination step that there is no disappearance, the hardware for correcting the error not including the disappearance is provided with the syndrome generation step. An error correction method, characterized in that an error correction step without loss is executed, which causes an error correction of the code word to be performed based on the generated syndrome. (Appendix 12) In the error correction method described in Appendix 10 or Appendix 11, The hardware that corrects the error that does not include the loss in the error correction step after erasure correction is based on the syndrome generated by the syndrome generation step, and calculates the error position polynomial, the error evaluation polynomial, and the chain search. An error correction method characterized by performing. (Appendix 13) In the error correction method described in any of the appendices 10 to 12, the hardware that corrects the error not including the disappearance in the error correction step without disappearance is the syndrome generation step or the syndrome regeneration. An error correction method characterized by calculating an error position polynomial, calculating an error evaluation polynomial, and performing a chain search based on the syndrome generated by the step. (Appendix 14) In the error correction method described in any of the appendices 10 to 13, the disappearance correction step calculates an error position polynomial based on the syndrome generated by the syndrome generator and the disappearance information. Error evaluation An error correction method characterized by performing polynomial calculations.

<figref num="1">It is a block diagram which shows the structure of the error correction apparatus of this invention.</figref><figref num="2">It is a conceptual diagram which shows the structure and operation flow of the error correction apparatus of this invention.</figref><figref num="3">It is a data conceptual diagram which shows an example of the error correction performed by the error correction apparatus of this invention shown in FIG.</figref><figref num="4">It is a conceptual diagram which shows the structure and operation flow of the conventional error correction apparatus which does not include loss.</figref><figref num="5">It is a conceptual diagram which shows the structure and operation flow of the conventional error correction apparatus including disappearance.</figref>

Code description

1 Data storage disk, 2 RDC (read channel), 3 Hard disk controller, 3a Error correction circuit that does not include loss, 3a1 Loss information holding section, 3a2 Syndrome generation section, 3a3 Loss judgment section, 3a4 Polygonometric calculation section, 3a5 Chain search section , 3a6 error correction section, 3b RAM, 4 MPU, 4a1 disappearance information / syndrome acquisition section, 4a2 MPU polypoly calculation section, 4a3 loss error value calculation section, 4a4 disappearance correction section, 5 switch, 6 data bus