Substrate with built-in semiconductor ic and its manufacturing method

The present invention relates to a semiconductor IC-embedded substrate and a method for manufacturing the same, and more particularly to a semiconductor IC-embedded substrate suitable for embedding a semiconductor IC having a very narrow electrode pitch and a method for manufacturing the same.

In recent years, in order to meet the demand for miniaturization and thinning of semiconductor IC mounting modules, many proposals have been made to mount the semiconductor IC to be mounted on a printed circuit board in a bare chip state. A bare-chip semiconductor IC has a much narrower electrode pitch than a packaged semiconductor IC. Therefore, when this is mounted on a printed circuit board, the electrodes provided on the semiconductor IC (hereinafter referred to as "pad electrodes"). An important issue is how to connect the circuit board to the wiring provided on the printed circuit board (hereinafter referred to as "wiring pattern").

As one method of connecting the pad electrode and the wiring pattern, a method of connecting them by wire bonding is known. According to this method, a bare-chip semiconductor IC can be mounted relatively easily, but the area for mounting the semiconductor IC and the area for connecting the bonding wires need to be different planes on the printed circuit board. , There was a problem that the mounting area became large.

Further, as another method for connecting the pad electrode and the wiring pattern, a method of flip-chip connecting a bare-chip semiconductor IC to a printed circuit board is also known. According to this method, the mounting area can be reduced, but in order to secure sufficient mechanical connection strength between the pad electrode and the wiring pattern, a multi-layered underbarrier metal is provided on the surface of the pad electrode. There was a problem that the process became complicated, such as the need to apply.

Moreover, since both of the above-mentioned two methods mount the semiconductor IC on the surface of the printed circuit board, there is a common problem that it is difficult to make the entire module thin. As a method for solving this, as described in Patent Documents 1 to 7, a method of forming a cavity in a printed circuit board and embedding a semiconductor IC in a bare chip state inside the cavity to form a semiconductor IC built-in substrate. Can be considered.

However, in the methods described in Patent Documents 1 to 7, it is necessary to increase the thickness of the printed circuit board to some extent in order to secure the strength of the portion where the cavity is formed, which hinders the thinning of the module. There was a problem. Furthermore, since it is necessary to set the size of the cavity in the plane direction to some extent larger than the size in the plane direction of the semiconductor IC, the relative positional relationship between the pad electrode and the wiring pattern is deviated, which causes the electrode. It was very difficult to use a semiconductor IC with a pitch as narrow as 100 μm or less.

Moreover, since each pad electrode is exposed by irradiating a laser each time the semiconductor IC is embedded, the narrower the electrode pitch of the semiconductor IC, the higher the processing accuracy is required. There is also a problem that the processing time increases in proportion to the number of pad electrodes. Further, when the electrode pitch of the semiconductor IC is narrowed, it is necessary to reduce the diameter of the via formed by the laser irradiation, so that there is a problem that the desmear treatment inside the via becomes difficult.

On the other hand, in Patent Document 8, in a state where the semiconductor IC is fixed to the transfer substrate, the post electrode provided on the printed circuit board is inserted into the positioning hole provided on the transfer substrate to be uncured or semi-cured. A method of embedding a semiconductor IC in a cured resin layer and then exposing the pad electrode by polishing or blasting is disclosed. According to this method, not only can the semiconductor IC be positioned with high accuracy, but also the above-mentioned problem that occurs when individual pad electrodes are exposed by laser irradiation can be solved.

However, the method of Patent Document 8 has a restriction that the post electrode must be formed on the printed circuit board in advance and requires processing of the transfer substrate. Therefore, all the semiconductor IC built-in substrates are not necessarily available. It could not be said that it was suitable for manufacturing.

In addition, although it is not related to a method for manufacturing a substrate with a built-in semiconductor IC, Patent Documents 9 to 11 disclose examples of using polishing or blasting as a method for cueing electrodes provided in a semiconductor IC.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 9-321408</text></patcit><patcit num="2"><text>Japanese Patent Application Laid-Open No. 2002-246500</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2001-339165</text></patcit><patcit num="4"><text>Japanese Patent Application Laid-Open No. 2002-50874</text></patcit><patcit num="5"><text>Japanese Unexamined Patent Publication No. 2002-170840</text></patcit><patcit num="6"><text>Japanese Patent Application Laid-Open No. 2002-246507</text></patcit><patcit num="7"><text>Japanese Unexamined Patent Publication No. 2003-7896</text></patcit><patcit num="8"><text>Japanese Patent Application Laid-Open No. 2005-64470</text></patcit><patcit num="9"><text>Japanese Unexamined Patent Publication No. 11-274241</text></patcit><patcit num="10"><text>Japanese Unexamined Patent Publication No. 2001-250902</text></patcit><patcit num="11"><text>Japanese Unexamined Patent Publication No. 2003-197655</text></patcit>

<p> As described above, in the conventional method, various problems have occurred when a semiconductor IC having a narrow electrode pitch is embedded in a substrate. An object of the present invention is to solve such a problem, and to provide a semiconductor IC built-in substrate suitable for embedding a semiconductor IC having a very narrow electrode pitch and a method for manufacturing the same.</p>

<p> The semiconductor IC built-in substrate according to the present invention includes a semiconductor IC having conductive protrusions on its main surface, a first resin layer covering the main surface of the semiconductor IC, and a second resin layer covering the back surface of the semiconductor IC. The conductive protrusion of the semiconductor IC is provided with the above resin layer, and is characterized in that the conductive protrusion is projected from the surface of the first resin layer. It is preferable that at least one of the first and second resin layers is in contact with the side surface of the semiconductor IC. It is also preferable that the first resin layer is in contact with the main surface of the semiconductor IC and the second resin layer is in contact with the back surface of the semiconductor IC.</p><p> A die attach film is provided on either the main surface or the back surface of the semiconductor IC, and the one of the main surface and the back surface of the semiconductor IC is covered with either one of the first and second resin layers via the die attach film. It doesn't matter if you do.</p><p> The semiconductor IC-embedded substrate according to the present invention preferably further includes through electrodes provided so as to penetrate the first and second resin layers. Further, it is more preferable that the semiconductor IC is made thinner.</p><p> Further, the semiconductor IC built-in substrate according to the present invention further includes a wiring pattern formed on the surface of the first resin layer and connected to the conductive protrusions, and the width of the wiring pattern on the conductive protrusions is conductive. It is preferably smaller than the diameter of the protruding portion of the sex protrusion.</p><p> Further, the method for manufacturing a semiconductor IC-embedded substrate according to the present invention includes a first step of sandwiching a semiconductor IC having conductive protrusions on its main surface between first and second resin layers, and the first resin layer. The second step of projecting the conductive protrusion of the semiconductor IC from one surface of the first resin layer and the one surface of the first resin layer by reducing the thickness of the semiconductor IC. It is characterized by including a third step of forming a wiring pattern.</p><p> In the second step, it is preferable to reduce the thickness by wet blasting one surface of the first resin layer.</p><p> In the first step, the other surface of the first resin layer and the main surface of the semiconductor IC are overlapped so as to face each other, and one surface of the second resin layer and the back surface of the semiconductor IC face each other. It is preferable to include a step of superimposing these. In this case, in the first step, it is preferable to mount the semiconductor IC on the other surface of the first resin layer with reference to the alignment mark formed on one or the other surface of the first resin layer. ..</p><p> Further, it is preferable that the first step is performed with the support substrate attached to one surface side of the first resin layer. In this case, after the first step and before the second step, the step of attaching the other support substrate to the other surface side of the second resin layer and one of the first resin layers It is more preferable to perform a step of peeling the support substrate from the surface side.</p><p> On the other hand, in the first step, one surface of the second resin layer and the back surface of the semiconductor IC are overlapped so as to face each other, and the other surface of the first resin layer and the main surface of the semiconductor IC face each other. It is also preferable to include a step of superimposing these. In this case, in the first step, it is preferable to mount the semiconductor IC on one surface of the second resin layer with reference to the alignment mark formed on one or the other surface of the second resin layer. Further, it is more preferable that the first step is performed with the support substrate attached to the other surface side of the second resin layer.</p><p> In the third step, it is preferable to set the width of the wiring pattern on the conductive protrusions to be smaller than the diameter of the protruding portion of the conductive protrusions. It is also preferable to further include a fourth step of forming through electrodes that penetrate the first and second resin layers.</p>

<p> According to the present invention, as a method of exposing the conductive protrusions provided on the semiconductor IC, the thickness of the first resin layer is reduced as a whole by a wet blast method or the like instead of laser irradiation. Even when the electrode pitch is narrow, the conductive protrusions can be correctly cueed. Moreover, cueing can be performed in a short time regardless of the number of conductive protrusions. Further, since smear is not generated as in the case of forming minute vias by laser irradiation, it is possible to omit the desmear treatment.</p><p> Further, when mounting a semiconductor IC, if the alignment is aligned with the alignment mark as a reference, high mounting position accuracy can be obtained.</p><p> Further, if the width of the wiring pattern formed on the first resin layer is set smaller than the diameter of the protruding portion of the conductive protrusion, short-circuit defects can be prevented even when the electrode pitch is particularly narrow. It becomes possible to do.</p><p> As a result, according to the present embodiment, it is possible to solve various problems that have conventionally occurred when a semiconductor IC having a narrow electrode pitch is embedded in a substrate.</p>

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view showing the structure of the semiconductor IC built-in substrate 100 according to the preferred first embodiment of the present invention.

As shown in FIG. 1, the semiconductor IC-embedded substrate 100 according to the present embodiment includes the laminated resin layers 111 to 114, the semiconductor IC 120 embedded between the resin layer 111 and the resin layer 112, and the alignment mark 130. , Various wiring patterns 140,150,161,162 and through electrodes 152,163 to 165 are provided. Stud bumps 121, which are a type of conductive protrusions, are formed on the pad electrodes (not shown in FIG. 1) of the semiconductor IC 120, and each pad electrode is formed via the corresponding stud bump 121. It is electrically connected to the wiring pattern 150. As shown in FIG. 1, the stud bump 121 projects from the surface of the resin layer 111.

However, in the present invention, the conductive protrusions provided on the semiconductor IC 120 are not limited to stud bumps, and various bumps such as plate bumps, plated bumps, and ball bumps can be used. When stud bumps are used as the conductive protrusions, silver or copper can be formed by wire bonding, and when plate bumps are used, they can be formed by plating, sputtering or vapor deposition. When a plated bump is used, it can be formed by plating. When a ball bump is used, a solder ball is placed on the land electrode and then melted, or cream solder is placed on the land electrode. After printing on, it can be formed by melting it. The metal type that can be used for the conductive protrusion is not particularly limited, and for example, gold (Au), silver (Ag), copper (Cu), nickel (Ni), tin (Sn), chromium (Cr), nickel. -Chromium alloy (Ni-Cr), solder, etc. can be used. Further, it is also possible to use a bump obtained by screen-printing a conductive material and curing it into a conical or columnar bump, or by printing a nanopaste and sintering it by heating.

The height of the conductive protrusions such as the stud bump 121 is preferably set to about 5 to 200 μm, and particularly preferably set to about 10 to 80 μm. This is because if the height is less than 5 μm, all the resin layer 111 covering the main surface 120a of the semiconductor IC 120 disappears in the cueing process of the stud bump 121 described later, and the main surface 120a of the semiconductor IC 120 is damaged. This is because there is a risk of joining. On the other hand, it is difficult to form a conductive protrusion having a height of more than 200 μm, and the height variation becomes large.

Although not shown in FIG. 1, a passive component such as a capacitor can be mounted on at least one of the wiring patterns 161, 162 of the outermost layer.

In the semiconductor IC built-in substrate 100 according to the present embodiment, the built-in semiconductor IC 120 is thinned by polishing, whereby the overall thickness of the semiconductor IC built-in substrate 100 can be reduced to 1 mm or less, for example, about 200 μm. It is possible. Further, as will be described later, in the present embodiment, the semiconductor IC 120 is aligned with the alignment mark 130, and therefore, the position of each stud bump 121 in the plane direction and the relative position of the various wiring patterns 140, 150, 161, 162. There is very little deviation in the relationship.

FIG. 2 is a schematic perspective view showing the structure of the semiconductor IC 120.

As shown in FIG. 2, the semiconductor IC 120 is a bare-chip semiconductor IC, and its main surface 120a is provided with a large number of pad electrodes 121a. As will be described later, in the semiconductor IC built-in substrate 100 according to the present embodiment, since the stud bumps 121 are cueed collectively by the wet blast method, there is no problem when the pad electrodes are exposed by laser irradiation as in the conventional case. .. Therefore, although not particularly limited, it is possible to use a semiconductor IC having a pad electrode 121a having a pitch (electrode pitch) of 100 μm or less, for example, 60 μm.

Further, the back surface 120b of the semiconductor IC 120 is polished, so that the thickness t (distance from the main surface 120a to the back surface 120b) of the semiconductor IC 120 is much thinner than that of a normal semiconductor IC. The thickness t of the semiconductor IC 120 is not particularly limited, but is preferably set to 200 μm or less, for example, about 20 to 100 μm. It is preferable that the back surface 120b is polished on a large number of semiconductor ICs in a wafer state at once, and then separated into individual semiconductor ICs 120 by dicing. When the semiconductor IC 120 is separated into individual semiconductor ICs 120 by dicing before being thinned by polishing, the work efficiency is good if the back surface 120b is polished with the main surface 120a of the semiconductor IC 120 covered with a thermosetting resin or the like.

However, in the present invention, the thinning method of the semiconductor IC 120 is not limited to polishing, and other methods such as etching, plasma treatment, laser irradiation, and blasting may be used.

Further, a stud bump 121 is formed on each pad electrode 121a. The size of the stud bump 121 may be appropriately set according to the electrode pitch. For example, when the electrode pitch is about 100 μm, the diameter should be set to about 30 to 80 μm and the height should be set to about 10 to 80 μm. Just do it. The stud bumps 121 can be formed by separating them into individual semiconductor ICs 120 by dicing and then forming them on each pad electrode 121a using a wire bonder. The material of the stud bump 121 is not particularly limited, but it is preferable to use copper (Cu). When copper (Cu) is used as the material of the stud bump 121, higher bonding strength can be obtained with respect to the pad electrode 121a as compared with the case where gold (Au) is used, and the reliability is improved.

As shown in FIG. 1, in the semiconductor IC built-in substrate 100 according to the present embodiment, the main surface 120a of the semiconductor IC 120 is directly covered by the resin layer 111, and the back surface 120b of the semiconductor IC 120 is directly covered by the resin layer 112. Further, the stud bump 121 of the semiconductor IC 120 protrudes from the surface of the resin layer 111, and is connected to the wiring pattern 150 at this protruding portion.

Further, a metal layer 122 is formed on the back surface 120b of the semiconductor IC 120. The metal layer 122 serves as a heat dissipation path for heat generated by the operation of the semiconductor IC 120, and also plays a role of more effectively preventing cracks generated on the back surface 120b of the semiconductor IC 120. Furthermore, it also plays a role of improving the handleability of the semiconductor IC 120.

The metal layer 122 is connected to the wiring pattern 162 formed in the outermost layer by a through electrode 165 provided so as to penetrate the resin layers 112 and 114. Since the through silicon via 165 serves as a heat dissipation path for the heat generated by the semiconductor IC 120, the heat can be dissipated to the motherboard extremely efficiently. Therefore, although not particularly limited, it is possible to select a digital IC having a very high operating frequency, such as a CPU or DSP, as the type of the semiconductor IC 120.

As the material of the resin layers 111 to 114, any thermosetting or thermoplastic resin can be used as long as it is a material having reflow durability. Specifically, epoxy resin, bismaleimide-triazine resin (BT resin), phenol resin, vinylbenzyl resin, polyphenylene ether (polyphenylene ether oxide) resin (PPE, PPO), cyanate resin, benzoxazine resin, polyimide resin, aromatic Group polyester resin, polyphenylene sulfide resin, polyetherimide resin, polyarylate resin, polyether ether ketone resin and the like can be selected. Further, a material obtained by impregnating a non-woven fabric such as glass cloth, aramid, or aromatic polyester with the above resin, or a material containing the above resin with a filler may be used.

Next, the manufacturing method of the semiconductor IC built-in substrate 100 shown in FIG. 1 will be described with reference to the drawings.

3 to 22 are process diagrams for explaining the manufacturing method of the semiconductor IC built-in substrate 100 shown in FIG.

First, as shown in FIG. 3, a resin layer 111 on which the alignment mark 130 is formed is prepared, and the support substrate 181 is attached to the resin layer 111. The alignment mark 130 may be formed by patterning a conductor layer formed on the surface of the resin layer 111, or may be formed on the surface of the resin layer 111 by a transfer method. In any case, since the alignment mark 130 is used for the alignment of the semiconductor IC 120, it is necessary to accurately control the formation position thereof. The alignment mark 130 may be replaced by an actual wiring pattern, or may be a pattern dedicated to alignment.

The material of the support substrate 181 is not particularly limited, but for example, nickel (Ni) or stainless steel can be used. The thickness of the support substrate 181 is not particularly limited as long as the required mechanical strength is secured, and may be set to, for example, about 50 to 2000 μm. On the other hand, the thickness of the resin layer 111 needs to be at least higher than the height of the stud bump 121.

Next, as shown in FIG. 4, the semiconductor IC 120 is mounted on the surface of the resin layer 111 while aligning with the alignment mark 130. In this embodiment, the semiconductor IC 120 is mounted in a face-down manner, that is, the main surface 120a is on the lower side. At this time, in the case of a thermosetting resin, the resin layer 111 is melted by heating, or in the case of a thermoplastic resin, the stud bump 121 is sunk into the resin layer 111 due to its elasticity. As a result, the semiconductor IC 120 is temporarily fixed to the resin layer 111. Further, the main surface 120a of the semiconductor IC 120 and the resin layer 111 are in contact with each other. When the material of the resin layer 111 is a thermosetting resin, it can be completely fixed by heating thereafter. Further, even in the case of a thermoplastic resin, it is possible to improve the adhesion by heating and melting and fix the resin.

Next, as shown in FIG. 5, the laminated sheets of the uncured or semi-cured resin layer 112 and the conductor layer 140a are stacked so that the resin layer 112 and the back surface 120b of the semiconductor IC 120 face each other, and both are applied while applying heat. Press. As a result, the resin layer 112 is cured, and as shown in FIG. 6, the back surface 120b and the side surface 120c of the semiconductor IC 120 are completely covered by the resin layer 112. Further, when the material of the resin layer 112 is a thermoplastic material, the same state is obtained by pressing both of them while applying heat after superimposing them. That is, at this point, the semiconductor IC 120 is in a state of being sandwiched between the resin layers 111 and 112.

Next, as shown in FIG. 6, another support substrate 182 is attached to the surface opposite to the support substrate 181 when viewed from the semiconductor IC 120. In this way, after the other support substrate 182 is attached, the previously attached support substrate 181 is peeled off as shown in FIG.

Next, as shown in FIG. 8, the surface of the resin layer 111 is etched by the wet blast method. In the wet blast method, the etching rate differs depending on the malleability of the material to be etched. Specifically, a material having a relatively low malleability (such as a cured resin) has a high etching rate and a material having a relatively high malleability. Etching rate is small for (metal, etc.). Therefore, when the surface of the resin layer 111 is etched by the wet blast method, the stud bump 121 provided on the semiconductor IC 120 can be made to protrude from the surface of the resin layer 111 by adjusting the etching amount and the etching conditions. The amount of protrusion is not particularly limited, but is preferably set to about 0.1 to 20 μm.

However, the method for reducing the thickness of the resin layer 111 is not limited to the wet blast method, and other etching methods such as a drive last method, an ion milling method, and a plasma etching method may be used. However, it is very preferable to use the wet blast method because a sufficient selection ratio can be secured, high processing accuracy can be obtained, and work efficiency is excellent. As a method of reducing the thickness of the resin layer 111, polishing using a buff or the like is not suitable in the present invention. This is because, in polishing using a buff or the like, the stud bump 121 and the resin layer 111 become the same plane, and not only the stud bump 121 cannot be projected, but also the conductive material constituting the stud bump 121 depending on the polishing conditions. Is a streak in the direction of rotation of the buff and extends, which may cause a short circuit.

In this way, as a method of exposing the stud bump 121, instead of forming a laser via on the resin layer 111 by laser irradiation as in the conventional case, the thickness of the resin layer 111 is reduced as a whole by a wet blast method or the like. Therefore, even when the electrode pitch is narrow, the stud bumps 121 can be correctly cueed all at once.

Next, as shown in FIG. 9, by irradiating the laser from the resin layer 111 side, a through hole 112a penetrating the resin layers 111 and 112 is formed. However, a method other than laser irradiation may be used to form the through hole 112a.

Next, as shown in FIG. 10, a thin base conductor layer 151 is formed on the entire surface on the resin layer 111 side including the inside of the through hole 112a by a vapor phase growth method such as a sputtering method. As a result, the portion of the conductor layer 140a exposed at the bottom of the through hole 112a and the protruding portion of the stud bump 121 are directly covered by the base conductor layer 151. However, in forming the base conductor layer 151, an electroless plating method or a thin film deposition method may be used instead of the vapor phase growth method. Since unnecessary portions of the base conductor layer 151 are subsequently removed, the thickness of the base conductor layer 151 needs to be set sufficiently thin, and is preferably set to about 0.005 to 3 μm, for example, about 0.3 to 2 μm.

In the present embodiment, since the stud bump 121 is in a state of protruding from the surface of the resin layer 111 by the wet blast treatment, pretreatment such as removal of etching residue is performed before forming the base conductor layer 151. There is no need to do. That is, if the stud bump 121 and the resin layer 111 are on the same plane, the surface of the stud bump 121 may be covered with the etching residue, and if the base conductor layer 151 is formed as it is, conduction failure may occur. is there. On the other hand, if the wet blast treatment is performed under the condition that the stud bump 121 protrudes from the surface of the resin layer 111 as in the present embodiment, the etching residue is surely removed from the surface of the stud bump 121. It is possible to form the base conductor layer 151 without performing any treatment or the like.

Next, as shown in FIG. 11, after the photosensitive dry films 101 and 102 are attached to both sides of the base material, that is, the surface of the base conductor layer 151 and the surface of the support substrate 182, respectively, a photomask (not shown) is used. The dry film 101 is exposed to remove the dry film 101 in the region 150a where the wiring pattern 150 should be formed. As a result, the base conductor layer 151 is exposed in the region 150a where the wiring pattern 150 should be formed.

At this time, the dry film 102 is not removed, whereby the surface of the support substrate 182 is kept substantially entirely covered. The thickness of the dry film 101 needs to be set to be slightly thicker than that of the wiring pattern 150. For example, when the thickness of the wiring pattern 150 is about 20 μm, the thickness of the dry film 101 is about 25 μm. You can set it. On the other hand, the dry film 102 is provided for the purpose of preventing the surface of the support substrate 182 from being plated, and its thickness is arbitrary.

Here, the region 150a on which the wiring pattern 150 should be formed includes a region corresponding to the stud bump 121 as shown in FIG. When a semiconductor IC 120 having a very narrow electrode pitch is used, a large deviation in the positional relationship between the stud bump 121 and the region 150a in the plane direction is not allowed, but in the present embodiment, the semiconductor IC 120 is aligned with the alignment mark 130. Therefore, it is possible to reduce the deviation that occurs in the positional relationship between the stud bump 121 and the region 150a in the plane direction.

Here, in the example shown in FIG. 11, the width of the region 150a in which the wiring pattern 150 should be formed is set to be larger than the diameter of the stud bump 121, but when the electrode pitch is particularly narrow, the wiring pattern 150 is formed. By setting the width of the region 150a to be to be smaller than the diameter of the stud bump 121, it is possible to secure a manufacturing margin.

That is, as shown in FIG. 12, which is a schematic plan view, when the diameter of the protruding portion of the stud bump 121 is A and the width of the region 150a in which the wiring pattern 150 is to be formed is B, A &lt;B or When A = B, as shown in FIG. 13, if a large deviation occurs during patterning of the dry film 101, two stud bumps 121 will be included in one region 150a. When such a deviation occurs, these two stud bumps 121 are finally short-circuited by the wiring pattern 150, resulting in a short-circuit defect.

Such a problem can be solved by setting A&gt; B as shown in FIG. 14 when the diameter of the protruding portion of the stud bump 121 is A and the width of the region 150a in which the wiring pattern 150 is to be formed is B. can be solved. According to this, even if some deviation occurs during patterning of the dry film 101, it is possible to reduce the possibility that the two stud bumps 121 are included in one region 150a. Specifically, the margin is expanded by the distance given by AB as compared with the case where A = B. Therefore, assuming that the feasible margin is X, if the width B of the region 150a is set so as to satisfy B &lt;AX, it is possible to reliably prevent short circuits of adjacent stud bumps 121.

However, it is not essential to set A&gt; B in the present invention, and A &lt;B or A = B may be set as in the example shown in FIG.

After exposing a part of the base conductor layer 151 in this way, as shown in FIG. 15, electrolytic plating is performed using the base conductor layer 151 as a base. As a result, the wiring pattern 150 is formed in the region 150a where the base conductor layer 151 is exposed. Therefore, if the width of the region 150a is set to B, the width of the formed wiring pattern 150 is also B. Further, the inside of the through hole 112a is filled with the through electrode 152. That is, the through electrode 152 penetrates the resin layers 111 and 112, whereby the conductor layer 140a and the wiring pattern 150 are connected via the through electrode 152. Since the entire surface of the support substrate 182 is substantially covered with the dry film 102, no plating is formed.

The type of plating solution may be appropriately selected according to the material to be formed of the wiring pattern 150 and the through electrode 152. For example, when these materials are copper (Cu), a copper sulfate bath is used as the plating solution. Should be used.

Next, as shown in FIG. 16, the dry films 101 and 102 are peeled off, and further, the unnecessary base conductor layer 151 in the portion where the wiring pattern 150 is not formed is removed (soft etching) using an etching solution such as acid. ..

Next, as shown in FIG. 17, the laminated sheet of the resin layer 113 and the conductor layer 171 is pressed and heated. As a result, as shown in FIG. 18, the wiring pattern 150 and the resin layer 111 are covered with the resin layer 113.

Next, the support substrate 182 attached later is peeled off, and the exposed conductor layer 140a is patterned to form the wiring pattern 140 as shown in FIG.

Next, as shown in FIG. 20, the laminated sheet of the resin layer 114 and the conductor layer 172 is pressed and heated. As a result, as shown in FIG. 21, the wiring pattern 140 and the resin layer 112 are covered with the resin layer 114.

Further, as shown in FIG. 22, after removing or thinning the conductor layers 171,172, through holes 113a, 114a, 114b are formed by laser irradiation or the like. The through hole 113a is a through hole that penetrates the resin layer 113 to expose the wiring pattern 150, the through hole 114a is a through hole that penetrates the resin layer 114 and exposes the wiring pattern 140, and the through hole 114b is. , A through hole that penetrates the resin layers 114 and 112 to expose the metal layer 122.

Then, a thin base conductor layer 160 is formed on the entire surface including the inside of the through holes 113a, 114a, 114b, and then the same steps as those described with reference to FIGS. 11, 15 and 16 are performed. The outermost wiring patterns 161, 162 shown in FIG. 1 are formed. By this step, the inside of the through hole 113a is filled with the through electrode 163, whereby the wiring pattern 161 and the wiring pattern 150 are connected. Further, the inside of the through hole 114a is filled with the through electrode 164, whereby the wiring pattern 162 and the wiring pattern 140 are connected. Further, the inside of the through hole 114b is filled with the through electrode 165, whereby the wiring pattern 162 and the metal layer 122 are connected.

In this way, the semiconductor IC built-in substrate 100 shown in FIG. 1 is completed.

As described above, in the present embodiment, as a method of exposing the stud bump 121, the thickness of the resin layer 111 is reduced as a whole by a wet blast method or the like instead of laser irradiation. Therefore, the electrode pitch Even when the stud bump 121 is narrow, the stud bump 121 can be cued correctly. Moreover, regardless of the number of stud bumps 121, the stud bumps 121 can be cueed in a short time. Further, since smear is not generated as in the case of forming minute vias by laser irradiation, it is possible to omit the desmear treatment.

In particular, in the present embodiment, the wet blast method is used as the cueing method of the stud bump 121, and the stud bump 121 is projected from the surface of the resin layer 111 by adjusting the etching amount and the etching conditions. It is not necessary to perform pretreatment such as removal of etching residue before forming 151.

Further, when the semiconductor IC 120 is mounted, the alignment mark 130 formed on the surface of the resin layer 111 is used as a reference for alignment, so that high mounting position accuracy can be obtained.

As a result, according to the present embodiment, it is possible to solve various problems that have conventionally occurred when a semiconductor IC having a narrow electrode pitch is embedded in a substrate. Moreover, in the present embodiment, since the semiconductor IC 120 is mounted in a face-down manner, the stud bump 121 can be mounted while recognizing an image from the lower side, so that extremely high mounting position accuracy can be obtained. It becomes.

Further, since the thickness t of the semiconductor IC 120 used in the present embodiment is set to be very thin by polishing or the like, the thickness of the entire semiconductor IC built-in substrate 100 is set to be very thin, for example, about 200 μm. It becomes possible.

Further, in the present embodiment, in most of the series of steps, the process is carried out while the base material in progress is held by the support substrate 181 or the support substrate 182, so that the handleability is improved and the base material is improved. It is possible to reduce the load on the semiconductor IC 120 due to cracks, chips, and deformation. In addition, it is possible to prevent dimensional changes and distortions of the base material during patterning. As a result, the deviation and distortion between the stud bump 121 and the wiring pattern 150 can be suppressed, and the connection stability can be improved.

Moreover, if the width (B) of the wiring pattern 150 is set to be smaller than the diameter (A) of the protruding portion of the stud bump 121, short-circuit defects can be prevented even when the electrode pitch is particularly narrow. It becomes possible. Such a configuration is difficult to adopt by the method of exposing the stud bump 121 by laser irradiation, and this point is also a great advantage of the present embodiment in which the stud bump 121 is cueed by the wet blast method.

That is, in the method of exposing the stud bump 121 by laser irradiation, the reduction of the laser aperture diameter is limited to about 50 μm to 80 μm. Moreover, since misalignment inevitably occurs during laser irradiation, if the diameter of the stud bump 121 is, for example, about 50 to 60 μm, it is virtually impossible to correctly expose only the desired stud bump 121 by laser irradiation. It becomes. The laser after forming the vias over the case of forming a wiring pattern 150 by using a semi-additive method, the width of the wiring pattern 150 (B) attempts to set the same or less than the diameter of the via, a dry film There will be problems with the exposure, development, and peelability of the film, and it will not be possible to pattern correctly. Even when the subtractive method is used, if the width (B) of the wiring pattern 150 is made smaller than the diameter of the via, the plating inside the via is also etched, resulting in an open defect.

As described above, in the method of exposing the stud bump 121 by laser irradiation, it is extremely difficult to set the width (B) of the wiring pattern 150 to be smaller than the diameter of the stud bump 121. On the other hand, in the present embodiment, since the stud bump 121 is cueed by using the wet blast method, such a problem does not occur and the width (B) of the wiring pattern 150 is set to the stud bump 121. It is possible to set it to be smaller than the diameter (A) of the protruding portion of.

Next, the semiconductor IC built-in substrate according to the preferred second embodiment of the present invention will be described.

FIG. 23 is a schematic cross-sectional view showing the structure of the semiconductor IC built-in substrate 200 according to the preferred second embodiment of the present invention.

As shown in FIG. 23, the semiconductor IC built-in substrate 200 according to the present embodiment includes the laminated resin layers 211 to 214, the semiconductor IC 220 embedded between the resin layer 211 and the resin layer 212, and the alignment mark 230. , Various wiring patterns 250,261,262 and through electrodes 252,263 to 265 are provided. The semiconductor IC 220 has the same configuration as the semiconductor IC 120 shown in FIG. Also in this embodiment, the stud bump 221 protrudes from the surface of the resin layer 211, and is electrically connected to the wiring pattern 250 at the protruding portion.

Also in this embodiment, a passive component such as a capacitor can be mounted on at least one of the wiring patterns 261,262 of the outermost layer. Further, as the material of the resin layers 211 to 214, the same materials as those of the resin layers 111 to 114 in the first embodiment can be used.

Next, a method of manufacturing the semiconductor IC built-in substrate 200 shown in FIG. 23 will be described with reference to the drawings.

24 to 38 are process diagrams for explaining the manufacturing method of the semiconductor IC built-in substrate 200 shown in FIG. 23.

First, as shown in FIG. 24, a resin layer 213 having conductor layers 230a and 271 formed on both sides is prepared, and a support substrate 281 is attached to the resin layer 213.

Next, as shown in FIG. 25, the conductor layer 230a is patterned to form the alignment mark 230. The alignment mark 230 in this embodiment is a pattern that is also used as an actual wiring pattern.

Next, as shown in FIG. 26, the resin layer 212 covering the resin layer 213 and the alignment mark 230 is formed.

Next, as shown in FIG. 27, the semiconductor IC 220 is mounted on the surface of the resin layer 212 while being aligned using the alignment mark 230. In this embodiment, the semiconductor IC 220 is mounted in a face-up manner, that is, the main surface 220a is on the upper side. As a result, the back surface 220b of the semiconductor IC 220 is completely covered with the resin layer 212.

Next, as shown in FIG. 28, the laminated sheets of the resin layer 211 and the conductor layer 270 are stacked so that the resin layer 211 and the main surface 220a of the semiconductor IC 220 face each other, and both are pressed while applying heat. As a result, as shown in FIG. 29, the main surface 220a and the side surface 220c of the semiconductor IC 220 are completely covered by the resin layer 211. That is, at this point, the semiconductor IC 220 is sandwiched between the resin layers 211 and 212.

Next, as shown in FIG. 30, after removing the conductor layer 270, the surface of the resin layer 211 is etched by a wet blast method or the like. At this time, as in the above embodiment, the stud bump 221 provided on the semiconductor IC 220 is projected from the surface of the resin layer 211 by adjusting the etching amount and the etching conditions.

Next, as shown in FIG. 31, by irradiating the laser from the resin layer 211 side, a through hole 211a penetrating the resin layers 211 and 212 is formed. However, a method other than laser irradiation may be used to form the through hole 211a.

Next, as shown in FIG. 32, a thin base conductor layer 251 is formed on the entire surface of the resin layer 211 side including the inside of the through hole 211a by a vapor phase growth method such as a sputtering method. As a result, the portion of the alignment mark 230 exposed at the bottom of the through hole 211a and the protruding portion of the stud bump 221 are directly covered by the base conductor layer 251. Also in this embodiment, since the stud bump 221 is in a state of protruding from the surface of the resin layer 211 by the wet blast treatment, pretreatment such as removal of etching residue is performed before forming the base conductor layer 251. You don't have to do it.

Next, as shown in FIG. 33, the photosensitive dry films 201 and 202 are attached to both sides of the base material, that is, the surface of the base conductor layer 251 and the surface of the support substrate 281, respectively, and then a photomask (not shown) is used. The dry film 201 is exposed to remove the dry film 201 in the region 250a where the wiring pattern 250 should be formed. As a result, the base conductor layer 251 is exposed in the region 250a where the wiring pattern 250 should be formed. At this time, the dry film 202 is not removed, whereby the surface of the support substrate 281 is kept substantially entirely covered.

Also in this embodiment, the region 250a on which the wiring pattern 250 should be formed includes the region corresponding to the stud bump 221 as shown in FIG. 33, but the semiconductor IC 220 is aligned with the alignment mark 230. Therefore, there is little deviation in the positional relationship between the stud bump 221 and the region 250a in the plane direction.

Again, when the electrode pitch is particularly narrow, it is preferable to set A&gt; B when the diameter of the protruding portion of the stud bump 221 is A and the width of the region 250a where the wiring pattern 250 should be formed is B. ..

After exposing a part of the base conductor layer 251 in this way, as shown in FIG. 34, electrolytic plating is performed using the base conductor layer 251 as a base. As a result, the wiring pattern 250 is formed in the region 250a where the base conductor layer 251 is exposed. Therefore, if the width of the region 250a is set to B, the width of the formed wiring pattern 250 is also B. Further, the inside of the through hole 211a is filled with the through electrode 252. That is, the through electrode 252 penetrates the resin layers 211 and 212, whereby the alignment mark 230 and the wiring pattern 250 are connected via the through electrode 252. Since the entire surface of the support substrate 281 is substantially covered with the dry film 202, no plating is formed.

Next, as shown in FIG. 35, the dry films 201 and 202 are peeled off, and further, the unnecessary base conductor layer 251 in the portion where the wiring pattern 250 is not formed is removed (soft etching) using an etching solution such as acid. ..

Next, as shown in FIG. 36, the laminated sheet of the resin layer 214 and the conductor layer 272 is pressed and heated. As a result, as shown in FIG. 37, the wiring pattern 250 and the resin layer 211 are covered with the resin layer 214. Then, the support substrate 281 is peeled off.

Further, as shown in FIG. 38, after removing or thinning the conductor layers 271,272, through holes 213a, 213b, 214a are formed by laser irradiation or the like. The through hole 213a is a through hole that penetrates the resin layer 213 to expose the alignment mark 230, the through hole 213b is a through hole that penetrates the resin layers 213 and 212 to expose the metal layer 222, and the through hole 214a is. , A through hole that penetrates the resin layer 214 and exposes the wiring pattern 250.

Then, a thin base conductor layer 260 is formed on the entire surface including the insides of the through holes 213a, 213b, and 214a, and then the same steps as those described with reference to FIGS. 33 to 35 are performed. The outermost wiring patterns 261,262 shown are formed. By this step, the inside of the through hole 213a is filled with the through electrode 263, whereby the wiring pattern 261 and the alignment mark 230 are connected. Further, the inside of the through hole 213b is filled with the through electrode 264, whereby the wiring pattern 261 and the metal layer 222 are connected. Further, the inside of the through hole 214a is filled with the through electrode 265, whereby the wiring pattern 262 and the wiring pattern 250 are connected.

In this way, the semiconductor IC built-in substrate 200 shown in FIG. 23 is completed.

As described above, also in the present embodiment, the thickness of the resin layer 211 is reduced as a whole by the wet blast method or the like, whereby the stud bump 221 is projected from the surface of the resin layer 211. It is possible to obtain the same effect as that of the above embodiment. Moreover, in the present embodiment, since the semiconductor IC 220 is mounted in a face-up manner, only one support substrate 281 is required, and it is not necessary to replace the semiconductor IC 220 in the middle of the process. Therefore, it is possible to prevent deformation of the base material by a simpler process.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention, and these are also the present invention. Needless to say, it is included in the range.

For example, in the first and second embodiments described above, the conductor pattern is used as the alignment mark, but the alignment mark is not limited to the conductor pattern, and a recess or the like provided in the resin layer is used as the alignment mark. It doesn't matter. As an example, as shown in FIG. 39, a recess 130a is formed in the resin layer 111 by a press using a die 301 having a protrusion 302, and as shown in FIG. 40, the recess 130a is used as an alignment mark and the semiconductor IC 120 is used. May be installed.

Further, in the first embodiment, the alignment mark 130 is provided on the surface of the resin layer 111 on the side on which the semiconductor IC 120 is mounted, but the position of the alignment mark 130 is limited to this. Instead, for example, it may be provided on the surface opposite to the resin layer 111. Similarly, in the second embodiment, the alignment mark 230 is provided on the surface of the resin layer 212 on the side opposite to the side on which the semiconductor IC 220 is mounted, but this is the position of the alignment mark 230. The resin layer 212 may be provided on the surface opposite to the resin layer 212, for example.

Further, in the first and second embodiments described above, the semiconductor IC is directly mounted on the resin layer, but the semiconductor IC may be provided with a die attach film and mounted on the resin layer via the die attach film. Absent. As an example, as shown in FIG. 41, the semiconductor IC 220 may be temporarily fixed to the resin layer 212 by providing a die attach film 229 on the back surface of the semiconductor IC 220 and adhering the die attach film 229 and the resin layer 212. Absent. In this case, the resin layer 212 does not need to have adhesiveness. In the case of the example shown in FIG. 42, since the die attach film 229 is interposed between the back surface 220b of the semiconductor IC 200 and the resin layer 212, they do not come into direct contact with each other. It will be covered by the resin layer 212 through.

<figref num="1">It is a schematic cross-sectional view which shows the structure of the semiconductor IC built-in substrate 100 by the preferable 1st Embodiment of this invention.</figref><figref num="2">It is a schematic perspective view which shows the structure of a semiconductor IC 120.</figref><figref num="3">It is a figure which shows a part (formation of the alignment mark 130) of the manufacturing process of the semiconductor IC built-in substrate 100.</figref><figref num="4">It is a figure which shows a part of the manufacturing process (mounting semiconductor IC 120) of the semiconductor IC built-in substrate 100.</figref><figref num="5">It is a figure which shows a part (pressing of a resin layer 112) of the manufacturing process of the semiconductor IC built-in substrate 100.</figref><figref num="6">It is a figure which shows a part of the manufacturing process (attachment of the support substrate 182) of the semiconductor IC built-in substrate 100.</figref><figref num="7">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 100 (peeling of a support substrate 181).</figref><figref num="8">It is a figure which shows a part (etching of a resin layer 111) of the manufacturing process of the semiconductor IC built-in substrate 100.</figref><figref num="9">It is a figure which shows a part (formation of a through hole 112a) of the manufacturing process of the semiconductor IC built-in substrate 100.</figref><figref num="10">It is a figure which shows a part of the manufacturing process (formation of the base conductor layer 151) of the semiconductor IC built-in substrate 100.</figref><figref num="11">It is a figure which shows a part of the manufacturing process (pasting and exposure of dry films 101, 102) of the semiconductor IC built-in substrate 100.</figref><figref num="12">It is a schematic plan view which shows the relationship between a stud bump 121 and a region 150a which should form a wiring pattern 150, and shows the case where A &lt;B.</figref><figref num="13">It is a schematic plan view which shows the state which a large deviation occurred in the region 150a shown in FIG.</figref><figref num="14">It is a schematic plan view which shows the relationship between the stud bump 121 and the region 150a which should form the wiring pattern 150, and shows the case where A&gt; B.</figref><figref num="15">It is a figure which shows a part (formation of a wiring pattern 150) of the manufacturing process of the semiconductor IC built-in substrate 100.</figref><figref num="16">It is a figure which shows a part of the manufacturing process (removal of dry films 101, 102 and the base conductor layer 151) of the semiconductor IC built-in substrate 100.</figref><figref num="17">It is a figure which shows a part of the manufacturing process (press (before pressing) of a resin layer 113) of the semiconductor IC built-in substrate 100.</figref><figref num="18">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 100 (pressing (after pressing) of resin layer 113).</figref><figref num="19">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 100 (peeling of a support substrate 182).</figref><figref num="20">It is a figure which shows a part of the manufacturing process (press (before pressing) of a resin layer 114) of the semiconductor IC built-in substrate 100.</figref><figref num="21">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 100 (pressing (after pressing) of resin layer 114).</figref><figref num="22">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 100 (the formation of the through hole 113a, 114a, 114b and the base conductor layer 160).</figref><figref num="23">It is a schematic sectional drawing which shows the structure of the semiconductor IC built-in substrate 200 by the 2nd Embodiment of this invention.</figref><figref num="24">It is a figure which shows a part of the manufacturing process (attachment of the support substrate 281) of the semiconductor IC built-in substrate 200.</figref><figref num="25">It is a figure which shows a part of the manufacturing process (formation of alignment mark 230) of the semiconductor IC built-in substrate 200.</figref><figref num="26">It is a figure which shows a part (formation of resin layer 212) of the manufacturing process of the semiconductor IC built-in substrate 200.</figref><figref num="27">It is a figure which shows a part of the manufacturing process (mounting semiconductor IC 220) of the semiconductor IC built-in substrate 200.</figref><figref num="28">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 200 (press of resin layer 211 (before press)).</figref><figref num="29">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 200 (pressing (after pressing) of resin layer 211).</figref><figref num="30">It is a figure which shows a part (etching of a resin layer 211) of the manufacturing process of the semiconductor IC built-in substrate 200.</figref><figref num="31">It is a figure which shows a part (formation of a through hole 211a) of the manufacturing process of the semiconductor IC built-in substrate 200.</figref><figref num="32">It is a figure which shows a part of the manufacturing process (formation of the base conductor layer 251) of the semiconductor IC built-in substrate 200.</figref><figref num="33">It is a figure which shows a part of the manufacturing process (pasting and exposure of dry films 201, 202) of the semiconductor IC built-in substrate 200.</figref><figref num="34">It is a figure which shows a part (formation of a wiring pattern 250) of the manufacturing process of the semiconductor IC built-in substrate 200.</figref><figref num="35">It is a figure which shows a part of the manufacturing process (removal of dry films 201, 202 and the base conductor layer 251) of the semiconductor IC built-in substrate 200.</figref><figref num="36">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 200 (press of resin layer 214 (before press)).</figref><figref num="37">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 200 (pressing (after pressing) of resin layer 214).</figref><figref num="38">It is a figure which shows a part of the manufacturing process of the semiconductor IC built-in substrate 200 (formation of through hole 213a, 213b, 214a and base conductor layer 260).</figref><figref num="39">It is a figure for demonstrating the method of forming the recess 130a in the resin layer 111.</figref><figref num="40">It is a figure which shows the state which mounted the semiconductor IC 120 with the recess 130a provided in the resin layer 111 as an alignment mark.</figref><figref num="41">It is a figure which shows the state which mounted the semiconductor IC 220 on the resin layer 212 via the die attach film 229.</figref>

Code description

100,200 Semiconductor IC built-in substrate 101,102,201,202 Dry film 111-114,211-214 Resin layer 112a, 113a, 114a, 114b, 211a, 213a, 213b, 214a Through hole 120,220 Semiconductor IC 120a, 220a Main surface of semiconductor IC 120b, 220b Back surface of semiconductor IC 120c , 220c Side of semiconductor IC 121,221 Stud bump 121a Pad electrode 122,222 Metal layer 130,230 Alignment mark 130a Recess 140,150,161,162,250,261,262 Wiring pattern 140a,171,172,230a,271,261,262,270,271,272 Conductor layer 150a,250a Region where conductor layer should be formed 151,160,251,260 Through electrode 181,182,281 Support substrate 229 Dia-attach film 301 Mold 302 Protrusion