Thin film transistor array substrate and liquid crystal display

The present invention generally relates to a device array substrate and a display panel, and more specifically to a thin film transistor (TFT) array substrate and a liquid crystal display (LCD) panel having antistatic performance.

With the rapid progress of electro-optical technology and semiconductor manufacturing technology in recent years, the development of flat display panels has progressed rapidly. Among flat display panels, the thin film transistor liquid crystal display panel (TFT-LCD) type has become mainstream due to low voltage operation, high speed operation, light weight and reduced space requirements.

The thin film transistor LCD mainly includes an LCD panel and a backlight module, and the LCD panel has a color filter (C / F), a thin film transistor array substrate (TFT array substrate), and a liquid crystal layer arranged between the filter and the substrate. The backlight module serves to provide the planar light source required for the LCD panel to display the image.

FIG. 1 shows a substrate 110, multiple scan lines 120, multiple data lines 130, multiple pixel units 150, multiple scan bonding pads 160, multiple data bonding pads 170, multiple inner antistatic protection rings 192, and multiple. FIG. 5 shows a conventional TFT array substrate 100 with an outer antistatic protective ring 194.

The substrate 110 includes a display area 112 and a peripheral circuit area 114. The scanning lines 120 and the data lines 130 are arranged on the substrate 110, and the scanning lines 120 and the data lines 130 divide the display area 112 into a plurality of pixel areas 140. Each of the pixel units 150 is arranged in one of the pixel areas 140 and is driven by scanning lines 120 and data lines 130. The pixel unit 150 includes a TFT 152 and a pixel electrode 154.

In FIG. 1, the scanning bonding pad 160 is located in the peripheral circuit area 114 and is electrically connected to the scanning line 120. The data bonding pad 170 is located in the peripheral circuit area 114 and is electrically connected to the data line 130. The inner antistatic protection ring 192 is similarly disposed in the peripheral circuit area 114 between the scanning bonding pad 160 and the display area 112, and between the data bonding pad 170 and the display area 112. Further, the inner antistatic protection ring 192 is electrically connected to the scanning line 120 and the data line 130, and is composed of an active switch element (for example, a TFT or a diode) and a scanning line 120 and the data line 130 surrounding the active switch element. It is a charge protection circuit. Further, the outer antistatic protective ring 194 is located in the peripheral circuit region 114 and is located between the scanning bonding pad 160 and the outside of the substrate 110 and between the data bonding pad 170 and the outside of the substrate 110. Similarly, the outer antistatic protection ring 194 is electrically connected to the scan line 120 and the data line 130 and is charged with an active switch element (eg, a TFT or diode) and the scan line and data line surrounding the active switch element. It is a protection circuit.

The TFT substrate 100 tends to accumulate static charges due to external factors such as transportation during the manufacture of the TFT substrate or changes in the environment. Therefore, when the static charge is accumulated to a certain extent, the circuit arranged on the TFT substrate 100 and the TFT 152 may be damaged due to the static charge. Therefore, the inner antistatic protection ring 192 and the outer antistatic protection ring 194 are such that the static charge is TFT so that the locally accumulated static charge does not damage the circuit or the pixel unit 150 of the display area 112. It is used to prevent leakage to the entire substrate 100.

Specifically, the inner antistatic protection ring 192 and the outer antistatic protection ring 194 have a structure connected to the scanning line 120 and the data line 130 via an active switch element (not shown). Therefore, when the static charge on the scan line 120, data line 130 or TFT 152 becomes overloaded, the active switch element is switched on to dissipate the static charge to the inner antistatic protection ring 192 and / or the outer antistatic protection ring 194. And execute the antistatic function.

However, in the design of the inner antistatic protection ring and the outer antistatic protection ring 194, due to the large area and the ease of static charge accumulation, static charge damage is caused, especially in the areas of the scanning bonding pad 160 and the data bonding pad 170. It can still happen. Therefore, if the static charge cannot be dissipated, the circuit arranged on the TFT substrate 100 and the TFT 152 will be damaged by the static charge.

<p> Therefore, the present invention is directed to providing a TFT substrate suitable for further reducing damage caused by static charges by dissipating a large amount of static charges accumulated on the TFT substrate.</p><p> Therefore, the present invention is directed to an LCD panel that utilizes the aforementioned TFT substrate so that the LCD panel can have antistatic protection performance.</p>

<p> Based on the above object or other object, the present invention comprises a substrate, a plurality of scanning lines and data lines, a plurality of pixel units, a plurality of scanning bonding pads and a data bonding pad, and a plurality of first and second switching elements. To provide a TFT array substrate to be provided. The board includes a display area and a peripheral circuit area. Scanning lines and data lines that divide the display area into a plurality of pixel areas are arranged on the substrate. Each pixel unit is located in one of the pixel areas and is driven by a scan line and a data line. The scanning bonding pad is located in the peripheral circuit area and is electrically connected to the scanning line. The data bonding pad is located in the peripheral circuit area and is electrically connected to the data line. The first switching element is arranged in the peripheral circuit area. At least one of the first switching elements is located between two adjacent scanning bonding pads and is electrically connected there. The second switching element is arranged in the peripheral circuit area. At least one of the second switching elements is located between two adjacent data bonding pads and is electrically connected there.</p><p> In one embodiment of the invention, two first switching elements connected in parallel are arranged between two adjacent scanning bonding pads.</p><p> In one embodiment of the invention, two second switching elements connected in parallel are arranged between two adjacent scanning bonding pads.</p><p> In one embodiment of the invention, each of the first switching elements includes a floating gate, a gate insulating layer, a semiconductor layer, a source and a drain. The floating gate is arranged on the substrate and is covered with a gate insulating layer. The semiconductor layer is arranged in the gate insulating layer on the floating gate. The source and drain are located on the semiconductor layer and are electrically connected to scanning bonding pads located on its two sides. Also, the source and drain are arranged asymmetrically or symmetrically.</p><p> In one embodiment of the invention, each of the second switching elements comprises a floating gate, a gate insulating layer, a semiconductor layer, a source and a drain. The floating gate is arranged on the substrate and is covered with a gate insulating layer. The semiconductor layer is arranged in the gate insulating layer on the floating gate. The source and drain are located on the semiconductor layer and are electrically connected to data bonding pads located on their two sides (of the source and drain). Also, the source and drain are arranged asymmetrically or symmetrically.</p><p> In one embodiment of the present invention, each of the pixel units includes a TFT and a pixel electrode. The TFT is located in one of the pixel areas. The pixel electrode is located in one of the pixel areas and is electrically connected to the TFT.</p><p> In one embodiment of the invention, the TFT array substrate is located in a peripheral circuit area and further comprises a plurality of inner protective rings located between the scanning bonding pad and the display area and between the data bonding pad and the display area. .. The inner protection ring is electrically connected to the scan line and the data line.</p><p> In one embodiment of the invention, the TFT array substrate is located in a peripheral circuit area with a plurality of outer protective rings located between the scanning bonding pad and the outside of the substrate and between the data bonding pad and the outside of the substrate. Further prepare. The outer protection ring is electrically connected to the scan line and the data line.</p><p> To achieve these and other advantages, the present invention is a liquid crystal display comprising a color filter substrate, a TFT array substrate and a liquid crystal layer, as embodied and broadly described herein in accordance with the purposes of the invention. Provide a panel. The TFT array substrate may be, for example, the above-mentioned TFT array substrate, and the liquid crystal layer is arranged between the color filter substrate and the TFT array substrate.</p>

<p> The present invention utilizes first and second switching elements located between two adjacent scanning bonding pads and between two adjacent data bonding pads, respectively. When a large amount of static charge is accumulated on the scanning bonding pad or data bonding pad, the first and second switching elements are switched on so that the accumulated electrostatic charge switches the first switching element and the second switching element on. A charge-coupling effect occurs on the switching element of. Therefore, the accumulated electrostatic charge moves between adjacent scanning bonding pads or adjacent data bonding pads, thereby reducing damage to the TFT array substrate caused by the accumulated electrostatic charge.</p>

The present invention will be described in detail below, and examples thereof are shown in the accompanying drawings. Where possible, the same reference numerals are used to refer to the same or similar parts in the drawings and specifications.

FIG. 2 shows a TFT array substrate according to an embodiment of the present invention. The TFT array substrate 200 includes a substrate 210, a plurality of scanning lines 220 and a data line 230, a plurality of pixel units 250, a plurality of scanning bonding pads 260 and a data bonding pad 270, and a plurality of first switching elements 280a and a second switching. It has an element 280b.

The substrate 210 has a display area 212 and a peripheral circuit area 214. A scanning line 220 and a data line 230 that divide the display area 212 into a plurality of pixel areas 240 are arranged on the substrate 210. Each pixel unit 250 is located in one of the pixel areas 240 and is driven by scan lines 220 and data lines 230. The scanning bonding pad 260 is located in the peripheral circuit area 214 and is electrically connected to the scanning line 220. The data bonding pad 270 is located in the peripheral circuit area 214 and is electrically connected to the data line 230. The first switching element 280a and the second switching element 280b are arranged in the peripheral circuit region 214. At least one of the first switching elements 280a (two second switching elements are shown in FIG. 2) is located between two adjacent scanning bonding pads 260 and electrically connected to them. At least one of the second switching elements 280b (two second switching elements are shown in FIG. 2) is located between two adjacent data bonding pads 270 and electrically connected to them.

FIG. 2 is an embodiment of the present invention. Each of the pixel units includes a TFT 252 and a pixel electrode 254. The TFT 252 is located in one of the pixel areas 240. The pixel electrode 254 is located in one of the pixel areas 240 and is electrically connected to the TFT 252.

Further, as shown in FIG. 2, the TFT array substrate 200 is arranged between the scanning bonding pad 260 and the display area 212 and between the data bonding pad 270 and the display area 212, for example, in the peripheral circuit area 214. Further equipped with an inner protective ring 292. The inner protection ring 292 is electrically connected to the scan line 220 and the data line 230. The TFT array substrate 200 further comprises a plurality of outer protection rings 294 located between the scanning bonding pad 260 and the outside of the substrate 210 and between the data bonding pad 270 and the outside of the substrate 210, for example in the peripheral circuit area 214. The outer protection ring 294 is electrically connected to the scan line 220 and the data line 230.

Specifically, the inner antistatic protection ring 292 or the outer antistatic protection ring 294 is a structure connected to the scanning line 220 and the data line 230 via an active switch element (not shown). Therefore, when the static charge on the scan line 220, data line 230 or TFT 252 becomes overloaded, the active switch element is switched on to dissipate the static charge to the inner antistatic protection ring 292 and / or the outer antistatic protection ring 294. To realize the antistatic effect. However, a large amount of static charge is still accumulated in the areas of the scanning bonding pad 260 and the data bonding pad 270. Therefore, in the present invention, the first switching element 280a and the second switching element 280b are arranged between the two adjacent scanning bonding pads 260 and between the two adjacent data bonding pads 270, respectively. In one embodiment of the invention, two first switching elements 280a connected in parallel are arranged between two adjacent scanning bonding pads 260. In one embodiment of the present invention, two second switching elements 280b connected in parallel are arranged between two adjacent data bonding pads 270 to discharge static charges bidirectionally.

FIG. 3 is an enlarged top view of the scanning bonding pad arranged at position A shown in FIG. FIG. 3A is a cross-sectional view taken along the line A-A'of FIG. 3, and FIG. 3B is a cross-sectional view taken along the line B-B'of FIG.

In FIGS. 3 and 3A of one embodiment of the invention, each of the first switching elements 280a comprises a floating gate 282a, a gate insulating layer 284, a semiconductor layer 286a, and a source and drain 288a. The floating gate 282a is arranged on the substrate 210, and the gate insulating layer 284 covers the floating gate 282a. The semiconductor layer 286a is arranged in the gate insulating layer 284 on the floating gate 282a. The source and drain 288a are located on the semiconductor layer 286a and are electrically connected to scanning bonding pads 260 located on both sides of the source and drain.

In the conventional process of forming a pixel array, conductor lines (scanning lines and data lines, etc.), TFTs and pixel electrodes are formed on the substrate 210. The conventional process of forming a pixel array may be a 5-mask process, a 4-mask process, or any known process of forming a pixel array. In Figures 3, 3A and 3B, three numbers represent a five-mask process. In FIG. 3, the scan line 220, scan bonding pad 260 and floating gate 282a of the first switching element 280a are simultaneously formed on the substrate 210 using a 5-mask process (metal 1 mask). Next, a gate insulating layer 284 is formed as a whole on the substrate 210 to cover the scanning line 220, the scanning bonding pad 260, and the floating gate 282a. The semiconductor layer 286a is then formed on the floating gate 282a by applying a second masking process. The source and drain 288a are then formed by plating the metal layer in a third mask process (metal 2). A protective layer 300 is then formed entirely on the substrate 210 and a fourth mask process is used to define the first opening 300a and the second opening 300b. That is, a first opening 300a that exposes the source and drain 288a is formed on the protective layer 300 that covers the scan line 220, and a second opening 300b that exposes the scan bonding pad 260 covers the scan bonding pad 260. It is formed on the layer 300 and the gate insulating layer 284. The conductor layer 310 (such as ITO) is then formed using a fifth mask to cover the scan lines 220 and the scan bonding pads 260. Note that in FIGS. 3, 3A and 3B, the conductor layer 310 allows the source and drain 288a and the scanning bonding pad 260 to be electrically connected through the first opening 300a and the second opening 300b. I want to be.

That is, in FIG. 3, when a large amount of static charge is accumulated in one of the scanning bonding pads 260, the static charge can be transmitted from the scanning bonding pad 260 to the source and drain 288a of the first switching element 280a. .. Then, the charge coupling effect occurs between the source and drain 288a and the floating gate 282a, so that the first switching element 280a is switched on. Therefore, the electrostatic charge accumulated on the scanning bonding pad 260 can be transmitted to the adjacent scanning line 260 through the semiconductor layer 286a of the first switching element 280a. Therefore, the electrostatic charge is not accumulated on the scanning bonding pad 260, and it is possible to prevent the adjacent region of the scanning bonding pad 260 from being damaged.

Also note that the source and drain 288a of the first switching element 280a can be arranged asymmetrically or symmetrically. In FIG. 3, according to one embodiment of the present invention, the source and drain 288a of the first switching element 280a have the source and drain 288a charge-coupling effect between the source and drain 288a and the floating gate 282a in a limited space. Arranged asymmetrically, for example, to enhance and provide better electrostatic charge storage performance. Specifically, the source (or drain) length of the first switching element 280a is L1, the drain (source) length is L2, and L2 is longer than L1. The longer L2, the more space the drain with length L2 can store static charge so that the charge binding effect can easily occur between the drain 288a and the floating gate 282a. As a result, when the static charge is accumulated, the first switching element 280a is more easily switched on, and the static charge can be transmitted from the drain of length L2 to the source of length L1.

Also, when the two first switching elements 280a and 280a'are placed between two adjacent scanning bonding pads 260, the source and drain 288a placed on the floating gate 282a of the first switching element 280a' The first switching element 280a'is preferably arranged asymmetrically, especially when the length is contrary to the length of the case. That is, the first switching element 280a'in FIG. 3 has a source (or drain) of length L3, the first switching element has a drain (or source) of length L4, and L3 is more than L4. long. As a result, the electrostatic charge is transferred from the drain of length L3 to the source of length L4. In summary, when two first switching elements 280a and 280a'connected in parallel are placed between two adjacent scanning bonding pads, and the source and drain 288a are placed asymmetrically, the first switching When the elements (280a, 280a') are quickly switched on, static charge transmission takes place in both directions.

FIG. 4 is an enlarged top view of the scanning bonding pad arranged at position B shown in FIG. 4A is a cross-sectional view of the C-C'line of FIG. 4, and FIG. 4B is a cross-sectional view of the D-D'line of FIG.

In FIGS. 4 and 4A, according to one embodiment of the invention, each of the second switching elements 280b comprises a floating gate 282b, a gate insulating layer 284, a semiconductor layer 286b, and a source and drain 288b. The floating gate 282b is arranged on the substrate 210, and the gate insulating layer 284 covers the floating gate 282b. The semiconductor layer 286b is arranged in the gate insulating layer 284 on the floating gate 282b. The source and drain 288b are located on the semiconductor layer and are electrically connected to data bonding pads 270 arranged on both sides of the source and drain.

Similarly, a 5-mask process, a 4-mask process, or any known process for forming a pixel array can be employed to manufacture the device. 5 Take the mask process as an example. In FIGS. 4, 4A and 4B, the floating gate 282b of the second switching element 280b is formed on the substrate 210 using a 5-mask process (metal 1 mask). Next, a gate insulating layer 284 is entirely formed on the substrate 210 to cover the floating gate 282b. The semiconductor layer 286b is then formed on the floating gate 282b by applying a second masking process. The metal layer formed by the scan line 220, the data bonding pad 270, and the source and drain 288a is simultaneously formed by patterning the same metal layer with a third mask (metal 2). The protective layer 300 is then entirely formed on the substrate 210, and the protective layer 300 is patterned using a fourth mask to form a third opening 300c for exposing the data bonding pad 270. .. The conductor layer 310 (such as ITO) is then formed using a fifth mask to cover the data lines 230 and the data bonding pad 270. Note that in FIGS. 4, 4A and 4B, the source and drain 288b and the data bonding pad 270 are electrically connected to each other by being formed of the same metal layer.

That is, as shown in FIG. 4, when a large amount of static charge is accumulated in one of the data bonding pads 270, the static charge is transmitted from the data bonding pad 270 to the source and drain 288b of the second switching element 280b. Can be made to. Then, a charge-coupling effect occurs between the source and drain 288b and the floating gate 282b, so that the second switching element 280b is switched on. Therefore, the static charge accumulated on the data bonding pad 270 can be transmitted to the adjacent data line 230 through the semiconductor layer 286b of the second switching element 280b. Therefore, the static charge is not accumulated on the data bonding pad 270, and it is possible to prevent the periphery of the data bonding pad 270 from being damaged.

Similarly, the source and drain 288b of the second switching element 280b can be arranged asymmetrically or symmetrically. Since the purpose, method, and effect of this asymmetrical or symmetrical arrangement have been described above, description thereof will be omitted here. In summary, two second switching elements 280b are placed between two adjacent data bonding pads 270, source and drain 288b are asymmetrically placed, and the second switching element (280b') turns on quickly. When switched, the static charge can be transferred in both directions.

In short, the placement of the first and second switching elements is achieved using a 5-mask process so that no additional process is required. Also, when the first and second switching elements are placed between two adjacent scanning bonding pads and between two adjacent data bonding pads, respectively, static charges are generated between the first switching element and / or the second. By causing the charge-coupling effect of the switching element, the first switching element and / or the second switching element is switched on. Therefore, the damage caused by the static charge is reduced by reducing the possibility that the static charge is locally accumulated on the scanning bonding pad and the data bonding pad. Further, the LCD panel mounts the above-mentioned TFT array substrate to form an LCD panel having better antistatic protection performance.

FIG. 5 shows an LCD panel of a preferred embodiment of the present invention. The LCD panel 400 includes a color filter substrate 410, a TFT substrate 420, and a liquid crystal layer 430. The TFT substrate 420 may be, for example, the TFT substrate 200 shown in FIG. The liquid crystal layer 430 is arranged between the color filter substrate 410 and the TFT substrate 420.

A common electrode (not shown) and a color filter array (not shown) are arranged on the color filter substrate 410. An electric field is generated between the common electrode and the pixel electrode (not shown) of the TFT array substrate 420 so as to rotate the liquid crystal molecules arranged between the color filter substrate 410 and the TFT array substrate 420 to fluctuate the intensity of the incident light. Occurs. In addition, the color filter substrate 410 completely colors the LCD panel 400. Since the present invention employs the TFT array substrate 200 shown in FIG. 2, the LCD panel 400 of the present invention has better antistatic protection performance.

In summary, the TFT array substrate and LCD panel of the present invention have the following advantages. (1) When the first and second switching elements are placed between two adjacent scanning bonding pads and between two adjacent data bonding pads, respectively, the electrostatic charge is placed between the first switching element and / or the second. The first switching element and / or the second switching element is switched on by causing the charge-coupling effect of the switching element. Therefore, the damage caused by the static charge is reduced by reducing the possibility that the static charge is locally accumulated on the scanning bonding pad and the data bonding pad. (2) In the limited space, the sources and drains of the first and second switching elements are asymmetrically arranged, and when static charges are accumulated on the scanning bonding pad or data bonding pad, the first and second switching elements The switching element can be quickly switched on to transfer static charges to nearby scan lines or data lines. (3) The transfer of electrostatic charges can be carried out in both directions using two first switching elements connected in parallel or two second switching elements connected in parallel. (4) The first and second switching elements are formed using the conventional 5-mask process without any additional process. (5) The TFT array substrate having antistatic protection performance is mounted on the LCD panel so that the LCD panel operates better because the damage due to static charge is reduced.

It will be apparent to those skilled in the art that various improvements and modifications can be made to the structure of the invention without departing from the scope and spirit of the invention. In view of the above, the present invention includes improvements and modifications of the present invention as long as it belongs to the following claims and their equivalents.

The accompanying drawings are included for the purpose of deepening the understanding of the present invention and are incorporated in the present specification to form a part thereof. The drawings, along with the specification, show embodiments of the invention and are provided to illustrate the principles of the invention.

<figref num="1">The conventional TFT array board is shown.</figref><figref num="2">The TFT array substrate of one embodiment of the present invention is shown.</figref><figref num="3">It is an enlarged top view of the scanning bonding pad arranged at the position A shown in FIG.</figref><figref num="3A">It is sectional drawing of the AA'line of FIG.</figref><figref num="3B">It is sectional drawing of the B-B'line of FIG.</figref><figref num="4">It is an enlarged top view of the scanning bonding pad arranged at the position B shown in FIG.</figref><figref num="4A">It is sectional drawing of the C-C'line of FIG.</figref><figref num="4B">It is sectional drawing of the D-D'line of FIG.</figref><figref num="5">An LCD panel according to an embodiment of the present invention is shown.</figref>

Code description

100 TFT array board 110 board 112 display area 114 peripheral circuit area 120 scanning line 130 data line 140 pixel area 150 pixel unit 154 pixel electrode 160 scanning bonding pad 170 data bonding pad 192 inner antistatic protection ring 194 outer antistatic protection ring 200 TFT Array board 210 Board 212 Display area 214 Peripheral circuit area 220 Scan line 230 Data line 240 Pixel area 250 Pixel unit 254 Pixel electrode 260 Scan bonding pad 270 Data bonding pad 280a First switching element 280b Second switching element 282a Floating gate 282b Floating Gate 284 Gate Insulation Layer 286a Semiconductor Layer 286b Semiconductor Layer 288a Source and Drain 288b Source and Drain 292 Inner Antistatic Protective Ring 294 Outer Antistatic Protective Ring 300 Protective Layer 300a ~ 300c Opening 310 Conductor Layer 400 Panel 410 Color Filter Substrate 420 TFT array board 430 LCD layer