Method of patterning oxide semiconductor and method of manufacturing thin-film transistor

The present invention relates to a method for patterning a laminated thin film in which an InGaZnO4 thin film and a Sn-doped indium oxide (ITO) thin film are directly laminated, which can be used as an element constituting an electronic circuit, and a method for manufacturing a thin film transistor using the same.

Field-effect transistors are used as various switching elements such as unit electronic elements, high-frequency signal amplification elements, and liquid crystal drive elements of semiconductor memory integrated circuits, and thin-film transistors (hereinafter referred to as TFTs) are particularly well known. ..

Silicon or a silicon compound is widely used as the active layer of these TFTs. Silicon single crystals are used for high-frequency amplification elements and integrated circuit elements that require high-speed operation, and amorphous silicon is used for display elements that are sufficient for low-speed operation due to the demand for larger areas. ..

On the other hand, a flexible display requires a TFT using a flexible substrate. Since the substrate for producing such a TFT generally has a low heat resistant temperature, it is required to further reduce the process temperature for forming a thin film. CVD is widely used for producing the above-mentioned amorphous silicon thin film. Especially in plasma CVD, plasma decomposes silane, which is a raw material gas, so that a film can be formed at a lower temperature than thermal CVD. However, a reaction temperature of 200 to 300 ° C is required to form this plasma CVD thin film. Therefore, it has been difficult to form a thin film on a substrate having low heat resistance.

In recent years, an oxide semiconductor InGaZnO4 capable of forming a film at room temperature and having a field effect mobility equal to or higher than that of amorphous silicon has been proposed, and its potential as an active layer of a thin film transistor has been shown (see Non-Patent Document 1).

<nplcit num="1"><text>K.Nomura, H.Ohta, A.Takagi, T.Kamiyama, M.Hirano, H.Hosono: Nature 432 (2004) 488.</text></nplcit>

InGaZnO4 described in Non-Patent Document 1 is a material known as a transparent conductive film, but by controlling the oxygen partial pressure at the time of film formation, oxygen vacancies serving as a carrier source can be reduced and an off current can be obtained. Has succeeded in reducing. Moreover, since an amorphous state can be easily obtained, it is suitable for application to a flexible display. Further, since it is transparent, a transparent thin film transistor can be formed by using a transparent material for the gate insulating film, the gate electrode, and the source / drain electrode.

For the patterning of InGaZnO4, an etching method similar to that of the ITO film which is a transparent conductive film can be used. That is, it is soluble in general acids and insoluble in alkalis. Therefore, the etching technology cultivated in ITO can basically be applied to the patterning of InGaZnO4.

<p> However, in the case of a thin film transistor in which an InGaZnO4 thin film is used as an active layer and ITO is used as a source / drain electrode, a laminated structure is formed in which one portion is directly laminated on the other portion. When patterning both parts with different patterns, if one part is formed and then the other part is formed by etching in the same manner, the thin film part formed earlier is used to etch the later thin film part. Since it was etched by the etchant, it was not possible to obtain a laminated substrate having the desired pattern. Therefore, after forming one part, a lift-off process is used for patterning the other part, and a plurality of different processes are prepared and patterning is performed by the combination thereof, which is inefficient.</p><p> Further, the lift-off process, which is a forming means other than etching, has problems such as a long processing time for lift-off and the inability to cut fine patterns, which has been an obstacle in advancing microfabrication.</p><p> The present invention has been made in view of this problem. By patterning both the ITO thin film as the electrode layer and the InGaZnO4 thin film as the semiconductor active layer by etching, oxidation is performed without using a process unsuitable for mass production such as lift-off. The purpose is to manufacture a thin film semiconductor transistor.</p>

<p> In order to achieve the above problems, the first invention first describes a step of patterning an ITO thin film provided on a substrate by etching and patterning an InGaZnO4 thin film provided on the patterned ITO thin film by etching. This is an oxide semiconductor thin film pattern forming method, characterized in that the same type of etching solution or etching gas is used for the two types of thin films, and different concentrations of the etching solution or etching gas are used. As a result of examining the etching of the amorphous ITO thin film and the amorphous InGaZnO4 thin film, it was found that it is possible to etch the two separately by appropriately selecting the concentration of the etching solution. As a result, when the density is high, the influence of the error of the film thickness of the base becomes large on the error of the etching time. On the other hand, if the concentration is low, the etching time becomes long, and the throughput decreases. Therefore, when etching the ITO thin film, a high-concentration etching solution is used, and when etching InGaZnO4, the same type and low-concentration etching solution is used to pattern both of them by etching. It became possible. Here, assuming that the film thickness of InGaZnO4 is d, the film thickness of the ITO thin film is increased by 0.25 d from the minimum required amount, so that the patterned lamination is performed without falling below the minimum required amount of the ITO film thickness at the end of etching. A substrate can be obtained.</p><p> The second invention of the present invention is a step of patterning an ITO thin film provided on a base material by etching, and a step of patterning an InGaZnO4 thin film provided on the patterned ITO thin film by etching. Is an oxide semiconductor thin film pattern forming method, which comprises etching with different etching times using the same kind and the same concentration of etching solution or etching gas. Since an etching solution or an etching gas having the same etching concentration can be used, the etching solution or the etching gas can be easily managed.</p><p> The third invention of the present invention is the oxide semiconductor thin film pattern forming method according to claim 1 or 2, wherein the ITO film is crystalline. The etching rate of crystalline ITO is about 1 to 2 orders of magnitude slower than that of amorphous ITO. As a result, the selection ratio with InGaZnO4 is increased by 1 to 2 orders of magnitude, and the etching process window can be widened.</p><p> The fourth invention of the present invention is the pattern forming method according to any one of claims 1 to 3, wherein a wet etching method is used in the etching. By using wet etching, the expensive etching apparatus required for dry etching becomes unnecessary, and the manufacturing cost can be reduced.</p><p> A fifth aspect of the present invention is the pattern forming method according to claim 4, wherein an acid containing hydrochloric acid as a main component is used as the etching solution in the etching. The effect of the present invention is maximized when hydrochloric acid is used as the etching solution. In addition, hydrochloric acid is easily available and is easily neutralized with sodium hydroxide to form water and salt, so the environmental load is low.</p><p> The sixth invention of the present invention is a method for manufacturing a top-gate type thin film transistor using a non-single crystal InGaZnO4 thin film as an active layer and an ITO thin film as a source electrode and / and a drain electrode, wherein the source / drain is on a substrate. A step of forming an electrode layer, a step of patterning the source / drain electrode layer, a step of forming an active layer, a step of patterning the active layer, a step of forming a gate insulating film, and a step of forming a gate electrode layer. In a method for manufacturing a top-gate type thin film transistor including a step of forming and a step of patterning the gate electrode layer, the thin film transistor is characterized in that at least the active layer and the source / drain electrode layer are both patterned by etching. It is a manufacturing method. With such a configuration, a top-gate type transparent thin film transistor using a transparent oxide semiconductor can be formed without using a lift-off process.</p><p> The seventh invention of the present invention is a method for manufacturing a bottom gate type bottom contact thin film transistor using a non-single crystal InGaZnO4 thin film as an active layer and an ITO thin film as a source electrode and / and a drain electrode, wherein the gate is formed on a substrate. A step of forming an electrode layer, a step of patterning the gate electrode layer, a step of forming a gate insulating film, a step of forming a source / drain electrode layer, and a step of patterning the source / drain electrode layer. In a method for manufacturing a bottom gate type bottom contact thin film transistor including a step of forming an active layer and a step of patterning the active layer, at least the active layer and the source / drain electrode are both patterned by etching. This is a method for manufacturing a thin film transistor. With such a configuration, a bottom gate type bottom contact transparent thin film transistor using a transparent oxide semiconductor can be formed without using a lift-off step.</p>

<p> From the above configuration, the present invention has the following effects.</p><p> By patterning both the ITO thin film and the InGaZnO4 thin film directly laminated on the ITO thin film by etching, it becomes possible to manufacture a transparent oxide semiconductor thin film transistor without using a process unsuitable for mass production such as lift-off.</p>

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 and 2.

An example of the thin film transistor of the present invention is shown in FIG. Although the figure and this example describe a bottom gate type bottom contact thin film transistor, a top gate type may be used.

First, the substrate 1 is prepared (Fig. 2 (a)). As the material of the substrate 1, a lightweight and flexible plastic substrate is preferable. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE). , Polypropylene (PP), nylon, etc. can be used. However, it is advisable to perform surface treatment with UV, plasma, etc. in order to improve adhesion.

Next, the gate electrode 2 is formed on the substrate 1 (FIG. 2 (b)). The material of the gate electrode does not matter, but a material having high transmittance is desirable for producing a transparent thin film transistor. ITO is suitable from the viewpoint of transmittance and conductivity. This does not apply if transparency is not a concern. The manufacturing method does not matter. Further, since the gate electrode does not come into direct contact with the active layer, the patterning method does not matter. Examples include reactive mask deposition (including sputtering) of metals, alloys and transparent conductive films.

Next, the gate insulating film 3 is produced (Fig. 2 (c)). The material, manufacturing method, and patterning method of the gate insulating film 3 are not limited. For example, SiO2, SiN, SiON and the like can be used, but it is preferable to use a high dielectric constant (high-k) material such as HfO2, Y2O3 and Ta2O5.

Next, the source / drain electrode 4 is formed (Fig. 2 (d)). ITO is used as the material for the source and drain electrodes. When the film thickness of InGaZnO4 to be laminated later is d, the film thickness of ITO does not fall below the minimum required amount of ITO film thickness at the end of etching if the film thickness is increased by 0.25 d from the minimum required amount. The film formation method does not matter. It is desirable to use an acid resistant resist for patterning. Both dry and wet etching can be applied to the etching. The etching solution and etching gas are not limited, but wet etching using hydrochloric acid is desirable from the environmental point of view and in order to maximize the effect. If the ITO film is crystallized, etching will be facilitated by using a mixed solution of 6M hydrochloric acid heated to 50 ° C and 6M ferric chloride aqueous solution. If the ITO membrane is not crystallized, it is sufficient to treat it with only 1M hydrochloric acid at room temperature. After the etching is completed, the resist is peeled off.

Next, the active layer 5 is formed (Fig. 2 (e)). InGaZnO4 is used as the material. As a forming method, a sputtering method capable of forming a uniform film over a large area is preferable, and it can be easily formed by using an InGaZnO4 target. A film may be formed by a reactive sputtering method using an alloy target. Not limited to the sputtering method, other methods such as pulsed laser deposition (PLD) are also possible. It is desirable to use an acid resistant resist for patterning. Both dry and wet etching can be applied to the etching. The etching solution and etching gas are not limited, but wet etching using hydrochloric acid is desirable from the environmental point of view and in order to maximize the effect. At this time, if the concentration of hydrochloric acid is high, the time until the end of etching is shortened, and the error in the processing time has a non-negligible effect on the film thickness of the underlying ITO film. Therefore, in some cases, the ITO film is completely etched and disappears. Therefore, it is necessary to make the concentration sufficiently thin, preferably about 0.1 M with respect to the InGaZnO4 active layer having a film thickness of 50 nm. After the etching is completed, the resist is peeled off. The thin film transistor is completed as described above (Fig. 1).

Using PEN as the substrate 1 (see Fig. 2 (a)), an ITO layer was formed on the substrate 1 with a film thickness of 100 nm by the dc magnetron sputtering method, and then patterned to form the gate electrode 2 (Fig. 2 (Fig. 2). b) See). The patterning of the gate electrode 2 was formed by processing the ITO layer by wet etching using a general photolithography method. Next, a 300 nm SiO2 film was formed at a substrate temperature of 50 ° C. or less using plasma CVD to form a gate insulating film 3 (see FIG. 2 (c)). Next, an ITO layer was formed on the gate insulating film 3 with a film thickness of 100 nm by the dc magnetron sputtering method, and the resist was processed into the shape of an electrode by ordinary photolithography using a photoresist, and then 1M. The ITO thin film was etched with hydrochloric acid for 2 minutes to form the source / drain electrode 4, and the resist was peeled off (see FIG. 2 (d)). Finally, an InGaZnO4 thin film was formed to a thickness of 50 nm by the rf magnetron sputtering method using an InGaZnO4 target, and the resist was processed into a semiconductor pattern by ordinary photolithography using a photoresist, and 0.1 M hydrochloric acid was added. After etching the InGaZnO4 thin film for 3 minutes using the resist, the resist was peeled off to form a patterned active layer 4 (see FIG. 2 (e)). As described above, a bottom gate type bottom contact thin film transistor having a channel length of 50 μm and a channel width of 800 μm was completed (see Fig. 1).

<figref num="1">Explanatory drawing which shows the upper surface and side surface of the thin film transistor of this invention.</figref><figref num="2">The explanatory view which shows an example of the manufacturing process of the thin film transistor of this invention.</figref>

Code description

1 ... Substrate 2 ... Gate electrode 3 ... Gate insulating film 4 ... Source / drain electrode 5 ... Active layer