Image compression circuit, semiconductor integrated circuit and image compressing method

The present invention relates to an image compression circuit for compressing image data, a semiconductor integrated circuit, and an image compression method.

Currently, a still image compression standard called JPEG (Joint Photographic Expert Group) is used in various devices. This still image compression standard is defined in ISO / IEC 10918-1: 1994, ITU-TS T.81, JIS X 4301, etc.

As a conventional technique relating to JPEG, for example, the following Patent Document 1 is known.

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 6-289156 (Page 1, Fig. 1)</text></patcit>

In addition, Motion JPEG is used as a moving image compression technique. Although motion JPEG is not specified as a standard, it is generally regarded as a technique for composing moving image data by bundling a plurality of JPEG still image data.

FIG. 3 is a block diagram showing a conventional mobile phone device using motion JPEG. In FIG. 3, the mobile phone device 30 is roughly classified into a communication function unit 40 and an additional function unit 50. The communication function unit 40 has various known blocks for processing signals (including compressed moving images) transmitted and received by the antenna 41. Although the description of all the blocks of the communication function unit 40 will be omitted, the baseband LSI 42 is a processor that mainly processes voice and the like, and is always installed in the mobile phone device 30. The baseband LSI 42 is equipped with a baseband engine (BBE), an application processor, and the like. The additional function unit 50 has a host CPU (central processing unit) 51 connected to the baseband LSI 42 of the communication function unit 40. An LCD controller LSI 52 is connected to this host CPU 51. This LCD controller LSI 52 is connected to a liquid crystal display (LCD) 53 and a CCD camera 54, and compresses the still image data supplied from the CCD camera 54 into JPEG data or a moving image supplied from the CCD camera 54. It has a function to compress image data into motion JPEG data.

FIG. 4 is a diagram showing the internal configuration of the LCD controller LSI 52. As shown in FIG. 4, the LCD controller LSI 52 includes a resizing processing circuit 62, a shutter processing circuit 63, a JPEG encoding module 64, a frame memory 65, and a host interface 66. The JPEG encoding module 64 includes a JPEG encoding processing circuit 67 and a control circuit 68. The JPEG encoding processing circuit 67 includes a discrete cosine transform (DCT) processing unit 71, a quantization processing unit 72, and a Huffman coding processing unit 73. The control circuit 68 includes a register group 81 and a control processing unit 82.

The resizing processing circuit 62 is a circuit for performing resizing processing on the frame data supplied from the CCD camera 54. The shutter processing circuit 63 is a circuit for taking in the frame data output from the resizing processing circuit 62 according to the shutter control signal supplied from the control processing unit 82.

The discrete cosine transform processing unit 71 performs discrete cosine transform (DCT) processing on the frame data captured by the shutter processing circuit 63, and the quantization processing unit 72 performs discrete cosine transform by the discrete cosine transform processing unit 71. Quantize the data. The Huffman coding processing unit 73 performs Huffman coding processing on the data quantized by the quantization processing unit 72, and writes the obtained JPEG data to the frame memory 65. The frame memory 65 has a storage capacity capable of storing JPEG data for one frame, and can be read-accessed from the host CPU 51 via the host interface 66.

The register group 81 includes a plurality of registers for receiving instructions or data from the host CPU 51 or notifying the host CPU 51 of various statuses of the JPEG encoding module 64. The control processing unit 82 controls the shutter processing circuit 63 and the JPEG encoding processing circuit 67 according to the instructions or data written in the registers by the host CPU 51. Further, the control processing unit 82 performs JPEG encoding when the encoding of a predetermined amount of data (for example, half of one frame, which can be set by a register) is completed, when the encoding for one frame is completed, and when the encoding for one frame is completed. When various errors occur in the module 64, the data indicating the status of the JPEG-encoded module 64 is written to the status register in the register group 81, and the interrupt signal is output to the host CPU 51. When the host CPU 51 receives an interrupt signal, the host CPU 51 can identify the cause of the interrupt by referring to the status register.

FIG. 5 is a flowchart showing the processing of the host CPU 51 and the LCD controller LSI 52 during motion image (motion JPEG) compression. When performing video compression, the host CPU 51 first gives an initialization instruction to the control circuit 68 (step S31). Specifically, the host CPU 51 sets a bit (JPEG encoding processing circuit reset bit) in a predetermined register in the register group 81 for instructing the reset of the JPEG encoding processing circuit 67. Further, the host CPU 51 defines a quantization table for the quantization processing unit 72 to use for the quantization processing and a Huffman coding table for the Huffman coding processing unit 73 to use for the Huffman coding processing in the register group 81. Write to the register of. Further, the host CPU 51 writes the configuration data of the resizing circuit 62 to a predetermined register in the register group 81.

When the control processing unit 82 in the control circuit 68 receives the initialization instruction from the host CPU 51, the control processing unit 82 performs the initialization processing (step S41). Specifically, the control processing unit 82 resets the JPEG encoding processing circuit 67 when the JPEG encoding processing circuit reset bit is set by the host CPU 51. Further, when the quantization table and the Huffman coding table are written to a predetermined register in the register group 81 by the host CPU 51, the control processing unit 82 sends the quantization table to the quantization processing unit 72 and the Huffman coding table. Transfer to the Huffman coding processing unit 73. Further, the control processing unit 82 configures the resizing processing circuit 62 when the configuration data of the resizing processing circuit 62 is written to a predetermined register in the register group 81 by the host CPU 51.

Next, the host CPU 51 instructs the control circuit 68 to start encoding the frame data for one frame of the moving image (step S32). Specifically, the host CPU 51 clears the status register in the register group 81. Further, the host CPU 51 sets a bit (interrupt enable bit) in a predetermined register in the register group 81 for permitting the generation of an interrupt signal from the control circuit 68. Further, the host CPU 51 sets a bit in a predetermined register in the register group 81 for instructing the start of the JPEG encoding operation of the JPEG encoding processing circuit 67 (JPEG encoding operation start instruction bit). Further, the host CPU 51 sets a bit (shutter control bit) in a predetermined register in the register group 81 for instructing the shutter processing circuit 63 to capture frame data.

When the control processing unit 82 in the control circuit 68 receives the instruction to start encoding the frame data for one frame of the moving image from the host CPU 51, the control processing unit 82 performs the frame encoding control processing (step S42). Specifically, the control processing unit 82 causes the JPEG encoding processing circuit 67 to start the JPEG encoding operation. Further, the control processing unit 82 activates a shutter control signal for causing the shutter processing circuit 63 to capture the frame data. As a result, the shutter processing circuit 63 captures frame data for one frame supplied from the CCD camera 54. The frame data captured by the shutter processing circuit 63 is encoded by the JPEG encoding processing circuit 67. When the shutter control signal is activated and the shutter processing circuit 63 starts capturing frame data, a register (JPEG effective data size) that is a register in the register group 81 and represents the number of valid data in the frame memory 65. The value of the register) will be updated appropriately by the control processing unit 82, and the JPEG valid data size register will be read-accessible from the host CPU 51.

As described above, in the LCD controller LSI52, when the encoding of a predetermined amount of data is completed, the encoding for one frame is completed, various errors occur in the JPEG encoding module 64, etc. , The interrupt signal is sent to the host CPU 51. That is, even in the slowest case, the interrupt signal is transmitted to the host CPU 51 by the time the JPEG encoding of the frame data for one frame is completed. Further, even before the completion of JPEG encoding of the frame data for one frame, an interrupt signal is transmitted to the host CPU 51 when the encoding of a predetermined amount of data is completed or when some error occurs. If the register is set so that an interrupt is generated when the encoding of a predetermined amount of data is completed, multiple interrupts are generated by the time the JPEG encoding of the frame data for one frame is completed, and the host CPU51 Will execute interrupt processing multiple times. Also, when the JPEG encoding of the frame data for one frame is completed, the JPEG data that has been encoded in the register (encoding size result register) that represents the size of the JPEG data for one frame, which is one of the registers in the register group 81. The size of is written by the control processing unit 82, and the encoding size result register becomes read-accessible from the host CPU 51.

When the host CPU 51 receives an interrupt signal from the control processing unit 82, the host CPU 51 performs interrupt processing (step S33). Specifically, the host CPU 51 clears the interrupt enable bit and sets the JPEG encoding processing circuit reset bit. When the JPEG encoding processing circuit reset bit is set, the JPEG valid data size register cannot be read-accessed from the host CPU 51. Next, the host CPU 51 refers to the status register and identifies the cause of the interrupt. Then, when the cause of the interrupt is an error, the host CPU 51 performs predetermined error processing, and the cause of the interrupt is the end of encoding of a predetermined amount of data or the completion of encoding of one frame of data. In this case, data is read from the frame memory 65.

The JPEG encoding of the frame data for one frame is completed by the above-mentioned frame encoding start instruction (step S32), frame encoding control processing (step S42), and interrupt processing (step S33), but the frame data of the next frame In order to perform JPEG encoding, the host CPU 51 issues a frame encoding start instruction again (step S34). The processing content of this step S34 is the same as the processing content of step S32. When the control circuit 68 receives the frame encoding start instruction from the host CPU 51, the control circuit 68 performs the frame encoding control process (step S43). The processing content of this step S43 is the same as the processing content of step S42.

In this way, the host CPU 51 repeats the frame encoding start instruction and the interrupt processing, so that the control circuit 68 can repeat the frame encoding control processing. As a result, JPEG encoding processing of a plurality of frame data, that is, motion JPEG encoding processing is realized.

In such a conventional LCD controller LSI 52, the host CPU 51 needs to give a frame encoding start instruction at the start of encoding of each frame. Therefore, there is a problem that the load on the host CPU 51 becomes heavy. Further, when the JPEG encoding of the frame data for at least one frame is completed, the interrupt signal is transmitted to the host CPU 51, so that there is a problem that the load on the host CPU 51 becomes heavy. Further, since the host CPU 51 must manage the size of the encoded data and the effective data size read from the frame memory 65, there is a problem that the load on the host CPU 51 becomes heavy.

<p> Therefore, in view of the above points, the first object of the present invention is to provide an image compression circuit capable of reducing the load on the host CPU. A second object of the present invention is to provide a semiconductor integrated circuit including such an image compression circuit. Furthermore, a third object of the present invention is to provide such an image compression method.</p>

<p> In order to solve the above problems, the image compression circuit according to the present invention is an image compression circuit for compressing moving image data supplied from the first external circuit and outputting it to the second external circuit. A shutter circuit for capturing moving image data supplied from the first external circuit, an interface circuit for transmitting and receiving signals or data between the second external circuit, and a second via the interface circuit. A buffer memory connected to the external circuit of 2, an image compression processing circuit for performing image compression processing on the moving image data taken in by the shutter circuit and writing it to the buffer memory, and a second external circuit via an interface circuit. The shutter circuit is controlled so as to capture the moving image data supplied from the first external circuit when it is instructed to start the compression of the moving image data from the second external circuit. At the same time, it is provided with a control circuit for controlling the image compression processing circuit so as to perform image compression processing on the moving image data captured by the shutter circuit.</p><p> In this image compression circuit, the control circuit controls the shutter circuit so as to sequentially capture a plurality of frame data constituting the moving image data supplied from the first external circuit, and a plurality of frame data sequentially captured by the shutter circuit. The image compression processing circuit may be controlled so that the image compression processing is sequentially performed on the frame data.</p><p> The control circuit may also include at least one register for receiving instructions or data from the second external circuit.</p><p> Further, the control circuit may supply an interrupt signal to the second external circuit for notifying that a predetermined error has occurred or that a predetermined amount of data has been accumulated in the buffer memory.</p><p> Further, the buffer memory may have a storage capacity of one or more frame data compressed by the image compression processing circuit.</p><p> Further, the control circuit may manage the size of the compressed data and the effective data size stored in the buffer memory.</p><p> Further, the moving image data output to the second external circuit may be motion JPEG data.</p><p> Further, the semiconductor integrated circuit according to the present invention includes an image compression circuit according to the present invention.</p><p> Further, the image compression method according to the present invention is for transmitting and receiving signals or data between a shutter circuit for capturing moving image data supplied from a first external circuit and a second external circuit. Interface circuit, buffer memory connected to the second external circuit via the interface circuit, and image compression processing circuit for performing image compression processing on the moving image data taken in by the shutter circuit and writing it to the buffer memory. A method for performing image compression in an image compression circuit including a control circuit for controlling a shutter circuit and an image compression processing circuit, which is connected to a second external circuit via an interface circuit. When an instruction to start compression of image data is received from the second external circuit, the shutter circuit is controlled so as to capture the moving image data supplied from the first external circuit, and the shutter circuit controls the shutter circuit. The image compression processing circuit is controlled so as to perform image compression processing on the captured moving image data.</p>

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings. The same components are designated by the same reference numerals, and the description thereof will be omitted. FIG. 1 is a diagram showing an outline of an LCD controller LSI as an embodiment of the present invention. In this embodiment, the present invention is applied to an LCD controller LSI. This LCD controller LSI can be used in various devices, but here, a case where it is used as a substitute for the conventional LCD controller LSI 52 in the mobile phone device 30 (see FIG. 3) described above will be described.

As shown in FIG. 1, the LCD controller LSI 1 includes a resizing processing circuit 2, a shutter processing circuit 3, a JPEG encoding module 4, a FIFO buffer 5, and a host interface 6. The JPEG encoding module 4 includes a JPEG encoding processing circuit 7 and a control circuit 8. The JPEG encoding processing circuit 7 includes a discrete cosine transform (DCT) processing unit 11, a quantization processing unit 12, and a Huffman coding processing unit 13. The control circuit 8 includes a register group 21 and a control processing unit 22.

The resizing processing circuit 2 is a circuit for performing resizing processing on the frame data supplied from the CCD camera 54. The shutter processing circuit 3 is a circuit for taking in the frame data output from the resizing processing circuit 2 according to the shutter control signal supplied from the control processing unit 22.

The discrete cosine transform processing unit 11 performs discrete cosine transform (DCT) processing on the frame data captured by the shutter processing circuit 3, and the quantization processing unit 12 performs discrete cosine transform by the discrete cosine transform processing unit 11. Quantize the data. The Huffman coding processing unit 13 performs Huffman coding processing on the data quantized by the quantization processing unit 12, and writes the obtained JPEG data to the FIFO buffer memory 5. The FIFO buffer 5 has a storage capacity capable of storing one frame or more (for example, two frames or more) of JPEG data, and is read-accessible from the host CPU 51 via the host interface 6.

The register group 21 includes a plurality of registers for receiving instructions or data from the host CPU 51 or notifying the host CPU 51 of various statuses of the JPEG encoding module 4.

The control processing unit 22 controls the shutter processing circuit 3 and the JPEG encoding processing circuit 7 according to the instruction or data written in the register by the host CPU 51. Further, when the control processing unit 22 finishes encoding a predetermined amount of data (for example, half of one frame and can be set by a register), when various errors occur in the JPEG encoding module 4. Etc., the data indicating the status of the JPEG encoding module 4 is written to the status register in the register group 21, and the interrupt signal is output to the host CPU 51. When the host CPU 51 receives an interrupt signal, the host CPU 51 can identify the cause of the interrupt by referring to the status register.

Next, the operation of the LCD controller LSI1 will be described. FIG. 2 is a flowchart showing the processing of the host CPU 51 and the LCD controller LSI 1 during motion image (motion JPEG) compression. It is assumed that a predetermined register in the register group 21 has a bit (motion JPEG enable bit) for receiving an instruction from the host CPU 51 whether to encode a still image or a moving image, and LCD. The controller LSI1 may encode the moving image when the motion JPEG bit is set by the host CPU 51, and encode the still image when the motion JPEG bit is not set.

When performing video compression, the host CPU 51 first gives an initialization instruction to the control circuit 8 (step S11). Specifically, the host CPU 51 sets a bit (JPEG encoding processing circuit reset bit) in a predetermined register in the register group 21 for instructing the reset of the JPEG encoding processing circuit 7. Further, the host CPU 51 defines a quantization table for the quantization processing unit 12 to use for the quantization processing and a Huffman coding table for the Huffman coding processing unit 13 to use for the Huffman coding processing in the register group 21. Write to the register of. Further, the host CPU 51 writes the configuration data of the resizing processing circuit 2 to a predetermined register in the register group 21.

When the control processing unit 22 in the control circuit 8 receives the initialization instruction from the host CPU 51, the control processing unit 22 performs the initialization processing (step S21). Specifically, the control processing unit 22 resets the JPEG encoding processing circuit 7 when the JPEG encoding processing circuit reset bit is set by the host CPU 51. Further, when the quantization table and the Huffman coding table are written to a predetermined register in the register group 21 by the host CPU 51, the control processing unit 22 sends the quantization table to the quantization processing unit 12 and the Huffman coding table. Transfer to the Huffman coding processing unit 13. Further, the control processing unit 22 configures the resizing processing circuit 2 when the configuration data of the resizing processing circuit 2 is written to a predetermined register in the register group 21 by the host CPU 51.

Next, the host CPU 51 instructs the control circuit 8 to start encoding the moving image (step S12). Specifically, the host CPU 51 clears the status register in the register group 21. Further, the host CPU 51 sets a bit (interrupt enable bit) in a predetermined register in the register group 21 for permitting the generation of an interrupt signal from the control circuit 8. Further, the host CPU 51 sets a bit in a predetermined register in the register group 21 for instructing the start of the JPEG encoding operation of the JPEG encoding processing circuit 7 (JPEG encoding operation start instruction bit).

When the control processing unit 22 in the control circuit 8 receives the instruction to start encoding the moving image from the host CPU 51, the control processing unit 22 performs the encoding control processing (step S22). Specifically, the control processing unit 22 causes the JPEG encoding processing circuit 7 to start the JPEG encoding operation. Further, the control processing unit 2 activates a shutter control signal for causing the shutter processing circuit 3 to capture the frame data. As a result, the shutter processing circuit 3 captures the frame data supplied from the CCD camera 54. The frame data captured by the shutter processing circuit 3 is encoded into JPEG data by the JPEG encoding processing circuit 7. When the shutter control signal is activated and the shutter processing circuit 3 starts capturing frame data, it is a register in the register group 21 and is a register for expressing the number of valid data in the FIFO buffer 5 (JPEG effective data size). The value of the register) will be updated appropriately by the control processing unit 22, and the JPEG valid data size register will be read-accessible from the host CPU 51. When the JPEG encoding of the frame data for one frame is completed, the encoding is completed in the register (encoding size result register) that is the register in the register group 81 and represents the size of the JPEG data for one frame, and the FIFO buffer 5 is filled. The size of the stored JPEG data is written by the control processing unit 22, and the encode size result register is read-accessible from the host CPU 51. Further, the control processing unit 22 manages the size of the encoded data and the effective data size stored in the FIFO buffer 5.

In step S22, the control processing unit 22 activates the shutter control signal and inputs the frame data to the shutter processing circuit 3 without receiving an instruction from the host CPU 51 every time the encoding for one frame is completed. In addition to sequentially performing, the JPEG encoding processing circuit 7 sequentially encodes the frame data sequentially captured by the shutter processing circuit 3.

As described above, in the LCD controller LSI1, an interrupt signal is transmitted to the host CPU 51 when the encoding of a predetermined amount of data is completed, when various errors occur in the JPEG encoding module 4, and the like. When the host CPU 51 receives an interrupt signal from the control processing unit 22, it performs interrupt processing (step S13). Specifically, the host CPU 51 clears the interrupt enable bit. Next, the host CPU 51 refers to the status register and identifies the cause of the interrupt. Then, the host CPU 51 performs predetermined error processing when the cause of the interrupt is an error, and when the cause of the interrupt is the end of encoding of a predetermined amount of data, the data from the FIFO buffer 5 is processed. Read out. After that, the host CPU 51 sets the interrupt enable bit.

When the register group 21 has a register (encode size limit register) for receiving an instruction of the maximum size that can be encoded from the host CPU 51, and the encoded data size reaches the value in the encode size limit register. In addition, an interrupt signal may be generated.

In this way, according to the LCD controller LSI1, when the host CPU 51 gives an encoding start instruction (see step S12 in FIG. 2), the control processing unit 22 performs the moving image encoding control processing (encoding processing of a plurality of frames). Do this (see step S22 in Figure 2). Therefore, unlike the conventional LCD controller LSI52, the host CPU 51 does not need to give a frame encoding start instruction at the start of encoding each frame. Therefore, the load on the host CPU 51 can be reduced. In particular, since the control processing unit 22 activates the shutter control signal without receiving an instruction from the host CPU 51, the load of shutter control of the host CPU 51 can be reduced.

Further, in the conventional LCD controller LSI 52, the host CPU 51 performs interrupt processing (step S34 in FIG. 5) and sends the following instruction to the LCD controller LSI 52 every time the encoding for at least one frame is completed (FIG. 5). (See step S34 in step S34). On the other hand, in the LCD controller LSI1, since the control processing unit 22 encodes a plurality of frames without receiving an instruction from the host CPU 51, the storage capacity of the FIFO buffer 5 should be larger than one frame. For example, the number of interrupt signal generations can be reduced, and the number of interrupt processes (see steps S13 and S14 in FIG. 2) can be reduced. As a result, the load of interrupt processing of the host CPU 51 can be reduced.

Moreover, since the control processing unit 22 manages the size of the encoded data and the effective data size stored in the FIFO buffer 5, the host CPU 51 does not need to manage these, and the load on the host CPU 51 is reduced. can do.

Also, here, the LCD controller LSI1 encodes to motion JPEG data, but motion JPEG2000 (specified in ISO / IEC 15444-3: 2002, JIS X 4350-3: 2003, etc.) and other videos. The image data may be encoded.

The present invention can be used in image compression circuits. This image compression circuit can be used in an LCD controller or the like, and can be further incorporated in a mobile phone device or the like.

<figref num="1">The block diagram which shows the LCD controller LSI as one Embodiment of this invention.</figref><figref num="2">The flowchart which shows the operation of the LCD controller LSI1 of FIG.</figref><figref num="3">The block diagram which shows the structure of the mobile phone device.</figref><figref num="4">The block diagram which shows the structure of the LCD controller LSI 52 of FIG.</figref><figref num="5">The flowchart which shows the operation of the LCD controller LSI 52 of FIG.</figref>

Code description

1, 52 LCD controller LSI, 2, 62 Resize processing circuit, 3, 63 Shutter processing circuit, 4 JPEG encoding module, 5 FIFO buffer, 6 host interface, 7 JPEG encoding processing circuit, 8 control circuit, 11 Discrete cosine transform processing unit , 12 Quantization processing unit, 13 Huffman coding processing unit, 21 Register group, 22 Control processing unit, 30 Mobile phone device, 40 Communication function unit, 41 Antenna, 42 Baseband LSI, 50 Additional function unit, 51 Host CPU, 53 LCD, 54 CCD camera