Liquid crystal device and electronic equipment

The present invention relates to a liquid crystal device and an electronic device, and particularly to a liquid crystal device using an active matrix substrate.

In recent years, liquid crystal devices using active matrix circuits using active elements such as TFTs have rapidly become widespread, especially for notebook PCs and monitors.

In a liquid crystal apparatus using a normal nematic phase liquid crystal material, the display state of each pixel is controlled by a potential difference between a pixel electrode switched by an active element and a common electrode called a common electrode. When the potential difference between the pixel electrode and the common electrode is large, that is, when displaying black in normal white mode and when displaying white in normal black mode, the maximum potential difference between the common electrode and pixel electrode depends on the liquid crystal material used, liquid crystal mode, liquid crystal gap, etc. Although it is different, it is usually about 3V to 5V. In the liquid crystal device, in order to ensure the reliability of the liquid crystal element, AC drive that reverses the polarity of the voltage applied to the liquid crystal in a certain period of time is required, and when the potential of the common electrode is fixed, the potential signal written to the pixel electrode, that is, the active matrix The potential amplitude of the video signal input to the data line of the circuit is 6V to 10V.

However, when writing the video signal input to the data line with an external data driver IC, it is not an ordinary CMOS process to output a potential amplitude of 5V or more, and it is not an expensive IC manufactured by a high withstand voltage process. However, the cost will increase and the power consumption will be disadvantageous. In order to solve this problem, for example, Patent Document 1 proposes a driving method in which the common electrode is inverted for each polarity, and the input signal amplitude of the data line is halved by using the common inversion drive.

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 62-49399</text></patcit>

<p> However, in Patent Document 1, when the common inversion drive is performed, the capacity of the common electrode increases as the panel becomes larger and has higher definition, and the relaxation time at the time of inversion and the instantaneous maximum current increase.</p><p> The present invention has been made in view of such circumstances, and an object of the present invention is to provide a liquid crystal device and an electronic device having a small panel peripheral dimension and a low current consumption.</p>

<p> In order to solve the above problems, the liquid crystal apparatus of the present invention corresponds to a plurality of scanning lines, a plurality of data lines arranged intersecting the plurality of scanning lines, and the intersection of the data lines and the scanning lines. A plurality of pixel switching elements arranged in a row, a plurality of pixel electrodes arranged corresponding to the plurality of pixel switching elements, a common electrode facing the pixel electrode to form a capacitance, and the common electrode. A common power supply circuit that is connected and outputs a rectangular wave signal that inverts between a relatively high potential and a relatively low potential for a certain period of time, and a common power supply circuit that is constant in the plurality of scanning lines at the common inversion timing in which the output is inverted. It is a liquid crystal device including a first reference potential power supply circuit that outputs a first reference potential which is a potential, and the first reference potential power supply circuit is connected to the common power supply circuit with low impedance. Therefore, it is a gist that the impedance RA from the common power supply circuit to the common electrode and the impedance RB from the first reference potential power supply circuit to the scanning line are substantially equal.</p><p> According to this configuration, the relaxation time at the time of common potential reversal can be suppressed, and the period from the common potential reversal timing to the writing of the selective potential on the scanning line and the scanning line selection period can be secured. This enables common reversal drive even for panels for which common reversal drive was difficult, and can be manufactured with a high yield. Then, while using an inexpensive low-voltage IC as the external drive IC, it is possible to realize a liquid crystal device that does not reduce the yield, is cheaper, and consumes less current.</p><p> Further, in the liquid crystal apparatus of the present invention, the wiring width of the first wiring that electrically connects the first reference potential power supply circuit and the plurality of scanning lines is such that the common power supply circuit and the common electrode are electrically connected. Approximately equal to the wiring width of the second wiring to be connected.</p><p> According to this configuration, the relaxation time at the time of common potential reversal can be optimized by defining the widths of the first and second wirings.</p><p> Further, in the liquid crystal apparatus of the present invention, among the wiring widths for wiring each signal source and power supply to the drive circuit for driving the liquid crystal apparatus, the wiring width of the first wiring and the wiring width of the second wiring are , Larger than the wiring width of other wiring.</p><p> According to this configuration, by reducing the wiring resistance values of the other wirings, it is possible to optimize the relaxation time at the time of common potential reversal with the wiring resistance values of the first and second wirings.</p><p> Further, in the liquid crystal apparatus of the present invention, the plurality of scanning lines, the plurality of data lines, the plurality of pixel electrodes, the plurality of pixel switching elements, and a plurality of mounting terminals are formed on the same substrate. The first reference potential power supply circuit is connected to the first mounting terminal which is a part of the plurality of mounting terminals, and the common power supply circuit is a part of the plurality of mounting terminals. It is connected to a second mounting terminal, and the first mounting terminal and the second mounting terminal are substantially equal in the number of constituent terminals or the terminal area.</p><p> According to this configuration, by defining the terminal areas of the first mounting terminal and the second mounting terminal, the relaxation time at the time of common inversion is optimized while optimizing the panel outer shape, so that the display area is large and the panel. It is possible to manufacture a liquid crystal device having a small peripheral dimension and a low current consumption. In addition, the cost can be reduced by using an IC with a low withstand voltage.</p><p> Further, in the liquid crystal apparatus of the present invention, in the plurality of mounting terminals, the first mounting terminal and the second mounting terminal have a larger number of terminals or a larger terminal area than other signal and power supply mounting terminals. large.</p><p> According to this configuration, by reducing the resistance values of the other mounting terminals, the relaxation time at the time of common potential reversal can be optimized by the resistance values of the first and second mounting terminals.</p><p> Further, in the liquid crystal apparatus of the present invention, the common power supply circuit includes the plurality of data lines of the second reference potential power supply circuit that outputs a second reference potential which is a constant potential at the common inversion timing at which the output is inverted. It is connected to the low impedance.</p><p> According to this configuration, since the precharge operation is performed before and after the common inversion, the writing time can be reduced, a larger display area can be realized, and the power consumption can be reduced.</p><p> Further, in the liquid crystal apparatus of the present invention, the wiring width of the first wiring that electrically connects the first reference potential power supply circuit and the plurality of scanning lines, the second reference potential power supply circuit, and the plurality of The sum of the wiring width of the third wiring that electrically connects the data lines is approximately equal to the wiring width of the second wiring that electrically connects the common power supply circuit and the common electrode.</p><p> According to this configuration, by considering the wiring width of the third wiring that electrically connects the data lines, it is possible to optimize the relaxation time at the time of common potential reversal even in the liquid crystal device having the precharge function. it can.</p><p> Further, in the liquid crystal apparatus of the present invention, among the wiring widths for wiring each signal source and power supply to the drive circuit, the wiring widths of the first wiring, the second wiring, and the third wiring are other. Larger than wiring.</p><p> According to this configuration, by reducing the wiring resistance values of the other wirings, it is possible to optimize the relaxation time at the time of common potential reversal with the wiring resistance values of the first, second, and third wirings.</p><p> Further, in the liquid crystal apparatus of the present invention, the first reference potential power supply circuit is connected to the first mounting terminal which is a part of the plurality of mounting terminals, and the common power supply circuit is the plurality of mountings. The second reference potential power supply circuit is connected to a second mounting terminal that is a part of the terminals, and the second reference potential power supply circuit is connected to a third mounting terminal that is a part of the plurality of mounting terminals. The sum of the number of terminals or the sum of the terminal areas of the mounting terminal 1 and the third mounting terminal is approximately equal to the number of terminals or the terminal area of the second mounting terminal.</p><p> According to this configuration, by considering the terminal area of the third mounting terminal that electrically connects the data lines, the relaxation time at the time of common potential reversal can be optimized even in the liquid crystal device having the precharge function. Can be done.</p><p> Further, in the liquid crystal apparatus of the present invention, in the plurality of mounting terminals, the first mounting terminal, the second mounting terminal, and the third mounting terminal are terminals as compared with mounting terminals for other signals and power supplies. Large number or large terminal area.</p><p> According to this configuration, by reducing the resistance value of the other mounting terminals, the relaxation time at the time of common inversion is optimized while optimizing the panel outer shape even when the precharge operation is performed before and after the common inversion, so that the display area is displayed. It is possible to manufacture a liquid crystal device having a large size, a small panel peripheral dimension, and a low current consumption.</p><p> Further, the liquid crystal device of the present invention includes a plurality of scanning lines, a plurality of data lines arranged intersecting the plurality of scanning lines, and a plurality of data lines arranged corresponding to the intersection of the data lines and the scanning lines. A pixel switching element, a plurality of pixel electrodes arranged corresponding to the plurality of pixel switching elements, a common electrode that forms a capacitance facing the pixel electrode, and a common electrode connected to the common electrode for a certain period of time. A common power supply circuit that outputs a rectangular wave signal whose output potential is inverted between a relatively high potential and a relatively low potential, a first reference potential power supply circuit that supplies a non-selective potential to the scanning line, and the common power supply. A common potential wiring that electrically connects a common potential terminal to which a rectangular wave signal is supplied from a circuit and the common electrode, a power supply terminal to which a non-selective potential is supplied from the first reference potential power supply circuit, and the scanning line. It is a gist that the power supply wiring for electrically connecting the scanning line drive circuit for driving the power supply is provided, and the impedance of the common potential wiring and the impedance of the power supply wiring are substantially equal to each other.</p><p> According to this configuration, the relaxation time at the time of common potential reversal can be suppressed, and the period from the common potential reversal timing to the writing of the selective potential on the scanning line and the scanning line selection period can be secured. This enables common reversal drive even for panels for which common reversal drive was difficult, and can be manufactured with a high yield. Then, while using an inexpensive low-voltage IC as the external drive IC, it is possible to realize a liquid crystal device that does not reduce the yield, is cheaper, and consumes less current.</p><p> Further, the electronic device of the present invention includes the above-mentioned liquid crystal device of the present invention.</p><p> According to this configuration, since an inexpensive driver with low withstand voltage can be used as an external IC, the cost is low, and since flicker is difficult to see, a liquid crystal device capable of high image quality and low power consumption can be used as a display. It is possible to use electronic devices that are inexpensive, have high image quality, and have a long battery life. Specific examples of electronic devices include monitors, TVs, laptop computers, PDAs, digital cameras, video cameras, mobile phones, mobile photo viewers, portable video players, portable DVD players, and portable audio players.</p>

Hereinafter, embodiments of the liquid crystal apparatus according to the present invention will be described with reference to the drawings. (First Embodiment)

&lt;Structure of Liquid Crystal Device&gt; FIG. 1 is a perspective view showing a configuration of a liquid crystal device according to the first embodiment of the present invention. FIG. 1 is a perspective view (partial cross-sectional view) of the liquid crystal device 10 having a diagonal 4-inch transmissive VGA resolution. In the liquid crystal device 10, the nematic phase liquid crystal material 22 is sandwiched between the active matrix substrate 11 and the opposing substrate 12, and both substrates 11 and 12 are bonded together with the sealing material 23 to enclose the liquid crystal material 22. An alignment film (not shown) coated with an alignment material such as polyimide and subjected to rubbing treatment is formed on the pixel electrodes of the active matrix substrate 11. Further, on the counter substrate 12, although not shown, a color filter corresponding to a pixel and a counter electrode 30 made of an ITO film to which a common potential is supplied are formed, and an orientation material made of polyimide or the like is formed on a surface in contact with the liquid crystal material 22. Is applied, and the active matrix substrate 11 is rubbed in a direction orthogonal to the direction of the rubbing treatment of the alignment film. Further, although not shown, the counter electrode 30 is electrically connected to the vertical conductive portion 56 on the active matrix substrate 11 by a conductive material or the like.

Further, an upper polarizing plate 24 is arranged on the outside of the facing substrate 12, and a lower polarizing plate 25 is arranged on the outside of the active matrix substrate 11, so that the polarization directions are orthogonal to each other (cross-nicol shape). Further, a backlight unit 26 forming a surface light source is arranged under the lower polarizing plate 25. The backlight unit 26 may be a cold cathode tube or LED to which a light guide plate or a scattering plate is attached, or a unit that emits light entirely by an EL element. The backlight unit 26 is connected to the electronic device main body through the connector 26a to supply power and control signals. Although not shown, if necessary, the periphery may be covered with an outer shell, or a protective glass or acrylic plate may be attached above the upper polarizing plate 24, and optics may be used to improve the viewing angle. A compensation film may be attached.

Further, the active matrix substrate 11 is provided with an overhanging portion 27 overhanging from the facing substrate 12, and the overhanging portion 27 is provided with a plurality of signal input terminals 53 (not shown). An FPC (flexible substrate) 28 and an external drive IC 29 are mounted on the overhanging portion 27 and are electrically connected to a plurality of signal input terminals 53. In FIG. 1, the external drive IC 29 is composed of two ICs, but may be one or three or more. The FPC (Flexible Circuit Board) is connected to an electronic device and supplies a reference potential, a control signal, and video data.

&lt;Structure of Active Matrix Board&gt; Next, the configuration of the active matrix board 11 will be described with reference to FIG. FIG. 2 is a diagram showing the active matrix substrate 11. On the active matrix substrate 11, m (m is a natural number, m = 480 in this embodiment) scanning lines 31 and n (n is a natural number, n = 1920 in this embodiment) data lines 32 are connected to each other. It is formed so as to intersect with each other, and m capacitance lines 33 are alternately arranged so as to be parallel to the scanning line 31 and paired with the scanning line 31.

Further, the scanning line 31 is connected to the scanning line driving circuit 41, the power supply terminal 51 is connected to the scanning line driving circuit 41 via the power supply wiring 52, and the plurality of signal input terminals 53 also have the plurality of signal wirings 57. Connected via. The DC power supply potential VBB (= -4V) that holds the scanning line from the power supply terminal 51 (non-selected state) and the various signals required from the signal input terminal 53 and the signal for giving the power supply potential are scanned respectively. It is supplied to the line drive circuit 41. A data line drive circuit 42 is connected to the data line 32. A plurality of signal input terminals 53 are connected to the data line drive circuit 42 via the signal wiring 57, and various necessary signals and signals for giving a power supply potential are supplied.

The capacitance lines 33 are short-circuited to each other, connected to the common potential input terminal 54 via the common potential wiring 55, and a common potential signal (VCOM = -4.5V to -0.5V inverted signal) is supplied. Further, at the four corners of the active matrix substrate 11, upper and lower conductive portions 56 that conduct with the opposite electrodes of the opposite substrate are arranged, and are similarly connected to the common potential input terminal 54 via the common potential wiring 55.

&lt;Structure of Pixel Circuit&gt; Next, the configuration of the pixel circuit will be described with reference to FIG. FIG. 3 is an enlarged view of the intersection of the scanning line 31 and the data line 32 shown by the dotted line A in FIG. A pixel switching element 34 made of an N-channel field effect polysilicon thin film transistor is formed corresponding to each intersection of the scanning line 31 and the data line 32, and its gate electrode is on the scanning line 31 and the source electrode is on the data line 32. , The drain electrode is connected to the pixel electrode 35. The pixel electrode 35 forms a liquid crystal capacity 36 with the counter electrode 30 (common electrode) of the facing substrate 12 with the liquid crystal material 22 sandwiched between them, and in parallel with the liquid crystal capacity 36, the pixel electrode 35 on the pixel potential side and the capacitance line 33 Form an auxiliary capacity Cs.

&lt;Structure of Scanning Line Drive Circuit&gt; Next, the configuration of the scanning line driving circuit will be described with reference to FIGS. 4 and 5. FIG. 4 is a circuit block diagram of the scanning line drive circuit 41, and FIG. 5 is a detailed circuit configuration diagram of each of the constituent circuits.

The scanning line drive circuit 41 includes a clock control circuit (CCC) 72, a clock generation circuit (CGC) 73, a latch circuit (LAT) 74, and a bidirectional transfer circuit (DIR) 75. , NAND circuit 76, level shifter circuit (L / S) 81, and output circuit 82. Although not shown here, the clock control circuit 72, the clock generation circuit 73, the latch circuit 74, the bidirectional transfer circuit 75, and the NAND circuit 76 have a power supply potential VD (= 5V) and a power supply potential VS ( = 0V) is assumed to be supplied from the external drive IC 29 via the signal input terminal 53 and the signal wiring 57. Further, the level shifter circuit 81 is similarly supplied with the power supply potential VS (= 0V), the power supply potential VHH (= 9V), and the power supply potential VBB (= -4V), and the output circuit 82 is supplied with the power supply potential VHH (= 9V) and the power supply. It is assumed that the potential VBB (= -4V) is supplied in the same manner.

As shown in FIGS. 4 and 5 (A), the clock control circuit 72 inputs the clock signal VCLK from the signal input terminal 53 to the IN terminal via the clock signal line 77, and inputs the signal OUT1 of the bidirectional transfer circuit 75 to the IN terminal. By inputting to the CT2 terminal and inputting the OUT signal of the latch circuit 74 to the CT1 terminal, an OUT signal that supplies or cuts off the clock signal to the clock generation circuit 73 based on the signals of CT1 and CT2 is output. That is, when either the signals CT1 and CT2 are High, the clock signal is passed, and when both are Low, the clock signal is cut off and the VS or VD level is output as a fixed potential. As a result, the load of the clock signal VCLK can be reduced by supplying the clock only to the required stage and shutting off the others. In the first embodiment, VS is used for odd-numbered stages and VD level is used for even-numbered stages. With this configuration, the capacity of the clock signal line 77 is reduced by supplying the clock signal only to the stage where the signal is transferred, the malfunction due to the delay is prevented, and the current consumption is reduced. The clock control circuit 72 can be omitted if the load on the clock signal line 77 does not matter.

Next, as shown in FIGS. 4 and 5 (B), the clock generation circuit 73 inputs the unipolar clock signal VCLK output from the OUT terminal of the clock control circuit 72 from the IN terminal, and there is no phase shift. This is a circuit that generates a bipolar clock signal and outputs it from the OUT terminal and OUTX terminal to the latch circuit 74. With this configuration, it is possible to prevent a malfunction of the latch circuit 74 due to a phase shift between the output bipolar clock signals. The clock generation circuit 73 can be omitted by inputting a reverse polarity signal of the clock signal VLCK when the phase shift of the clock signal does not matter.

As shown in FIGS. 4 and 5 (C), the latch circuit 74 inputs the start pulse signal VSP input from the signal input terminal 53 from the IN terminal via the bidirectional transfer circuit 75, and from the clock signal VCLK. The clock signal generated by the clock generation circuit 73 is used for latching or sequential transfer. That is, the latch circuit 74 transfers the start pulse signal VSP when the clock signal CL = High and the inverted clock signal CX = Low, and performs the latch operation when the clock signal CL = Low and the inverted clock signal CX = High. When the initialization signal INIT is High, Low output is forcibly performed and reset is performed.

Further, as shown in FIGS. 4 and 5 (D), the bidirectional transfer circuit 75 is the first to mth of the scanning line 31 when the transfer direction control signal VDIR = High and the transfer direction inversion control signal VDIRX = Low. When the transfer direction control signal VDIR = Low and the transfer direction reversal control signal VDIRX = High, the forward transfer is performed in the forward direction to transfer in the direction of, and the reverse direction transfer is performed to transfer in the mth to the first direction of the scanning line 31. If bidirectional transfer is not required, the bidirectional transfer circuit 75 can be omitted.

The NAND circuit 76 inputs the output signals OUT of the front and rear stages of the latch circuit 74 and the enable signal VENB input from the signal input terminal 53, and outputs the NAND results of these signals. Specifically, the output signal OUT from the latch circuit 74 is input to the NAND circuit 76, and the NAND circuit 76 outputs Low (= VS level) only at the stage where the enable signal VENB is selected at the timing of High (= VD). However, the other stage outputs the High (= VD) level. The VD to VS level signals are converted to VHH to VBB levels by the level shifter circuit 81 and input to the gate electrodes of the p-channel transistor 83 and the n-channel transistor 84 of the output circuit 82.

FIG. 5 (E) is a configuration diagram of the level shifter circuit 81. By arranging two stages of so-called flip-flop type level shifters in series, VD to VS level signals are converted into VHH to VBB level signals. If the output signal from the NAND circuit 76 is Low (= VS), that is, in the selected state, the VHH potential is written to the scanning line 31 by the p-channel transistor 83. As a result, the potential of VHH is supplied to the gate electrode of the transistor of the pixel switching element 34 as a selective potential, and the pixel switching element 34 is electrically lowered in impedance. When the output signal from the NAND circuit 76 is High (= VHH), the power supply potential VBB is written to the scanning line 31 by the n-channel transistor 84. As a result, a potential of VBB (= -4V) is supplied to the gate electrode of the transistor of the pixel switching element 34 as a non-selective potential, and the pixel switching element 34 is electrically made to have a high impedance.

&lt;Configuration of data line drive circuit&gt; Next, the configuration of the data line drive circuit will be described with reference to FIG. FIG. 6 is a configuration example of the data line drive circuit 42. The video signals VIDEO1 to 320 supplied from the signal input terminal 53 are connected to six transmission gate switches 92 for each block, and one transmission gate switch 92 is connected to the data line 32. The selection signals SEL1 to SEL1 to 6 are at VHH (= 9V) to VBB (= -4V) level, are connected to the inverter circuit 93 that generates the reverse polarity signal of the selection signals SEL1 to SEL1, and the power supply is at VHH to VBB level. .. The video signals VIDEO1 to 320 have a potential amplitude of 0.5 to 4.5V.

With the configuration shown in Fig. 6, when the selection signal SEL1 is High (= VHH) and the other selection signals SEL2 to 6 are Low (= VBB), the video signal VIDEO1 and the first data line 32 in the block are short-circuited. , The 2nd to 6th of other data lines 32 in the same block are insulated. Next, when the selection signal SEL2 becomes High (= VHH) and the other selection signals SEL1 and SEL3 to 6 become Low (= VBB), the second of the video signal VIDEO1 and the data line 32 in the block is short-circuited, and the other The data line 32 is insulated. By sequentially setting the selection signals SEL1 to SEL1 to High within one scanning line selection period in this way, the video signal VIDEO1 signal can be distributed to the six data lines 32. This is a partial driver method using a so-called 1: 6 multiplexer. Further, by setting all SEL1 to 6 to the Low (VBB) potential, all the data lines 32 can be insulated and put into a floating state.

&lt;Operation of common potential signal and scanning line&gt; Next, the operation of the common potential signal and the scanning line will be described with reference to FIG. 7. FIG. 7 is a timing chart showing the potentials of the common potential signal VCOM and the scanning line 31 input to the common potential input terminal 54 in the present embodiment. Graph 101 shows the common potential signal VCOM input to the common potential input terminal 54, and graph 102 shows the potential of the scanning line 31. The common potential signal VCOM is reverse-driven between 4.5V and 0.5V at the timing shown at time point B in FIG. 7 (called the common potential inversion timing) every 34.7 μsec, and the potential of the scanning line 31 is 16.7 msec. VHH = 9V potential is obtained during the period t2 (scanning line selection period) in each cycle, VBB = -4V potential is obtained at other timings, and VBB = -4V potential is always given at the common potential reversal timing. This is the so-called 1H common inversion drive. Further, in the present embodiment, at the common potential inversion timing, all the SEL1 to 6 signals in FIG. 6 are held at the VBB = -4V potential, and all the data lines 32 are in a floating state separated from the data line drive circuit 42. .. Further, the period t1 is the time from the common potential inversion timing to the writing of the VHH potential to any one of the scanning lines 31, and the period t3 is the time from the time of writing the VBB potential to all the scanning lines 31 to the next common. It is the period until the potential reversal timing, and t1 + t2 + t3 = 34.7 μsec. The determination method for t1 to t3 will be described later.

&lt;Capacity of common potential input terminal at common potential inversion timing&gt; Next, the capacitance of the common potential input terminal at common potential inversion timing will be described with reference to FIGS. 8 and 9. FIG. 8 is a schematic circuit diagram in which each element / wiring on the active matrix substrate 11 is integrated into a lumped constant model in order to explain the capacitance of the common potential input terminal at the common potential inversion timing in the present embodiment. Is. In the following description, a lumped constant model will be used for simplification. Actually, the load is distributed in two dimensions in the display area, and the effect due to the charge delay in the distribution constant circuit also occurs, but it is difficult to handle analytically, so it is ignored here. In the actual design, the logic analog simulation software shall be used to simulate using a two-dimensional model, and the final adjustment shall be made.

The external drive IC 29 contains a VCOM power supply circuit 111, a VBB power supply circuit 112, a plurality of video signal circuits 113, and a VHH power supply circuit 114, respectively. The VCOM power supply circuit 111 is an AC power supply that outputs the potential shown in the graph 101 of FIG. 7, and has an IC internal impedance Ric1. The output signal of the VCOM power supply circuit 111 is connected to the common potential input terminal 54, is connected to the common potential wiring 55 on the active matrix board 11 with the mounting resistor Rin1, and is further connected to each capacitance line 33 and the vertical conduction portion 56. Will be done. That is, the common potential wiring 55 is a wiring connecting the common potential input terminal 54 and the vertical conductive portion 56. This common potential wiring 55 has a wiring resistance Rl1, and each capacitance line 33 connected to the common potential wiring 55 has a resistance of Rc (Ω) × m (m is the number of scanning lines). Since it is a lumped constant model in which the total capacitance line 33 is approximated to one wiring, the resistance is Rc / 2. Further, the vertical conductive portion 56 is connected to the counter electrode 30 on the counter substrate by a conductive material with a resistor Rq. The sheet resistance of the counter electrode is Rs.

Next, the VBB power supply circuit 112 is a DC power supply that outputs a power supply potential VBB (= -4V), has an IC internal impedance Ric2, and is connected to a power supply terminal 51. The VBB power supply circuit 112 has a mounting resistor Rin2, and the VBB potential is further input to the scanning line drive circuit 41 via the power supply wiring 52 on the active matrix substrate 11. That is, the power supply wiring 52 is a wiring connecting the power supply terminal 51 and the scanning line drive circuit 41. This power supply wiring 52 has a wiring resistance Rl2. At the common inversion timing, all the scanning lines 31 are connected to the power supply potential VBB via the n-channel transistor 84 (the output impedance per one is Rn × m). Assuming that the VBB line impedance per scanning line in the scanning line drive circuit is Rg × m, it is approximated to the resistance value Rg / 2 in the lumped constant model. The scanning line 31 has a resistance Rg and is connected to the gate electrode of each pixel switching element 34.

Next, the video signal circuit 113 is a circuit that outputs 320 video signals (VIDEO1 to 320), has an IC internal impedance Ric3, and is connected to the signal input terminal 53. The video signal circuit 113 has a mounting resistor Rin3, and video signals (VIDEO1 to 320) are input to the data line drive circuit 42, but all the data lines 32 are in a hein impedance state at the common inversion timing.

Next, the VHH power supply circuit 114 is a DC power supply that outputs a power supply potential VHH (= 9V) as a selective potential, has an IC internal impedance Ric4, and is connected to a signal input terminal 53. The VHH power supply circuit 114 has a mounting resistor Rin4, and the VHH potential is further input to the scanning line drive circuit 41 via the power supply wiring on the active matrix board 11. However, at the common inversion timing, all the scanning lines 31 have hein impedance. It is in a state.

Further, between the scanning line 31 (the potential of the scanning line) and the pixel electrode 35 (the potential of the pixel electrode), the total capacitance of all pixels is Cgd, and the scanning line 31 (potential of the scanning line) and the data line 32 (potential of the scanning line) ( Between the potential of the data line), the total capacitance of all pixels has a capacitance of Cgs, and between the pixel electrode 35 (potential of the pixel electrode) and the counter electrode 30 (potential of the counter electrode), the total capacitance of all pixels has Clc. Then, between the pixel electrode 35 (potential of the pixel electrode) and the capacitance line 33 (potential of the capacitance line), there is a capacitance Cs in total for all pixels, and the capacitance line 33 (potential of the capacitance line) and the data line 32 (data line). It is assumed that the total potential of all pixels has a capacitance Ccs.

Further, since all the scanning lines 31 are connected to the power supply potential VBB (= -4V), all the pixel switching elements 34 are in a high impedance state.

Here, the capacitance values in the present embodiment are Cs = 600nF, Clc = 100nF, Cgd = 1nF, Ccs = 5nF, Cgs = 2nF from the result of the electric field calculation, and further approximation is performed using these, and high. By omitting the elements in the impedance state, the circuit diagram of FIG. 8 is simplified as the circuit diagram of FIG. 9 before and after the common inversion timing.

Here, the relaxation time τcom at the time of VCOM inversion is τcom = (Cgd + 1 / (1 / Ccs + 1 / Cgs)) × (Ric1 + Ric2 + Rin1 + Rin2 + Rl1 + Rl2 + Rn + Rg / 2 + Rc / 2). Cgd, Ccs, and Cgs are values that are almost determined by the number of pixels, aperture ratio of pixels, design rules, device structure of TFT, etc., and there is little room for reduction without trade-off with performance in design, and the number of pixels and It increases in proportion to the display area area.

However, if the VHH potential is written to the scanning line 31 before the common potential is completely inverted, the pixel switching element 34 connected to the scanning line 31 has a low impedance, so that the capacitance increases. Therefore, the period t1 in FIG. 7 must be the time during which the common potential is completely reversed by about 95%, that is, 3 × τcom t1 so that the VHH potential is not written on the scanning line 31 before the common potential is completely reversed. , The period t1 increases as the number of pixels and the display area area increase.

On the other hand, the period t3 must be similarly set to 3 × τgate t3 using the VBB potential write relaxation time τgate = (Rg / 2 + Rn + Rl2) × (capacity of scanning line 31) of the scanning line 31. Similarly, the larger the number of pixels and the display area area, the larger the number.

Therefore, the period t2 decreases as the number of pixels and the display area area increase, and finally the writing time to the data line 32 and the pixel electrode 35 becomes insufficient, and the yield decreases due to the process margin. To go. Here, the period t3 is constant regardless of the driving method, but the period t1 can be set to almost 0 by using the common fixed driving method in which the common potential (VCOM) is fixed to the DC potential. Compared to the common fixed drive method, there are more restrictions due to the higher definition and larger screen. To reduce this constraint, it is necessary to reduce the relaxation time τcom at the time of common potential inversion.

For this purpose, optimization must be performed so that the values of Ric1 + Ric2 + Rin1 + Rin2 + Rl1 + Rl2 + Rn + Rg / 2 + Rc / 2 are made as small as possible. Here, Rc &lt;Rg &lt;Rn &lt;&lt; Rl1, Rl2, Rin1, Rin2, and the IC internal impedances Ric1 and Ric2 are fixed values because they are determined by the performance on the IC side. Further, in order to reduce the output impedance Rn of the n-channel transistor 84 of the level shifter circuit 82, the size of the n-channel transistor 84 becomes large, which causes a trade-off with the outer dimensions of the liquid crystal device. Therefore, in design, it is necessary to reduce Rl1 + Rl2 + Rin1 + Rin2 as much as possible. Here, the impedance RA from the common power supply circuit 111 to the counter electrode 30 (common electrode) described in the claim is RA = Rin1 (mounting resistance of the common potential input terminal 54) + Rl1 (wiring resistance of the common potential wiring 55). ), And the impedance RB from the VBB power supply circuit 112 to the scanning line 31 is RB = Rin2 (mounting resistance of the power supply terminal 51 of the power supply potential VBB) + Rl2 (wiring resistance of the power supply wiring 52).

The wiring resistance Rl1 of the common potential wiring 55 is inversely proportional to the wiring width W1 of the common potential wiring 55, and the wiring resistance Rl2 of the power supply wiring 52 is inversely proportional to the wiring width W2 of the power supply wiring 52. However, the size of the active matrix substrate 11 is defined by the required external size of the liquid crystal device 10, and if the sum of the line widths of the signal wiring 57 is W3, W1 + W2 + W3 must be a constant value. For W3, the minimum line width is determined by the requirements of the circuit design or process, so the minimum value may be set within this range. If the wiring lengths of the common potential wiring 55 and the power supply wiring 52 are approximately the same, minimize Rl1 + Rl2 (1 / W1) + (1 / W2) while satisfying W1 + W2 = W0 (constant). The solution is W1 = W2 = W0 / 2. In the embodiment, since W0 = 600 μm when the line width of the signal wiring 57 is set to the practical minimum of 10 μm due to the requirement of the external size, the line width of the common potential wiring 55 is 300 μm and the line width of the power supply wiring 52 is 300 μm. Was set to 300 μm, and the other signal wiring 57 was set to a line width of 10 μm. At this time, Rl1 = Rl2 = 30Ω.

In this way, by minimizing the line width of the other signal wiring 57 and setting the line widths of the common potential wiring 55 and the power supply wiring 52 as approximately the same and largest line width, the common inversion relaxation time τcom is minimized. Can be done. In this embodiment, the widths of the common potential wiring 55 and the power supply wiring 52 are completely the same, but if the lengths of the common potential wiring 55 and the power supply wiring 52 are different, or if there are layout restrictions, they are mutually exclusive. Although a slight difference may be provided, it is preferable that the wiring resistance Rl1 of the common potential wiring 55 and the wiring resistance Rl2 of the power supply wiring 52 are substantially the same. Further, the signal wiring 57 may have different line widths depending on the role of each signal, but it is preferably smaller than the line widths of the common potential wiring 55 and the power supply wiring 52. Here, the signal line 57 is a wiring that supplies a clock signal VCLK, a start pulse signal VSP, an enable signal VENB, and a VHH potential as a selective potential to the scanning line driving circuit 41, and a video signal (VIDEO1 to 320) to the data line driving circuit 42. ) Supply wiring.

Next, the mounting resistance Rin1 of the common potential input terminal 54 is approximately inversely proportional to the total area S1 of the common potential input terminal 54, and the mounting resistance Rin2 of the power supply terminal 51 of the power supply potential VBB is approximately inversely proportional to the total area S2 of the power supply terminal 51. Inversely proportional. However, the sum of the total areas of the power supply terminal 51, the signal input terminal 53, and the common potential input terminal 54 must be less than a certain value depending on the size of the external IC to be mounted, the restrictions of the mounting process, etc., and the signal input terminal 53 The minimum area S3 is also constant depending on the mounting resistance and mounting accuracy. That is, S1 + S2 must also be a constant value, and Rin1 + Rin2 (1 / S1) + (1 / S2) must be minimized while satisfying S1 + S2 = S0 (constant). Yes, and similarly S1 = S2 = S0 / 2 is the optimal solution. In this embodiment, S0 = 15000 square μm due to various restrictions, so S1 = S2 = 7500 square μm was set.

&lt;Arrangement of mounting terminals&gt; Next, the arrangement of mounting terminals will be described with reference to FIG. FIG. 10 is a layout diagram of the power supply terminal 51, the signal input terminal 53, and the common potential input terminal 54 arranged on the overhanging portion 27 in the present embodiment. Each mounting terminal is configured with a mounting terminal of 30 μm × 50 μm as one unit according to the request of the mounting process, and 2 rows × 190 columns are arranged in a staggered pattern. Here, the common potential input terminal 54 uses five 30 μm × 50 μm mounting terminals in parallel, and similarly, five 30 μm × 50 μm mounting terminals are used as the power supply terminals 51. Further, the plurality of signal input terminals 53 assign one mounting terminal of 30 μm × 50 μm to each signal. In this way, the minimum mounting area may be allocated to the signal input terminal 53, and the rest may be allocated to the power supply terminal 51 and the common potential input terminal 54 substantially evenly. At this time, the mounting resistance Rin1 = 5Ω of the common potential input terminal 54 and the mounting resistance Rin2 = 5Ω of the power supply terminal 51 of the power supply potential VBB. Therefore, RA = RB = 35Ω.

In the present embodiment, the plurality of signal input terminals 53 are all set to have the same mounting terminal area, but different terminal areas may be set according to the role of each signal. However, even in that case, it is preferable that the area of the other signal input terminals 53 is smaller than the area of the common potential input terminal 54 and the power supply terminal 51. If the sum of the number of terminals assigned to the power supply terminal 51 and the common potential input terminal 54 is an odd number, the number of terminals to either of them may be increased.

In this embodiment, since Ric1 = 35Ω, Ric2 = 20Ω, Rn = 3Ω, Rg = 10Ω, and Rc = 2Ω, the common inversion relaxation time is τcom = 140Ω × 2.4nF = 340n seconds, and the scanning line starts from the common potential inversion timing. The period t1 until the VHH potential was written to 31 was set to 1 μsec, and a sufficient writing time was secured with the scanning line selection period t2 = 32.7 μsec. As a result, even a panel called diagonal 4-inch VGA, which was difficult to drive in common inversion in the past, can be driven in common inversion, and can be manufactured with a high yield. Therefore, it is possible to realize a liquid crystal device that does not reduce the yield, costs less, and consumes less current while using an inexpensive low-voltage IC for the external drive IC 29.

(Second Embodiment) Next, the second embodiment of the liquid crystal apparatus according to the present invention will be described. FIG. 11 is a diagram showing an active matrix substrate 11 that realizes the second embodiment of the present invention. The configuration of the liquid crystal device 10 using the active matrix substrate 11 is not different from that of the first embodiment, and thus will be omitted.

According to the present embodiment, m scanning lines 31 and n data lines 32 are formed on the active matrix substrate 11 so as to intersect each other, and m capacitance lines 33 are parallel to the scanning lines 31. Moreover, they are arranged alternately so as to be paired with the scanning lines 31.

Further, the scanning line 31 is connected to the scanning line driving circuit 41, the power supply terminal 51 is connected to the scanning line driving circuit 41 via the power supply wiring 52, and the plurality of signal input terminals 53 also have the plurality of signal wirings 57. Connected via. From the power supply terminal 51, the DC power supply potential VBB (= -4V) that holds the scanning line 31 in the holding state (non-selected state), and from the signal input terminal 53, various necessary signals and signals for giving the power supply potential are scanning lines. It is supplied to the drive circuit 41. Further, the data line drive circuit 42 is connected to one end side and the data line precharge circuit 43 is connected to the data line 32 on the other end side. A plurality of signal input terminals 53 are connected to the data line drive circuit 42 via the signal wiring 57, and various necessary signals and signals for giving a power supply potential are supplied. The timing signal terminal 151 is connected to the data line precharge circuit 43 via the timing signal wiring 152, and the precharge potential terminal 153 is connected to the data line precharge circuit 43 via the precharge potential wiring 154.

The capacitance lines 33 are short-circuited to each other, connected to the common potential input terminal 54 via the common potential wiring 55, and a common potential signal (VCOM = -4.5V to -0.5V) is supplied. Further, at the four corners of the active matrix substrate 11, upper and lower conductive portions 56 that conduct with the opposite electrodes of the opposite substrate are arranged, and are similarly connected to the common potential input terminal 54 via the common potential wiring 55.

FIG. 12 is a block diagram of the data line precharge circuit 43. Each data line 32 is connected to a drain electrode of a precharge switch 161 composed of an N-channel thin film transistor, and each gate electrode of the precharge switch 161 is connected to a timing signal terminal 151 via a timing signal wiring 152. Given the timing signal PRC. Further, each source electrode of the precharge switch 161 is connected to the precharge potential terminal 153 via the precharge potential wiring 154, and is given a precharge potential PRV.

Further, as shown in FIG. 13, the timing signal PRC is a signal that becomes High (9V) for a period of 5 μsec before and after the VCOM signal is inverted, and becomes Low (-4V) for another period. During the period when the timing signal PRC is high, the data line 32 is short-circuited to the precharge potential PRV. By adopting such a configuration, the voltage before and after VCOM inversion is constant as compared with the configuration without the data line precharge circuit 43, so that the writing time to the data line can be shortened and the data line can be shortened. Since the power supply voltage of the drive circuit 42 can also be lowered, the power consumption is low. At this time, the precharge potential PRV can further reduce the drive voltage of the data line drive circuit 42 by taking an intermediate value between the high voltage value and the low voltage value of the common potential. In this embodiment, the precharge potential PRV is a DC potential of 2.5V.

The configuration of each pixel arranged at the intersection of the scanning line 31 and the data line 32, the configuration of the scanning line driving circuit 41, and the configuration of the data line driving circuit 42 are the same as those in the first embodiment, and thus are omitted. As described above, the present embodiment is significantly different from the first embodiment in that the data line 32 is short-circuited to the precharge potential PRV at the moment of VCOM inversion.

FIG. 14 is a schematic circuit diagram of a centralized model in which each element / wiring on the active matrix substrate 11 is integrated in order to explain the capacitance of the common potential input terminal at the common potential inversion timing in the present embodiment. .. Compared with FIG. 8 in the first embodiment, the external drive IC 29 includes a VCOM power supply circuit 111, a VBB power supply circuit 112, a plurality of video signal circuits 113, a VHH power supply circuit 114, and a precharge potential power supply circuit 160. Built-in, the data line 32 is short-circuited with the precharge potential power supply circuit 160 via the data line precharge circuit 43, the precharge potential wiring 154, and the precharge potential terminal 153.

The capacitance values in this embodiment are: capacitance Cs = 600nF between the pixel electrode 35 and the capacitance line 33, capacitance Clc = 100nF between the pixel electrode 35 and the counter electrode 30, capacitance Cgd = 1nF between the scanning line 31 and the pixel electrode 35, The capacitance between the capacitance line 33 and the data line 32 is Ccs = 5nF, and the capacitance between the scanning line 31 and the data line 32 is Cgs = 2nF. become. In this case, the conditions for minimizing the relaxation time τcom at the time of common potential reversal are Rl1 (wiring resistance of common potential wiring 55) = (Ccs + Cgd) / Cgd × Rl2 (wiring resistance of power supply wiring 52), Rl4 (pre). Wiring resistance of charge potential wiring 154) = (Ccs + Cgd) / Ccs × Rl2 (wiring resistance of power supply wiring 52), Rin1 (mounting resistance of common potential input terminal 54) = (Ccs + Cgd) / Cgd × Rin2 (power supply) Power supply so that the mounting resistance of the power supply terminal 51 of the potential VBB) and Rin4 (mounting resistance of the precharge potential terminal 153) = (Ccs + Cgd) / Ccs × Rin2 (mounting resistance of the power supply terminal 51 of the power supply potential VBB) The line width of the wiring 52 and the number of power supply terminals 51 may be taken into consideration. That is, 1 / Rl1 + 1 / Rl4 = 1 / Rl2 and 1 / Rin1 + 1 / Rin4 = 1 / Rin2, and the sum of the wiring width of the power supply wiring 52 and the wiring width of the precharge potential wiring 154 is the common potential wiring. The wiring width of 55 may be approximately equal, and the sum of the terminal area of the power supply terminal 51 and the terminal area of the precharge potential terminal 153 may be approximately equal to the terminal area of the common potential input terminal 54.

Based on the above, in the present embodiment, the line width of the common potential wiring 55 is set to 300 μm, the line width of the precharge potential wiring 154 is set to 250 μm, and the line width of the power supply wiring 52 is set to 50 μm. The wiring width of each signal wiring 57 and timing signal wiring 152 is 10 μm, which is the minimum rule. At this time, Rl2 = 30Ω, Rl1 = 180Ω, and Rl4 = 36Ω. Further, as shown in FIG. 16, the common potential input terminal 54 uses five 30 μm × 50 μm mounting terminals in parallel, and similarly, the precharge potential terminal 153 has four 30 μm × 50 μm mounting terminals, the power supply terminal 51, and the like. One mounting terminal of 30 μm × 50 μm is used as each signal input terminal 53 and timing signal terminal 151. At this time, Rin2 = 5Ω, Rin4 = 6.3Ω, and Rin1 = 25Ω.

With this setting, the common reversal relaxation time τcom = 1.3 μsec, and the period from the common potential reversal timing to writing the VHH potential to the scanning line 31 is set to t1 = 4μsec and the scanning line selection period t2 = 29.7μsec. As a result, sufficient common reversal relaxation time and charging time were obtained.

&lt;Electronic Equipment&gt; Hereinafter, the electronic equipment according to the present invention will be described with reference to embodiments. It should be noted that this embodiment shows an example of the present invention, and the present invention is not limited to this embodiment.

FIG. 17 shows an embodiment of an electronic device according to the present invention. The electronic device shown here includes a liquid crystal device 10, a display information processing circuit 780 that controls the liquid crystal device 10, a central calculation circuit 781, an external I / F circuit 782, an input / output device 783, and a power supply circuit 784.

The display information processing circuit 780 appropriately rewrites the video data stored in the RAM (Random Access Memory) based on the command from the central arithmetic circuit 781, and supplies the video signal to the liquid crystal device 10 together with the timing signal. The central arithmetic circuit 781 performs various operations based on the input from the external I / F circuit 782, and outputs commands to the display information processing circuit 780 and the external I / F circuit 782 based on the results. The external I / F circuit 782 sends information from the input / output device 783 to the central arithmetic circuit 781, and controls the input / output device 783 based on a command from the central arithmetic circuit 781. The input / output device 783 is a switch, a keyboard, a hard disk, a flash memory unit, and the like. Further, the power supply circuit 784 supplies a predetermined power supply voltage to each of the above components.

Here, the electronic device is specifically a monitor, a TV, a laptop computer, a PDA, a digital camera, a video camera, a mobile phone, a photo viewer, a video player, a DVD player, an audio player, and the like.

The present invention is not limited to the embodiment, and is not limited to the TN mode, but is used for a vertical alignment mode (VA mode) using a liquid crystal having a negative dielectric anisotropy and an IPS mode liquid crystal device using a transverse electric field. You may use it. Further, not only the total transmission type but also the total reflection type and the reflection transmission combined type may be used. Further, the active element may be an amorphous silicon TFT as well as a polysilicon TFT, or may be another active element.

<figref num="1">FIG. 3 is a perspective view (partial cross section) of the liquid crystal device according to the embodiment of the present invention.</figref><figref num="2">The block diagram of an active matrix substrate in 1st Embodiment of this invention.</figref><figref num="3">FIG. 6 is a configuration diagram of each pixel on an active matrix substrate according to an embodiment of the present invention.</figref><figref num="4">The block diagram of the scanning line drive circuit in embodiment of this invention.</figref><figref num="5">Each structural circuit diagram of the scanning line drive circuit in embodiment of this invention.</figref><figref num="6">The block diagram of the data line drive circuit in embodiment of this invention.</figref><figref num="7">The timing chart figure in 1st Embodiment of this invention.</figref><figref num="8">Schematic diagram of the load at the common reversal timing in the first embodiment of the present invention.</figref><figref num="9">The simplified load schematic diagram in the 1st Embodiment of this invention.</figref><figref num="10">The mounting terminal diagram in the 1st Embodiment of this invention.</figref><figref num="11">FIG. 6 is a block diagram of an active matrix substrate according to a second embodiment of the present invention.</figref><figref num="12">The data line precharge circuit block diagram in 2nd Embodiment of this invention.</figref><figref num="13">The timing chart figure in the 2nd Embodiment of this invention.</figref><figref num="14">Schematic diagram of the load at the common reversal timing in the second embodiment of the present invention.</figref><figref num="15">The simplified load schematic diagram in the 2nd Embodiment of this invention.</figref><figref num="16">The mounting terminal diagram in the 2nd Embodiment of this invention.</figref><figref num="17">The block diagram of the electronic device in embodiment of this invention.</figref>

Code description

10 ... Liquid crystal device, 11 ... Active matrix board, 12 ... Opposite board, 31 ... Scan line, 32 ... Data line, 33 ... Capacitive line, 41 ... Scan line drive Circuit, 42 ... data line drive circuit, 43 ... data line precharge circuit, 51 ... power supply terminal, 52 ... power supply wiring, 53 ... signal terminal, 54 ... common potential input terminal , 55 ... common potential wiring, 57 ... signal wiring, 151 ... timing terminal, 152 ... timing wiring, 153 ... precharge potential terminal, 154 ... precharge potential wiring.