Semiconductor device and its manufacturing method

The present invention relates to a semiconductor device including a vertical MOS transistor.

The vertical MOS transistor can be highly integrated as compared with the horizontal MOS transistor, and is suitable for electric power applications such as electric power control.

FIG. 16 is an example of a general vertical MOS transistor, FIG. 16 (a) is a schematic cross-sectional view of an N-channel vertical MOS transistor 9N, and FIG. 16 (b) is a P-channel vertical MOS transistor 9P. It is a schematic cross-sectional view of.

The N-channel vertical MOS transistor 9N shown in FIG. 16A has a high-concentration N-conductive (N +) semiconductor substrate 1d as a drain region on the back surface side, and is formed on the semiconductor substrate 1d with a low-concentration N-conductive type (N +). The epitaxial layer 1a of N-) is used as the drift region. Further, the medium-concentration P conductive type (P) well 1c formed on the surface layer of the epitaxial layer 1a is used as a channel region, and the high-concentration N conductive type (N +) region 1s formed in the well 1c is used as the main surface side. It is the source area of.

On the contrary, in the P-channel vertical MOS transistor 9P shown in FIG. 16B, the high-concentration P conductive type (P +) semiconductor substrate 2d is used as the drain region on the back surface side, and the low-concentration P formed on the semiconductor substrate 2d. The conductive type (P-) epitaxial layer 2a is used as the drift region. Further, the medium-concentration N conductive type (N) well 2c formed on the surface layer of the epitaxial layer 2a is used as the channel region, and the high-concentration P conductive type (P +) region 2s formed in the well 2c is used as the main surface side. It is the source area of.

The vertical MOS transistors 9N and 9P shown in FIGS. 16A and 16B have a trench gate structure that provides low on-resistance, and each gate has a well 1c that is a channel region as shown in the figure. It is formed so as to penetrate through 2c and protrude into the epitaxial layers 1a and 2a which are drift regions.

In recent years, in the field of semiconductor devices used for electric power applications, vertical MOS transistors having a super junction (SJ) structure composed of a PN column layer capable of high withstand voltage and low on-resistance have been known. It is disclosed in Japanese Patent Application Laid-Open No. 2000-260984 (Patent Document 1).

FIG. 17 is a perspective view schematically showing an N-channel vertical MOS transistor 10N having an SJ structure disclosed in Patent Document 1. In the N-channel vertical MOS transistor 10N of FIG. 17, the same reference numerals are given to the parts corresponding to the components of the N-channel vertical MOS transistor 9N of FIG. 16 (a).

The N-channel vertical MOS transistor 10N shown in FIG. 17 is formed in the middle portion of the cross section of the semiconductor substrate 3, has a strip shape in the cross section of the substrate, and has a repeating pattern in which the p-conductive region and the n-conductive region are striped in the substrate surface. It has a pn column layer 3a. The pn column layer 3a functions as a drift layer.

In the N-channel vertical MOS transistor 10N having the SJ structure shown in FIG. 17, the electrons flowing out from the source region 1s pass through the channel formed in the p-conductive region 1c around the trench gate G in the drift region. It flows into the n conductive region of a certain pn column layer 3a. Therefore, by increasing the impurity concentration in the n-conductive region, which is the drift region, the on-resistance of the N-channel vertical MOS transistor 10N in FIG. 17 can be reduced. On the other hand, in the off state, the pn column layer 3a can be completely depleted to achieve a high withstand voltage. In this way, by appropriately setting the width, depth, and impurity concentration of the pn column layer, an N-channel vertical MOS transistor having a desired on-resistance and withstand voltage can be obtained. Similarly, by reversing all the conductive types of each component of the N-channel vertical MOS transistor 10N shown in FIG. 17, a P-channel vertical MOS transistor having an SJ structure can be obtained.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2000-260984</text></patcit>

<p> When applying a vertical MOS transistor to a power application such as power control, both the N-channel MOS transistor 9N shown in FIG. 16 (a) and the P-channel MOS transistor 9P shown in FIG. 16 (b) may be required.</p><p> FIG. 18 is an example of a semiconductor device that requires both the N-channel MOS transistor and the P-channel MOS transistor, and is an equivalent circuit diagram of the semiconductor device 90 in which an H-type bridge circuit for driving a motor or the like is formed. ..</p><p> In the semiconductor device 90 in which the H-type bridge circuit shown in FIG. 18 is formed, a motor (M) and two P-channel vertical MOS transistors 9P and two N-channel vertical MOS transistors are connected between the power supply Vdd and the ground GND. The circuit of 9N is configured to form an H shape as shown in the figure. The N-channel MOS transistor 9N and the P-channel MOS transistor 9P are switches for the current circuit, respectively. By appropriately switching between the N-channel MOS transistor 9N, which is a low-side switch, and the P-channel vertical MOS transistor 9p, which is a high-side switch, a reverse current is passed through the motor M as shown by the thick arrow in the figure, and the motor is driven in reverse. Can be made to.</p><p> On the other hand, the two N-channel vertical MOS transistors 9N and the two P-channel vertical MOS transistors 9P constituting the H-type bridge circuit are shown in FIGS. 16 (a) and 16 (b), respectively. The conductive type of the component is completely reversed. Therefore, it is difficult to form the vertical MOS transistors 9N and 9P of both channels on one chip. In the conventional semiconductor device 90, the N-channel vertical MOS transistor 9N and the P-channel vertical MOS transistor 9P are respectively. It is formed from different chips and used in combination. Therefore, in the conventional semiconductor device 90, it is necessary to mount the transistors separately, and the wiring connecting each transistor becomes long, which causes problems such as restrictions on miniaturization, an increase in manufacturing cost, and an increase in parasitic inductance of the wiring. There is.</p><p> Therefore, an object of the present invention is to provide a semiconductor device in which an N-channel vertical MOS transistor and a P-channel vertical MOS transistor are formed on one chip, and to provide a compact and inexpensive semiconductor device and a method for manufacturing the same. There is.</p>

<p> In the semiconductor device of the present invention according to claim 1, a source region is formed on the main surface side of the semiconductor substrate, a drain region is formed on the back surface side of the semiconductor substrate, and the semiconductor device is sandwiched between the source region and the drain region. It is a semiconductor device equipped with a vertical MOS transistor having a PN column layer as a drift layer, which is strip-shaped in the cross section of the substrate and has a repeating pattern on at least one of them in the substrate surface, which is composed of a P conductive type region and an N conductive type region. The vertical MOS transistor (N channel) having a high-concentration N conductive region as a source and drain and the vertical MOS transistor (P channel) having a high-concentration P conductive region as a source and drain are described above. It is characterized in that it is integrally formed on a semiconductor substrate.</p><p> The semiconductor device of the present invention is a semiconductor device in which a vertical MOS transistor having a PN column layer is formed, and utilizes the fact that the PN column layer is the same for the N channel and the P channel, so that the N channel vertical type is used. A MOS transistor and a P-channel vertical MOS transistor are formed on the same semiconductor substrate. Therefore, the semiconductor device is a semiconductor device in which a P-channel vertical MOS transistor and an N-channel vertical MOS transistor are formed on one chip, and can be a compact and inexpensive semiconductor device. Further, the PN column layer in the semiconductor device can be used as a super junction (SJ) structure. Therefore, the N-channel vertical MOS transistor and the P-channel vertical MOS transistor constituting the semiconductor device can be made into a transistor having a high withstand voltage and a low on-resistance.</p><p> As described in claims 2 and 3, in the semiconductor device, the repeating pattern may be, for example, a striped repeating pattern, or a circular or polygonal repeating pattern. The PN column layer can function as an SJ structure in any of the above repeating patterns, and the N-channel vertical MOS transistor and P-channel vertical MOS transistor constituting the semiconductor device have high withstand voltage and low on-resistance. Can be a transistor.</p><p> As described in claim 4, in the semiconductor device, the gate structure of the vertical MOS transistor is a trench gate structure, and the trench gate of the N-channel vertical MOS transistor and the P-channel vertical MOS transistor of the trench gate and the P-channel vertical MOS transistor. The trench gate is formed so as to penetrate the P conductive type well and the N conductive type well formed on the main surface side of the substrate and protrude into the N conductive type region and the P conductive type region in the PN column layer, respectively. It can be configured to be.</p><p> By adopting the trench gate structure as described above, it is possible to increase the integration and reduce the on-resistance per unit area as compared with the case where the gate structure of the vertical MOS transistor is a planar gate structure.</p><p> As described in claim 5, the trench gate and the repeating pattern can both be striped and arranged so that the stripe of the trench gate and the stripe of the repeating pattern are parallel to each other. In this case, the maximum current can be secured by the shortest current path to the PN column layer. Further, as described in claim 6, the stripes of the trench gate and the stripes of the repeating pattern can be arranged so as to intersect with each other. In this case, it is not necessary to precisely align the trench gate with the PN column layer, and the semiconductor device can be manufactured at low cost.</p><p> Further, as described in claim 7, the gate structure of the vertical MOS transistor is a planar gate structure, and the channel regions of the N-channel vertical MOS transistor and the P-channel vertical MOS transistor are respectively the substrate. It is also possible to configure the surface layer portion of the P conductive type well in the N conductive type region and the surface layer portion of the N conductive type well in the P conductive type region on the PN column layer on the main surface side of the above.</p><p> In the case of the planar gate structure, the planar gate and the PN column layer are separated from each other, so that the alignment accuracy of the planar gate and the PN column layer is not required as in the case of the trench gate structure. However, when both the flat gate and the repeating pattern are striped, the following effects can be obtained as in the case of the trench gate. That is, as described in claim 8, when the stripes of the flat gate and the stripes of the repeating pattern are arranged so as to be parallel to each other, the maximum current can be secured in the shortest current path with respect to the PN column layer. Further, as described in claim 9, when the stripes of the planar gate and the stripes of the repeating pattern are arranged so as to intersect with each other, it is not necessary to precisely align the planar gate with respect to the PN column layer, and the semiconductor device is concerned. Can be manufactured at low cost.</p><p> In the above semiconductor device, the terminal portions of the N-channel vertical MOS transistor and the P-channel vertical MOS transistor integrally formed on the semiconductor substrate are shared and arranged close to each other, and as described in claim 10, a predetermined substrate cross section is provided. In the above, the shortest outer peripheral distance between the P conductive type well and the N conductive type well can be set to be smaller than twice the depth of the PN column layer.</p><p> As a result, the semiconductor device can be miniaturized.</p><p> In the invention according to claim 11, the drain region of the vertical MOS transistor is formed between the intrinsic semiconductor layer as a support substrate and the PN column layer on the back surface side of the substrate, and the intrinsic semiconductor layer is formed. A semiconductor device is configured such that a trench is formed so as to penetrate the trench and reach the drain region, and a metal is embedded in the trench.</p><p> In the semiconductor device, the drain electrode is formed by the metal embedded in the trench reaching the drain region. Therefore, in the above semiconductor device, when arranging the drain region on the back surface side of the substrate under the PN column layer, it is not necessary to grind and polish the back surface side of the substrate to make the wafer thinner. Therefore, it is possible to obtain a semiconductor device that is easy to manufacture and inexpensive.</p><p> In the above semiconductor device, the drain region of the N-channel vertical MOS transistor and the P-channel vertical MOS transistor may be short-circuited and shared, but as described in claim 12, the back side of the substrate is covered with the above. An insulating separation trench reaching the PN column layer is formed, and the drain region of at least one of the vertical MOS transistors is insulated and separated from the drain region of the other vertical MOS transistor by the insulating separation trench. You may. Further, as described in claim 13, an intrinsic semiconductor region extending from the front surface to the PN column layer is formed on the back surface side of the substrate, and the intrinsic semiconductor region provides a drain region of at least one vertical MOS transistor. However, it may be configured to be isolated from the drain region of another vertical MOS transistor.</p><p> As a result, any combination of an N-channel vertical MOS transistor and a P-channel vertical MOS transistor integrally formed on the same semiconductor substrate can be connected, and various circuits can be configured.</p><p> In the semiconductor device, as described in claim 14, a pair of vertical MOS transistors including one N-channel vertical MOS transistor and one P-channel vertical MOS transistor is formed on the semiconductor substrate. Two pairs are formed, and the drain regions of the two pairs are isolated from each other by the insulating separation trench or the intrinsic semiconductor region, and the H-type bridge circuit is formed by the two pairs. It is suitable as a semiconductor device.</p><p> Further, as described in claim 15, the semiconductor device is a pair of vertical MOS transistors in which one N-channel vertical MOS transistor and one P-channel vertical MOS transistor are paired, and the N It is suitable as a semiconductor device in which the gate of the channel vertical MOS transistor and the gate of the P channel vertical MOS transistor are short-circuited and a CMOS inverter circuit is formed by the pair.</p><p> The inventions according to claims 16 and 17 are inventions relating to a method for manufacturing the above-mentioned semiconductor device.</p><p> In the manufacturing method according to claim 16, a source region is formed on the main surface side of the semiconductor substrate, a drain region is formed on the back surface side of the semiconductor substrate, and the drain region is sandwiched between the source region and the drain region. A high-concentration N-conducting region is provided by providing a vertical MOS transistor with a PN column layer as a drift layer, which is strip-shaped and has a P-conductive region and an N-conductive region in which at least one of them has a repeating pattern in the substrate surface. A semiconductor in which the vertical MOS transistor (N channel) as a source and drain and the vertical MOS transistor (P channel) having a high-concentration P conductive region as a source and drain are integrally formed on the semiconductor substrate. A method for manufacturing an apparatus, in which a trench is formed in an N conductive type layer or a P conductive type layer formed on one surface side of a semiconductor substrate, and a different conductive type epitaxial layer is embedded in the trench to form the PN column. A PN column layer forming step as a layer, an epitaxial layer forming step of forming an epitaxial layer on the PN column layer after polishing and flattening the surface of the PN column layer, and P conductive type and A source region forming step in which N conductive type impurities are injected at a high concentration to form a source region on the main surface side of the substrate, and the semiconductor substrate is ground and polished from the other surface side to form the PN column. It has a drain region forming step in which the semiconductor substrate under the layer is set to a predetermined thickness, and P-conductive type and N-conductive type impurities are injected into high concentrations to form a drain region on the back surface side of the substrate. It is characterized by that.</p><p> As a result, the semiconductor device according to claims 1 to 10 is manufactured.</p><p> Further, in the manufacturing method according to claim 17, a source region is formed on the main surface side of the semiconductor substrate, a drain region is formed on the back surface side of the semiconductor substrate, and the substrate is sandwiched between the source region and the drain region. A high-concentration N-conducting type with a vertical MOS transistor whose drift layer is a PN column layer composed of a P-conducting type region and an N-conducting type region, which are strip-shaped in cross section and at least one of which is a repeating pattern in the substrate surface. The vertical MOS transistor (N channel) having a region as a source and drain and the vertical MOS transistor (P channel) having a high-concentration P conductive region as a source and drain are integrally formed on the semiconductor substrate. On the back surface side of the substrate, the drain region of the vertical MOS transistor is formed between the intrinsic semiconductor layer which is a support substrate and the PN column layer, penetrates the intrinsic semiconductor layer, and reaches the drain region. A method for manufacturing a semiconductor device in which a trench is formed and a metal is embedded in the trench. A high concentration of P-conductive and N-conductive impurities is injected into one surface of an intrinsic semiconductor substrate. After forming a drain region forming step as a drain region on the back surface side of the substrate and forming an N conductive type or P conductive type epitaxial layer on one surface of the semiconductor substrate, the N conductive type or P conductive type is formed. After forming a trench in the epitaxial layer of the mold and embedding a different conductive type epitakisha layer in the trench to form the PN column layer, the PN column layer forming step and the surface of the PN column layer being polished and flattened. , The epitaxial layer forming step of forming an epitaxial layer on the PN column layer, and the source region on the main surface side of the substrate by injecting high concentrations of P-conductive and N-conductive impurities into the epitaxial layer. It is characterized by having a source region forming step of forming a trench, and a drain electrode forming step of forming a trench reaching the drain region on the other surface of the semiconductor substrate and embedding a metal in the trench to serve as a drain electrode. There is.</p><p> As a result, the semiconductor device according to claim 11 is manufactured.</p><p> The effects of the semiconductor devices manufactured by the manufacturing methods of claims 16 and 17 are as described above, respectively, and the description thereof will be omitted.</p>

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.

FIG. 1 is an example of the semiconductor device of the present invention, and is a schematic cross-sectional view of the semiconductor device 101.

The semiconductor device 101 shown in FIG. 1 is a semiconductor device in which an N-channel vertical MOS transistor 11N and a P-channel vertical MOS transistor 11P are integrally formed on the same semiconductor substrate 4. In the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P formed in the semiconductor device 101 of FIG. 1, the N-channel vertical MOS transistor 9N and the P-channel vertical MOS transistor 9N and P-channel vertical in FIGS. 16 (a) and 16 (b), respectively. The same reference numerals are given to the parts corresponding to each component of the type MOS transistor 9P.

The N-channel vertical MOS transistor 11N constituting the semiconductor device 101 of FIG. 1 is formed on the back surface side of the semiconductor substrate 4 with the high-concentration N conductive region 1s formed on the main surface side of the semiconductor substrate 4 as the source region. This is a vertical MOS transistor whose drain region is the high-concentration N conductive region 1d. The P-channel vertical MOS transistor 11P has a high-concentration P conductive region 2s formed on the main surface side of the semiconductor substrate 4 as a source region, and a high-concentration P conductive region 2d formed on the back surface side of the semiconductor substrate 4 as a source region. It is a vertical MOS transistor used as a drain region. Both the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P are sandwiched between the source regions 1s and 2s and the drain regions 1d and 2d, form a strip in the substrate cross section, and have a P conductive region in the substrate surface. The PN column layer 4a, in which the N conductive region is a repeating pattern, is used as a common drift layer.

The gate structure of the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P is a trench gate structure. The shape of the trench gate of the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P and the repeating pattern of the PN column layer 4a in the substrate surface is striped, and the stripe of the trench gate and the stripe of the repeating pattern are parallel. It is arranged like this. As a result, the maximum current can be secured in the shortest current path for the PN column layer 4a.

Further, the trench gate of the N-channel vertical MOS transistor 11N penetrates the P conductive well 1c, which is a channel region in the extremely low concentration P conductive (P--) region 4b formed on the PN column layer 4a. , It is formed so as to protrude into the N conductive type region in the PN column layer 4a. The trench gate of the P-channel vertical MOS transistor 11P penetrates the N-conductive well 2c, which is the channel region in the extremely low-concentration N-conductive (N--) region 4c formed on the PN column layer 4a, and PN. It is formed so as to protrude into the P conductive type region in the column layer 4a. By adopting such a trench gate structure, it is possible to increase the integration of the vertical MOS transistors 11N and 11P and reduce the on-resistance per unit area as compared with the case of adopting the planar gate structure described later. The tips of the P conductive wells 1c and the N conductive wells 2c, which are the channel regions of both vertical MOS transistors 11N and 11P, reach the PN column layer 4a. Therefore, the low-concentration P conductive region 4b and the low-concentration N conductive region 4c on the PN column layer 4a may be any conductive type common layer as long as the concentration is extremely low, and the intrinsic semiconductor layer without conductivity may be used. May be.

The semiconductor device 101 of FIG. 1 is a semiconductor device in which a vertical MOS transistor having a PN column layer 4a is formed, and utilizes the fact that the PN column layer 4a is the same in the N channel and the P channel, so that N The channel vertical MOS transistor 11N and the P channel vertical MOS transistor 11P are formed on the same semiconductor substrate 4.

The PN column layer 4a in the semiconductor device 101 can be used as a super junction (SJ) structure. Therefore, the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P constituting the semiconductor device can be made into a transistor having a high withstand voltage and a low on-resistance.

2 (a) and 2 (b) are diagrams for explaining the operating state when the semiconductor device 101 of FIG. 1 is applied to the H-type bridge circuit of FIG. FIG. 2 (a) shows the state when the N-channel vertical MOS transistor 11N, which is a low-side switch, is turned on, and FIG. 2 (b) shows the state when the P-channel vertical MOS transistor 11P, which is a high-side switch, is turned on. It shows the state when it was done.

As shown in FIG. 2A, when the gate G of the N-channel vertical MOS transistor 11N is turned on, the drain region 1d of the N-channel vertical MOS transistor 11N passes through the N conductive region of the PN column layer 4a. Then, a current flows toward the source region 1s. At this time, the P-channel vertical MOS transistor 11P and its surroundings are completely depleted, and the withstand voltage of the P-channel vertical MOS transistor 11P is supported by the PN column layer 4a. On the contrary, as shown in FIG. 2B, when the gate G of the P-channel vertical MOS transistor 11P is turned on, the P-conductive type of the PN column layer 4a is formed from the source region 2s of the P-channel vertical MOS transistor 11P. A current flows through the region toward the drain region 2d. At this time, the N-channel vertical MOS transistor 11N and its surroundings are completely depleted, and the withstand voltage of the N-channel vertical MOS transistor 11N is supported by the PN column layer 4a. As described above, in the semiconductor device 101 of FIG. 1, the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P formed on the same semiconductor substrate 4 can be independently turned on and off.

Therefore, even in a circuit that requires both an N-channel vertical MOS transistor and a P-channel vertical MOS transistor, such as the H-type bridge circuit in FIG. 18, as in the conventional case, FIGS. 16 (a) and 16 (b) It is not necessary to form the N-channel vertical MOS transistor 9N and the P-channel vertical MOS transistor 9P on different chips. In this way, in a system that conventionally required two MOS transistors, an N-channel vertical MOS transistor and a P-channel vertical MOS transistor, the number of parts can be reduced to one, and the system can be miniaturized. Become. Further, in the semiconductor device 101 of FIG. 1, the integration of the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P eliminates the need for wiring between the drains, so that the parasitic inductance and the parasitic capacitance can be reduced. Can be done.

FIG. 3 is an example of another semiconductor device, which is a schematic cross-sectional view of the semiconductor device 101a.

In the semi-device device 101a of FIG. 3, two N-channel vertical MOS transistors 11N and two P-channel vertical MOS transistors 11P are alternately arranged and integrally formed on the same semiconductor substrate 4. In the semi-device device 101a of FIG. 3, the layer on the PN column layer 4a is a true (I) semiconductor layer 4c having no common conductivity.

In the semiconductor device 101a of FIG. 3, the terminal portion of the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P integrally formed on the semiconductor substrate 4 are shared, and the N-channel vertical MOS transistor 11N and the P-channel vertical type are shared. MOS transistors 11P are placed close to each other. Therefore, as shown in FIG. 3, in a predetermined substrate cross section, the shortest outer peripheral distances L1 to L3 of the P conductive well 1c and the N conductive well 2c are set to be smaller than twice the depth d of the PN column layer 4a. Can be arranged so as to. As a result, the semiconductor device in which the N-channel vertical MOS transistor and the P-channel vertical MOS transistor are integrally formed on the same semiconductor substrate, as in the semi-device device 101a of FIG. 3, can be further miniaturized.

Next, a method of manufacturing the semiconductor device 101 shown in FIG. 1 will be described.

4 (a) to 4 (e) are process-specific cross-sectional views showing a manufacturing method of the semiconductor device 101.

First, as shown in FIG. 4A, a semiconductor substrate 4 on which the N conductive layer 4n formed on one surface side is formed is prepared. The semiconductor substrate 4 on which the N conductive layer 4n is formed may be a silicon (Si) single crystal substrate formed with the N conductive epitaxial layer 4n, or the entire N conductive single crystal substrate may be formed. It may be. Further, instead of the N conductive type layer 4n, the semiconductor substrate may have a P conductive type layer formed on one surface side.

Next, as shown in FIG. 4 (b), a trench is formed in the N conductive layer (or P conductive layer) 4n, and a different conductive epitakisha layer is embedded in the trench to form a PN column layer. After the formation of the PN column layer 4a, the surface of the PN column layer 4a is polished and flattened.

Next, as shown in FIG. 4 (c), an extremely low concentration P conductive type (P--) epitaxial layer is formed on the PN column layer 4a, and then N conductive type impurities are partially ion-implanted. .. As a result, an extremely low concentration P conductive type (P--) region 4b and an extremely low concentration N conductive type (N--) region 4c are formed on the PN column layer 4a.

Next, as shown in FIG. 4 (d), the extremely low concentration P conductive type (P--) region 4b and the extremely low concentration N conductive type (N--) formed in the epitaxial layer on the PN column layer 4a. P-conductive and N-conductive impurities are ion-injected into region 4c to form P-conductive and N-conductive wells, and P-conductive and N-conductive impurities are ion-injected at high concentrations to form P-conductive wells. Form a mold source and an N conductive sauce. As a result, the P conductive type well 1c and the N conductive type well 2c, which are the channel regions, and the high concentration N conductive type region 1s and the high concentration P conductive type region 2s, which are the source regions, are formed. Further, a trench gate reaching the P conductive type region and the N conductive type region of the PN column layer 4a is formed at a predetermined position.

Next, the source wiring, the gate wiring, and the like are formed, and the process on the main surface side of the semiconductor substrate 4 shown in FIG. 4D is completed.

Next, as shown in FIG. 4 (e), the semiconductor substrate 4 is ground and polished from the back surface side to make it thinner, and the semiconductor substrate under the PN column layer 4a is set to a predetermined thickness. Next, P-conductive and N-conductive impurities are ion-implanted at a high concentration to form a high-concentration N-conductive region 1d and a high-concentration P-conductive region 2d, which are drain regions, on the back surface side of the substrate 4.

Next, the drain wiring is formed, and the process on the back surface side of the semiconductor substrate 4 shown in FIG. 4 (e) is completed.

With the above, the semiconductor device 101 shown in FIG. 1 is manufactured.

In the manufacturing method of the semiconductor device 101 shown in FIGS. 4A to 4E, it is not necessary to separately form the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P, which simplifies the manufacturing process. To.

As described above, the semiconductor device 101 shown in FIG. 1 is a semiconductor device in which an N-channel vertical MOS transistor 11N and a P-channel vertical MOS transistor 11P are formed on one chip, and is a compact and inexpensive semiconductor. It can be a device.

In the semiconductor device 101 of FIG. 1, the PN column layer 4a functioning as the SJ structure has a strip shape in the cross section of the substrate, and the P conductive region and the N conductive region have a repeating pattern in the substrate surface. The repeating pattern in the substrate surface may be, for example, a striped repeating pattern, or a circular or polygonal repeating pattern.

FIG. 5 shows an example of the repeating pattern in the substrate surface. In FIG. 5A, the P conductive type region and the N conductive type region form a striped repeating pattern in the substrate surface. In FIG. 5 (b), the N conductive region has a repeating pattern of circles in the substrate surface. Further, in FIG. 5 (c), the P conductive type region has a square repeating pattern in the substrate surface, and in FIG. 5 (d), the N conductive type region has a hexagonal repeating pattern in the substrate surface. ing. The repeating pattern shown in FIGS. 5 (b) to 5 (d) is a repeating pattern in which either one of the P conductive type region or the N conductive type region is symmetrically arranged in a dot shape in the other, and is a P conductive type. The region and the N conductive region may be reversed. The shape of the dots is not particularly limited.

In each of the repeating patterns shown in FIGS. 5 (a) to 5 (d), at least one of the P conductive type region and the N conductive type region is a repeating pattern in the substrate surface, and as shown in FIG. 1, the substrate cross section. It becomes a strip shape in. In any of the repeating patterns of FIGS. 5 (a) to 5 (d), the PN column layer 4a shown in FIG. 1 can function as the SJ structure, and the N-channel vertical MOS transistor constituting the semiconductor device 101 can be used. The 11N and P-channel vertical MOS transistor 11P can be used as a transistor with high withstand voltage and low on-resistance.

6 to 8 are perspective views showing a cross section of another semiconductor device 102 to 104.

In the semiconductor devices 102 to 104 shown in FIGS. 6 to 8, the PN column layer 4a has a striped repeating pattern in the substrate surface shown in FIG. 5 (a). Further, the N-channel vertical MOS transistors 12N to 14N and the P-channel vertical MOS transistors 12P to 14P formed in the semiconductor devices 102 to 104 both have a striped trench gate. On the other hand, the semiconductor devices 102 to 104 have different arrangement relationships of the N-channel vertical MOS transistors 12N to 14N and the P-channel vertical MOS transistors 12P to 14P, respectively.

In the semiconductor device 102 of FIG. 6, similarly to the semiconductor device 101 of FIG. 1, the striped trench gates of the N-channel vertical MOS transistor 12N and the P-channel vertical MOS transistor 12P are repeated in a striped manner of the PN column layer 4a. It is arranged parallel to the pattern. In the semiconductor device 101 of FIG. 1, the N-channel vertical MOS transistor 11N and the P-channel vertical MOS transistor 11P are arranged side by side with respect to the striped repeating pattern of the PN column layer 4a. On the other hand, in the semiconductor device 102 of FIG. 6, the N-channel vertical MOS transistor 12N and the P-channel vertical MOS transistor 12P are arranged vertically side by side with respect to the striped repeating pattern of the PN column layer 4a. ing.

On the other hand, in the semiconductor devices 103 and 104 of FIGS. 7 and 8, unlike the semiconductor devices 101 and 102 of FIGS. 1 and 6, the striped trench gates of the N-channel vertical MOS transistors 13N and 14N and the P-channel vertical MOS transistors 13P and 14P are formed. It is arranged so as to be orthogonal to the striped repeating pattern of the PN column layer 4a. Further, in the semiconductor device 103 of FIG. 7, the N-channel vertical MOS transistor 13N and the P-channel vertical MOS transistor 13P are arranged side by side with respect to the striped repeating pattern of the PN column layer 4a. On the other hand, in the semiconductor device 104 of FIG. 8, the N-channel vertical MOS transistor 14N and the P-channel vertical MOS transistor 14P are arranged vertically side by side with respect to the striped repeating pattern of the PN column layer 4a. ing.

When the trench gate stripes and the repeating pattern stripes of the PN column layer 4a are arranged so as to intersect with each other as in the semiconductor devices 103 and 104 shown in FIGS. 7 and 8, the trench gates are precisely aligned with the PN column layer 4a. You don't have to. Therefore, the semiconductor devices 103 and 104 shown in FIGS. 7 and 8 can be manufactured at low cost.

9 (a) and 9 (b) are perspective views showing cross sections of different semiconductor devices 105a and 105b, respectively. In the semiconductor devices 105a and 105b of FIGS. 9A and 9B, the parts corresponding to the respective components of the semiconductor device 101 of FIG. 1 are designated by the same reference numerals.

In each of the semiconductor devices 105a and 105b shown in FIGS. 9A and 9B, the gates of the N-channel vertical MOS transistors 15aN and 15bN and the P-channel vertical MOS transistors 15aP and 15bP have a planar gate structure. In the semiconductor device 105a of FIG. 9A, the striped planar gate of the N-channel vertical MOS transistor 15aN and the P-channel vertical MOS transistor 15aP is parallel to the stripe of the repeating pattern of the PN column layer 4a in the substrate surface. It is arranged so as to be. In the semiconductor device 105b of FIG. 9B, the striped planar gate of the N-channel vertical MOS transistor 15bN and the P-channel vertical MOS transistor 15bP intersects the striped pattern of the repeating pattern of the PN column layer 4a in the substrate surface. It is arranged like this.

In the case of the planar gate structure, the planar gate and the PN column layer 4a are separated from each other, so that the alignment accuracy of the planar gate and the PN column layer 4a is not required as in the case of the trench gate structure. However, as in the case of the trench gate, the following effects can be obtained. That is, when the stripes of the planar gate and the stripes of the repeating pattern of the PN column layer 4a are arranged in parallel as in the semiconductor device 105a shown in FIG. 9A, the shortest current path with respect to the PN column layer 4a. Therefore, the maximum current can be secured. Further, when the stripes of the planar gate and the stripes of the repeating pattern of the PN column layer 4a are arranged so as to intersect each other as in the semiconductor device 105b shown in FIG. 9B, the planar gate is provided with respect to the PN column layer 4a. The semiconductor device 105b can be manufactured at low cost without the need for precise alignment.

FIG. 10 is an example of another semiconductor device, which is a schematic cross-sectional view of the semiconductor device 106. In the semiconductor device 106 of FIG. 10, the same reference numerals are given to the parts corresponding to the respective components of the semiconductor device 101 of FIG.

In the semi-device 106 of FIG. 10, on the back surface side of the substrate, the high-concentration N conductive region 1d and the high-concentration P conductive region 2d, which are the drain regions of the vertical MOS transistors 16N and 16P, are the intrinsic semiconductors that are the supporting substrates. (I) It is formed between the layer 5d and the PN column layer 4a. Further, a trench is formed which penetrates the intrinsic semiconductor layer 5d and reaches the drain regions 1d and 2d, and a metal 5 m is embedded in the trench. The intrinsic semiconductor (I) layer 5d, which is a support substrate, may be a layer (substrate) containing impurities having an extremely low concentration as long as it has a sufficiently large resistance value.

In the semi-device device 101 of FIG. 1, after grinding and polishing the back surface side of the semiconductor substrate 4, N-conductive and P-conductive impurities are ion-implanted to form drain regions 1d and 2d, so that the semiconductor substrate 4 is formed. It was thin overall. On the other hand, in the semi-device 106 of FIG. 10, as shown below, the back surface side of the semiconductor substrate 5 is used as it is thick without grinding and polishing, and is embedded in the trench reaching the drain regions 1d and 2d. The drain electrode is formed by 5 m of the metal.

11 (a) to 11 (d) are process-specific cross-sectional views showing a manufacturing method of the semiconductor device 106.

First, as shown in FIG. 11 (a), P-conductive and N-conductive impurities are ion-implanted at a high concentration on one surface of the intrinsic semiconductor (I) substrate 5d to achieve a high concentration in the drain region. N Conductive region 1d and high-concentration P conductive region 2d are formed. Next, an N-conducting epitaxial layer 4n is formed on the intrinsic semiconductor (I) substrate 5d on which the high-concentration N-conductive region 1d and the high-concentration P-conducting region 2d are formed. A P conductive type epitaxial layer may be formed instead of the N conductive type epitaxial layer 4n.

The steps of forming the PN column layer 4a shown in FIG. 11 (b) and the steps of the semiconductor substrate 5 shown in FIG. 11 (c) on the main surface side of the semiconductor substrate 5 are shown in FIGS. 4 (b) to 4 (d). The process is the same as that described, and the description thereof will be omitted.

Next, as shown in FIG. 11D, trenches reaching the drain regions 1d and 2d are formed on the back surface of the semiconductor substrate 5, and 5 m of metal is embedded in the trenches to form a drain electrode.

Next, the drain wiring is formed, and the process on the back surface side of the semiconductor substrate 5 shown in FIG. 11D is completed.

With the above, the semiconductor device 106 shown in FIG. 10 is manufactured.

In the manufacture of the semiconductor device 106 of FIG. 10, as shown in FIGS. 11A to 11D, when the drain regions 1d and 2d are arranged on the back surface side of the substrate 5d under the PN column layer 4a, the substrate 5d There is no need to grind and polish the back side of the. Therefore, it is easy to manufacture, and the semiconductor device 106 can be an inexpensive semiconductor device.

FIG. 12 is an example of a semiconductor device in which an H-type bridge circuit for driving a motor or the like is formed, FIG. 12 (a) is an equivalent circuit diagram of the semiconductor device 107, and FIG. 12 (b) is a semiconductor. It is a schematic cross-sectional view of apparatus 107. In the semiconductor device 107 of FIG. 12 (b), the same reference numerals are given to the parts corresponding to the respective components of the semiconductor device 101 of FIG.

As shown in FIG. 12A, in the semiconductor device 107 in which the H-type bridge circuit is formed, the short-circuited common drain D1 of the N-channel vertical MOS transistor 11NL and the P-channel vertical MOS transistor 11PL on the left side is used. The short-circuited common drain D2 of the N-channel vertical MOS transistor 11NR and the P-channel vertical MOS transistor 11PR on the right side must be separated.

As shown in FIG. 12B, in the semiconductor device 107, an insulation separation trench 4t reaching the PN column layer 4a is formed on the back surface side of the semiconductor substrate 4, and the insulation separation trench 4t forms drain D1 and drain D2. I try to separate.

In this way, in a semiconductor device in which an N-channel vertical MOS transistor and a P-channel vertical MOS transistor are integrally formed on the same semiconductor group 4, an insulating separation trench 4t reaching the PN column layer 4a on the back surface side of the semiconductor substrate 4 By forming the above, the drain region of at least one vertical MOS transistor can be isolated from the drain region of the other vertical MOS transistor.

FIG. 13 is an example of another semiconductor device, which is a schematic cross-sectional view of the semiconductor device 108.

As shown in FIG. 13, in the semiconductor device 108, the back surface side of the semiconductor substrate 4 under the PN column layer 4a is the intrinsic semiconductor layer 4d, and the high concentration N conductive type region 1d and the high concentration P conductive type, which are drain regions, are used. The region 2d is formed small to leave the intrinsic semiconductor regions 4d1 to 4d3. The drain regions of the high-concentration N conductive region 1d and the high-concentration P conductive region 2d are separated by the intrinsic semiconductor regions 4d1 to 4d3.

In this way, in a semiconductor device in which an N-channel vertical MOS transistor and a P-channel vertical MOS transistor are integrally formed on the same semiconductor group 4, an intrinsic semiconductor region reaching the PN column layer 4a is provided on the back surface side of the semiconductor substrate 4. By forming the drain region of at least one vertical MOS transistor, the drain region of the other vertical MOS transistor can be isolated from the drain region of the other vertical MOS transistor.

14 (a) and 14 (b) are examples of operating states when an H-type bridge circuit for driving a motor is formed using the semiconductor device 108 of FIG. 13, and FIG. 14 (a) is a semiconductor device. FIG. 14 (b) is a diagram showing a current flow in the equivalent circuit of 108, and FIG. 14 (b) is a diagram showing a current flow and a state of formation of a depleted region in a cross section of the semiconductor device 108.

As shown in the semiconductor devices 107 and 108 shown in FIGS. 12 and 13, an N-channel vertical MOS transistor and a P-channel vertical MOS transistor integrally formed on the same semiconductor substrate 4 by using an insulating separation trench 4t and an intrinsic semiconductor region 4d1 to 4d3. By insulating and separating the transistors, any combination of connections can be made by wiring, and various circuits can be configured.

As shown in the semiconductor devices 107 and 108 shown in FIGS. 12 and 13, the semiconductor device of the present invention is a pair of vertical MOS transistors in which one N-channel vertical MOS transistor and one P-channel vertical MOS transistor are paired. 11PL, 11NL), (11PR, 11NR), (12PL, 12NL), (12PR, 12NR), 2 sets (11PL, 11NL), (11PR, 11NR) and (12PL, 12NL), (12PR, 12NR) on the semiconductor substrate 12NR) is formed, and the drain regions D1 and D2 of these two pairs are isolated from each other by the insulating separation trench 4t or the intrinsic semiconductor region 4d1 to 4d3, and the H-type bridge circuit is formed by the two pairs. Is suitable as a semiconductor device in which the above is formed.

FIG. 15 shows an example in which the semiconductor device 101 of FIG. 1 is used as a CMOS inverter circuit, FIG. 15 (a) is a diagram showing wiring of the semiconductor device 101 in an equivalent circuit, and FIG. 15 (b) is a cross section. It is a figure which shows the wiring of the semiconductor device 101 in.

As shown in the semiconductor device 101 shown in FIG. 15, the semiconductor device of the present invention is a pair of vertical MOS transistors (11P) in which one N-channel vertical MOS transistor 11N and one P-channel vertical MOS transistor 11P are paired. , 11N), the gate of the N-channel vertical MOS transistor 11N and the gate of the P-channel vertical MOS transistor 11P are short-circuited, and a CMOS inverter circuit is formed by the pair (11P, 11N), which is suitable as a semiconductor device. is there.

As described above, the semiconductor device of the present invention and the method for manufacturing the same are semiconductor devices in which an N-channel vertical MOS transistor and a P-channel vertical MOS transistor are formed on one chip, and are compact and inexpensive. It is a semiconductor device and its manufacturing method.

<figref num="1">It is an example of the semiconductor device of the present invention, and is a schematic cross-sectional view of the semiconductor device 101.</figref><figref num="2">It is a figure explaining the operation state when the semiconductor device 101 of FIG. 1 is applied to the H-type bridge circuit of FIG. (a) shows the state when the N-channel vertical MOS transistor 11N, which is a low-side switch, is turned on, and (b) is the state when the P-channel vertical MOS transistor 11P, which is a high-side switch, is turned on. Is shown.</figref><figref num="3">Another example of a semiconductor device is a schematic cross-sectional view of the semiconductor device 101a.</figref><figref num="4">(a) to (e) are process-specific cross-sectional views showing a manufacturing method of the semiconductor device 101 of FIG.</figref><figref num="5">(a) to (d) are examples of repeating patterns in the substrate surface of the P conductive type region and the N conductive type region of the PN column layer.</figref><figref num="6">It is a perspective view which showed the cross section of another semiconductor device 102.</figref><figref num="7">It is a perspective view which showed the cross section of another semiconductor device 103.</figref><figref num="8">It is a perspective view which showed the cross section of another semiconductor device 104.</figref><figref num="9">(a) and (b) are perspective views showing cross sections of different semiconductor devices 105a and 105b, respectively.</figref><figref num="10">Another example of a semiconductor device is a schematic cross-sectional view of the semiconductor device 106.</figref><figref num="11">(a) to (d) are process-specific cross-sectional views showing a manufacturing method of the semiconductor device 106 of FIG.</figref><figref num="12">In an example of a semiconductor device in which an H-type bridge circuit for driving a motor or the like is formed, (a) is an equivalent circuit diagram of the semiconductor device 107, and (b) is a schematic cross-sectional view of the semiconductor device 107. Is.</figref><figref num="13">Another example of a semiconductor device is a schematic cross-sectional view of the semiconductor device 108.</figref><figref num="14">An example of an operating state when an H-type bridge circuit for driving a motor is formed using the semiconductor device 108 of FIG. 13, (a) is a diagram showing a current flow in an equivalent circuit of the semiconductor device 108. , (B) are diagrams showing the current flow and the formation state of the depleted region in the cross section of the semiconductor device 108.</figref><figref num="15">In an example of using the semiconductor device 101 of FIG. 1 as a CMOS inverter circuit, (a) is a diagram showing the wiring of the semiconductor device 101 in an equivalent circuit, and (b) shows the wiring of the semiconductor device 101 in a cross section. It is a figure.</figref><figref num="16">An example of a general vertical MOS transistor, (a) is a schematic cross-sectional view of an N-channel vertical MOS transistor 9N, and (b) is a schematic cross-sectional view of a P-channel vertical MOS transistor 9P. ..</figref><figref num="17">It is a perspective view which shows typically the N channel vertical MOS transistor 10N which has the SJ structure part disclosed in Patent Document 1.</figref><figref num="18">It is an example of a semiconductor device that requires both an N-channel MOS transistor and a P-channel MOS transistor, and is an equivalent circuit diagram of a semiconductor device 90 in which an H-type bridge circuit for driving a motor or the like is formed.</figref>

Code description

90,101,101a, 102 ~ 104,105a, 105b, 106 ~ 108 Semiconductor devices 9N, 10N, 11N ~ 14N, 15aN, 15bN, 16N, 11NL, 11NR, 12NL, 12NR N-channel vertical MOS conductors 9P, 11P ~ 14P, 15aP, 15bP, 16P, 11PL, 11PR, 12PL, 12PR P-channel vertical MOS transistor 3,4,5 Semiconductor substrate 3a, 4a PN column layer (SJ structure) 1s High concentration N Conductive region (source region) 1d High concentration N Conductive region (drain region) 1c P Conductive well (channel region) 2s High concentration P conductive region (source region) 2d High concentration P conductive region (drain region) 2c N Conductive well (channel region) 4t Insulation separation Trench 4d Intrinsic semiconductor layer 4d1 ~ 4d3 Intrinsic semiconductor region 5d Intrinsic semiconductor layer (support substrate) 5m Metal