Devices with depinned fermi level of a semiconductor at an electrical junction

Related application

This application was filed by the inventors of the present specification on January 14, 2003, and was given to the assignee as this application, entitled "INSULATED GATED FILD EFFCT TRANSISTOR HAVING SCHOTTKY BARRIERS TO THE CHANNEL" in the United States. Related to Patent Simultaneous Application No. 10 / 342,576. This related application is incorporated herein by reference in its entirety.

The present invention generally relates to semiconductor processes and semiconductor devices. More specifically, the present invention relates to a method of depinning a Fermi level of a semiconductor with a metal-interface layer-semiconductor junction and a device using such a junction.

One of the most basic electrical junctions in modern devices is the metal-semiconductor junction. In such a junction, a metal (such as aluminum) is brought into contact with a semiconductor (such as silicon). This basically forms a rectifying device (diode). That is, this junction tends to guide the current in one direction more favorably than in the other direction. In another example, depending on the material used, the junction will be an ohmic junction (eg, the contact will have negligible resistance regardless of the direction of the current). In 1926, Grondhal and Geiger first tested the rectification aspects of these junctions, and in 1938 Schottky developed a theoretical explanation for the observed rectification.

Schottky theory explained the rectifying effect of metal-semiconductor contacts, which depends on the barrier on the surface of the contact between the metal and the semiconductor. In this model, the height of the barrier (as measured by the potential required to move an electron from a metal to a semiconductor) is the work function of the metal (the work function is the release of the electron at the Fermi level of the metal). The Fermi level is the energy level that occupies the highest at T = 0) and the electron affinity of the semiconductor (the electron affinity is the energy of free electrons and the end of the conduction band of the semiconductor. It is assumed that it is the difference between (the difference between) and, and is expressed as the following equation. φ_B= Φ_M-χ_S [1]

In the above formula, Φ_BIs the barrier height, Φ_MIs the work function of metal, χ_SIs the electron affinity of the semiconductor.

Not surprisingly, numerous attempts have been made to experimentally test this theory. If this theory is correct, it is not surprising that in contact with common semiconductors, direct fluctuations in barrier heights for metals with different working functions are observed. However, what was observed was not direct scaling, but weaker fluctuations to the work function than the model suggests.

Bardeen sought to explain this difference between theoretical predictions and experimental observations by introducing the notion that the surface states of semiconductors play a role in determining barrier height. Surface states are energy levels (in the bandgap between the valence band and the conductive band) at the ends of a semiconductor crystal resulting from the effects of imperfect covalent bonds, impurities, and crystal terminations. FIG. 1 shows a cross section of an un-passivated silicon surface 100. The specific silicon surface shown is a Si (100) 2 × 1 surface. As shown, silicon atoms such as atom 110 on the surface are not fully coordinated and contain inadequate dangling bonds such as dangling bonds 120. These dangling bonds may be responsible for the surface states that take up the charge.

The Bardeen model assumes that its surface states are sufficient to pin the Fermi level in the semiconductor at some point between the valence band and the conduction band. If this is correct, the barrier height in metal-semiconductor junctions must be independent of the metal work function. However, since this condition is rarely observed experimentally, the Bardeen model (as well as Schottky) is considered to be the best limited example.

The cause of the pinning of the Fermi level of semiconductors in metal-semiconductor junctions remains unclear for many years. In fact, to date, no description satisfies all of the experimental observations on such junctions. However, in 1984, Tersoff proposed a model that well explains the physics of such junctions. See Phys.REv.Lett.52 (6), J. Tersoff, "Schottky Barrier Heights and the Continuum of Gap States," published February 6, 1984.

Tersoff model (which is built on research by Heine and Flores and Tejedor. See also Phys. REv. B15,2154 (1977), Louie, Chelikowsky, and Cohen's "Ionicity and the theory of Schottky barriers". That) proposes to pin the Fermi level of the semiconductor at the metal-semiconductor interface near the effective "gap center" associated with the energy band structure of the bulk semiconductor. Pinning is due to the so-called metal-induced gap level (MIGS), which is the energy level of the semiconductor bandgap that is dense due to the proximity of the metal. That is, the wavefunction of the electrons in the metal does not end abruptly on the surface of the metal, but decreases in proportion to the distance from that surface (ie, extends inside the semiconductor). General rule on density of states in semiconductors (sun) In order to maintain the rule), the electrons near the surface occupy the energy level in the gap derived from the valence band so that the density of states of the valence band is reduced. To maintain charge neutrality, the highest occupied level (which determines the Fermi level of the semiconductor) will then be at the intersection from the valence band-derived state to the conduction band-derived state. .. This intersection occurs at the branch point of the band structure. Barrier height calculations based on the Tersoff model do not satisfy all experimentally observed barrier heights for all metal-semiconductor junctions, but are generally in good agreement for many such junctions. ..

<p> One final source of surface effect on diode properties is heterogeneity. That is, if the factors affecting the barrier height (eg, surface density of states) fluctuate across the surfaces of the junction, it is recognized that the resulting junction properties are not a linear combination of the properties of the different regions. In summary, conventional metal-semiconductor junctions are characterized by Schottky barriers whose properties (eg, barrier height) depend on surface conditions, MIGS, and heterogeneity.</p><p> The importance of barrier height at the metal-semiconductor interface is that it determines the electrical properties of the junction. Therefore, if the barrier height of the metal-semiconductor interface can be controlled or adjusted, an electrical device with desired properties could be manufactured. Such adjustment of barrier height will become even more important as the dimensions of the device become smaller. However, the Fermi level of the semiconductor must be depinned before the barrier height can be adjusted. As discussed in detail below, we have achieved this goal in devices that still allow a substantial current to flow between the metal and the semiconductor.</p>

<p> We determined the barrier height for a thin interface layer placed between a metal and a silicon-based semiconductor (eg, Si, SiC, and SiGe) to form a metal-interface layer-semiconductor junction. .. There is a corresponding minimum intrinsic contact resistance there. The interface layer thickness corresponding to this minimum intrinsic contact resistance will vary depending on the material used, but the thickness will vary between metals and semiconductors when a bias (forward or reverse bias) is applied to the junction. It allows the Fermi level of the semiconductor to be unpinned while still allowing current to flow between them. By unpinning the Fermi level, we terminate all or substantially all dangling bonds that may be present on the surface of the semiconductor if not unpinned, and also the semiconductor. Indicates a condition in which the effects of PMIGS have been overcome or at least reduced by separating the PMIGS from the metal by a sufficient distance. Approximately 10Ω-μm²Below or even about 1Ω-μm²The following minimum intrinsic contact resistances will be achieved for such junctions according to the present invention.</p><p> Thus, in one embodiment, the present invention still presents an electrical current between the metal and the semiconductor when the interface layer is placed between and brought into contact with the metal and the semiconductor and a bias is applied to the electrical device. Provided is an electrical device configured to be able to unpin a semiconductor Fermi level while allowing current to flow. The minimum intrinsic contact resistance of this electrical device is approximately 10Ω-μm²Smaller. The interface layer may include passivation materials (eg, nitrides, oxides, silicon nitride, arsenic, hydroxides, and / or fluorides) and may sometimes include a separation layer. In some cases, this interface layer may basically be a single layer (or some single layer) of semiconductor passivation material.</p><p> In another embodiment, the interface layer is generated from the plasma process, eg, ammonia (NH).₃), Nitrogen (N₂), Or made from a passivation layer produced by heating a semiconductor in the presence of a nitrogenous substance such as unbonded gaseous nitrogen (N). In such a case, the interface layer is produced by heating the semiconductor in a vacuum chamber with the semiconductor exposed to a nitrogenous substance.</p><p> A further embodiment of the present invention provides a method of unpinning a Fermi level of a semiconductor in an electrical junction using an interface layer disposed between the surface of the semiconductor and a conductor. The interface layer is preferably (i) thick enough to reduce MIGS in the semiconductor, and (ii) preferably pacitates the surface of the semiconductor. Significant currents can flow between the conductor and the semiconductor despite the presence of the interfacial layer, which provides the minimum (and near-minimum) inherent contact resistance of the interfacial layer to the junction. This is because it may be chosen to do so. As mentioned above, this interface contains passivation materials such as nitrides, oxides, silicon nitride, arsenic, hydroxides, and / or fluorides.</p><p> Further embodiments of the present invention include (i) aligning the Fermi level of the semiconductor from the semiconductor with the conduction band of the semiconductor, (ii) aligning it with the valence band of the semiconductor, or (i). iii) Provide a junction with a conductor separated by an interfacial layer configured to be independent of the Fermi level of the semiconductor. In some or all of these cases, current can flow between the conductor and the semiconductor when a bias is applied to the junction. This is because the interface layer has a thickness corresponding to the minimum or almost minimum natural contact resistance with respect to the junction. For example, about 2500Ω-μm², Approximately 1000Ω-μm², Approximately 100Ω-μm², Approximately 50Ω-μm², Approximately 10Ω-μm²The following, or even about 1Ω-μm²The following minimum intrinsic contact resistances may be achieved:</p><p> Methods of depinning Fermi levels of silicon-based semiconductors (eg, Si, SiC, SiGe) in devices using such junctions as well as metal-semiconductor junctions are described herein. An interface layer is introduced between the semiconductor and the metal, as fully described below. This interface layer pacifies the semiconductor surface (ie, to ensure the chemical stability of the surface, to terminate dangling bonds that may be present on the semiconductor surface if not pacified), and It functions to separate the semiconductor from the metal so as to reduce the effects of MIGS.</p><p> As described in more detail above, we have a thin interface located between a metal and a silicon-based semiconductor (eg, Si, SiC, SiCe) to form a metal-interface layer-semiconductor junction. The barrier height was determined for the layer. There is a corresponding minimum intrinsic contact resistance there. In fact, in such a junction according to the invention, about 10Ω-μm²Below, or even more, about 1Ω-μm²The following minimum inherent contact resistance can be achieved. In order to achieve such low contact resistance, a metal having a work function close to the conduction band of the semiconductor is selected for an n-type semiconductor, or a metal having a work function close to the valence band is selected for a p-type semiconductor. Will be done.</p><p> The Schottky barrier has already been minimized in such a junction, which is the Schottky barrier indicated by the junction in which the Fermi level is pinned approximately in the center of the semiconductor bandgap. It means that it is smaller than that. Since the current-to-voltage (IV) characteristics of such a junction are non-linear and generally have a slope that rises with increasing voltage, the derivative of the current with respect to voltage rises with respect to voltage. As a result, the differential resistance (dV / dI) decreases and the resistance (V / I) decreases. Therefore, a junction with a high or high derivative near the origin (0 volt) of the IV characteristic may have a significantly lower or lower derivative at higher voltages.</p><p> The present invention achieves low resistance and low differential resistance near the origin of current-voltage for metal-interface layer-semiconductor junctions. In general, the voltage near the origin should be less than about 100 mV and more preferably 10 mV in order to measure, determine and utilize such low resistance junctions. The higher the voltage, the lower the junction resistance will be. Therefore, a feature of the present invention is to set an upper limit for the resistance of a certain contact, and this upper limit occurs at a low voltage.</p><p> In a junction where the Schottky barrier is minimized as described above, is the Fermi level at the junction interface at 0 volts (for each of the n-type and p-type semiconductors) at the end of the conduction band or the end of the valence band? It should be further noted that the IV characteristics will be nearly symmetrical, especially at low voltages, as they are located in the vicinity. In this case, the term "forward bias" is not defined in the general sense of a diode in which forward bias corresponds to the direction in which a larger current flows. Therefore, the voltage may be either positive or negative when determining or utilizing the low resistance junctions of the present invention.</p><p> Schottky barriers (according to further embodiments of the invention) have higher junctions than Schottky barriers, which would normally be around the midgap of a semiconductor if the Fermi level at the junction interface is pinned. It is also possible to make it. In the present invention, is such a junction close to the conduction band end of a p-type semiconductor, or formed between metals with substantially the same work function, or close to the valence band end of an n-type semiconductor? , Or formed between metals with substantially equal work functions. These junctions are diodes in that a small current flows when an n-type (p-type) semiconductor is applied to a metal with a positive (negative) bias, and a large current flows when the voltage is reversed. The low current state is called reverse bias and the high current state is called positive bias.</p><p> The low resistance in the case of diodes is only relevant under forward bias conditions. In a junction made according to the present invention, the contribution of the resistance of the interface layer is smaller than the resistance of the Schottky barrier. That is, under forward bias conditions for junctions made according to the present invention, charge transfer is primarily due to thermal radiation of carriers from the semiconductor on the interfacial barrier, not tunneling through the interfacial dielectric. Therefore, the low resistance in the case of a diode means that it is lower than the resistance indicated by the Schottky barrier.</p><p> In some applications of diodes, the ability to withstand high reverse bias is more desirable than the high current in forward bias. These applications will be high voltage / low output applications. In such cases, low resistance is not essential and a junction made according to yet another embodiment of the invention is achieved if the Fermi level of the semiconductor within the junction is pinned, otherwise. Provided is a high voltage diode that can withstand a higher voltage than would be.</p><p> The present invention will be discussed below with respect to its current preferred embodiments, but this discussion is not intended to limit the scope of the invention. By considering the disclosure of the present invention, other skilled in the art may recognize equivalent procedures, materials, or structures that may replace those described herein in order to achieve the same effect. It should be advised and pointed out to the reader that the use of such equivalents is considered to be within the present invention. For example, if the following discussion refers to well-known structures and devices, block diagrams are used to partially illustrate the broad applicability of the invention to a wide range of such structures and devices.</p>

I. Introduction and Definitions The discussion of the present invention is familiar to those skilled in the art, but uses terms that may not be familiar to all readers. Therefore, it is useful to define specific terms and concepts before starting a detailed discussion of the present invention. In order to understand the properties of metal-semiconductor junctions and the effects of the present invention, it is necessary to refer to some important energy measures visually shown in FIG. So-called vacuum level (E₀) Represents the minimum energy that an electron needs to have in order for the electron itself to be completely free from metal or semiconductor. For metals, the Fermi level (E)_F) Represents the highest occupied energy level for the material. That is, almost all energy levels below the Fermi level are filled, but almost all energy levels above the Fermi level are empty. Next, the work function of metal (Φ_M) Is defined as the energy required to release an electron at the Fermi level, and mathematically the difference between the vacuum level and the Fermi level. This work function is the invariant bulk property of the metal.

As shown, the semiconductor is Fermi level (E)_F) And work function (Φ_S), But the work function is not an invariant property of semiconductors. Since the Fermi level varies depending on the doping level in the semiconductor (that is, the relative amount of impurities introduced into the semiconductor crystal that changes the electron carrier concentration and the hole carrier concentration), another parameter, that is, electron affinity, is used. (χ_S) Is determined. Electron affinity is an invariant property of a semiconductor, the difference between the vacuum level and the end of the conduction band of the semiconductor. In some semiconductors, almost all energy levels are in the valence band (E)_V), But the conduction band (E)_C) Is almost empty.

Here, the work function is smaller than the metal and the work function of the metal (ie, Φ_S&lt;Φ_M) Is considered as a conventional junction with an n-type semiconductor. An n-type semiconductor is a type of semiconductor in which electrons are a large number of charge carriers (in a p-type semiconductor, holes are a large number of charge carriers). As shown in FIG. 3, since the Fermi level in the semiconductor is higher than the Fermi level in the metal, electrons move from the semiconductor 310 to the metal 320 when the materials come into contact with each other. Thus, the depleted region (ie, the region in the absence of free charge carriers) 330 forms a junction interface 340 in the vicinity.

As the electrons approach the junction interface from the semiconductor side, the formation of the depletion region causes an electric field and so-called "band bending" (see Figure 4). The bending of the band forms an energy barrier (above) that prevents the movement of electrons to or from the semiconductor. A similar barrier is formed for the junction between the metal and the p-type semiconductor when the work function of the metal is smaller than the work function of the semiconductor. However, a metal-n-type semiconductor junction in which the work function of a semiconductor is larger than the work function of a metal or a metal-p-type semiconductor junction in which the work function of a semiconductor is smaller than the work function of a metal, such an energy barrier is not formed. Contacts are said to be basically ohmic.

As mentioned above, Schottky is the first energy barrier (Φ) formed in the metal-semiconductor junction._b) Is simply the difference between the work function of the metal and the electron affinity of the semiconductor, but experiments have not proved this relationship. Instead, a more complex explanation has emerged that considers surface defect states, heterogeneity, and the effects of MIGS in order to accurately estimate barrier height by explaining Fermi level pinning in semiconductors. To do. We pacify the semiconductor surface (to eliminate or at least reduce surface levels and possible heterogeneity) and (to eliminate or at least reduce the effects of MIGS). By separating the metal from the conductor, we have created a technique that is believed to unpin the Fermi level of Si-based semiconductors in the junction with the metal (hence the ability to control or adjust the barrier height). It was. This depinning is achieved by introducing an interfacial layer between the semiconductor and the metal when a forward bias is applied to the junction.

This latter point is important. As further discussed below, the energy band of the semiconductor and the valence band of the conductor match (ie, the Fermi level of the semiconductor matches the conduction band or valence band of the semiconductor, depending on the type of semiconductor and / or the application of the contact. For (fit) contacts, if the interface layer is very thin, the presence of MIGS will increase the intrinsic contact resistance of the junction, resulting in a higher barrier height. Therefore, the current is hindered. Conversely, if the interface layer is very thick, the intrinsic contact resistance will increase again and the current flowing through the junction will be low due to tunneling limitations. The present invention achieves a layer thick enough to reduce or eliminate the effects of MIGS, while still thin enough to allow large current flow.

II. Semiconductor surface passivation A common processing process performed during a semiconductor device manufacturing process is silicon surface passivation. Surface passivation (using oxides or other materials) chemically neutralizes and physically protects the underlying silicon. For example, when the silicon surface is exposed to oxygen (in an appropriate environment to form a protective film of silicon dioxide), the oxygen reacts with the dangling bonds on the silicon surface to reduce the valence of silicon on the surface. It is possible to form a covalent bond that fills and leaves the surface in a completely coordinated state. These covalent bonds provide chemical stability to the silicon surface. Covalent bonds also bind unbonded charges present on the silicon surface as a result of semiconductor crystal interruptions on the surface.

However, pacitate with silicon dioxide has some major disadvantages. For example, silicon dioxide is a dielectric insulator that provides a large barrier to current flow. Therefore, a single layer of silicon dioxide deposited or grown on a silicon surface can significantly reduce the ability of current to flow on that surface. The use of silicon dioxide on surfaces outside the active region of the semiconductor device (eg, the gate oxide layer) through which current passes during device operation has been practically restricted. This disadvantage is exacerbated by the fact that it is difficult to limit the growth to thin films because silicon dioxide grows very quickly and easily on the silicon surface.

Instead of using silicon dioxide, in one embodiment, we utilize a nitride semiconductor surface to provide chemical passivation. That is, a nitride layer is introduced to passivate the semiconductor surface by eliminating or at least reducing the effects of surface conditions and possibly non-uniformity. The nitrided layer also separates the metal from the semiconductor, eliminating or at least reducing the effects of MIGS. As a result of introducing the nitride layer as the interface between the semiconductor and the metal, the Fermi level of the semiconductor is unpinned. When the Fermi level of this semiconductor is unpinned, the Fermi level of the metal at the interface becomes the Fermi level of the bulk metal and will not be influenced by the interface. In addition to the above, the inventors propose a technique for providing a non-insulating, passivated semiconductor surface using materials other than nitrogen, such as oxides, hydroxides, arsenic, and / or fluorides.

These developments have a wide range of applications in the manufacture of Schottky diodes, Schottky barrier diodes and other electrical components. For Schottky diodes, for example, the ability to control the height of the energy barrier at the diode junction is important when adjusting the device for a particular application. By using the technique of the present invention, it is possible to adjust the height of the barrier. For example, for three-terminal devices with Schottky-barrier isolated channels, device property control relies on the use of metals with different work functions instead of dopants, n-type and p-type. It is possible to utilize the present invention by enabling the device to be manufactured.

FIG. 5 shows a semiconductor device 510 that includes a semiconductor 530 and an interface layer 520 formed on the surface 540 of the semiconductor according to the present invention. The terms semiconductor device, microelectronic device, monolithic device, chip, and integrated circuit are often used synonymously in the art. Some or all of such devices each include an interfacial layer formed on the semiconductor surface according to the present invention.

Semiconductor 530 includes semiconductor materials. The term semiconductor material means a material with a bandgap greater than about 0.1 eV and less than about 4 eV. The term band gap is a forbidden energy that separates the conduction band, which is the upper energy band where electrons are almost absent and can conduct electrons, and the valence band, which is an energy band filled with electrons and cannot conduct electrons. Means level. This semiconductor material has a wide range of doping levels, including levels that do not dope at all.

The semiconductor 530 has a surface 540 pacified by the interface layer 520. In this context (and as used elsewhere herein), the term passive means eliminating or at least reducing the effects of surface states due to defects or dangling bonds on the semiconductor surface 540. It should be noted that the passive does not actually require the removal of all surface states. Rather, it is the effect of surface states on device properties that is restricted or eliminated during passivation. Although the presence of MIGS may be considered a surface state, the term passivation as used herein (in some cases, the passivation layer reduces MIGS between semiconductors and metals). Also note that it does not attempt to imply removal of MIGS (although it may have sufficient thickness to provide a separation layer sufficient to remove). The semiconductor 530 functions to be electrically coupled to the initial voltage of the semiconductor device 510 and to direct a current 550 over the pacified surface 540.

The interface layer 520 includes a passivation material formed on the semiconductor 530 and bonded to the semiconductor material by a covalent (or other) bond formed between the passivation material and the semiconductor material. For example, one atom in a passivation material could supply bond with a dangling bond of a silicon atom on the surface to fully coordinate the silicon atom, thereby facilitating the passage of the silicon atom. There is. In some cases, this passivation material may be the sole constituent of interface layer 520, while in other cases interface layer 520 is a compound layer that includes both a passivation layer and a separation layer. That is, this interface layer acts to (i) chemically pass the semiconductor surface 540 and (ii) sufficiently separate the semiconductor from the metal to eliminate or at least reduce the effects of MIGS. .. As described below, this may need to include a separation layer within the interface layer in addition to the passivation layer, depending on the passivation material selected. Of course, the combination of the passivation layer and the separation layer needs to be thin enough to allow for the low intrinsic contact resistance described herein.

Consider various passivation materials. According to one embodiment, the interface layer 520 is formed using a material preferably selected from the group consisting of hydrogen (H), oxygen (O), nitrogen (N), arsenic (As), fluorine (F). (Ie, the interface layer 520 contains nitrogen, oxygen, hydroxides, arsenic, and / or fluoride). Other materials with similar chemical properties or valences to these materials are used. When H, As, or F passivation layers are used, these layers tend to form monolayer coverage rather than process-dependent layers of Si-containing compounds, thus forming a well-defined separation layer (ie, a passivation layer). Note that) may be required. In contrast, passivation layers made with N and / or O can form a layer of Si compounds with a thickness that allows these elements to vary depending on the process, so a clear separation. Does not require layers.

Consider different amounts of passivation material useful in different embodiments of the present invention. The interface layer 52 includes or is formed from a single passivation layer having a thickness of about 0.1 nm to about 5 nm. For example, depending on the particular practice, this thickness may be about 1 nm, less than 0.5 nm, less than 0.2 nm, or at a thickness corresponding to a single layer or single layer of the passivation material bonded to the semiconductor. The number of atoms in the passivation material required to pass substantially all of the dangling bonds, either present or associated with the semiconductor surface 540.

In some cases, the pacifate of the semiconductor surface 540 includes dangling bonds located close to the surface of the semiconductor material, including dangling bonds on the surface as well as dangling bonds within a few molecular dimensions of the surface. It will include the step of removing (or terminating) the bond. This process will stabilize the surface of the semiconductor material and improve the controllability of the next manufacturing process. Passivet may reduce the surface density of states that may be present on the semiconductor surface as a result of the interruption of the semiconductor crystal on the surface. This can improve the integrity and performance of semiconductor devices, as such conditions are known to interfere with proper device operation. For example, they may provide a surface charge state that results in pinning of the Fermi level.

III. Interfacial layer formation (i) Provides passivation of the semiconductor surface and (ii) eliminates or at least reduces the effects of MIGS in the semiconductor in the presence of metals containing hydrogen, fluorine, or nitrogen. An exemplary method of forming an interface layer to provide a separation of a semiconductor from a metal to allow it (collectively referred to herein as unpinning of the Fermi level of a semiconductor) is described below. The concept will be further explained. Other passivation materials may include arsenic, oxygen, or oxynitrides, and in some cases such passivation layers may be combined with a separating layer (eg, made of oxide) to complete the interfacial layer. To be combined.

A. Hydrogen and Fluorine The interface layer may contain hydrogen, fluorine, or both hydrogen and fluorine (in the form of hydroxides and / or fluorides). One method of forming an interface layer on a semiconductor surface with hydrogen and fluorine is to clean the semiconductor substrate with a cleaning solution and hydrogen fluoride, typically having an effective concentration of about 1% to 50% by weight. Immerse the washed substrate in a solution (or other liquid containing hydrogen and fluorine ions), typically wait for a valid time interval of about a few seconds to about 5 seconds, and then remove the substrate from the hydrogen fluoride solution. It comprises the steps of taking out, optionally rinsing the substrate with deionized water and blowing dry the substrate with nitrogen. Such a method may form a hydrogen and fluorine-containing interface layer that is (eg, covalently) bonded to the surface of the semiconductor.

It should be noted that rinsing with deionized water for longer than about 30 seconds in general may remove the hydrogen passivation. Therefore, in order to maintain hydrogen passivation, it may be advantageous to keep the rinse with deionized water shorter than about 30 seconds. Also, the higher the concentration of hydrogen fluoride during immersion, the higher the concentration of fluorine passivation. Finally, we also consider how the ratio of hydrogen to fluorine passivation can be changed by removing either hydrogen or fluorine.

The interface layer formed in this way may be optimal for applications in which the next metal layer is deposited onto the interface layer in a non-invasive manner, for example using a thermal deposition source. From experiments by the present inventors to date, other approaches (eg, plasma deposition) can be used to create thin (eg, monolayer-thick) interface layers that are considered part of the invention. It has been suggested that it may cause damage.

B. Nitrogen In further embodiments, the interface layer may contain nitrogen (eg, in the form of silicon nitride). One method of forming an interface layer on a semiconductor surface with nitrogen involves heating the semiconductor surface in the presence of a nitrogenous material (ie, a nitrogen-containing gas or other material). For example, a substrate containing an exposed silicon surface, at an effective partial pressure, eg, ammonia (NH).₃) May be annealed at a temperature of about 300 ° C to about 750 ° C, which is lower than the temperature conventionally used for rapid heating nitride formation (RTN). We mean that exposure is clean and nothing but silicon. Such a method forms an interface layer containing nitrogen, which is often a nitride, bonded to the surface of the semiconductor. The present inventors suggest that the growth of the interface layer is self-restricting under such low temperature conditions and depends only on the temperature.

According to another embodiment, the nitrogen-containing interface layer heats the semiconductor material to a substantially high temperature under vacuum and exposes the semiconductor material to a substantially small amount of a nitrogenous gas such as ammonia. May be formed on the exposed surface of the semiconductor material by a method comprising. This method places a semiconductor with an exposed semiconductor surface in a heating chamber and has a vacuum of less than about one millionth torr, or more preferably 10.^-9It involves drawing an ultra-high vacuum lower than Thor and then heating the semiconductor to a substantially higher temperature in the heating chamber. The higher the vacuum, the longer the substrate is heated without growing oxides from the oxygen or water remaining in the heating chamber. Therefore, this step may include the step of heating the semiconductor to about 900 ° C to about 1000 ° C or higher in an inert environment. As required, semiconductors are exposed to hydrogen gas or the like to reduce natural oxides on the semiconductor. Such high temperatures provide a larger passive semiconductor surface compared to the results that would be obtained at lower temperatures.

The heated semiconductor is then exposed to a substantially small amount of nitrogenous material such as ammonia. This step involves exposing the semiconductor surface to ammonia for a substantially short period of time. For example, the surface is exposed to a burst or pulse of ammonia for a time interval of about 0.5 seconds to about 5 seconds. Alternatively, the surface is optionally exposed to a controlled amount of ammonia over longer time intervals. In this way, a substantially small amount of ammonia reacts with the surface to form a nitrogenous interfacial layer such as a nitride layer on the surface, after which further interfacial layer growth ceases. The semiconductor is then cooled from a substantially high temperature to an ambient temperature and removed from the heating chamber. Further annealing of the substrate and the grown nitride layer may be performed in a vacuum chamber at a substantially high temperature of about 700 ° C to about 1000 ° C prior to removal.

Advantageously, it is unexpected that a thin but effective interface layer is controllably formed using a process that incorporates a substantially short period of substantially high temperature exposure, such as the process described above. Was observed in. That is, the present inventors have noticed that temperature may be a dominant factor in controlling the thickness in the formation of a thin interface layer containing a nitrogenous substance. For example, by such a method, a valid interface layer with a thickness of less than about 1 nm, thinner than about 0.5 nm, thinner than about 0.2 nm, or basically all dangling bonds in close proximity to the semiconductor surface are passed. An effective interfacial layer is formed that is thick enough to do so, essentially equivalent to one single layer.

In addition, an advantageously thin interface layer is grown on the semiconductor in the presence of nitrogenous gas or other inert nitrogen-containing gas. The reaction rate of a semiconductor such as silicon and nitrogen gas is significantly lower than the reaction rate of a reactive nitrogen-containing gas such as ammonia. This slow growth rate is sufficient to pass basically all dangling bonds on semiconductors thinner than about 1 nm, thinner than about 0.5 nm, thinner than about 0.2 nm, or close to the silicon surface. It is preferable to better control the nitrogen film on a semiconductor having a thickness basically corresponding to one single layer.

IV. Diodes with Passed Semiconductor Surfaces Diodes made from Schottky barriers (ie, the asymmetric potential formed between the metal and the semiconductor) are widely used in power supply rectifiers and control applications. As used herein, the terms Schottky diode, metal-semiconductor junction diode, diode, and rectifier are all relevant, with left-to-right more specific to more general. are doing. Similarly, the terms Schottky barrier, metal-semiconductor barrier, conductor-semiconductor junction, and multi-material junction are all relevant, with the more specific to the more general from left to right. .. The term Schottky diode would mean a diode with a Schottky barrier.

As mentioned above, we have an interface layer (containing or sometimes composed of oxides, nitrides, nitrides, arsenides, hydroxides, fluorides, or their equivalents). We devised a scheme for controlling or adjusting the height of the Schottky barrier by forming the arsenide between the metal and the semiconductor. This scheme differs from others' attempts to control barrier height, either using silicide as the contact metal or using an esoteric substrate with a wide bandgap. It was necessary. Moreover, in conventional devices, the Fermi level of the semiconductor remains unpinned, independent of the barrier height of the metal used. Eventually, substrate doping was also attempted, but it was not found to really affect the barrier height of the substrate material. For example, PtSi contacts have reduced resistance due to high silicon doping so that the current across the junction is occupied by tunneling the barrier. This can lead to situations where doping is essentially permeable to electrons at the top of the barrier, but doping cannot actually adjust the barrier height.

FIG. 6 shows an embodiment of a diode 600 according to the invention that includes an interface layer 620 disposed between the semiconductor 610 and the conductor 630 and coupled to both. Conductors and semiconductors conduct current so that they are electrically coupled to various voltages associated with the operation of the diode 600 and pass through a passivated semiconductor surface formed at the junction between the semiconductor 610 and the interface layer 620. Works like.

The conductor 630 includes a conductive material such as a metal or an alloy of metals. The terms metal, conductive material, and conductor are all relevant, with the more specific and more general from left to right. In general, these terms refer to electrically highly conductive materials with Fermi levels present in partially filled bands. Unless otherwise specified, conductors include metals (eg, pure metals and alloys), and doped polysilicon (non-porous silicon with randomly oriented crystal structures), doped single crystal silicon, and metal silicates. Includes other conductors. Note that alloys may have a different work function than their constituents and may be designed to have a unique work function by selectively using the ratio of constituent metals.

Metals will provide advantages over conductive semiconductors, including lower resistance, higher carrier mobility that provides superior high frequency performance and switching, favorable power characteristics, and ease of manufacturing control. Often the conductor is a metal. The use of metals can also avoid the need for semiconductor doping, simplifying manufacturing and improving quality control.

The metals considered include pure metals, alloys, refractory metals, metals that do not form silicides, metals that are physically deposited by virtually non-invasive processes such as the condensation of heat-evaporated metal vapors, and There are metals that have a given work function. Non-invasively deposited metals can be used to form metals on thin interfacial layers without compromising the passivate properties of the layers.

A metal having a predetermined work function is a metal having a work function smaller or larger than that of a semiconductor depending on a desired application. In many cases, this semiconductor will be silicon. In this case, we use the work function of semiconductors or silicon to indicate intermediate energy within the semiconductor bandgap. Illustrative metals with a smaller work function than silicon are Group 3A elements, aluminum (Al), indium (In), titanium (Ti), chromium (Cr), tantalum (Ta), cesium (Cs), magnesium ( Includes Mg), Elbium (Er), Itterbium (Yb), Manganese (Mn), Lead (Pb), Silver (Ag), Ittrium (Y), and Zinc (Zn). Illustrative metals with greater work functions than silicon are platinum (Pt), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), copper (Cu), cobalt (Co), and Contains palladium (Pd).

The semiconductor-interfacial layer-conductor configuration shown in FIG. 6 defines the one selected to be called a "passive shotkey barrier". This pacified Schottky barrier is a naturally formed potential barrier for electrons or holes in the fermi energy (electrochemical potential) in the conductor due to the depleted region formed in the semiconductor close to the conductor. is there. This pacified Schottky barrier is a barrier from the standard unpassive Schottky barrier that would naturally form between the semiconductor and the conductor without the interface layer being placed between the semiconductor and the conductor. Height may deviate. That is, the pacified Schottky barrier may have a barrier height that is highly dependent on the bulk properties of the semiconductor and conductor rather than on the surface properties and may be partially dependent on the properties of the interface layer.

In fact, the present inventors have determined that the fluctuation of the barrier height is monotonous and continuous with respect to the change in the thickness of the surface passivation due to the formation of nitrides in the semiconductor substrate. More specifically, experiments by the present inventors have shown that in a regimen where the nitride layer is thick enough to remove MIGS, the temperature of interface layer formation has the strongest effect on barrier height. ing. In other regimens, thickness can be important. Ideally, if all surface states have been removed, the barrier height should be controllable by simply selecting the metal used.

To understand why the thickness of the interface layer is important, a brief reference to FIG. 8 provides a graph of interface-specific contact resistance vs. interface thickness. Since this graph relates to a structure in which the work function of the metal is the same as the electron affinity in the semiconductor, the Fermi level of the metal is aligned with the conduction band of the semiconductor. At higher thicknesses, the interface layer provides greater resistance to current. As the thickness decreases, the tunneling current decreases and the resistance decreases. However, as the interface layer becomes thinner and thinner, there is a point where the resistance increases. This is due to the influence of MIGS, which further lowers the Fermi level of the metal towards the semiconductor midgap, forming a Schottky barrier. We have found that this competition results in optimum thickness as shown in the graph, in which case the resistance is minimal. At this thickness, the effect of MIGS is reduced enough to unpin the metal and lower the Schottky barrier, and the layer is still thin enough to carry large currents across the interfacial layer. .. Approximately 2500Ω-μm²Below, about 1000Ω-μm²Below, about 100Ω-μm²Below, about 50Ω-μm²Below, about 10Ω-μm²Below, or even about 1Ω-μm²The following contact resistances may be achieved:

Therefore, properties that may be adjustable to provide the desired barrier height include the passivation material used (eg, bandgap-based selection), the thickness of the interfacial layer (eg, especially the interfacial layer is passivation). An interface layer that is substantially similar to the degree of penetration of MIGS formed at the metal interface, the method of forming the interface layer (eg, control of parameters such as temperature), if it is a compound layer formed from layers and separation layers. Includes thickness, source and / or metal used as drain, and other properties.

One of the advantages of the ability to adjust the Schottky barrier height by introducing the interface layer 620 is the ability to form a substantially higher barrier height. Greater than achieved with metal silicide, greater than about 2.0 eV, or greater than about 2.5 eV (at least with semiconductors with a bandgap of this magnitude), or silicon with an interfacial layer. A shotky barrier with a barrier height of approximately 1.0 V may be formed using. Such barrier heights suggest that they are capable of withstanding high voltages before rupture occurs. Therefore, a Schottky barrier with such a barrier height may be useful in high voltage Schottky diodes.

Another advantage achieved by using the interface layer 620 is that it provides greater flexibility in choosing the conductor 630. Typically, the metal of choice for application to conventional Schottky diodes is a metal capable of forming silicates using silicon semiconductors. The formation of silicate helps reduce the surface level (obtained from the dungling bond), but not the effect of MIGS. Therefore, the Fermi level on the semiconductor surface is still pinned. Therefore, the use of metals that form silicon compounds when in contact with silicon helps to produce more reproducible devices in the manufacturing environment, but has the disadvantage that such devices have a fixed barrier height. Still bears.

However, according to one embodiment of the present invention, a conductor that cannot (or cannot easily form) silicide using the semiconductor is selected. The interface layer provided in accordance with the present invention does not require metal silicides as it pacifies the semiconductor surface and reduces or also eliminates the effects of MIGS. This may not form metal silicide, but may allow selection of metals with properties such as the desired work function or Fermi level.

For example, in order to make a large barrier diode, for an n-type doped silicon semiconductor, it is substantially equal to the valence band energy of the semiconductor, or within about 0.1 eV to about 0.3 eV of the valence band energy of the semiconductor. A metal having the work function of is selected. Similarly, for p-type doped silicon semiconductors, a metal having a work function substantially equal to the conduction band energy of the semiconductor is selected. For Schottky diodes constructed according to the present invention, the Fermi level of the metal may be somewhere in the semiconductor bandgap when the interface layer is placed in the junction, resulting in various barriers. A diode of height is obtained. The Fermi level of this metal exists in the conduction band or valence band of the semiconductor.

Therefore, the use of interface layer 620 provides a way to adjust, adjust, or control the height of the barrier between the conductor and the semiconductor. Without the interface layer 620, the barrier height would be substantially non-adjustable, non-adjustable, and fixed (as described above).

The role played by the interface layer 620 in adjusting, adjusting, and controlling the height of the barrier between the conductor 630 and the semiconductor 610 may be understood as the depinning of the Fermi level of the semiconductor. That is, the interface layer may reduce the surface states by binding to the semiconductor material and consuming dangling bonds. In addition, the interface layer may reduce the formation of MIGS in the semiconductor by providing a thickness and bandgap that prevents the (metal) electron wavefunction from entering the semiconductor. Rather, the electron wavefunction can penetrate the interfacial layer and form MIGS within the interfacial layer with the energy associated with the state of the interfacial layer material. As required, the density of MIGS and the depth of MIGS penetration into the interface layer are reduced by selecting the interface layer material or multiple materials with a larger bandgap and higher effective mass compared to semiconductors.

Next, according to one embodiment of the invention, the interface layer 620 is incorporated into a device that functions to conduct current through the semiconductor surface and the interface layer during device operation. In such an embodiment, the interfacial layer unpins the Fermi level (so that the barrier height largely depends on the bulk properties of the bonding material) and is monolayered to allow sufficient current transfer. It is desirable to use an interface layer having a thickness of, for example, about 0.1 nm to about 0.3 nm, and also having a wide bandgap (compared to the bandgap of semiconductors). Advantageously, such an interface layer is thin enough to provide low impedance to current, which is desirable for many semiconductor devices (due to the exponential dependence on the barrier thickness of direct tunneling). It may be one, and at the same time provides sufficient semiconductor surface passivation to allow adjustable barrier height. That is, this interface layer uses a substantially thin layer capable of transferring sufficient current across the interface layer to allow adjustable barrier heights of the surface states and MIGS in the semiconductor. Reduce (or remove).

There are several ways in which the barrier height can be adjusted. For example, the adjustment is made by adjusting the degree of pinning of the Fermi level. That is, some embodiments can be a sufficiently thin interface layer so that all the effects of MIGS in Si are not eliminated. In addition, pinning can be varied by combining the thickness of the interface layer and the choice of sea level material. The metal in contact with the interface layer is pinned by MIGS at different levels within different materials. Conversely, or even more, the passivate is left incomplete to allow effective levels of unpassive level. Complete depinning of the Fermi level (ie, removal of all surface levels in Si, including MIGS) is another option. In this case the barrier height could be adjusted simply by selecting a pure metal or alloy with the desired work function. In this case, the barrier height is determined by equation (1), which was an ideal that was not feasible until now. It is noted that the type of adjustment as described herein is the adjustment of the barrier height by changing the structure of the joint during manufacturing, rather than changing the conditions applied externally during the joining process. thing.

Figures 7a-7d show the relationship between Fermi energy, conduction band energy, and valence band energy for various Schottky barriers containing metals that come into contact with (or are in close proximity to) the semiconductor, and show the band gap (E) of the semiconductor._g) Is the conduction band (E)_c) And valence band (E)_v) Exists. In this example, metal Φ_MThe work function of is the electron affinity of the semiconductor χ_SIs selected to be approximately equal to. Figure 7a shows the Ampassive Schottky Barrier 700. In this example, the Fermi level of metal 730 (E)_F) Is pinned in the bandgap of the semiconductor 710. As a result, the vacuum level created by the charged dipole stops at the interface.

In Figure 7b, the interface layer 720b is thick enough to pass the surface dangling bonds on the surface of the semiconductor 710, but not thick enough to eliminate or sufficiently reduce the effects of MIGS. As a result, the band structure is not significantly different from the band structure seen in the figure shown above. Similarly, in Figure 7c, the interface layer 720c is thick enough to eliminate or reduce the effects of MIGS, but if it is not thick enough to pass the semiconductor surface, there is little change in the energy band structure. I can't. However, as shown in Figure 7d, if the interface layer 720d is sufficient to eliminate or reduce the effects of MIGS and passivate the semiconductor surface, then the Fermi level of the metal will be with the conduction band of the semiconductor. It can be seen that they match (ie, the Fermi level of the semiconductor has been unpinned and no longer matches the Fermi level of the metal). The vacuum level is continuous here because there are no charged dipoles at the interface. Therefore, the band structure of devices made in this way is a result of bulk material properties, not surface properties. As an example, the materials in such cases are Al and Si, and the work function Φ for Al._M= Approximately 4.1 eV and electron affinity for Si χ_S= Approximately 4.05 eV.

V. Transistors Containing Passive Semiconductor Surfaces The interface layers described herein may be used with the semiconductor surfaces of channels within field effect transistors. That is, the interface layer may be arranged between the source and the channel, between the channel and the drain, or both of the electric field effect transistors. Such use of the interface layer was made in 2002.<u style="single"></u>A US patent simultaneous application entitled "INSULATED GATED FILD EFFCT TRANSISTOR HAVING SCHOTTKY BARRIERS TO THE CHANNEL" filed by the inventors of the present specification and granted to the assignee of the present invention.<u style="single"></u>It is described in detail in the issue.

Source-drain contact in the channel of an electric field effect transistor is an example of a broader range of metal-interfacial layer-semiconductor contacts that make up the present invention. Traditionally, such contacts are generally silicides-n⁺Composed of a -Si junction, it formed a somewhat "leaky" Schottky diode with the Fermi level of the semiconductor pinned at the midgap. In contrast, the present invention (eg, as shown in Figure 7d) provides contacts in which the Fermi level of the metal is aligned with the conduction band of the semiconductor. In other cases, depending on the type of semiconductor material and conductor used, the Fermi level of the metal is matched with the valence band of the semiconductor.

Both types of junctions (ie, newly pacated Schottky barrier junctions and conventional silicide-semiconductor junctions) allow tunneling current, but the junctions of the present invention are more than the thickness of the conventionally used silicide layer. It can be manufactured using a thinner interface layer. In fact, a girder thickness smaller than the silicide thickness is expected. In conventional silicide-semiconductor junctions, a Schottky barrier containing a depletion region is formed. The tunnel barrier represented by such a depletion layer may be an order of magnitude larger than the dielectric tunnel barrier in the present invention. As the interfacial layer provided by the present invention becomes thinner, higher current flows between the junctions (ie, lowers the junction intrinsic contact resistance).

The other two properties of the dielectric are worthy of mention. The first is the characteristic of the height of the barrier (for electrons) compared to the semiconductor conduction band. If the barrier is made thinner than the silicate barrier, the trade-off can be a higher tunnel barrier (for example, for nitrides compared to about half of the 0.6eV gap for silicates). 2eV). Barrier with lower spacer layer (eg TiO)₂May be used with (has a barrier less than 1 eV). However, when a higher barrier to electrons was used, we determined that it would still be less than 1/100 of the contact to silicon with a resistive silicide barrier.

The second property is the effective amount of electrons in the dielectric. Larger masses of electrons (ie, due to the shorter wavelength of the electrons) will not enter the semiconductor from the metal. The fewer electrons that enter the dielectric, the smaller the effect of MIGS in the dielectric. Therefore, MIGS in the dielectric is reduced with a larger bandgap and a larger effective mass.

In addition, the junctions of the present invention could be used to make contacts to wells with embedded sources or drains, reducing the need for high doping levels (now reaching their solid solution limits). Traditionally, high doping profiles have been required to keep the depleted layer of the junction relatively thin so as to increase the tunneling current and thus reduce the junction resistance. However, increasing the doping profile to provide low resistance junctions is becoming more difficult. The same level of resistance may be reached with the lower doping concentrations used in the present invention. In addition, lower resistances may be reached with lower doping concentrations. If the present invention is used at high doping concentrations, resistance will be further reduced.

Therefore, methods and applications for semiconductor-interfacial layer-metal bonding have been described. Although described with respect to specific embodiments, it should be noted that the techniques described herein may be modified and modified without departing from the broad spirit and scope of the invention. Therefore, the specification and drawings should be regarded as exemplary rather than in a limited sense, and the present invention should be evaluated only in terms of the scope of patent claims.

<figref num="1">It is sectional drawing which shows the surface of the ampassibate silicon containing the silicon atom of the surface which has a dangling bond.</figref><figref num="2">It is a schematic diagram showing various energy levels of metals and semiconductors, and symbols are added to show the work function of metals and the electron affinity of semiconductors.</figref><figref num="3">It is a schematic diagram showing the energy level of a conventional metal-n-type semiconductor junction, and also shows the concept of a depletion region formed in a semiconductor when materials come into contact with each other.</figref><figref num="4">It is a schematic diagram which shows the bending of the band in the conventional metal-n type semiconductor junction.</figref><figref num="5">FIG. 5 is a schematic diagram showing a semiconductor device including a semiconductor material having a surface through which an electric current flows during operation of the semiconductor device and including an interface layer formed on the surface according to an embodiment of the present invention.</figref><figref num="6">It is a schematic diagram which shows the electric junction including the interface layer arranged between a semiconductor and a conductor according to one Embodiment of this invention.</figref><figref num="7">An unpassed shotkey diode, a pacified shotkey diode without MIGS removed, an unpassed shotkey diode with MIGS removed, and a pacitated removed MIGS, respectively, which are embodiments of the present invention. It is a graph which shows the relationship between Fermi energy, conductor energy, and valence band energy about a Schottky diode.</figref><figref num="8">It is a graph which shows the interface layer resistance vs. the interface layer thickness about the electric junction including the interface layer arranged between the semiconductor and the conductor according to one Embodiment of this invention.</figref>