Current mode switching regulator having predetermined conduction period

The present invention relates to a switching regulator, and in particular, switching capable of efficiently operating in a wide range of supply voltages and load currents by using a simplified dual-mode controller having excellent transient response and high accuracy in a steady state. Regarding regulators.

As conventionally known, when a change in load current or input supply voltage is large, in order to react quickly to the change, a step-down switching regulator, that is, a back switching regulator that controls peak current at a constant frequency. Is most often used. An example of such a conventional switching regulator is shown in FIG. 1A. FIG. 1B is a timing diagram showing the operation of the conventional switching regulator shown in FIG. 1A in the non-continuous current mode and the continuous current mode.

As shown in FIG. 1A, a conventional switching regulator has an input voltage source 101 having a first wire connected to a first wire of the switch SW103, a current measuring unit 102, and a second wire of the switch 103. A diode 137 with a connected cathode, an inductor 105 with a first wire connected to the second wire of the switch 103, and a capacitor 106 with a first wire connected to the second wire of the inductor 105. And a pair of resistors 111, 110 connected in series with each other and in parallel with the capacitor 106, a load 112 connected in parallel with the capacitor 106, and function to control the overall operation of the switching regulator. It is equipped with a control unit 200. As shown in FIG. 1A, the second wiring of each of the voltage source 101, the diode 137 (anode), the capacitor 106, the series resistors 110, 111, and the load 112 is grounded.

The control unit 200 first inputs the error amplifier 114 that receives the reference voltage as a non-inverting input, the loop filter 115 that receives the output of the error amplifier 114, and the output from the loop filter 115 and the output of the current measurement unit 102, respectively. And the adder 118 that receives as the second input, the comparator 119 that receives the output of the adder 118 as an input, the clock generator 121, and the latch 123 (SR) that receives both the output of the clock 121 and the output of the comparator 119 as input signals. Flip flop, etc.) Further, as shown in FIG. 1A, the output of the latch 123 functions as a control signal for controlling the opening / closing of the switch 103, and a part of the voltage applied to the load 112 is input to the inverting input of the error amplifier 114 of the control circuit 200. Be fed back. Here, the operation of the switching regulator shown in FIG. 1A is shown.

See again Figure 1A and Figure 1B. During operation, a portion of the voltage applied to the load 112 as a tuned output voltage is determined by the resistors 110, 111, which is applied to the negative terminal or inverting input of the error amplifier 114 via the wiring 109. A set value or reference voltage 113, which is determined based on the desired load voltage, is given to the positive or non-inverting input of the error amplifier 114. The output of the error amplifier indicates the difference between the desired value and the measured value of the output voltage 108. The output of the error amplifier is connected to the loop filter 115, which has the function of performing frequency compensation to ensure that the control loop obtains proper transient response and steady-state accuracy.

The clock 121 has a repetition period T._CLOCKGenerate a pulse with. This pulse is used to set the SR latch 123 via the set input S, which causes the Q output of the SR latch 123 to turn on the switch 103 through the wiring 124. While the switch SW103 is ON, the current flowing through the inductor 105 increases little by little. Inductor current I_LThe increased value of 104 is converted by the switch current measuring unit 102 into a voltage proportional to the value, and the converted voltage is applied to the input 131 of the adding unit 118 via the wiring 117. The output 132 of the adder 118 is the output 116 of the loop filter 115 and the actually increasing inductor current I._LIt shows the voltage difference from 104 and is converted to a logical level by the comparator 119. Then, the output of the comparator 119 is applied to the reset input of the SR latch 123. When the SR latch 123 is reset at input 135 by the output of comparator 119, switch SW103 is turned off. This is the inductor current I_LOccurs when 104 reaches the positive value set by the output of loop filter 115.

When the switch SW103 is turned off, the inductor current I_L104 flows through diode 137 until it reaches 0, but with load current I_LoadIf is small, it remains at 0 until the next clock pulse is generated by clock 121. As shown in Fig. 1B, the switch ON time T_ONImmediately after it expires (T_ON(When = 0) is the inductor current I_L104 decreases to 0 until switch SW103 is turned on again. Load current I_LoadIf 107 is small, the inductor current I_L104 remains 0 until the next clock pulse or cycle. Also, as shown in FIG. 1B, the load current I_LoadIf 107 is large (load current does not reach 0), inductor current I_LThe value of 104 is I at the next clock pulse_VALLEYTo reach. Capacitor 106 has an inductor current I_LSmoothing and averaging 104, load current I_LoadGenerate 107.

Inductor current I_LIf 104 is 0 for a period of time in the period, the mode of operation is referred to as the discontinuous current mode (DCM), while the inductor current I_LIf 104 is greater than 0 over the entire period of the period, the mode of operation is referred to as continuous current mode (CCM).

While the above circuit can operate as a switching regulator, it is not suitable for use in many applications such as, for example, a device powered by a portable battery (such as a mobile phone). As is known, in order to charge and maximize execution time, regulators for those devices must obtain high efficiency under the condition that the load and input voltage change significantly. The conventional technique shown in FIG. 1A above is not suitable because it suffers a great loss due to the forward voltage drop in the diode 137.

Conventional methods to solve this problem have focused on replacing the diode with a low voltage side MOS transistor switch to reduce the ON voltage drop. Moreover, significant changes must be made to the controller to generate a suitable gate drive signal for MOS transistors in this method.

In the continuous current mode, the gate drive signal of the low voltage side switch is usually an inverted signal of the drive signal of the main switch. On the other hand, in the discontinuous current mode, the low voltage side switch must be OFF when the inductor current is reduced to 0 to prevent inverting current and significant power loss. Furthermore, the operations of the low voltage side switch and the main switch must not overlap or must not conduct at the same time. Even for a short time, if both the low voltage side switch and the main switch are turned on at the same time, a large through current will flow from the input voltage VIN to the ground GND. This significantly reduces circuit efficiency and can even damage the switch due to overheating. Conversely, if both the low voltage side switch and the main switch are off at the same time, there will be a "dead time" or a non-conducting period. This causes the inductor current to flow through the body diode of the switch, resulting in power loss due to the large forward voltage drop of the diode.

One way to solve the above problem is to provide an adaptive dead time gate drive controller. This solution is described in detail, for example, in US Pat. No. 6,396,250, "CONTROL METHOD TO REDUCE BODY DIODE CONDUCTION AND REVERSE RECOVERY LOSSES." Briefly, according to the device disclosed in the above patent, for sensing the voltage of the terminal between the high voltage side switch and the low voltage side switch and operating the high voltage side switch or the low voltage side switch. Detect the pulse delay period. A learning circuit is used to avoid through currents to set the time delay to a minimum. In this way, power loss can be reduced by minimizing the non-overlapping time during which the body diode of the synchronous rectifier circuit is in a conductive state. However, in the above-mentioned prior art, it is necessary to add the components associated with the above-mentioned learning circuit, which increases the cost and complicates the design. Therefore, it is used in many applications as a practical solution. It becomes unusable.

As shown in the regulator of FIG. 1A, the above-mentioned conventional method has another disadvantage because the efficiency is further reduced due to the switching loss in the gate drive for the MOS switch. This switching loss is particularly significant at low load currents. This allows a small load current to be easily supplied from the charge stored in the capacitor 106 over a relatively long period of time, for example, by significantly reducing the switching frequency, without causing a noticeable change in the output voltage 108. Even so, switching loss occurs every time the clock changes.

In order to solve this problem, it has been proposed that the controller that controls the switching regulator be operated in a burst manner by dividing it into a "pause time" period in which all power switches and all parts of the controller are turned off. .. According to this method, switching loss with a small load current is minimized. This prior art is described in US Pat. No. 6,304,066, "CONTROL CIRCUIT AND METHOD FOR MAINTAINING HIGH EFFICIENCY OVER BROAD CURRENT RANGES IN A SWITCHING REGULAR CIRCUIT". And US Pat. No. 6,307,356, "VOLTAGE MODE FEEDBACK BURST MODE CIRCUIT) is explained in detail. Needless to say, these methods require many additional parts to be added to the controller of the switching regulator, and one drawback is that the circuit becomes more complicated. Further, since such a switching regulator has a plurality of switching cycles at the time of burst, it cannot be said that the maximum effect is brought about from the viewpoint of efficiency.

The fixed frequency current mode switching regulator shown in Figure 1A has a T_ONFrom T_CLOCKDisadvantages due to inherent stability issues when the duty cycle for switching to exceeds 50% (when the switch is on for longer than 50% of any switching cycle). There is. To adjust the load voltage 108 by controlling the duty ratio of switch SW103, T_ONFrom T_CLOCKWhen the duty ratio for switching to is exceeded 50%, the switch SW103 causes a load voltage and the switching regulator 100 becomes unstable. This phenomenon is of concern because it interferes with the sufficient current supply capacity of the switching regulator achieved at higher duty ratios. To maintain the stability of the current mode switching regulator, a tilt compensation signal may be supplied to tune the signal generated from the current for the controller that controls the switching regulator. However, when the duty ratio is large, tilt compensation in turn causes the load current and power efficiency of the switching regulator to decrease.

U.S. Pat. No. 6,498,466, "CANCELLATION OF SLOPE COMPENSATION EFFECT ON CURRENT LIMIT," provides a control circuit for the current-mode switching voltage regulator as a solution to the above problems. There is. The control circuit for this current mode switching voltage regulator adjusts the switching threshold with respect to the magnitude of the slope compensation signal so that the maximum current limit of the regulator itself is kept substantially constant at a larger duty ratio. The realization of such a control circuit would add a significant amount of electrical parts to the switching regulator, resulting in increased size and cost for the controller and increased design complexity. Is a drawback of this method.

<p> In view of the above, it is a first object of the present invention to provide a simplified switching regulator that solves the problems associated with the conventional methods and designs mentioned above.</p>

<p> According to one embodiment of the present invention, an example of a power supply switching regulator has a common terminal, an input terminal for supplying a DC current input, an output terminal, and a first terminal connected to the common terminal. An inductor having a recirculation diode, a first terminal connected to the second terminal of the recirculation diode, a second terminal connected to the output terminal, and a first terminal connected to the output terminal. And a capacitor having a second terminal connected to the common terminal, and connected between the input terminal and the first terminal of the inductor, the continuity of the direct current input given to the inductor. A switch capable of switching between a state and a non-conducting state in which the DC current input is cut off from the inductor, and a length of time during which the switch is connected to the switch and the switch is in the conducting state. A controller capable of controlling the length of the period during which the switch is in the conducting state and the non-conducting state is provided so as to be inversely proportional to the difference between the voltage of the input terminal and the voltage of the output terminal. ..</p><p> According to the present invention, it is possible to operate until the duty ratio in the ON state reaches 100%, and the ON time T_ONBy utilizing a predetermined value of, there is an advantage that a feasible current mode switching regulator can be provided without using tilt compensation.</p><p> In addition, according to the present invention, in order to improve the adjustment accuracy of the output voltage so as to be higher than the adjustment accuracy by the controller that only controls the proportional error, the output obtained by actually measuring the output voltage value is desired. It has the advantage of being able to provide a controller that integrates the error between voltage values.</p><p> Further, as an advantage of the present invention, the controller according to the present invention operates in the discontinuous inductor current mode "DCM" when the load current value is small, and can obtain excellent light load efficiency, and the load current can be obtained. When the value of is large, the continuous inductor current mode aims to reduce the ripple current value of the inductor and output capacitor (and therefore the ripple voltage of the voltage output) and to obtain excellent efficiency when the load is large. It works with "CCM".</p><p> Further, according to the present invention, by realizing the automatic transition between DCM and CCM and using the current mode control, the change of the load current and the input voltage in the output voltage is hindered, and the function of the load current operating point is also obtained. The change in transient response time can be minimized.</p><p> Further, an advantage of the present invention is that the circuit according to the present invention directly monitors the error signal for continuous time in front of the loop filter without using the sampling clock, whereby the filter slew rate and the clock can be obtained. The delay due to the cycle can be eliminated.</p><p> In addition, the objects, advantages, and novel features of the present invention will become apparent to those skilled in the art as they consider the detailed description that follows. In addition, the object, advantages, and features of the present invention may be understood by carrying out the present invention. The novel features of the invention are set forth below, but in addition to the other objectives and features of the invention, the invention is better understood and evaluated from the following detailed description with drawings, both in structure and content. Will be done.</p>

The accompanying drawings, which are incorporated herein by reference and constitute a portion of this specification, show some aspects and embodiments of the present invention. The attached drawings are for explaining the principle of the present invention together with the above-mentioned outline explanation and the following detailed explanation. These explanations will be given with reference to the drawings attached to the attached sheet. These drawings are used for the purpose of explaining preferred embodiments of the present invention and are not intended to limit the present invention. In all the above drawings, the common components are designated by the same reference numerals.

Hereinafter, the present invention will be described in detail with reference to the drawings. Here, the best form of the invention is shown. However, the present invention may be embodied in many different forms and is not limited to the embodiments shown herein. Rather, these embodiments are described so that this disclosure is complete and the scope of the invention can be communicated to those skilled in the art in detail, with similar components indicated by similar numbers.

FIG. 2 shows an example of the current mode switching regulator according to the present invention. Referring to FIG. 2, in the present embodiment, the switching regulator 1 is a voltage source V having a first wire connected to the first wire of the switch SW3._INIt has 10. V_INIs preferably supplied from a conventional power source such as a battery, and the switch SW3 is preferably a p-channel MOS transistor (PMOS transistor).

As shown in FIG. 2, the switching regulator further includes a diode 50 and a voltage amplifier 53, and the cathode terminal 83 of the diode 50 is connected to the second wiring of the switch SW3 and the inverting terminal 53a of the voltage amplifier 53. , The anode terminal 84 of the diode 50 is grounded and the reference voltage V_DTIt is connected to the non-inverting terminal 53b of the voltage amplifier 53 via 55. In this embodiment, the diode 50 includes an NMOS transistor 52 and its body diode 51. As shown in FIG. 2, the drain terminal of the NMOS transistor 52 is connected to the cathode of the body diode 51 and constitutes the cathode terminal of the diode 50. The source terminal of the NMOS transistor 52 is connected to the anode of the body diode 51 and constitutes the anode terminal of the diode 50. The reference voltage V should be as small as possible and always larger than the maximum value of the input offset voltage of the voltage amplifier 53._DTSelect a value of 55. The output of the voltage amplifier 53 is given to the control circuit 41 and fed back to the gate of the NMOS transistor 52.

Subsequently, the switching regulator 1 is in series with the inductor 5 having the first wire connected to the second wire of the switch SW3, the capacitor 6 having the first wire connected to the second wire of the inductor 5, and each other. It further comprises a pair of resistors 11 and 10 connected to the capacitor 6 and connected in parallel with the capacitor 6 and a load 12 connected in parallel with the capacitor 6. As shown in FIG. 2, the second wirings of the voltage source 10, the diode 50 (for example, the anode), the capacitor 6, the series resistor 10, and the load 12 are each grounded.

Further, the switching regulator includes a controller 41 that controls the operation of the circuit. More specifically, in the present embodiment, the controller 41 is a timer circuit T._ONIt includes 70, comparators 71, 73, 76, a transconductance amplifier 72, a driver 75, a loop filter 15, a logic circuit 74, and a reference voltage 13. A large number of each of the above components may be provided. Depending on the configuration and application of the switching regulator, some of the components may not be required. Further, in the present embodiment, the power of the component included in the controller 41 is V._INSupplied by 10.

Referring to FIG. 2, timer circuit T_ON70 is the signal V_IN, Signal V_LOAD, Signal V_REF, Receives the output signal from the logic circuit 74 as an input. Both the comparator 71 and the amplifier 72 have a signal V._REFAnd the output voltage V determined by resistor 11 and resistor 10_LOADReceives a given part of as input. The logic circuit 74 is a timing circuit T._ONThe outputs of 70, comparator 71, voltage amplifier 53, enable circuit 61A, comparator 73, and comparator 76 are received as inputs. The logic circuit 74 includes a signal 62 for enabling the active diode, a switch ON signal for the driver 75, and a RUN T._ONThe signal 78 is output as an output signal. The function of the logic circuit 74 that generates the recognized output by using these pre-recognized inputs is defined by the logic phase diagram of FIG. Figure 3 also shows the overall operation of regulator 1.

Further, the switching regulator of the present invention includes a current measuring circuit 57 for measuring the current flowing through the diode 50. The current measurement circuit 57 is enabled by the controller 41 via the AND gate 29. The AND gate 29 receives the signals from the logic circuit 74 and the comparator 76 as inputs.

Referring again to FIG. 2, the output of the transconductance amplifier 72 is connected to the input of the loop filter 15. The output of loop filter 15 is connected to the non-inverting inputs of both comparator 73 and comparator 76. The inverting input of the comparator 73 receives the output of the current measurement circuit 58 as an input signal, and the inverting input of the comparator 76 is connected to the offset voltage 27.

Further, the switching regulator of the present invention may include a safety circuit 61A controlled via a regulator enable signal 61. The safety circuit 61A checks, for example, temperature, power, short circuits of outputs, and possible anomalies in the components enclosed by the dotted lines. These components are preferably provided in a single integrated circuit, eg, an ASIC, which is an integrated circuit for a particular application. In the embodiment shown in FIG. 2, the ASIC has I / O pins represented by PIN1, PIN2, PIN3, PIN4, PIN5, PIN6.

Here, the operation of the switching regulator shown in FIG. 2 will be described. As described above, the inductor 5 is connected between the switch SW3 and the load 12. The cathode terminal 83 of the diode 50 is connected to the connection portion between the switch SW3 and the inductor 5. On the other hand, the anode terminal 84 of the diode 50 is grounded to the common ground GND0, and constitutes a normal back switching regulator, that is, a step-down switching regulator 1. The voltage amplifier 53 has an inverting input terminal 53a connected to the cathode terminal 83 of the diode 50 and a reference voltage V in order to significantly reduce the power loss of the diode 50._DTIt has a non-inverting input terminal 53b connected to the negative terminal 55a of 55. Reference voltage V_DTThe positive terminal 55b of 55 is connected to the anode terminal 84 of the diode 50, and the output 53c of the voltage amplifier 53 is connected to the gate terminal 52a of the NMOS transistor 52 and the body diode 51 included in the diode 50. .. As mentioned above, the reference voltage V_DTSet the value of 55 to a value as small as possible and larger than the value of the input offset voltage of the voltage amplifier 53 (usually about 10 mV). As a result, the diode current I in the positive direction, that is, in the forward direction_DWhen 56 flows into diode 50, the voltage amplifier 53 always has a diode forward voltage V._DAdjust the gate voltage of the NMOS transistor 52 so that the size is small and the polarity is positive. Generally, diode forward voltage V_DAlways from 0 to 2 × V_DTTry to be between. Diode current I_DWhen 56 is inverted and becomes a negative current, the diode forward voltage V_DAlso becomes negative, and the output 53c of the voltage amplifier 53 is brought close to the value closest to the negative value, for example, ground, so that the NMOS transistor 52 of the diode 50 and the body diode 51 are in a non-conducting state. As a result, the diode 50 operates with a small forward voltage drop and a small reverse current, and the diode 50 has no control input other than the active voltage of the diode 50 itself between the anode terminal 84 and the cathode terminal 83. As a diode, it works almost ideally.

Therefore, the diode 50 of the present invention is not a synchronous rectifier circuit or a synchronous switch in the usual sense described above, but rather an "active diode". In order to further reduce power consumption, the power of the voltage amplifier 53 may be turned off by the signal line 62 from the controller 41 when not in use. Further, a Schottky diode (not shown) can be provided outside the integrated circuit (enclosed by the dotted line 40 in FIG. 2) in parallel with the body diode 51 to further improve the efficiency of the switching regulator.

The operation of the switch SW3 is controlled by the output signal 60 generated by the driver 75 of the controller 41. The output signal of the driver 75 is given to the control switch SW3 so that the switch is turned on for a predetermined time, whereby the load voltage V_LOADIs adjusted to the desired value. To perform the desired operation of the switching regulator utilizing the output signal 60 of the controller 41, the diode current I_DIn addition to the input signals inside the integrated circuit surrounded by the dotted line 40, such as 56 and the recirculate signal 54, the input voltage V_INAnd ground GND 0, load voltage V_LOAD, Resistor R defined in equation (1)₁11 and resistor R₂Inputs from the outside of the integrated circuit surrounded by the dotted line 40, such as the voltage on the wiring 9 divided by 10 and the regulator enable signal 61, are given to the controller 41.

<maths num="1"><img file="JP2005295795A_D0001.tif" /></maths>

FIG. 3 is a state diagram showing the operation of the switching regulator according to the embodiment of the present invention having the logic circuit 74 of FIG. With reference to FIG. 3 as well as FIG. 2, the switching regulator operates as follows.

The controller 41 controls the switch SW3 so that it is in one of the two states of ON and OFF, and operates the regulator. Load current I_LOADIf 7 is small, the switching regulator will have both switch SW3 and diode 50 turned off, i.e. non-conducting, and inductor current I._LIt operates in a discontinuous inductor current mode (DCM), characterized in that 4 is virtually zero for some time. This state is referred to as the "idle" controller state. For the purposes described below, assume that one cycle of regulator operation in the DCM begins in the idle state when switch SW3 and diode 50 are off. In this state, in the load 12, the voltage of the wiring 9 is the reference voltage V._REFDecrease the voltage of capacitor 6 until it falls below 13, and output V of comparator 71._E77 is set to logic H, which causes controller 41 to be H from idle._ONTransition to the controller state, assert the output 78 from the logic circuit 74, and timer T_ONStart 70 and turn on switch SW3.

Refer to Figure 3, from this "idle" state to "H"_ONIn the transition up to, controller 41 is enabled and the load voltage (part of which is shown on signal line 9) is V._REFIs it below the voltage level of 13 (V)_E77 = H), occurs when the loop filter voltage is higher than the threshold of comparator 76 (signal 63, / DCM = H). Once this happens, the controller tells T_ONThe output of "H" is valid for a specified period of time._ONSwitch SW3 closes.

"H_ONDuring the controller state, timer T_ONInductor current I until_L4 keeps increasing. T_ONWhen is turned off (becomes logic L), switch SW3 is turned off through signal 60. Here, "E_NLOIt is important that the transition to the controller state does not occur until the inductor current begins to return through the diode 50 and the signal 54 becomes logic H. It is this operation of the switching regulator that prevents the through current when the switch SW3 is turned off and the transistor 52 is turned off. Seeing Figure 3, "H_ONFrom the "E" state_NLOThe transition to the state is Run T_ONThe signal is logic H and T at the end of the timer period_ONOccurs when it runs out. In addition, Run T_ON= H enables run timer and Run T_ON= L resets the timer as it did when it timed out. T_ONIs the output signal of the timer, Run T_ONWhen the signal is logic H, it becomes logic H and T_ONOver time or Run T_ONIt remains logic H until the signal becomes logic L.

Controller 41 is "E_NLOInductor current I while in controller state_L4 refluxes the active diode 50 and its magnitude gradually decreases toward 0. Inductor current I_LWhen 4 reaches 0, the output of the amplifier 53 is logic L, so the active diode 50 is turned off. When the gate voltage of the NMOS transistor 52 becomes logic L and the NMOS transistor 52 is turned off, the switching regulator "L" by the signal 54_{OFF OFF}A transition to the controller state occurs. As shown in FIG. 3, when the loop filter voltage is larger than the threshold voltage of the comparator 76 (/ DCM = H), the switching regulator is E._NLOFrom mode to L_{OFF OFF}You can transition to mode, I_COM79 is Logic H. Also, the inductor current is lower than the level instructed by the loop filter, but is a positive current. In addition, the positive value of signal 58 is I_DCorresponds to 56 positive directions.

L_{OFF OFF}In the controller state, the output voltage of the amplifier 53 (referred to as the return signal 54) is already logic L (ie, OFF), so the controller 41 immediately turns the switching regulator into a virtual starting point for the entire DCM duty cycle. Return to "idle" controller state.

When the load increases, V in the "idle" controller state_LOADDecreases rapidly and 0 inductor current for DCM operation I_LThe four periods will be even shorter and will no longer exist. The timer circuit T is the time when the switch SW3 is turned on in a certain cycle._ONT by 70_ONFixed to valley current I_VALLEYThat is, the maximum value of the negative peak inductor current is kept at 0 by the active diode 50 of the sequencer and DCM, and V._LOADWhen is further reduced, the average input voltage to the error transconductance amplifier 72 becomes negative. The output of the loop filter 15 becomes positive and increases. As a result, the output of the comparator 76 becomes the logic H represented by / DCM = H, and the controller operation mode is switched to the continuous current mode (CCM).

In CCM (that is, when / DCM = H), the timer circuit T_ON70 switch ON time T_S__ON(That is, the time SW3 is ON) drops to 90% of its value in DCM. Assume that the switching regulator is in the idle controller state at the start. At this time, if / DCM = H at the start of reflux, Run T_ONChange the signal, timer circuit T_ON70 immediately signal T_ONIs activated and the switching regulator is H_ONThe controller is entered and switch SW3 is turned on. T in DCM_ON90% T for time_ONTimer circuit T in time_ONWhen the signal output of 70 is cut off, switch SW3 is turned off, active diode 50 is enabled, signal 54, which is a reflux logic signal output from amplifier 53, becomes H, and inductor current I._LWith 4 refluxed at the diode 50, the switching regulator "E_NLOIt will be in the controller state. In CCM, diode current I_DCurrent measuring circuit 57 for 56 becomes active and current valley current I_VALLEYRepresents I_DThe value of is output to the inverting terminal of the comparator 73 on the wiring 58. Diode current I_D56 takes a value close to the peak, which is the valley current I set by the output of the loop filter 15._VALLEYOutput current I of comparator 73 because it is higher than the target value of_COMP79 is logic L. But diode current I_DAs 56 drops, I_D56 is gradually valley current I_VALLEYApproaches the target value of. As a result, the output I of the comparator 73_COMP79 changes from logic L to logic H, and the switching regulator is changed to "L"_{OFF OFF}After transitioning to the controller state, the voltage amplifier 53 and the current measurement current 57 are disabled by the signal 62. When the voltage level of the return signal 54 reaches the logic L threshold (that is, when the MIMO 52 is turned off), the switching regulator goes into an "idle" controller state and is immediately considered the starting point of the entire cycle in the CCM. H_ONIt goes into the controller state (because / DCM = H). After that, the switching regulator repeats this cycle.

In CCM, the switching regulator 1 controlled by the controller 41 has a load voltage V._LOADThe valley current I by integrating the deviation of the desired value with the error amplifier 72 and the loop filter 15._VALLEYAdjust the load voltage V_LOADOperates in a typical current mode, which exactly matches the steady-state value of. If the load drops when operating with CCM, the load voltage V_LOADIs on the rise, the output of the loop filter 15 and the valley power I until the comparator 76 switches to logic L and / DCM = L and DCM = H._VALLEYContinues to decline. As a result, control 41 switches to DCM operation. This causes the switching regulator to V to the desired value (or lower)._LOADThe switch SW3 remains off and remains in the "idle" controller state until is reduced. At that point, the output V of the comparator 71_E77 becomes logic H, the DCM control cycle starts again, and the above operation is repeated.

According to the operation of the switching regulator in the embodiment of the present invention described above, the switch ON time T in the DCM_S__ONIs the inductor current I_LPeak current of 4 I_LpeakValley current I against_LvalleyThe value of is the value I_TThe value T for a given time so that_TIs equal to. This value I_TIs the supply voltage V_IN, Load voltage V_LOADIt is preferable that the values are as independent as possible from the operating temperature, the allowable values of the components inside the integrated circuit, and the like. In doing so, the inductor current I of the switch ON time of switch SW3_LValue of 4 I_TThe change in (I_Lpeak-I_Lvalley), Which is expressed by the mathematical formula (1).

<maths num="2"><img file="JP2005295795A_D0002.tif" /></maths>

Therefore, the desired switch ON time T in DCM operation_S__ONThe value T for a given time_TIs rewritten as in the following formula (3).

<maths num="3"><img file="JP2005295795A_D0003.tif" /></maths>

According to equation (3), the value T for a predetermined time in DCM operation._TThat is, the switch ON time T_S__ONThe desired value of is obtained.

FIG. 6 shows the timer circuit T according to the present invention._ONAn example of a circuit that realizes 70 is shown. With reference to FIG. 6, the timer circuit T_ON70 is the signal V_IN1, V_LOAD8, V_REFReceives 13, run timer 78, / DCM63 as input. Note that these signals correspond to the same signals in FIG. Timer circuit T_ON70 is a current mirror composed of transistors 89a and transistor 89b, and V._INThe resistor 90 is connected to the current mirror, and the current source 91 is connected to the transistor 89a of the current mirror. Timer circuit T_ONReference numeral 70 denotes a transistor 89c having a drain terminal connected to the drain of the transistor 89b, a source terminal connected to the ground, and a gate terminal to which a run timer signal 78 which is an input signal is given via an inverter, and a switch 89c. The first capacitor 86a connected in parallel and the second capacitor 86b connected in series with the switch 89e (where the second capacitor 86b and the switch 89e are connected in parallel with the first capacitor). , A second capacitor 86b arranged in series, a switch 89f connected in parallel to the switch 89e, an inverting input connected to the drain of the transistor 89b, and a non-inverting input connected to the gate of the switch 89f to give VREF13. It further includes a capacitor 87 having a and, and an AND gate that receives the output of the capacitor 87 and the run timer signal 78 as inputs. As shown in FIG. 6, the signal 63 (/ DCM) is applied to the gate input of the transistor 89e via the inverter 99. In Fig. 6, the capacitance value of the first capacitor 86a is 9/10 × C._TAnd the capacitance value of the second capacitor 86b is C_T/ 10. Timer circuit T_ONOne of the advantages of the 70 embodiments is that they are less sensitive to the operating environment.

During operation, when the DCM is logic H, the timer circuit T_ON70 switch ON time T_S__ONIs expressed by the formula (4).

<maths num="4"><img file="JP2005295795A_D0004.tif" /></maths>

However, as mentioned above, in CCM (that is, when DCM = L), the capacitor 86b is disconnected and the switch ON time T._S__ONIs reduced to 90% of its value in DCM. Therefore, switch ON time T_S__ONIs expressed by the formula (5).

<maths num="5"><img file="JP2005295795A_D0005.tif" /></maths>

Value I in formulas (3), (4), (5)_TBy solving, the formula (6) is obtained.

<maths num="6"><img file="JP2005295795A_D0006.tif" /></maths>

Therefore, equation (5) is based on the peak current I._LpeakValley current I against_LvalleyValue that indicates the value of I_TIs V_IN1 or V_LOADIndicates that it is independent of 8. By setting formula (7), the user or operator adjusts the value of the external inductor L4 (in the integrated circuit) by formula (8), and the value I_T(That is, I_TIs the desired value of I_T__DESIRED) Can be set. Where L_NOMINALIs the nominal value of L and I_{T NOMINAL}Is i_TIs the nominal value of.

<maths num="7"><img file="JP2005295795A_D0007.tif" /></maths>

<maths num="8"><img file="JP2005295795A_D0008.tif" /></maths>

As described above, for proper operation of controller 41 in FIG. 2, the signal V output from comparator 71_E77 needs to change between logic H and logic L when the input voltages to the comparator 71 and the amplifier 72 are common values. The amplifier 72 causes a polarity change (that is, a change from the source to the sink) in the current flowing from the error amplifier 72 to the loop filter 15. When the comparator 71 and the error amplifier 72 are realized as separate functional blocks, it is inevitable that the input offset voltage values differ between the two functional blocks. Signal V output from comparator 71_E77 controls the operation of the switch SW3 in the DCM, but the signal given from the error amplifier 72 through the loop filter 15 to the comparator 76 controls the transition between the DCM operation and the CCM operation. This causes the V in the transition between the DCM and the CCM due to the difference in the input offset voltage between the comparator 71 and the error amplifier 72._LOADThe adjusted value of is changed. Therefore, this difference in input offset values must be minimized in order to reduce the voltage change as described above. This means that for the error amplifier 72, one drives the loop filter 15 and the other drives the comparator 71 and the output signal V, as shown in FIG._EAchieved by the present invention by providing a single common input stage with two current outputs driving the 77.

FIG. 4 shows a dual amplifier used in the second embodiment of the present invention. See Figure 4, I_OUT1 and I_OUTThe difference in input reference offset voltage between 2 is the current mirror output I from the current mirrors 93a, 93b, 93c._L1, I_L2, I_H1, I_H2The difference in input reference offsets, as determined by, is further enhanced by the transconductance gain of input stage 94. The input stage may be, for example, a differential pair of bipolar transistors having the best offset, or a differential pair of MOS transistors. As a result, when the above error amplifier is used in the embodiment shown in FIG. 2, the output voltage V is when a transition between DCM and CCM occurs._LOADUnfavorable change in load current I_LOADBy suppressing the occurrence as a function of 7, it is possible to improve the performance of the switching regulator while simplifying and reducing the area required for mounting in the integrated circuit.

FIG. 5 shows an example of a circuit diagram of a circuit for minimizing the number of pins in the implementation of the integrated circuit of the present invention. Referring to FIG. 5, the I / O pin connection required between the integrated circuit and the external components in order to realize the function shown in FIG. 2 in the integrated circuit is, for example, an external resistor that can be selected by the user. R₂10, R₁In the case of an adjustable regulator with 11, V in the integrated circuit_LOAD8 and V_ADJMust include at least two pins to supply both of the nines. However, the mean voltage and V at inductor input 25_LOADThe difference is the load current I multiplied by the DC resistance of the inductor 5._LOADEqual to 7. This difference is inherently small for high efficiency regulators. Therefore, the load power I_LOADEven if 7 changes, switch ON time T_S__ONWith only a slight increase in the change in, the mean value of the inductor input voltage is T in Figure 6._ONV in timer circuit_LOADCan be replaced. The mean value of the inductor input voltage that already has pin 98 of I / O or the value processed by the low-pass filter, V of I / O pin 94_LOADReplace the signal, V_LOADI / O pin 94 can be removed, for example, at the cost of an on-chip RC filter with a resistor 95 and a capacitor 97, as shown in FIG.

As mentioned above, the present invention has considerable advantages over conventional devices. One of the advantages of the present invention is that the current mode switching regulator is provided with a function capable of operating the duty ratio of the switch ON up to 100%. This is the switch ON time T without using tilt compensation_ONIt can be realized by using the predetermined value of.

As mentioned above, utilizing the ON time programmed according to the present invention eliminates the need to sense current during the (often) short high potential side switch ON time, and of the switching frequency without the need for a constant frequency clock. Change can be minimized.

Another advantage of the present invention is the integration of the error between the desired and actual values of the output voltage in order to improve the adjustment accuracy of the output voltage to a level that exceeds the accuracy of the controller that only controls the proportional error. It is to provide a controller to be used.

Besides, the controller of the present invention operates in the discontinuous inductor current mode DCM when the load current value is small, whereby excellent light load efficiency can be obtained, and the load current value is large. The advantage is that it can also operate in continuous inductor current mode CCM in order to reduce the ripple current in the inductor and output capacitor (and therefore the ripple voltage in the voltage output) and to obtain excellent efficiency even under heavy loads. have.

In addition, another advantage of the present invention is that automatic transitions between DCM and CCM are realized and current mode control is used to prevent changes in output voltage due to changes in both load current and input voltage. Minimizing changes in transient response time, which is a function of the load current operating point.

Another advantage of the circuit of the present invention is that the error signal is continuously and directly monitored before the loop filter without using the sampling clock to eliminate the delay due to the filter slew rate and the clock cycle.

Also, according to the present invention, automatic mode change between continuous current mode (CCM) and discontinuous mode (DCM) is performed reliably and consistently without the need to change the output voltage or sense the load current. be able to.

It also selectively turns off unused features without putting the entire system into "sleep mode" (usually with increased output voltage ripple and increased transient response delay). Therefore, it is also one of the advantages of the present invention that higher efficiency can be obtained (especially in the DCM mode).

Another advantage of the present invention is that the change in switching period between DCM and CCM is much smaller than that of a conventional regulator that operates in "sleep burst" mode during DCM. ..

Further, as a design advantage according to the present invention, the change in switching frequency in CCM is slightly different from the directly clocked device, V._IN-V_OUTAnd I_LOADIt takes a nominal value that is almost independent of. In other words, in the present invention, the steady-state CCM switching frequency is made substantially constant without using a clock (requiring gradient compensation) even in the presence of changes in supply voltage and load.

Although specific embodiments and examples of the present invention are provided herein for purposes of explanation, as will be appreciated by those skilled in the art, various equivalent modifications are possible within the scope of the present invention. The terms used in the claims of the present invention are not construed as limiting the present invention to the specific embodiments disclosed herein and in the claims. Rather, the scope of the present invention should be determined solely by the claims, and the claims should be construed according to the established principles of interpretation of the claims.

<figref num="1A">It is the schematic which shows the conventional switching regulator.</figref><figref num="1B">It is a timing diagram which shows the operation of the conventional switching regulator shown in FIG. 1A.</figref><figref num="2">It is the schematic which shows the current mode switching regulator which concerns on one Embodiment of this invention.</figref><figref num="3">It is a figure which shows the operation state and the control logic of the current mode switching regulator which concerns on one Embodiment of this invention shown in FIG.</figref><figref num="4">It is a figure which shows an example of the error amplifier used together with this invention.</figref><figref num="5">It is a circuit diagram of the integrated circuit of this invention, and shows the circuit for minimizing the number of pins at the time of mounting.</figref><figref num="6">T according to the present invention_ONIt is a figure which shows an example of a circuit.</figref>