Video/audio data reproducing device

The present invention relates to an apparatus for reproducing image and audio data from a recording medium on which image and audio signal data generated by using high-efficiency coding means are recorded.

The amount of image data is large. Therefore, when the image signal is digitally recorded on the medium, it is efficient to record the image and the audio data in which the data is compressed by the high-efficiency coding means on the medium. The compression is performed by removing redundancy and the like. A reproduction device for such a recording medium is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-165125. The outline of the reproduction apparatus disclosed in the publication will be described below.

The reproduction device includes a means for decoding compressed data of reproduced images and sounds. A disk type recording medium is used.

The data read from the disk is supplied to the decoding means via the buffer means, and is reconstituted here. The decoded image and audio signal are output to the outside. The reading of data from the disk is controlled based on the data occupancy in the buffer means. As a result, the code amount per predetermined time is not constant, and it can be applied to variable rate coded image data that changes in a partial portion.<patcit num="1"><text>Japanese Patent Application Laid-Open No. 6-165125</text></patcit>

<p> However, in conventional video, information equipment, etc., the data structure, storage method, etc. are different for each device. Therefore, it is difficult to handle the same data between different types of devices. At present, multimedia that integrates all media is being promoted, and a system form that can obtain interoperability across recording media, broadcasting, communication, etc. is strongly desired in terms of user's usability.</p><p> Further, high-efficiency coding is effective not only when recording information on the above medium but also when broadcasting or communicating an image signal in a digital manner.</p><p> An object of the present invention is to provide a playback device for a recording medium having interoperability with broadcasting and communication.</p>

<p> The present invention has been made to achieve the above object, and as the first aspect thereof, it is configured to include a header having reproduction clock information indicating the reproduction timing and bit rate information, and is encoded. In the playback device of the recording medium on which the video / audio data is recorded, the data reading means for reading the video / audio data from the recording medium, the memory means for temporarily storing the read playback data, and the above. The memory control means that controls the reading of the reproduction data from the memory means and the header information that analyzes the header contained in the reproduction data read from the memory means and extracts the reproduction clock information and the bit rate information. The analysis means, the reference clock information generating means for generating the reference clock information which is the criterion for determining the timing of reading the video / audio data from the memory means, the reproduction clock information extracted by the header information analysis means, and the reference. The memory control means includes a clock information comparison means for comparing clock information and an interface means for transmitting the reproduction data read from the memory means to the outside of the reproduction apparatus, and the memory control means is based on the clock information comparison means. Provided is a video / audio data reproduction device characterized in that the reading of reproduction data from the memory means is controlled based on the comparison result and the bit rate information extracted by the header information analysis means. To.</p><p> The memory control means starts reading the reproduction data corresponding to the header containing the reproduction clock information from the memory means at the timing indicated by the reproduction clock information, and intermittently reads the reproduction data according to the bit rate information. It is preferable that the data is used.</p><p> It is preferable that the interface means includes a transmission packet generating means for packetizing the reproduced data read from the memory means, and the interface means sends out the reproduced data packetized by the transmission packet generating means.</p><p> The transmission packet generating means preferably makes the video data and the audio data into separate packets.</p><p> It is preferable that the interface means accepts the input of a command input from the outside.</p><p> It is preferable that at least one of the header information analysis means, the reference clock information generation means, and the clock information comparison means includes a microprocessor.</p><p> The transmission packet generation means preferably includes a microprocessor.</p><p> As a second aspect of the present invention, in a playback device of a recording medium on which encoded video / audio data is recorded, a data reading means for reading video / audio data from the recording medium and the data reproducing means are used. A memory means for temporarily storing the read data (hereinafter referred to as "reproduced data"), and an interface means for sending the reproduced data to the outside of the reproduction device and receiving a command input from the outside and a request signal of the reproduced data. Provided is a video / audio data reproduction device comprising a memory control means for controlling reading of reproduction data from the memory means based on a request signal of reproduction data received by the interface.</p><p> The memory control means preferably includes a microprocessor.</p><p> It is preferable that the interface means includes a transmission packet generating means for packetizing the reproduced data, and the interface means transmits the reproduced data packetized by the transmission packet generating means.</p><p> The transmission packet generation means preferably includes a microprocessor.</p><p> A third aspect of the present invention includes a playback device for a recording medium on which encoded video / audio data is recorded, a decoding device having means for decoding the encoded video / audio data, and audio. In a video / audio data playback system configured to include and / or an output device capable of outputting an image, the playback device includes a memory and records the encoded video / audio data as the recording medium. After being read from the data and temporarily stored in the memory, the data is sent to the decoding device at a predetermined timing. The decoder device includes a memory and is sequentially sent from the playback device in an encoded state. The video / audio data is temporarily stored in the memory, decoded, and output as audio and / or images from the output device, and the decoder device further sends an operation command signal to the playback device. Further, the reproduction device is provided with a video / audio data reproduction system characterized in that the reproduction device operates according to an instruction signal sent from the decoder device.</p><p> The first aspect will be described. The data reading means reads video / audio data from the recording medium and stores it in the memory means. The interface means sends out the reproduction data read from the memory means to the outside. If the transmission packet generation means is provided, the interface means transmits the regenerated data packetized by the transmission packet generation means. When the transmission packet generation means separates the video data and the audio data into separate packets, the transmission packet can be matched to a transmission method such as communication.</p><p> The header information analysis means analyzes the header included in the reproduction data read from the memory means, and extracts the reproduction clock information and the bit rate information. On the other hand, the reference clock information generating means generates the reference clock information which is a criterion for determining the timing of reading the video / audio data from the memory means. The clock information comparison means compares the reproduction clock information extracted by the header information analysis means with the reference clock information. The memory control means controls the reading of the reproduced data from the memory means based on the comparison result by the clock information comparison means and the bit rate information extracted by the header information analysis means. That is, the memory control means starts reading the reproduction data corresponding to the header including the reproduction clock information from the memory means at the timing indicated by the reproduction clock information. In this case, the reading is interrupted according to the bit rate information. As a result, the time interval of the reproduced clock information is maintained, and the transmitted bit rate is substantially matched to the reproduced bit rate information.</p><p> The interface means may accept the input of a command input from the outside.</p><p> If the circuit including the microprocessor also serves as a header information analysis means, a reference clock information generation means, a clock information comparison means, and a transmission packet generation means, the device cost can be reduced.</p><p> The operation of the second aspect of the present invention will be described. The data reading / reproducing means reads video / audio data from the recording medium and stores it in the memory means.</p><p> The interface means sends the reproduced data read from the memory means to the outside. If the transmission packet generation means is provided, the interface means transmits the regenerated data packetized by the transmission packet generation means. Further, the interface means receives a command input from the outside and a request signal of the reproduction data.</p><p> The memory control means controls the reading of the reproduction data from the memory means based on the request signal of the reproduction data received by the interface.</p><p> If the circuit including the microprocessor also serves as a transmission packet generation means and a memory control means, the device cost can be reduced.</p><p> A third aspect of the present invention will be described. The playback device reads the encoded video / audio data from the recording medium, temporarily stores the data in the memory, and then sends the encoded video / audio data to the decoding device at a predetermined timing. The decoder device temporarily stores the encoded video / audio data sequentially sent from the playback device in the memory. Then, this is decoded and output as audio and / or an image from the output device.</p><p> Further, the decoder device sends an operation command signal to the reproduction device. The playback device operates according to a command signal sent from the decoder device.</p><p> As described above, the video / audio data playback device of the present invention can transmit the video / audio data as it is encoded. The decoder / display device can decode the playback data of the video / audio data playback device without data overflow or underflow in the same way as decoding the received data transmitted by the broadcast or communication recorder.</p>

<p> As described above, the present invention realizes a system capable of outputting encoded video / audio data from a playback device of a recording medium and obtaining interoperability with a receiver for broadcasting, communication, etc. it can. In addition, the cost of each playback device and system can be reduced.</p>

Hereinafter, description will be made with reference to the drawings attached with examples of the present invention.

First Example The digital video / audio data playback device (video disc player) of this embodiment will be described with reference to FIG. In FIG. 1, the optical disc to be a recording medium is designated by reference numeral 1. Similarly, reference numeral 2 is the rotation drive unit of the optical disk 1, 3 is the pickup, 4 is the tracking control unit of the pickup 3, 5 is the reproduction signal processing circuit, 6 is the memory, 7 is the memory control circuit, and 8 Refers to the transmission packet generation circuit, 9 refers to the pack header analysis circuit, 10 refers to the comparison circuit, 11 refers to the reference clock generation circuit, and 12 refers to the transmission bus interface.

Image data, audio data, and additional data thereof (for example, directory information such as audio data) are integrated and recorded on the optical disk 1. These data are recorded in a state where the code amount is compressed by high-efficiency coding. Further, a recording track is formed on the optical disc 1 in a spiral shape, and the above-mentioned data is recorded according to the recording track.

The rotation drive unit 2 rotates the optical disk 1 so that, for example, the linear velocity is constant.

The pickup 3 irradiates the optical disc 1 with a laser beam and detects the reflected light to read the data recorded on the optical disc 1. At this time, the tracking control unit 4 controls the position of the pickup 3 so that the laser beam is applied to the track on which the desired data is recorded.

The reproduction signal processing circuit 5 includes an error correction circuit, and after performing error correction on the reproduction data read by the pickup 3, sends it to the memory 6. The reproduction data is sent to the memory 6 in response to a data request from the memory control circuit 7. Further, the reproduction signal processing circuit 5 manages the continuity of the reproduction data to be transmitted, and outputs the reproduction track information to be traced to the tracking control unit 4 so that the desired reproduction data can be transmitted.

Memory 6 is a first-in first-out (FIFO) type memory. The memory 6 outputs the stored reproduction data to the transmission packet generation circuit 8 and the pack header analysis circuit 9 according to the instruction from the memory control circuit 7.

By the way, as shown in FIG. 2A, the reproduction data read from the optical disk 1 and stored in the memory 6 is a pack header, a video packet composed of video data, and an audio packet composed of audio data. It is composed of an additional data packet composed of additional data and an additional data packet. The pack header includes header information that integrates reproduction clock information, bit rate information, and the like. Further, one or a plurality of packets of each of these data are collected to form a pack. Note that FIG. 2A shows the reproduced data in chronological order. In FIG. 2A, the data located on the left side is the data read first from the disk 1, and is also read first from the memory 6.

The transmission packet generation circuit 8 converts the reproduced data sent from the memory 6 into a transmission packet, and sends each transmission packet to the transmission bus via the transmission bus interface 12. Figure 2 (b) shows the output of the transmission packet generation circuit 8 together with the read time. Fig. 2 (c) is an enlarged view of the time axis of Fig. 2 (b).

The transmission bus (see FIG. 1) is bidirectional, and not only sends playback data, but also receives various commands (for example, play / stop commands for optical disk 1) sent from the outside, and receives and stops playback commands. It is used to send back status information etc. to these commands.

On the other hand, the pack header analysis circuit 9 analyzes the clock information (reproduction clock information) and bit rate information included in the pack header in the reproduction data input from the memory 6. Then, the analysis result of the reproduction clock information is sent to the comparison circuit 10. Further, the analysis result of the bit rate information is transmitted to the memory control circuit 7. The pack header analysis circuit 9 considers the maximum value of the bit rate as bit rate information for the variable rate encoded reproduction data.

The comparison circuit 10 compares the above-mentioned reproduction clock information with the reference clock information generated by the reference clock generation circuit 11 including the self-propelled transmitter, and outputs the result to the memory control circuit 7. That is, in the initialization operation performed after the power-on (or after returning from another mode to the normal reproduction mode), the comparison circuit 10 uses the reproduction clock information included in the pack header first read at that time. , The preset value of the reference clock information. After that, the value of the preset reference clock information is compared with the reproduction clock information sent sequentially. The comparison circuit 10 outputs the comparison result to the memory control circuit 7.

The memory control circuit 7 controls reading from the memory 6 and the like based on the bit rate information and the comparison result input from the comparison circuit 10. The control is performed so that the average transmission bit rate for each predetermined section (for example, the section T1 to T2 in FIG. 2B) substantially matches the bit rate information on the output of the transmission packet generation circuit 8. It is a thing. For example, consider the case where the time indicated by the reproduction clock information is T1. At this time, if the time indicated by the reference clock information has not yet reached T1, the memory control unit 7 stops reading the playback data from the memory 6. Further, from time T1, reading of the reproduction data for one pack to which the pack header including the reproduction information belongs is started. The reading in this case is performed intermittently according to the bit rate information. As a result, the reproduced data is divided into sizes corresponding to one transmission packet and read from the memory 6 (see FIGS. 2 (b) and 2 (c)).

FIG. 3 shows an example of a digital video / audio data reproduction system including the video disc player of this embodiment.

The system is configured by integrating a video disc player 500, a broadcast receiver 200, a communication receiver 300, a video tape recorder 400, a video camera 600, and a decoder / display device 100.

The decoder / display device 100 includes a pointing device 101, a description card 102, a transmission bus interface 103, a buffer 104, 105, a video decoder 106, an audio decoder 107, a pointing device interface 108, an IC card interface unit 109, a display, and a speaker. It consists of a display unit 110 and a transmission bus terminator 601.

The transmission bus starting from the decoder / display device 100 is connected to the video disc player 500 in a daisy chain via a broadcast receiver 200, a communication receiver 300, and a video tape recorder 400. Furthermore, the video disc player 500 is also connected to the video camera 600. The connection order of these devices 100 to 600 is not limited to this figure.

When the broadcast receiver 200, the communication receiver 300, the video tape recorder 400, the video disc player 500, the video camera 600, and the like receive or reproduce audio and video data, they encode the audio and video data and output the data to the transmission bus.

The transmission bus transmits audio and video data to the decoder / display device 100. The data input through the transmission bus is input to the video decoder 106 and the audio decoder 107 via the transmission bus interface 103 and the buffers 104 and 105. The video decoder 106 and the audio decoder 107 decode the encoded data and display it on the display unit 110 as image data and audio data.

Data such as audio and video may be scrambled for concealment. The decryption card 102 is used to remove this concealment. The decryption card 102 stores information and the like for descrambling. By inserting this into the IC card interface 109, scrambling is released.

The user's command instructed by using the pointing device 101 is transmitted to a predetermined device among the broadcast receiver 200 to the video camera 600 via the pointing device interface 108, the transmission bus interface 103, and the transmission bus. As a result, the user can, for example, instruct the broadcast receiver 200 to receive a specific channel, or instruct the video disc player 500 to perform operations such as play and stop. As a result, it is not necessary to prepare a control device such as a remote controller for each device. In addition, one pointing device 101 can control all devices without manually switching the audio and video output of each device.

In this system, it is not necessary to provide the video decoder 106 and the audio decoder 107 in each device, so that the total cost of the system can be reduced.

In addition, if the video and audio data stored in the optical disk 1 are scrambled, they cannot be displayed without the description card 102. As a result, even if the data stored in the optical disk 1 is illegally copied using the video tape recorder 400, the copied data can be made virtually meaningless.

A second embodiment of the present invention will be described.

Similar to the reproduction device of the first embodiment (FIG. 1), the reproduction device of the second embodiment is also premised on being connected to the transmission bus of the system of FIG.

The configuration of the digital video / audio data playback device of the second embodiment is shown in FIG. The blocks having the same function as that of the first embodiment (FIG. 1) are numbered the same. The part with reference numeral 13 is an additional data extraction / transmission packet generation circuit. Similarly, reference numeral 14 indicates an audio data extraction / transmission packet generation circuit, 15 indicates a video data extraction / transmission packet generation circuit, 16 indicates a pack header analysis / transmission packet generation circuit, and 17 indicates a remultiplexing circuit.

The pickup 3, the reproduction signal processing circuit 5, and the like read the data recorded on the disk 1 according to the instruction from the memory control unit 7. Then, the read data is stored in the memory 6 as reproduction data. Further, the reproduced data is appropriately read according to the instruction from the memory control unit 7, and the pack header analysis / transmission packet generation circuit 16, the additional data extraction / transmission packet generation circuit 13, and the audio data extraction / transmission packet generation circuit 14 , Is sent to the video data extraction / transmission packet generation circuit 15. The instructions issued by the memory control unit 7 to the reproduction signal processing circuit 5 and the memory 6 are the bit rate information input from the pack header analysis / transmission packet generation circuit 16 and the reference clock and reproduction input from the comparison circuit 10. It is determined according to the comparison result with the clock.

Each of the circuits 13 to 16 extracts only data having a specific content (type) from the reproduced data, and generates a transmission packet composed of only the extracted data. For example, the additional data extraction transmission packet generation circuit 13 extracts only the additional data from the data sent from the memory 6. Further, by appropriately collecting the extracted additional data, an additional data transmission packet is generated. Then, this additional data transmission packet is output to the remultiplexing circuit 14.

Similarly, the audio data extraction / transmission packet generation circuit 14 extracts audio data, generates an audio data transmission packet, and outputs the audio data transmission packet to the remultiplexing circuit 14. Further, the video data extraction / transmission packet generation circuit 15 extracts video data to generate a video data transmission packet, and outputs the video data transmission packet to the remultiplexing circuit 14.

The configuration of the reproduced data in this embodiment is the same as that in the first embodiment (see FIG. 2 (a)).

The remultiplexing circuit 14 remultiplexes the additional data, the audio data, the video data, and the pack header information that have been made into transmission packets in units of transmission packets. Then, the signal obtained by the remultiplexing is transmitted via the transmission bus interface 12.

On the other hand, the pack header analysis / transmission packet generation circuit 16 extracts clock information and bit rate information from the pack header, similarly to the pack header analysis circuit 9 (see FIG. 1) shown in the first embodiment. Then, the clock information is sent directly to the comparison circuit 10, and the bit rate information is sent directly to the memory control circuit 7.

In this embodiment, since the transmission packet is generated by extracting each data type (audio data, video data, pack header) separately, the configuration of the generated transmission packet is determined by the transmission format of broadcasting or communication. Can be changed according to. For example, the transmission packet length can be determined, or a transmission packet header can be added to each transmission packet. Therefore, it is possible to output a bit stream (for example, Transport Stream in MPEG) in the same format as the received data of broadcasting or communication. As a result, the decoder / display device 100 obtains the data input through the transmission bus from the origin of the data (for example, the data obtained by reproducing the recording medium, or by receiving a broadcast or the like. It can be decoded into video or audio by the same method and means (decoder 106,107) without distinction by (whether it is the data obtained). Therefore, it helps to simplify the decoder / display device 100.

A third embodiment of the present invention will be described.

The playback device of the third embodiment is characterized in that the data reading operation from the disk is controlled in response to an instruction (request) from the outside.

The configuration of the digital video / audio data playback device of the embodiment is shown in FIG. The code 18 is attached to the reproduction data request detection circuit. The blocks having the same function as that of the first embodiment (FIG. 1) are given the same number.

The data read from the disk 1 is read by the pickup 3, the reproduction signal processing circuit 5, and the like according to the instruction from the memory control circuit 7'. Then, the read data is stored in the memory 6. However, the memory control circuit 7'of this embodiment operates according to a request input from the outside.

The reproduction data read from the memory 6 according to the instruction from the memory control circuit 7'is sent to an external transmission bus via the transmission packet generation circuit 8 and the transmission bus interface 12 as in the first embodiment.

On the other hand, from the transmission bus, a request signal for playback data is sent in addition to general commands.

The data request detection circuit 18 detects the request signal and transmits the request signal to the memory control circuit 7. The memory control circuit 7 causes the memory 6 to read the reproduced data only when the request signal is in the transmission request state.

When the playback device of this embodiment is connected to the transmission bus of the decoder / display device 100 (see FIG. 2), a part of the decoder / display device 100 (video decoder 102, audio decoder 104, etc.) is used. ) Needs to be changed. That is, it is necessary to change a part of the decoding procedure depending on whether the received data of the broadcast receiver 200 or the communication receiver 300 is decoded or the playback data of the video disc player or the like is decoded.

The decoder / display device 100'corresponding to the third embodiment is shown in FIG. A buffer occupancy check circuit 111 is added to the decoder display device 100'as compared to the decoder display device 100 (see FIG. 3). The buffer occupancy check circuit 111 monitors the freeness of the buffers 104 and 105. Then, when there is room to write new data to the buffers 104 and 105, the above-mentioned request signal is transmitted via the transmission bus interface 103.

The reproduction device of the third embodiment does not require the pack header analysis circuit 9, the clock information comparison circuit 12, and the like, and can reduce the cost.

This will be described with reference to a fourth embodiment of the present invention.

In the fourth embodiment, transmission packets are generated, pack headers are analyzed, and the like using a microprocessor. That is, in this embodiment, the microprocessor 20 described later fulfills the functions of the memory control circuit 7, the transmission packet generation circuit 8, the pack header analysis circuit 9, and the comparator 10 in the first embodiment.

The configuration of the playback device of this embodiment is as shown in FIG. The part with reference numeral 19 is the second memory. Similarly, reference numeral 20 refers to the microprocessor and 21 refers to the system interface. The blocks having the same function as that of the first embodiment (FIG. 1) are numbered the same. In the following description, memory 6 will be referred to as "first memory 6" for convenience.

In addition to its own operating clock (for example, 27 MHz), the microprocessor 20 also obtains a reference clock from the reference clock generation circuit 11. Therefore, the microprocessor 20 holds the reference clock information internally. The microprocessor 20 uses the reference clock information and the like to control the reading of the reproduced data from the memory 6 basically in the same manner as in the first embodiment.

The microprocessor 20 outputs the designation of the address to the first memory 6 through the address bus. The first memory 6 reads the data stored at the address and outputs the data to the data bus. The microprocessor 20 stores the data output to the data bus in the second memory 19. In this case, the microprocsa 20 discriminates the video data, the audio data, the additional data, and the pack header contained in the data so that they can be easily distinguished on the second memory 19. .. For example, these are divided according to the type of data (video data, audio data, pack header) and stored in different storage areas.

Further, when the data read from the first memory 6 is a pack header, the microprocessor 20 analyzes the reproduction clock information and the bit rate information contained in the pack header, and the data is obtained from the address obtained as a result. Is read.

When reading each data stored in the second memory 19, the microprocessor 20 converts these data into transmission packets. The microprocessor 20 sends the transmission packet to the transmission bus via the transmission bus interface 12.

The system controller interface 21 detects a command sent via the transmission bus and the transmission bus interface 12 and sends the command to the system controller (not shown) of the playback device. On the contrary, the status information sent from the system controller is sent to the transmission bus via the transmission bus interface 12.

In this embodiment, the microprocessor 20 performs read control of the first memory 6 and transmission packetization of all data. Therefore, the cost can be significantly reduced as compared with the first embodiment (see FIG. 1).

A fifth embodiment of the present invention will be described.

FIG. 8 shows the configuration of the digital video / audio data playback device of this embodiment.

The blocks having the same functions as those of the first embodiment (FIG. 1) and the fourth embodiment (FIG. 7) are numbered the same.

The fifth embodiment is different from the fourth embodiment in that the rotation drive unit 2, the tracking control unit 4, and the reproduction signal processing circuit 5 are connected to the address bus and the data bus of the microprocessor 20. different. Another difference is that it does not have a second memory 19. Here, the first memory 6 is simply referred to as "memory 6".

In this embodiment, the microprocessor 20 directly stores the reproduction data from the reproduction signal processing circuit 5 in the memory 6. In this case, the reproduced data should be able to be restored in chronological order as it is.

After that, the microprocessor 20 reads the reproduction data from the memory 6. The transmission packetization of the reproduced data is performed at the time of this reading. When the read data is a pack header, the microprocessor 20 compares the reference clock information with the reproduction clock information included in the pack header. Then, the reading from the memory 6 is controlled based on the comparison result and the bit rate information.

The microprocessor 20 also monitors the data occupancy rate in the memory 6. Then, if there is room to write data to the memory 6, the microprocessor 20 instructs to read new data. That is, the tracking control unit 4 is instructed to indicate the information (reproduced track information) in which the data to be read by the pickup 3 is written, and the reproduced signal processing circuit 5 writes new data to the memory 6.

The microprocessor 20 is also connected to the rotary drive unit 2. Therefore, the microprocessor 20 also plays a role as a system controller that controls each part based on instructions such as start and stop input via the transmission bus interface 12.

In this embodiment, the memory corresponding to the memory 19 in the fourth embodiment is unnecessary. Further, since the read control of the reproduced data, the transmission packetization, and the control of the system are performed by one microprocessor, the cost can be further reduced as compared with the fourth embodiment (FIG. 7).

In the fourth and fifth embodiments, as in the first embodiment, the reading of the reproduction data from the memory 6 (or the memory 19 is controlled by the comparison result between the reproduction clock information and the reference clock information and the bit rate information. However, as in the third embodiment (FIG. 5), the reading of the reproduced data may be controlled according to a request input from the outside. This is the reproduction data input from the transmission bus. The request can be easily realized by allowing the microprocessor 20 to detect it.

Further, the first to fifth embodiments described above were video disc players using a disc as a recording medium. However, the scope of application of the present invention is not limited to this. It can also be applied to a video tape playback device using a tape medium.

<figref num="1">It is a block diagram which shows the structure of the video / audio data reproduction apparatus which is 1st Example of this invention.</figref><figref num="2">It is a figure which shows an example of the reproduction data transmission method of the video / audio data reproduction apparatus of this invention.</figref><figref num="3">It is a block diagram which shows the example of the reproduction simtem of the video audio data of this invention.</figref><figref num="4">It is a block diagram which shows the structure of the video / audio data reproduction apparatus which is the 2nd Example of this invention.</figref><figref num="5">It is a block diagram which shows the structure of the video / audio data reproduction apparatus which is the 3rd Example of this invention.</figref><figref num="6">It is a block diagram which shows the example of the recorder display apparatus in the reproduction sim tem of the video audio data of this invention.</figref><figref num="7">It is a block diagram which shows the structure of the video / audio data reproduction apparatus which is 4th Embodiment of this invention.</figref><figref num="8">It is a block diagram which shows the structure of the video / audio data reproduction apparatus which is 5th Embodiment of this invention.</figref>

Code description

1 ... disk, 5 ... playback signal processing circuit, 6 ... memory, 7 ... memory control circuit, 8 ... transmission packet generation circuit, 9 ... pack header analysis circuit, 10.. .Comparison circuit, 11 ... Reference clock generation circuit, 12 ... Transmission bus interface circuit, 13 ... Additional data extraction / transmission packet generation circuit, 14 ... Audio data extraction / transmission packet generation circuit, 15. .. Video data extraction / transmission packet generation circuit, 16 ... pack header analysis / transmission packet generation circuit, 18 ... request detection circuit, 19 ... memory, 20 ... microprocessor, 100 ... decoder Display device, 500 ... Video disc player