Magnetic memory cell array and its manufacturing method

The present invention relates to a magnetic memory cell array provided with a plurality of magnetic tunnel junction elements and a method for manufacturing the same.

Conventionally, volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) have been used as general-purpose memories used in information processing devices such as computers and mobile communication devices. All information is lost in these volatile memories unless current is constantly supplied. Therefore, it is necessary to separately provide a non-volatile memory (for example, flash EEPROM) as a means for storing the situation. Since there is a strong demand for high-speed processing of this non-volatile memory, magnetic random access memory (MRAM) has been attracting attention as a non-volatile memory in recent years.

The MRAM has an array structure in which magnetic memory cells provided with magnetoresistive elements are arranged in a matrix. As a magnetoresistive element, a magnetic tunnel junction (MTJ) that can obtain a larger rate of change in resistance junction) elements are suitable. This MTJ element is permanently fixed so that the two ferromagnetic layers separated by the tunnel barrier layer (the magnetization free layer whose magnetization direction changes according to the applied magnetic field and the magnetization direction are parallel along the easy magnetization axis). It has a magnetized fixed layer). Although the magnetization free layer has a magnetization direction that can rotate freely, it is energetically stable because the magnetization directions are aligned along the easy magnetization axis that exhibits magnetocrystalline anisotropy. The tunnel barrier layer is a thin film made of an insulating material, and is thick enough to allow charge carriers (generally electrons) to pass through due to the tunnel effect based on quantum mechanics. Since the probability of charge carriers penetrating depends on the electron spin direction associated with the magnetization directions of the two ferromagnetic layers, if the above magnetization directions change while a voltage is applied, the tunnel current also changes. The magnitude of the tunnel current depends on the ratio of upspin to downspin.

In the MTJ element as described above, it is possible to determine each magnetization direction in the magnetization free layer and the magnetization fixed layer by detecting the change in the tunnel current from a certain reference state. This is because the resistance of the MTJ element differs depending on the angle between the magnetization directions of the two ferromagnetic layers. Specifically, when the magnetization direction of the magnetization free layer is antiparallel to the magnetization direction of the magnetization fixing layer, the tunnel current is the minimum (bonding resistance is the maximum), while the magnetization direction of the free layer is the magnetization fixation layer. When parallel to the magnetization direction of, the tunnel current is maximum (junction resistance is minimum).

MRAMs are generally parallel to each other so that they are orthogonal to a plurality of first leads that are parallel to each other in the first tier and to a plurality of first leads in a second tier that is different from the first tier. It is provided with a plurality of second conductors arranged in a row, and is configured to arrange MTJ elements at their intersections. If the first wire is a word wire, the second wire is a bit wire. Also, if the first lead wire is the lower electrode, the second lead wire is a bit wire (or word wire). The third lead wire may be formed as a word line or a bit line in a third layer located on the opposite side of the first layer based on the second layer. Optionally, another plurality of conductors may be provided below the first layer (opposite the second layer). Further, a device including a transistor, a diode, and the like can be provided below the first layer.

In such an MRAM, during a read operation, a sensing current is passed through a desired MTJ element through a bit line, a word line, or a lower electrode, and information is obtained by detecting the magnetization state (resistance level) of the MTJ element. It can be read. During the writing operation, information is written to a desired MTJ element by supplying a current to the bit line and the word line to generate a current magnetic field and converting the magnetization state.

FIG. 8 shows a conventional MRAM cell array 101 having MTJ elements 7 and two MRAM cells arranged adjacent to each other. In the MRAM cell array 101, the first insulating layer 111 and the two connecting layers 122 are formed on the substrate 121. The upper surface of each connection layer 122 is covered with a lower electrode 123, respectively. The upper surface of the lower electrode 123 forms the same plane as the upper surface of the second insulating layer 112 that fills the gap between the lower electrodes 123. The third insulating layer 113 is formed so as to cover the lower electrode 123 and the second insulating layer 112. However, an MTJ element 124 is provided on a part of each lower electrode 123, and the upper surface thereof is connected to a common first current line 125. Generally, the MRAM cell array has a plurality of lower electrodes 123 and a plurality of first current lines 125, and the MTJ element 124 is arranged at the intersection thereof. Further, the fourth insulating layer 114 is formed so as to cover the upper surface of the first current line 125. A fifth insulating layer 115 and a second current line 126 are formed on the third insulating layer 113. When the first current line 125 is a bit line, the second current line 126 is a word line. The first current line 125 and the second current line 126 are formed so as to be orthogonal to each other. Further, although transistors and diodes are formed inside the substrate 121, they are not shown here.

FIG. 9 shows the structure of the MTJ element 124. The MTJ element 124 is a laminate composed of a plurality of layers. For example, on the lower electrode 123, a bottom seed layer 151 made of a nickel-iron-chromium alloy (NiFeCr) or the like and an antiferromagnetism made of a manganese-platinum alloy (MnPt) or the like are formed. A pinning layer 152, a ferromagnetic pinned layer 153 containing a cobalt iron alloy (CoFe), and aluminum oxide (Al).₂O₃) And the like, a ferromagnetic free layer 155 made of nickel iron alloy (NiFe) and the like, and a cap layer 156 made of a non-magnetic conductor such as tantalum are formed in this order. The upper surface of the cap layer 156 is joined to the first current line 125. Such an MTJ element 124 has a so-called bottom spin valve structure. On the other hand, in the topspin valve structure, the free layer, the tunnel barrier layer, the pinned layer, the antiferromagnetic pinning layer, and the cap layer are laminated in this order on the seed layer.

By the way, the density of the MRAM cell array having the structure shown in FIGS. 8 and 9 is determined by various factors. For example, lithography and patterning processes are one of the constraints when arranging two MTJ elements in close proximity. It also depends on how many MRAM cells can be connected to each bit line. For example, by reducing the resistance value of the bit line, more MRAM cells can be connected to one bit line, resulting in high integration. In the case of the MRAM cell array as shown in FIG. 8, the lower limit of the resistance value of the bit wire is determined by the maximum width and the maximum thickness of the bit wire. These dimensions are set in consideration of the design and manufacturability of the MRAM cell array chip.

Patent Document 1 discloses a method for manufacturing a space-saving MRAM cell array. Here, a side wall spacer is inserted into the opening of the lithography pattern, the width of the opening is reduced by embedding a plug, and the plug is used as an etching mask to make minute particles between adjacent MRAM cells. The insulating layer of various dimensions is formed with high accuracy.<patcit num="1"><text>U.S. Pat. No. 6,689,943</text></patcit>

Patent Document 2 discloses a high-density MRAM cell array having an internally bonded laminate bonded to a via hole. However, it does not correspond to the end part or the metal pad which requires the lower limit of the dimension which is less than the dimensional accuracy which can be formed in the manufacturing process using the current lithography method, for example, less than 0.1 μm.<patcit num="2"><text>U.S. Pat. No. 6,365,419</text></patcit>

Patent Document 3 discloses an MRAM array in which a magnetic memory cell forming region and a peripheral circuit are brought close to each other in order to secure an empty space and improve the integration density. Peripheral circuits in a row in the magnetic memory cell forming region project into a corner of the magnetic memory cell forming region in the adjacent row.<patcit num="3"><text>U.S. Pat. No. 6,545,900</text></patcit>

Patent Document 4 discloses an MRAM array having a three-dimensional structure. An MRAM cell layer having a plurality of MRAM cells, respectively, is formed between a pair of conductive layers provided with a plurality of conductive wires. Conductive wires are formed in the pair of conductive layers sandwiching the MRAM cell layer so as to be parallel or orthogonal to each other. Here, the conductive layer as the upper layer of a certain MRAM cell layer also serves as the conductive layer as the lower layer of the second MRAM cell layer formed on the conductive layer. Therefore, when n MRAM cell layers are provided, n + 1 conductive layers are required.<patcit num="4"><text>U.S. Pat. No. 6,473,328</text></patcit>

<p> However, in recent years, as MRAM has become more highly integrated, the widths of word lines and bit lines have become narrower, and their resistance values tend to increase more and more. Therefore, an MRAM array having a new structure that realizes further reduction in the resistance of the bit line without causing deterioration in the characteristics of the device is desired. In addition, there is a need for a method in which an MRAM array having such a new structure can be manufactured by existing equipment and materials without increasing the cost.</p><p> The present invention has been made in view of such a problem, and an object of the present invention is to provide a more integrated magnetic memory cell array having a current line showing a lower resistance value and a method for manufacturing the same.</p>

<p> The first method for manufacturing a magnetic memory cell array of the present invention includes the following steps (A) to (C). (A) A step of forming a plurality of conductive film patterns patterned in a predetermined shape on a substrate. (B) A step of forming a plurality of magnetic tunnel junction elements so as to be in contact with the upper surfaces of the plurality of conductive film patterns. (C) A first current that is in contact with the upper surface of a plurality of magnetic tunnel junction elements, extends in the first direction so as to be parallel to each other, and has a thick portion and a thin portion that are divided along the first direction. The process of forming multiple lines. The "first direction" referred to here is a predetermined direction included in a plane parallel to the laminated plane. Further, the "thick portion" and the "thin portion" are a portion having a large area and a portion having a small area in a cross section orthogonal to the first direction.</p><p> In the first method for manufacturing a magnetic memory cell array of the present invention, the first current line is in contact with the upper surface of a plurality of magnetic tunnel junction elements, and a portion having a relatively small cross-sectional area (thin portion) and a portion having a relatively large cross-sectional area. Multiple pieces are formed so as to have (thick part). Therefore, compared to the case where the first current line has a uniform cross-sectional area (thickness), it is possible to have a shape that effectively utilizes the space according to the arrangement position of other components such as a magnetic tunnel junction element. It becomes.</p><p> In the first method for manufacturing a magnetic memory cell array of the present invention, for example, the portion of the first current line corresponding to the magnetic tunnel junction element is made a thin portion by increasing the thickness to 0.02 μm or more and 0.3 μm or less, and other than the above. A thick part can be made by forming the part so as to have a thickness larger than that of the thin part within the range of 0.08 μm or more and 1.1 μm or less.</p><p> In the first method for manufacturing a magnetic memory cell array of the present invention, a first diffusion barrier layer or an adhesive layer is formed as an upper layer of a magnetic tunnel junction element, and then copper (Cu) or gold (Au) is used to form the first diffusion barrier layer or an adhesive layer. It is desirable to form a lower metal layer that forms part of the thickness direction of the first current line by laminating a conductive film on the diffusion barrier layer or the adhesion layer. By laminating the second diffusion barrier layer and the upper metal layer in order on the lower metal layer, a thick portion of the first current line can be formed. In this case, the first and second diffusions are formed by forming a laminated structure of a tantalum (Ta) layer and a tantalum nitride alloy (TaN) layer or a laminated structure of a titanium (Ti) layer and a titanium nitride alloy (TiN) layer. It is desirable to form each barrier layer and to form the upper metal layer using the same material as the conductive film in the lower metal layer.</p><p> In the first method for manufacturing a magnetic memory cell array of the present invention, further, a step of forming a fourth insulating layer on the lower metal layer and a region corresponding to a plurality of magnetic tunnel junction elements on the fourth insulating layer. In the process of forming the second current line so as to extend parallel to each other along the second direction orthogonal to the first direction, and to surround the circumference of the second current line in the same layer as the second current line. It is possible to include a step of forming a fifth insulating layer.</p><p> The second method for manufacturing a magnetic memory cell array of the present invention includes the following steps (a) to (j). (a) A plurality of conductive film patterns having a predetermined shape and a second insulating layer surrounding the plurality of conductive film patterns are formed on a connecting layer penetrating the first insulating layer covering the substrate in the thickness direction. Process to do. (b) A plurality of magnetic tunnel junction elements are formed so as to be in contact with the upper surfaces of the plurality of conductive film patterns, and on the conductive film pattern and the second insulating layer so as to form a co-plane with the plurality of magnetic tunnel junction elements. The process of forming the third insulating layer. (c) On the co-plane of the plurality of magnetic tunnel junction elements and the third insulating layer, a lower metal layer extending in the first direction so as to be in contact with the upper surface of the plurality of magnetic tunnel junction elements and parallel to each other is formed. The process of forming multiple pieces. (d) A step of forming a fourth insulating layer on the lower metal layer and then forming an opening penetrating the fourth insulating layer on the lower metal layer in a region other than the region covering the magnetic tunnel junction element. (e) A step of forming a fifth insulating layer so as to cover the fourth insulating layer and the lower metal layer exposed to the opening. (f) A bottom surface made of the upper surface of the fourth insulating layer and a side wall made of the fifth insulating layer are provided so as to extend in the second direction orthogonal to the first direction so as to pass through the region corresponding to the magnetic tunnel junction element. A step of forming a plurality of first groove patterns having. (g) A step of forming a plurality of second groove patterns arranged in a region other than the region corresponding to the magnetic tunnel junction element and having a bottom surface composed of the upper surface of the lower metal layer and side walls composed of the fourth and fifth insulating layers. .. (h) A step of forming a diffusion barrier layer so as to cover at least the first groove pattern and the second groove pattern. (i) A step of forming an upper metal layer on the diffusion barrier layer so as to fill at least the inside of the first groove pattern and the second groove pattern. (j) By flattening the diffusion barrier layer, the upper metal layer and the fifth insulating layer so as to have a coplanarity, the upper metal layer filled in the second groove pattern is added on the lower metal layer. The first current line extending in the first direction and the second current line embedded in the first groove pattern and extending in the second direction.</p><p> In the method for manufacturing the second magnetic memory cell array of the present invention, the upper metal layer filled in the second groove pattern is formed so as to extend the first current line added on the lower metal layer in the first direction. Therefore, the first current line is divided into a region having a relatively large cross-sectional area (thick portion) and a region having a small cross-sectional area (thin portion) along the first direction. Therefore, compared to the case where the first current line has a uniform cross-sectional area (thickness), it is possible to have a shape that effectively utilizes the space according to the arrangement position of other components such as a magnetic tunnel junction element. It becomes.</p><p> In the method for manufacturing the second magnetic memory cell array of the present invention, it is desirable to form the lower metal layer so as to have a thickness of 0.02 μm or more and 0.3 μm or less and a dimension of 0.3 μm or more and 1.2 μm or less in the second direction. .. It is also desirable to form a second groove pattern at the same position as the opening. The thickness of the fourth insulating layer should be, for example, 0.01 μm or more and 0.3 μm or less.</p><p> In the second method for manufacturing a magnetic memory cell array of the present invention, a photoresist pattern is formed on the fifth insulating layer, and then the fifth insulating layer is selectively etched until it reaches the upper surface of the fourth insulating layer. It is preferable to form the first groove pattern and selectively etch the fifth insulating layer until it reaches the upper surface of the lower metal layer to form the second groove pattern. The fifth insulating layer is formed so as to have a thickness of, for example, 0.05 μm or more and 0.5 μm or less by using a material having an etching rate different from that of the constituent materials of the fourth insulating layer. Specifically, aluminum oxide (Al₂O₃) Is used to form the fourth insulating layer, silicon oxide is used to form the fifth insulating layer, and the fifth insulating layer is selectively etched by a plasma etching method using a fluorine-containing gas. In this case, the first groove pattern is formed so that the dimension in the first direction is 0.2 μm or more and 0.8 μm or less, and the second groove pattern is formed so that the dimension in the first direction is 0.5 μm or more and 1.5 μm or less. It is desirable to form as such. Further, the distance between the first groove pattern and the second groove pattern in the first direction may be 0.1 μm or more and 0.2 μm or less.</p><p> The first magnetic memory cell array of the present invention has a plurality of conductive film patterns of a predetermined shape formed on a substrate, and a thin portion and a thick portion divided along the first direction, respectively, and are parallel to each other. At each intersection of the plurality of first current lines extending in the first direction and the conductive film pattern and the first current line, they are arranged so as to be sandwiched between the conductive film pattern and the first current line. It is provided with a plurality of magnetic tunnel junction elements.</p><p> In the first magnetic memory cell array of the present invention, the first current line is in contact with the upper surface of a plurality of magnetic tunnel junction elements and has a thin portion having a relatively small cross-sectional area and a thick portion having a relatively large cross-sectional area. Multiple are formed. Therefore, the first current line has a shape that effectively utilizes the space according to the arrangement position of other components such as the magnetic tunnel junction element, as compared with the case where the first current line has a uniform cross-sectional area (thickness).</p><p> The second magnetic memory cell array of the present invention includes a plurality of conductive conductive patterns having a predetermined shape, which are provided on a substrate via a first insulating layer and whose circumference is surrounded by a second insulating layer, and their own. A plurality of magnetic tunnel junction elements, each of which is surrounded by a third insulating layer and is provided on a plurality of conductive film patterns so as to form a co-plane with the third insulating layer, and a plurality of magnetic tunnels. A dielectric that is formed so as to fill the space between a plurality of lower metal layers extending in the first direction so as to be in contact with the upper surface of the bonding element and parallel to each other and to form a co-plane with the lower metal layer. A second current that is placed over the layer and the dielectric and lower metal layers in the region corresponding to the magnetic tunnel junction element via a fourth insulating layer and extends parallel to each other in the second direction orthogonal to the first direction. A wire, a fifth insulating layer formed so as to surround the circumference of the second current line in the same layer as the second current line, and an additional conductive layer constituting the first current line together with a lower metal layer are provided. It is the one that was made. Here, the additional conductive layer is formed by sequentially laminating a second diffusion barrier layer and an upper metal layer on a lower metal layer in a region other than the region corresponding to the plurality of magnetic tunnel junction elements, and a second current. It is designed to form a coplanarity with the wire and the fifth insulating layer.</p><p> In the second magnetic memory cell array of the present invention, the first current line has a relatively large cross-sectional area (thick portion) by including the additional conductive layer in a region other than the region corresponding to the magnetic tunnel junction element. Therefore, as compared with the case where the cross-sectional area (thickness) is uniform, the first current line has a shape that effectively utilizes the space according to the arrangement position of other components such as the magnetic tunnel junction element.</p>

<p> According to the method for manufacturing the first and second magnetic memory cell arrays of the present invention, a first current line divided into a thin portion having a small cross-sectional area and a thick portion having a large cross-sectional area is formed along the first direction. Therefore, as compared with the case where the cross-sectional area (thickness) is uniform, the shape can effectively utilize the space according to the arrangement position of other components such as the magnetic tunnel junction element. Therefore, a highly integrated magnetic memory cell array can be easily obtained by providing a first current line showing a sufficiently reduced resistance value in the first direction.</p><p> According to the first magnetic memory cell array of the present invention, the first current line is in contact with the upper surface of a plurality of magnetic tunnel junction elements and has a thin portion having a relatively small cross-sectional area and a thick portion having a relatively large cross-sectional area. Therefore, as compared with the case where the cross-sectional area (thickness) is uniform, the shape can effectively utilize the space according to the arrangement position of other components such as the magnetic tunnel junction element. Therefore, the resistance value can be sufficiently reduced in the first direction, and high integration can be achieved.</p><p> According to the second magnetic memory cell array of the present invention, by providing the additional conductive layer, the first current line has a relatively large cross-sectional area (thickness) in a region other than the region corresponding to the magnetic tunnel junction element. Therefore, compared to the case of having a uniform cross-sectional area (thickness), the shape effectively utilizes the space according to the arrangement position of other components such as the magnetic tunnel junction element, and the resistance is sufficient in the first direction. The value can be reduced. As a result, high integration can be achieved.</p>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, the configuration of the magnetic memory cell array according to the embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is an enlarged view of a part of the planar configuration of the magnetic memory cell array (hereinafter referred to as MRAM array) 1 of the present embodiment. Fig. 2 shows the cross-sectional structure in the direction of the arrow along the II-II cutting line shown in Fig. 1.

The MRAM array 1 of the present embodiment has a plurality of bit lines 2 and a plurality of word lines 3 extending so as to be orthogonal to each other so as to form a matrix as a whole, and a plurality of word lines 3 arranged at each intersection thereof. It is equipped with an MTJ element 24. Each MTJ element 24 is arranged so as to be sandwiched between the bit line 2 and the word line 3 in the thickness direction at each intersection. MTJ cells 1 are arranged in the X-axis direction (first direction) to form a plurality of rows, and are arranged in the Y-axis direction (second direction) so as to be orthogonal to these to form a plurality of columns. There is. Note that FIG. 1 shows four MTJ elements 24 and two bit lines 2 and two word lines 3. Further, FIG. 2 shows two MTJ elements 24 and two word lines 3 and only one bit line 2.

As shown in FIG. 2, the MRAM array 1 is divided along the X-axis direction from the lower electrode 23 as a plurality of conductive film patterns having a predetermined shape (for example, a rectangular shape) formed on the substrate 21. A plurality of bit lines (first current lines) 2 having a first region R1 and a second region R2 having a thickness larger than that of the first region R1 and extending in the X-axis direction so as to be parallel to each other. At each intersection of the lower electrode 23 and the bit wire 2, a plurality of MTJ elements 24 arranged so as to be sandwiched between them in the thickness direction (Z-axis direction) are provided. In addition, the MRAM array 1 has a word line 3.

The lower electrode 23 is provided on the conductive connecting layer 22 that penetrates the first insulating layer 11 that covers the substrate 21. Further, the lower electrode 23 is surrounded by the second insulating layer 12 and forms a coplanar surface with the second insulating layer 12. The lower electrode 23 has a dimension W23 larger than the dimension W3 in the X-axis direction of the word line 3 (for example, 0.2 μm or more and 0.8 μm or less), and the dimension L2 in the Y-axis direction of the bit wire 2 (for example, 0.3 μm or more and 1.2 μm). It has a larger dimension L23 than (below). The substrate 21 is made of silicon (Si) or other semiconductor, and includes other devices such as transistors and diodes. The connecting layer 22 is made of tungsten (W), aluminum (Al) or copper (Cu), and the lower electrode 23 is made of tungsten (W), aluminum (Al) or copper (Cu), as well as tantalum (Ta) and ruthenium. It is formed by (Ru) and the like. The lower electrode 23 is arranged at a position corresponding to the connection layer 22 and is electrically connected. The first insulating layer 11 and the second insulating layer 12 are made of a low dielectric constant material such as silicon oxide.

The MTJ element 24 is provided as an upper layer of the lower electrode 23 and the second insulating layer 12 so that its surroundings are surrounded by the third insulating layer 13 and form a coplanarity with the third insulating layer 13. .. The third insulating layer 13 is made of a low dielectric constant material such as silicon oxide. The MTJ element 24 is electrically connected to the lower electrode 23, and is a laminate in which, for example, a seed layer, a pinning layer, a pinned layer, a dielectric layer, a free layer, and a cap layer are formed in this order from the bottom.

The bit wire 2 is composed of a lower metal layer 25 and an additional conductive layer 28. Here, the portion composed of only the lower metal layer 25 is the first region R1, and the portion where the additional conductive layer 28 is formed in addition to the lower metal layer 25 is the second region R2. The lower metal layer 25 is in contact with the upper surface of the MTJ element 24 and extends in the X-axis direction so as to be parallel to each other, and has a thickness of, for example, 0.02 μm or more and 0.3 μm or less. The dimension in the Y-axis direction of the additional conductive layer 28 and the lower metal layer 25, that is, the dimension L2 in the Y-axis direction of the bit wire 2, is, for example, 0.3 μm or more and 1.2 μm or less. The lower metal layer 25 is formed by laminating a diffusion barrier layer or an adhesive layer and a conductive film made of copper (Cu) or gold (Au) (neither shown) in this order from the side of the MTJ element 24. Further, a dielectric layer (not shown) forming a coplanarity with the lower metal layer 25 is formed between the lower metal layers 25. The diffusion barrier layer is, for example, a laminated structure "Ta / TaN" of a tantalum (Ta) layer and a tantalum nitride alloy (TaN) layer or a laminated structure "Ti /" of a titanium (Ti) layer and a titanium nitride alloy (TiN) layer. It consists of "TiN". Further, in the additional conductive layer 28, the diffusion barrier layer 26B and the upper metal layer 27B are sequentially laminated on the lower metal layer 25 in a region other than the region corresponding to each MTJ element 24 (that is, the second region R2). It is a thing. The dimension of the additional conductive layer 28 in the X-axis direction is, for example, 0.5 μm or more and 1.5 μm or less. Further, the total thickness of the lower metal layer 25 and the additional conductive layer 28, that is, the thickness of the second region R2 is, for example, the thickness of the first region R1 consisting of only the lower metal layer 25 in the range of 0.08 μm or more and 1.1 μm or less. Is configured to be larger than.

The word line 3 is arranged on the dielectric layer and the lower metal layer 25 in the region corresponding to the MTJ element 24 (that is, the first region R1) via the fourth insulating layer 14 and extends parallel to each other in the Y-axis direction. are doing. A fifth insulating layer 15 is formed on the same layer as the word line 3 so as to surround the word line 3. The word wire 3 and the fifth insulating layer 15 form a coplanarity together with the additional conductive layer 28 of the bit wire 2. The dimension of the word line 3 in the X-axis direction is, for example, 0.2 μm or more and 0.8 μm or less. The distance between the additional conductive layer 28 and the word line 3 in the X-axis direction is, for example, 0.1 μm or more and 0.2 μm or less.

The fourth insulating layer 14 has a thickness of, for example, 0.01 μm or more and 0.3 μm or less. On the other hand, the fifth insulating layer 15 is made of a material having a thickness of, for example, 0.05 μm or more and 0.5 μm or less and exhibiting an etching rate different from that of the constituent material of the fourth insulating layer 14. For example, aluminum oxide (Al₂O₃) Consists of the fourth insulating layer 14, and silicon oxide constitutes the fifth insulating layer 15.

In the MRAM array 1 having such a configuration, the bit wire 2 has a large cross-sectional area in the second region R2, so that the resistance value is reduced to about 60% of the conventional one. By reducing the resistance value of the bit wire 2, each bit wire 2 can be configured to be connected to more MTJ elements 24, so that high density and high integration can be achieved. ..

Subsequently, a method for manufacturing the MRAM array 1 according to the present embodiment will be described with reference to FIGS. 3 to 7. In the method for manufacturing the MRAM array 1 of the present embodiment, a plurality of MTJ elements 24 are arranged in the X-axis direction to form a plurality of rows and a plurality of columns are arranged in the Y-axis direction in a horizontal cross section. As a result, a matrix is formed as a whole.

First, the first insulating layer 11 is formed on the substrate 21 by a CVD (chemical vapor deposition) method, a PECVD (plasma enhanced CVD) method, a spin-on method, or the like. Next, a plurality of connecting layers 22 connected to the substrate 21 are formed by using the damascene method so as to form a coplanar surface with the upper surface of the first insulating layer 11. The connecting layer 22 is formed of tungsten (W), aluminum (Al), copper (Cu), or the like. After that, for example, a rectangular lower electrode 23 is formed so as to correspond to each connection layer 22, and a second insulating layer 12 is further formed so as to surround the periphery of each lower electrode 23. At this time, by flattening the lower electrode 23, a coplanarity is formed together with the second insulating layer 12. The lower electrode 23 is formed by using tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), ruthenium (Ru), or the like.

Next, the MTJ element 24 is formed so as to be in contact with the upper surface of the lower electrode 23. Here, a seed layer, a pinning layer, a pinned layer, a dielectric barrier layer, a free layer, and a cap layer are laminated on the lower electrode 23 in a predetermined order to form a multilayer film. It is selectively covered with a photoresist mask pattern (not shown) and the multilayer film in the unprotected region is removed by etching to form the MTJ element 24 as a laminate.

Then, after removing the photoresist mask pattern on the MTJ element 24 by plasma etching or a wet stripper, the third insulating layer 35 covers at least the entire MTJ element 24, the lower electrode 23, and the second insulating layer 12. It is formed so as to be thicker than the thickness of the MTJ element 24. The third insulating layer 13 is formed of, for example, silicon oxide, aluminum oxide, or a low dielectric constant material. The third insulating layer 13 formed in this way is flattened by, for example, CMP (chemical mechanical polish) until the thickness becomes equal to the thickness of the MTJ element 24, whereby the MTJ element 24 and the third insulating layer 13 are combined. Form a coplanarity.

Subsequently, on the coplanar surface of the MTJ element 24 and the third insulating layer 13, a plurality of lower metal layers 25 extending in the X-axis direction so as to be in contact with the upper surfaces of the plurality of MTJ elements 24 and to be parallel to each other are formed. .. Specifically, first, a dielectric layer (not shown) is formed on the coplanar surface of the third insulating layer 13 and the MTJ element 24 by using the CVD method or the PECVD method. Subsequently, a groove pattern (not shown) is formed in the dielectric layer by using a general patterning technique and an etching technique. A diffusion barrier layer or an adhesive layer is formed so as to cover the bottom surface and the side surface of the groove pattern, and then the conductive film is continuously filled with copper or gold, for example, to form a lower metal layer 25 having a thickness of, for example, 20 nm or more and 300 nm or less. To form. The lower metal layer 25 formed in this way is in contact with the upper surface of each MTJ element 24 arranged in a row in the X-axis direction and is arranged in parallel with each other, and is separated from each other by a dielectric layer. The lower metal layer 25 constitutes a part of the bit wire 2. Here, the diffusion barrier layer is formed by forming a laminated structure of a tantalum (Ta) layer and a tantalum nitride alloy (TaN) layer or a laminated structure of a titanium (Ti) layer and a titanium nitride alloy (TiN) layer. To.

Next, after forming the fourth insulating layer 14 over the entire surface on the lower metal layer 25, the fourth insulating layer 14 penetrates over the lower metal layer 25 in a region other than the region corresponding to the MTJ element 24. To form an opening 40. Specifically, a fourth insulating layer 14 is formed on the lower metal layer 25 by a CVD method, a PECVD method, or a spin-on method so as to have a thickness of, for example, 0.01 μm or more and 0.3 μm or less. Here, it is desirable to flatten the lower metal layer 25 in advance before forming the fourth insulating layer 14. This is because the fourth insulating layer 14 formed on the fourth insulating layer 14 is inevitably substantially flat. After forming the fourth insulating layer 14, a photoresist layer is formed over the entire surface by a spin coating method, and the photoresist layer is patterned to obtain a photoresist pattern 39 having an opening 39K having a predetermined shape. This opening 39K is formed in an intermediate region between the MTJ elements 24, which will later become the second region R2. After forming the opening 39K, the fourth insulating layer 14 in the region corresponding to the opening 39K is removed by a conventionally well-known plasma etching process. As a result, the opening 40 is formed. At this time, it is desirable to adopt a soft etching condition in order to avoid damage to the lower metal layer 25. Further, in order to improve the degree of freedom in the patterning process, an anti-reflective coating (ARC) may be formed on the fourth insulating layer 14 before forming the photoresist layer. Further, by forming a hard mask or a cap layer on the fourth insulating layer 14 before coating the photoresist layer, the etching selectivity can be improved.

After forming the opening 40, the photoresist pattern 39 is removed by plasma etching or a wet stripper. When ARC is formed on the fourth insulating layer 14, it can be removed by the same process. After that, the fifth insulating layer 15 is formed so as to cover the fourth insulating layer 14 and the lower metal layer 25 in the region exposed to the opening 40. Here, the fifth insulating layer 15 is formed so as to have a thickness of 0.05 μm or more and 0.5 μm or less by a CVD method, a PECVD method, or a spin-on method. Further, by forming the fifth insulating layer 15 using a material different from the constituent materials of the fourth insulating layer 14, sufficient etching selectivity is ensured. For example, aluminum oxide (Al₂O₃) Is used to form the fourth insulating layer 14, while the fifth insulating layer 15 is formed of silicon oxide. When the fourth insulating layer 14 is formed of silicon nitride, silicon oxide or silicon carbide, the fifth insulating layer 15 is formed of silicon oxide or aluminum oxide. The upper surface 15B of the fifth insulating layer 15 in the portion corresponding to the opening 40 is lower in height than the upper surface 15A of the fifth insulating layer 15 formed on the fourth insulating layer 14.

Subsequently, as shown in FIG. 6, the photoresist pattern 42 is formed on the fifth insulating layer 15, and then extends in the Y-axis direction so as to pass through the region corresponding to the MTJ element 24, and the fourth A first groove pattern 43 having a bottom surface composed of the upper surface of the insulating layer 14 is formed, and is arranged in a region corresponding to the opening 40, that is, an intermediate region between MTJ elements 24 adjacent to each other, and is arranged on the upper surface of the lower metal layer 25. A second groove pattern 44 having a bottom surface composed of a bottom surface and side walls composed of fourth and fifth insulating layers 14, 15 is formed. Here, a plurality of first groove patterns 43 and a plurality of second groove patterns 44 are formed. Before coating the photoresist pattern 42, an ARC or a cap layer (neither of which is shown) may be formed on the fifth insulating layer 15.

Specifically, the photoresist pattern 42 is used as an etching mask, the fifth insulating layer 15 in the region corresponding to the opening 42K1 is removed, and the first groove pattern 43 is dug down until it reaches the upper surface of the fourth insulating layer 14. To form. At the same time, the fifth insulating layer 15 in the region corresponding to the opening 42K2 is removed and dug down until it reaches the lower metal layer 25 to form the second groove pattern 44. At this time, since the fifth insulating layer 15 has sufficient etching selectivity, the etching stops when the lower metal layer 25 and the fourth insulating layer 14 are reached. The etching conditions vary depending on the etching apparatus and the constituent materials of the fourth insulating layer 14 and the fifth insulating layer 15. In the present embodiment, the constituent material of the fourth insulating layer 14 is Al.₂O₃The constituent material of the fifth insulating layer 15 is silicon oxide, and the first and second groove patterns 43 and 44 are formed by plasma etching using a fluorine-containing gas.

The photoresist pattern 42 is then removed by plasma etching or a wet stripper. Even if ARC or the like made of an organic material is present, it is removed at the same time as the photoresist pattern 42. However, if an inorganic ARC or cap layer is formed on the fifth insulating layer 15 before coating the photoresist pattern 42, a second etching step for removing the inorganic ARC or cap layer is performed. Is required. At this point, it is advisable to clean the etching residue deposited on the first and second groove patterns 43 and 44.

After that, as shown in FIG. 7, a diffusion barrier layer 26 is formed over the entire surface so as to cover the bottom surface and the side wall of the first groove pattern 43 and the second groove pattern 44, respectively, and further, the diffusion barrier layer 26 is formed. The upper metal layer 27 is formed on the top so as to completely fill the inside of at least the first groove pattern 43 and the second groove pattern 44. Here, the diffusion barrier layer 26 is formed as a laminate of tantalum (Ta) and tantalum nitride (TaN) or a laminate of titanium (Ti) and titanium nitride (TiN) so as to have a thickness of 2 nm or more and 25 nm or less. To do. The upper metal layer 27 is formed of gold or copper as a constituent material by an electroplating method, a physical vapor deposition method (PVD), or the like. The upper metal layer 27 is formed so as to completely fill the first groove pattern 43 and the second groove pattern 44. At this time, the upper surface 27S is often not flat and the height is uneven.

Finally, as shown in FIG. 2, flattening treatment is performed so that the diffusion barrier layer 26, the upper metal layer 27, and the fifth insulating layer 15 have a coplanarity. As a result, the second portion 27B of the upper metal layer 27 and the second portion 26B of the diffusion barrier layer 26 filled in the second groove pattern 44 are added as the additional conductive layer 28 on the lower metal layer 25, and the lower metal layer Together with 25, it becomes bit line 2 extending in the X-axis direction. Further, the first portion 27A of the upper metal layer 27 and the first portion 26A of the diffusion barrier layer 26 filled in the first groove pattern 43 form a word line 3 extending in the Y-axis direction. In the present embodiment, for example, as the first CMP step, the upper metal layer 27 is flattened until it reaches the diffusion barrier layer 26, and as the second CMP step, the diffusion barrier layer 26 on the fifth insulating layer 15 is performed. Is removed, and the upper metal layer 27 is buffed as a third CMP step. As a result, the first portion 27A of the upper metal layer 27 and the first portion 26A of the diffusion barrier layer 26 are filled in the first groove pattern 43 to form the word line 3. The second portion 27B of the upper metal layer 27 and the second portion 26B of the diffusion barrier layer 26 that fill the second groove pattern 44, together with the lower metal layer 25 located below them, are relatively thick in bit line 2. The second region R2 is configured. The second region R2 of the bit line 2 has a thickness of, for example, 0.08 μm or more and 1.1 μm or less. The region of the lower metal layer 25 other than the region corresponding to the second groove pattern 44 constitutes the first region R1 having a relatively small thickness in the bit wire 2, for example, having a thickness of 0.02 μm or more and 0.3 μm or less. Become. The second region R2 is arranged in a region where the MTJ element 24 does not exist. As a result, the plurality of bit lines 2 extending in parallel with each other have a first region R1 and a second region R2 that are divided along the X-axis direction, respectively. As described above, the production of the MRAM array 1 of the present embodiment is completed.

As described above, according to the MRAM array 1 of the present embodiment, the bit wire 2 has a thickness (cross-sectional area) due to the inclusion of the additional conductive layer 28 in the second region R2 other than the region corresponding to the MTJ element 24. Since it has a relatively large part of, the shape that effectively utilizes the space according to the arrangement position of other components such as MTJ element 24 and word line 3 compared to the case where it has a uniform thickness (cross-sectional area). Therefore, the resistance value can be sufficiently reduced in the X-axis direction. As a result, further high integration can be achieved.

Although the present invention has been described above with reference to embodiments, the present invention is not limited to the above embodiments and can be modified in various ways. That is, as can be understood by those skilled in the art, the above-described embodiment is a specific example of the present invention, and the present invention is not limited to the above-mentioned contents. Modifications and changes to the manufacturing method, structure, dimensions, etc. are made in accordance with preferred embodiments as long as they are consistent with the present invention. For example, in the present embodiment, the thickness of the first current line in the second region is made larger than that in the first region, but the present invention is not limited to this. By increasing the width (dimension in the second direction) of the first current line in the second region, the cross-sectional area thereof may be increased. Alternatively, both the thickness and the width of the first current line may be increased.

<figref num="1">It is the schematic which showed the planar structure in the MRAM array as one Embodiment of this invention in an enlarged manner.</figref><figref num="2">It is the schematic which shows the laminated cross-sectional structure in the MRAM array shown in FIG.</figref><figref num="3">It is sectional drawing which shows one step in the manufacturing method of the MRAM array shown in FIG.</figref><figref num="4">It is sectional drawing which shows one step following FIG.</figref><figref num="5">It is sectional drawing which shows one step following FIG.</figref><figref num="6">It is sectional drawing which shows one step following FIG.</figref><figref num="7">It is sectional drawing which shows one step following FIG.</figref><figref num="8">It is the schematic which shows the laminated cross-sectional structure in the conventional MRAM array.</figref><figref num="9">It is the schematic which shows the laminated cross-sectional structure of the MTJ element in the MRAM array shown in FIG.</figref>

Code description

1 ... Magnetic memory cell array, 2 ... Bit wire, 3 ... Word wire, 11 ~ 15 ... 1st ~ 5th insulating layer, 21 ... Base, 22 ... Connection layer, 23 ... lower electrode (conductive pattern), 24 ... magnetic tunnel junction element (MTJ element), 25 ... lower metal layer, 26 ... diffusion barrier layer, 27 ... upper metal layer, 28. .. Additional conductive layer, 40 ... opening, 43 ... 1st groove pattern, 44 ... 2nd groove pattern.