Electric insulation structure for forming electric insulation layer to be used for circuit board

The present invention relates to an electrically insulating structure for forming an electrically insulating layer that can be used as a circuit board, particularly an electrically insulating structure suitable for use in a multilayer circuit board, a chip carrier, or the like. More specifically, the present invention relates to structures that allow the circuit density of such products with an electrically insulating layer to be increased.

A printed circuit board (hereinafter, may be simply referred to as a PCB), a laminated chip carrier, or the like can form a plurality of circuits in a minimum volume or space. They generally have various layers of signal planes, ground planes, or power supply planes (lines) separated from each other by an insulating material layer. The lines are often electrically connected to each other with plated holes that penetrate the electrically insulating layer. The plating holes are "vias" when they are arranged inside, "blind vias" when they extend from the outer surface to the inside of the substrate by a predetermined depth, and "blind vias" when they extend substantially over the entire thickness of the substrate. Often referred to as "plated through holes" (PTH). When the term "through hole" is used herein, it is meant to include all three types of such substrate openings.

Known steps for manufacturing PCBs, chip carriers, etc. generally involve the manufacture of separate intermediate layer circuits (circuit layers), which apply a photosensitive layer or film over the copper layer of the copper clad intermediate layer base material. Form by doing. The photosensitive coating is exposed and developed, and the exposed copper is etched to form a conductor line. After etching, the photosensitive film is stripped from the copper, leaving a circuit pattern on the surface of the interlayer base material. This process is also called a photolithographic process in PCB technology and does not seem to need further explanation.

After forming separate intermediate layer circuits, for example, a glass (generally glass fiber) cloth is impregnated with an insulating material such as an epoxy resin, and the epoxy resin or the like is subjected to a B stage (semi-cured state) prepreg to each other. By preparing layups of electrically separated intermediate layers, ground planes, power supply surfaces, etc., a multi-layered laminate is formed. The upper and lower outer layers of the laminate usually have a copper clad layer, a glass-filled layer, and an epoxy flat substrate, and the copper clad layer includes an outer surface of the laminate. The laminated body is laminated, and the resin in the B stage is sufficiently cured by using heat and pressure to form an integrated structure.

The laminate thus formed generally has a metal (generally copper) clad layer on both outer surfaces thereof. The external circuit layer is formed in the copper clad layer by using the same procedure as that used for forming the intermediate layer circuit. The photosensitive film is formed on a copper clad layer. The coating film is exposed to a predetermined pattern of excitation light and developed. Next, the copper exposed by the development of the photosensitive film is removed by using an etching solution. Finally, the remaining photosensitive film is removed to provide an external circuit layer.

Conductive through-holes (or interconnects) are used to electrically connect separate circuit layers within the structure to each other and to the outer surface, generally penetrating all or part of the laminate. Through-holes are generally formed by drilling holes through the laminate at appropriate locations before forming the circuit on the outer surface. After several pretreatment steps, it is contacted with a plating catalyst to catalyze the walls of the pores and is generally metallized by contact with an electroless or electrolytic copper plating solution to form a conductive path between the circuit layers. To do. After forming the conductive through holes, an external circuit or outer layer is formed using the above procedure.

After constructing the multi-layer laminate as described above, a chip or other electrical component is generally used at an appropriate location on the external circuit layer of the multi-layer laminate using a solder mounting pad for connecting components to the PCB. To implement. Electrical components are often in electrical contact with circuits within the structure that penetrate the desired conductive through holes.

The solder mounting pad is generally formed by applying an organic solder mask on the external circuit layer. The solder mask can be formed by screen-coating the surface of the external circuit layer with a liquid solder mask coating material using a screen having an opening that regulates the area where the solder mounting pad is formed. It is also possible to apply a solder mounting mask capable of forming an optical pattern on the substrate, expose and develop it to generate an array of openings that regulate the pads. Next, solder is applied to the openings using a known process such as wave soldering.

As described herein, the complexity of the products obtained has increased significantly over the last few years. For example, a PCB for a mainframe computer can have more than 36 layers of circuitry, and the finished laminate is as thick as about 0.250 inches (250 mils). These substrates are typically designed with 3 or 5 mil wide signal lines and 12 mil diameter through holes. In response to increasing circuit densities in many of today's products such as PCBs and chip carriers, the industry wants to reduce signal line widths to less than 2 mils and through-hole diameters to less than 2 mils. Well-known commercial procedures, especially those described above, do not economically form the dimensions desired by the industry.

The industry also wants to avoid manufacturing problems often associated with PCBs, chip carriers, etc. As mentioned above, the current procedure uses intermediate layers (electrically insulating structures) of glass tempered resin or other suitable dielectric material layers, which are about thick with metal (generally copper) on both sides. It has a clad layer of 2-5 mils.

Glass tempered materials, which generally use continuous fiberglass strands, are used to spread across the width and length of the final substrate used to provide strength and rigidity to the final laminate. .. Since these strands are continuous, they extend over the width (or length) of the structure and do not include fractures or other segments as part of it.

Also, these fiberglass strands occupy a relatively large portion of the total board volume, and let's manufacture high density through-holes and very thin line circuits, especially to meet new design requirements. It becomes disadvantageous when. In particular, when drilling holes (using a laser or mechanical drill) to form through holes, fiberglass fibers can extend into the holes, which must be removed prior to metallization. Removing the glass fiber extending into the pores requires additional pretreatment steps such as using a glass etchant. Failure to remove the glass can result in discontinuities in the metal deposits. In addition, continuous fiberglass adds weight and thickness to the overall structure.

Further, since the laminating process is generally performed at a temperature higher than 150 ° C., the resin portion of the laminate shrinks during cooling by the amount allowed by the hard copper clad layer, and such shrinkage is a continuation of the glass fiber used. It does not occur with stranded wire or other continuous reinforcing materials. Therefore, the stranded wire occupies most of the volume of the substrate that follows such shrinkage, further increasing the manufacturing complexity of high density products. When the copper is etched to form a discontinuous pattern, the shrinkage of the laminate may not be suppressed beyond that due to the copper clad layer. Obviously, this problem gets worse as the shape (line width, thickness, and hole diameter) gets smaller. As a result, further contraction may occur. In part, the shrinkage is probably due to the presence of continuous fiber strands in a relatively large volume ratio within the separate layers used to form the final product with such many layers. It adversely affects the dimensional stability and alignment between the layers and adds more problems to the PCB.

Moreover, the presence of glass fibers, especially glass fiber fabrics, substantially impairs the ability to use lasers to form high quality, very small through holes. Glass cloth differs greatly in absorbency and heat resistance from other thermosetting or thermoplastic matrix resins. In a typical glass fabric, the glass density that the laser hits can vary from nearly 0% of the window area to about 50% (or more) in volume of the area on the fiber knuckle. This wide variation in collision class density becomes a problem in obtaining an accurate laser output for each hole, and the quality variation of holes also becomes large.

In addition, the presence of glass fiber causes an electrically defective mode known as CAF. CAF (cathode / youkyoku filament growth) is a defective electrical short circuit, with two shapes in which dendritic metal filaments grow along the interface (generally the glass fiber / epoxy resin interface) and should remain electrically insulated. It occurs when an electrical path is formed between them. Whether continuous (like woven fabrics) or semi-continuous (like shredded fiber mats), the length of fiberglass is sufficient compared to the common distance between insulated internal shapes. Largely, glass fiber is a major inhibitor of the reliability of PCB insulation resistance. Glass mats made of random, discontinuous shredded fibers can largely reduce the quality problems of laser-drilled holes, but such mats are also significantly longer than the spacing of the internal substrate shape. Since it contains fibers, the use of glass fibers containing mats is not a solution to the CAF problem.

An example of improvement in the manufacture of products such as PCBs is described in Patent Document 1. According to Patent Document 1, the manufacturing process comprises the continuous formation of layers using a photosensitive dielectric coating and a selective metal deposition procedure. The first layer of the substrate may be formed on a temporary or fixed carrier, which carrier may be integrated with the substrate. If the carrier is a circuit, the process involves the formation of an insulating coating on the circuit with openings patterned to regulate through holes. The pattern-formed opening can be obtained by exposing the photosensitive insulating coating film with excitation light through a mask having a predetermined pattern, developing the coating film, and forming the pattern of the opening. Further, the pattern formation may be laser removal, in which case the insulating material need not be photosensitive. The metal is deposited in the recesses of the insulating coating to form conductive through holes. Then, another electrical insulating layer is applied on the first electrical insulating layer, the circuit line is patterned, and the recess is plated with metal. Further, after forming the pattern of the first insulating coating film, the second insulating coating film may be applied, the pattern may be formed, the concave portion may be plated with metal, and the through hole and the circuit line may be formed at the same time. In both steps, the patterned opening or recess wall of the insulating coating contains a metal that deposits during plating to give a deposit of the desired cross-sectional shape. The plating is preferably filled in all the recesses in the patterned photosensitive coating. This process is obviously very complex and costly, but it is repeated continuously to form a continuous layer of circuits and through holes.

Another example of a PCB with a given insulating material composition is described in Patent Document 2, where the fibrous material of the electrically insulating layer is with a small amount of particles so that the woven member containing the particles completely surrounds it. Consists of a woven member with a sufficient amount of resin material, allowing the resin material to extend beyond the maximum protrusion of the woven member (ie, the fibrous material is thicker and is known in the given test standard ('595). Pass the HAST Level A exam). Therefore, woven fabrics are known to contain a certain amount of particles, and the term "particles" in this Patent Document 2 includes dry films, extra couplers, broken filaments, and debris on the gloss surface. The process applies the sizing agents polyvinyl alcohol, cornstarch and lubricant to the stranded fibers of the fibers prior to weaving in order to improve the weaving process and minimize stranded wire breakage. After weaving, the calcining step removes the sizing agent and cleans the lubricant and filaments of other materials. However, some sizing agents remain randomly as particles. The woven fabric containing the particles is surrounded by a certain amount of cured resin material. The resin may be an epoxy resin such as that often used in "FR4" composites ("FR4" is an existing abbreviation for the resulting substrate and the resins that make up part of it. Partially based on the flame retardant standards of these established products (hence the "FR" designation). Resin materials based on bismaleimide triazine (BT) are also acceptable for the construction of this patent. More preferably, the resin is a phenolic curable resin material known in the PCB industry. Therefore, the invention of Patent Document 2 requires a continuous fiber extending over the entire width (or length) of the electrically insulating layer, and accidentally drills through holes required in the final product. It can cause damage, and these fibers become what are called "fragments." Therefore, the patented process and the resulting structure can cause the aforementioned problems of fiber stranded wires exposed in the holes.

Patent Document 3 describes a PCB product in which the insulating substrate can contain a thermoplastic resin or a thermosetting resin. The thermosetting polymer materials referred to in Patent Document 3 include epoxies, phenolic base materials, polyimides and polyamides. Examples of some phenolic materials include copolymers of phenol, resorcinol and cresol. Examples of some suitable thermoplastic polymer materials are polyolefins such as polypropylene, polysulphon, polycarbonate, nitrile rubber, ABS polymers, and fluoropolymers such as polytetrafluoroethylene, chlorotrifluoroethylene polymers, fluoroethylene propylene. Includes polymers, polyvinylidene fluoride and polyhexafluoropropylene.

The insulating material may be a molding member of a polymer containing a filler such as a glass-filled polymer or a reinforcing agent. The "FR4" epoxy composition used in this patent includes 70 to 90 parts of bisphenol A brominated polyglycidyl ether and 10 to 30 parts of tetrakis (hydroxyphenyl) ethane tetraglycidyl ether cured with 3 to 4 parts of dicyandiamide. , And 0.2-0.4 parts of the tertiary amine (all are parts by weight with respect to 100 parts of the solid resin). Another "FR4" epoxy composition is about 25-30 parts by weight of tetrabrominated disilsidyl ether of bisphenol A with an epoxy equivalent weight of about 350-450, and about 600-750 parts of bisphenol A tetrabrominated zircidyl with an epoxy equivalent weight. Approximately 10-15% by weight of ether and at least 55-65 parts by weight of at least one epoxidized nonlinear novolak with at least 6 epoxy end groups can be included with a suitable polymerizing or curing agent. Yet another "FR4" epoxy composition includes 70-90 parts of bisphenol A brominated polyzircidyl ether and 10-30 parts of tetrakis (hydroxyphenyl) ethane tetrazircidyl ether cured with 0.8-1 phr of 2-methylimidazole. Is included. Yet another "FR4" epoxy composition uses tetrabromobisphenol A as the polymerization agent with dimethylimidazole as the catalyst.

In Patent Document 4, PCB is first formed by impregnating non-woven aramid shredded fiber mat or thermoplastic liquid crystal polymer (LCP) paper instead of the reinforcing material generally used in the electronic industry described as glass fiber woven fabric. To do. The aramid reinforcement consists of a random (in-plane) oriented mat of p-aramid poly (p-phenylene terephthalamide) fibers made of Kevlar (Kevlar is a registered trademark of EIDu Pont de Nemours and Company), standard E- It has a dielectric constant of 4.0 compared to 6.1 for glass cloth. The low dielectric constant of the non-woven aramid reinforcement provides faster signal propagation, enables higher wiring densities and lower crosstalk, and is more important for high I / O chips and miniaturization.

Since p-aramid fibers are transversely isotropic and have an axial CTE of about 3 to 6 ppm / ° C below the glass transition temperature, the final description in Patent Document 4 when combined with a thermosetting resin Composition is said to have a CTE that can be controlled or adjusted to match silicon or semiconductor chips in the range of about 3-10 ppm / ° C. Thermoplastic liquid crystal polymer paper is a material called Vecrus (Vecrus is a registered trademark of Hoechst Celanese Corp.). The LCP paper uses the company's Vectra polymer (Vectra is also a registered trademark of Hoechst Celanese Corp.).

According to Patent Document 4, the dielectric constant is 3.25 and the dissipation coefficient is 0.024 to 60 Hz. Polymer paper is UL94-V0 standard and has an in-plane CTE of less than 10ppm / ° C. The alleged advantages of this material on aramid mats are its low dielectric constant and very low hygroscopicity of less than 0.02%. Non-woven aramid or LCP paper is used with thermosetting resins to form a substrate of final composition. Examples of thermosetting resins described as useful in Patent Document 4 include epoxies, cyanate esters, bismaleimide, bismaleimide triazine, maleimide or combinations thereof. Next, the resin impregnated with the low CTE reinforcing material is partially polymerized up to the "B" stage to form a prepreg, and the prepreg is cut, laminated, and laminated to form a subcomposite with a copper sheet on the outside. To do.

Yet another type of insulating material known to be used in circuit boards includes what is known as "foamed PTFE" material, which refers to PTFE as well as polytetrafluoroethylene. A more common example of such a material is the aforementioned Teflon sold by EIDuPont de Nemours and Company.

Patent Document 5 describes an adhesive sheet (or "bonding film") material suitable to function as an adhesive layer in various adhesive applications such as circuit board lamination, multi-chip modules, and other electrical applications. It has been described.

It is described that the adhesive sheet is composed of foamed polytetrafluoroethylene (PTFE) material such as that disclosed in Patent Document 6. Preferably, the material is filled with an inorganic filler and is constructed as follows. The ceramic filler is included in the dispersed aqueous solution of the dispersed PTFE. The small particulate filler is typically less than 40 μm in size, preferably less than 15 μm. The fillers are introduced quantitatively prior to co-coagulation, providing 10-60% by weight, preferably 40-50% by weight of fillers in PTFE in the final resin impregnated composite. The packed PTFE dispersion is then usually rapidly agitated and coagulated. Next, coagulation-filled PTFE is attached. Next, the filling material is smoothed with a common paste extrusion lubricant such as mineral spirit or glycol and the paste is extruded. The extruded material is generally calendared and then rapidly stretched 1.2 to 5000 times, preferably 2 to 100 times in this patent, with a stretching rate of> 10% per second and a temperature of 35 to 327 ° C. The lubricant can also be removed from the extrude prior to stretching, if desired. The resulting porous foam-filled PTFE is then moistened with an adhesive by immersing it in a varnish solution containing about 2 to 70% of the adhesive in a solvent, calendaring, or doctor blade treatment. The moistened composite is then attached to the upholstery frame and stage B at approximately 165 ° C for 1-3 minutes. The sheet-like adhesive thus obtained was (a) PTFE 9 to 65% by weight, (b) particulate inorganic filler 9 to 60% by weight, and (c) an adhesive moistened in the porous structure of the filled PTFE web. It consists of 5-60% by weight.

Other types of foamed PTFE substrate materials are described in the above-mentioned Patent Document 6, and also Patent Documents 7 to 9. Patent Document 9 substantially explores both nodes and fibers used as part of such substrate materials and dimensionally constrains them such as node height, width, length, and fiber length. It is especially interesting because it is disassembled into.

Yet another example of a method of manufacturing a circuit board such as a PCB is described and illustrated in the following document. These documents include US Pat. No. 3,962,653 (Bassett), US Pat. No. 4,579,772 (Bat, et al.), US Pat. No. 4,642,160 (Berges), US Pat. No. 4,675,789 (Kwabara, et al.), US Pat. No. 4,713,137. (Sexton), U.S. Patent No. 4,783,345 (Krieberg, et al.), U.S. Patent No. 4,864,722 (Lazarini, et al.), U.S. Patent No. 5,129,142 (Bindra, et al.), U.S. Patent No. 5,229,550 (Bindra, et al.), U.S. Japanese Patent No. 5,368,921 (Ishii, etc.), US Patent No. 5,376,453 (Vongenzo, etc.), US Patent No. 5,483,101 (Shimoto, etc.), US Patent No. 5,565,267 (Kapot, etc.), US Patent No. 5,648,171 (Kapotto, etc.) Von Genzo, et al.), U.S. Patent No. 5,670,262 (Dalman), U.S. Patent No. 5,677,045 (Nagai, et al.), U.S. Patent No. 5,685,070 (Alpo, et al.), U.S. Patent No. 5,726,863 (Nakayama, et al.), U.S. Patent No. 5,814,405 (Blanca, etc.), US Patent No. 5,981,880 (Apel, etc.), US Patent No. 6,018,196 (Nodin), US Patent No. 6,042,685 (Sinada, etc.), US Patent No. 6,119,338 (Wang, etc.), US Patent No. 6,143,401 (Fitcher, et al.), US Patent No. 6,212,769 (Boyco, et al.), US Patent No. 6,248,959 (Sylvester), US Patent No. 6,291,779 (Le Vert, et al.), US Patent No. 6,378,201 (Tsukada, etc.) (Other), US Patent No. 6,405,431 (Park, etc.), US Patent No. 6,506,979 (Shellnut, etc.), US Patent No. 6,541,589 (Bailey, etc.), US Patent No. 6,586,687 (Lee, etc.), US Patent Application No. 2002-150673 (Tone, et al.), US Patent Application No. 2002-170827 (Furuya), US Patent Application No. 2002-172019 (Suzuki, et al.), US Patent Application No. 2002-190378 (Shoo, et al.) ), US Patent Application No. 2003-22013 (Jap, et al.), Japanese Patent Application Laid-Open No. 56-49271 (Nishikawa, et al.), Japanese Patent Application No. 70-86710 (Nagai, et al.), Japanese Patent Application Laid-Open No. 70- 97466 (Azuma, et al.), Japanese Patent Application Laid-Open No. 80-92394 (Yonekura, et al.), Japanese Patent Application Laid-Open No. 2001-15912A2 (Koji), Japanese Patent Application Laid-Open No. 2002-223070 (Koji, et al.).<patcit num="1"><text>U.S. Pat. No. 5,246,817</text></patcit><patcit num="2"><text>U.S. Pat. No. 6,207,595</text></patcit><patcit num="3"><text>U.S. Pat. No. 5,418,689</text></patcit><patcit num="4"><text>U.S. Pat. No. 6,323,436</text></patcit><patcit num="5"><text>U.S. Pat. No. 5,652,055</text></patcit><patcit num="6"><text>U.S. Pat. No. 3,953,566</text></patcit><patcit num="7"><text>U.S. Pat. No. 4,187,390</text></patcit><patcit num="8"><text>U.S. Pat. No. 4,482,516</text></patcit><patcit num="9"><text>U.S. Pat. No. 4,187,390</text></patcit>

<p> A primary object of the present invention is to expand circuit board technology.</p><p> Another purpose is to provide a new and unique electrically insulating structure, which is used to form an electrically insulating layer of a circuit board, which is an existing manufacturing procedure. Can be manufactured using.</p><p> According to an embodiment of the present invention, an electrically insulating structure suitable for use in PCBs, chip carriers, and similar electronic packaging products is provided, and the electrically insulating structure is made of a cured resin material and a cured resin. Having a particulate filler in the material, the electrical insulating structure forms a substantial solid layer for use in PCBs, chip carriers or similar electronic packaging products as an electrical insulating layer, the electrical insulating layer being continuous. Do not contain similar fibers, semi-continuous fibers or the like as part thereof.</p><p> The present invention provides significant improvements in electrically insulating structures such as those formed in electrically insulating layers used in the production of circuit boards such as PCBs. One of the particularly important features of the present invention is to provide an insulating material containing a resin and predetermined particles, but not as part of which is continuous or semi-continuous glass fiber or the like. As mentioned above, fibers of such continuous length have traditionally been used in many substrates to withstand the treatment of the layers described below (especially the intense pressurization and temperature of the laminate) into the final multilayer structure. It was thought necessary to provide sufficient strength for the electrically insulating layer obtained from an insulating material. Removing the continuous or substantially continuous and long strands of these materials with the use of particles facilitates the formation of pores, increases the chances of reducing wire width and thickness, and of substrate density. Satisfy design requirements for growth.</p><p> Such inventions are expected to show significant technological developments.</p>

<p> In order to solve the above problems, first, the means adopted by the invention according to claim 1 is "an electrically insulating structure suitable for use in a PCB, a chip carrier and a similar electronic package product, and is cured. An electrically insulating layer having a cured resin material and a particulate filler in the cured resin material is formed, and this electrically insulating layer is used in a PCB, a chip carrier, or a similar electronic package product. Electricity, which forms a substantially solid layer and does not contain continuous fibers, semi-continuous fibers, or the like as a part of the electrically insulating layer. The means adopted by the invention according to claim 2 is "the electrical insulating structure according to claim 1 in which the cured resin material is a polymer resin", and the means according to claim 3 is The means adopted by the invention is "the electrically insulating structure according to claim 2 in which the polymer resin exhibits a high glass transition temperature (Tg)", and the means adopted by the invention according to claim 4 is ". The electrically insulating structure according to claim 3, wherein the resin material does not substantially contain dicyandiamide.</p><p> The means adopted by the invention according to claim 5 is "the electrically insulating structure according to claim 2, wherein the cured resin is a high-molecular-weight reactive heat-curable resin", and claim 6. The means adopted by the invention according to the invention is "the electrically insulating structure according to claim 2, wherein the cured resin constitutes about 20 to 90% by weight of the substantially solid layer".</p><p> Further, the means adopted by the invention according to claim 7 is that "the particulate filler is alumina, aluminum oxide, aluminum nitride, silicon nitride, silicon carbide, beryllium oxide, boron nitride, diamond powder, titanium oxide, silica, ceramic. The electrically insulating structure according to claim 1, which is selected from the group consisting of and a combination thereof, and the means adopted by the invention according to claim 8 is "the silica is spherical." The electrically insulating structure according to claim 7, which is selected from the group consisting of amorphous silica, hollow silica microspheres, and a combination thereof. The electrically insulating structure according to claim 1, each having a size in the range of about 200 Å to 35 μm, and the means adopted by the invention according to claim 10 is that the particulate filler is about 10 to 80. The electrically insulating structure according to claim 1, which constitutes the electrically insulating layer by weight%, and the means adopted by the invention according to claim 11 is "the particulate filler has a coupling agent." The means adopted by the invention according to claim 12, which is the "electrically insulated structure according to claim 1". "The electrically insulating structure according to claim 11, wherein the coupling agent is silane."</p><p> Further, the means adopted by the invention according to claim 13 is "the electrically insulating structure according to claim 1, wherein the electrically insulating layer has a dielectric constant in the range of about 2.8 to 4.0". The means adopted by the invention according to claim 14 is "the electrically insulating structure according to claim 1, wherein the electrically insulating layer has a Tg in the range of about 165 ° C to 200 ° C", and claim 15. The means adopted by the invention according to claim 16 is "the electrically insulating structure according to claim 1, wherein the electrically insulating layer has a loss coefficient in the range of about 0.005 to 0.028 at 1 MHz". The means adopted by the present invention is "the electrically insulating structure according to claim 1, wherein the electrically insulating layer has a decomposition temperature in the range of about 300 to 330 ° C", and the invention according to claim 17. The means adopted by the above-mentioned method is "the electrically insulating structure according to claim 1, wherein the electrically insulating layer has a softening agent".</p><p> The means adopted by the invention according to claim 18 is "the electrically insulating structure according to claim 17, wherein the softening agent is Inchem PKHS-40", and the means adopted by the invention according to claim 19. Is "the electrically insulating structure according to claim 1 in which the resin material has a flow control additive", and the means adopted by the invention according to claim 20 is "the flow control additive is Degussa R". -972 The electrically insulating structure according to claim 19.</p>

<p> As described above, in the present invention, "an electrically insulating structure suitable for use in PCBs, chip carriers and similar electronic package products, in a cured resin material and in the cured resin material. An electrical insulating layer with a particulate filler is formed, and this electrical insulating layer forms a substantially solid layer for use in a PCB, chip carrier or similar electronic packaging product, and this electrical insulation. The main structural feature of the layer is that it does not contain continuous fibers, semi-continuous fibers, or the like, even in part, which expands circuit board technology. It is possible to provide a new and unique electrical insulating structure, and the electrical insulating structure is used to form an electrical insulating layer of a circuit board, and the circuit board is an existing circuit board. It can be manufactured using a manufacturing procedure.</p><p> Also. The present invention provides significant improvements in electrically insulating structures such as those formed in electrically insulating layers used in the production of circuit boards such as PCBs. One of the particularly important features of the present invention is to provide an insulating material containing a resin and predetermined particles, but not as part of which is continuous or semi-continuous glass fiber or the like. As mentioned above, fibers of such continuous length have traditionally been used in many substrates to withstand the treatment of the layers described below (especially the intense pressurization and temperature of the laminate) into the final multilayer structure. It was thought necessary to provide sufficient strength for the electrically insulating layer obtained from an insulating material. Removing the continuous or substantially continuous and long strands of these materials with the use of particles facilitates the formation of pores, increases the chances of reducing wire width and thickness, and of substrate density. Satisfy design requirements for growth.</p>

To better understand the invention, along with other and other purposes, advantages and functions, reference is made to the following disclosures and claims in connection with the accompanying drawings.

As used herein, an "information processing system" calculates, classifies, processes, transmits, receives, searches, devises, and switches information, knowledge, or data in any form of business, science, control, or other use. It shall mean any device or collection of devices primarily designed to be stored, displayed, certified, measured, detected, recorded, played, manipulated or utilized. Examples include personal computers and large processors such as computer servers and mainframes. Such products are known techniques and are also known to include PCBs and other forms of circuit boards as part of them, some of which include a plurality of such components according to their operating requirements.

FIG. 1 shows the first steps in the formation of a circuit board using the electrically insulating structure disclosed herein. As will be seen thereafter, the main feature of the present invention is an electrically insulating layer as part of the circuit board, which provides an array of dense through-holes within the substrate, while simultaneously closely spaced adjacent holes. It is possible to prevent an electrical short circuit between them. That is, relatively thin (diameter) through-holes can be concentrated at a very high density in this unique electrical insulation layer, and also conductive (generally plated) and incorporated with a circuit board. High density circuit connections can be provided between predetermined conductive layers (eg, signals, power supplies, grounding, etc.) in the final structure. Most importantly, this new insulating material is such as the fiberglass fibers required for the vast number of known electrical insulating layers (similarly the most known are the "FR4" materials mentioned above). Does not contain continuous or semi-continuous fibers.

As mentioned above, the use of such fibers often has an adverse effect on the formation of holes and the production of substrates at the plating stage because the fibers and their materials penetrate into the holes, which are adjacent conductive holes. May be the base of the conductive path to. A single electrical short circuit of this type results in a final PCB or chip carrier that cannot operate in its intended use, resulting in high manufacturing costs. The unique materials disclosed herein overcome this shortcoming, while at the same time ensuring relatively high insulation reliability and a relatively thin final layer, providing a substrate-based final product (eg, chip carrier or PCB). Both of these are highly desirable when meeting many of the current high density requirements.

The insulating material used to form the circuit board of the present invention uses a resin material together with fine particles of a predetermined volume, and the fine particles consist of various materials defined below, two examples of which are silica and ceramic, and they. It is a combination of. Others are listed below. In a preferred embodiment, the insulating resin is a high Tg (glass transition temperature) DICY (dicyandiamide) -free epoxy such as Huntsman LZ-8213 available from Huntsman Advanced Materials in Brewster, New York. In some cases, high molecular weight reactive thermosetting resins such as Inchem PKHS-40 available from Inchem Corporation in Rock Hill, South Carolina may be added to provide strength and coating film peel resistance. This material also functions as a fabric softener. Tatsumori PLV-6 Spherical amorphous silica can also be added to control the coefficient of thermal expansion (CTE).

This silica is available from Tatsumori, Ltd., Tokyo, Japan (distributor Tatsumori USA, Inc., New York, New York). The spherical nature of the filler allows for high volume loading of the filler and does not significantly increase the melt viscosity of the coating, so it is not necessary to exclude the usual laminating process as used in FR-4. In some cases, a thixotrope such as Degussa R-972, available from Degussa Corporation, Pigments Divition, Teterboro, New Jersey, is added to the dissolution viscosity of the solvent containing the coating varnish and the melting viscosity of the B-step insulating coating ( The coating film is assumed to be at this stage in the manufacturing process) to improve the balance. That is, Degussa R-972 functions as a flow control additive.

Suitable catalysts for epoxies include amines such as imidazole, benzyldimethylamine, 1.3-tetramethylbutanediamine, tris (dimethylaminomethyl) phenol, pyridine, tertiary amines such as triethylenediamine, and tin octylate. Contains acidic catalysts. Solvents such as MEK available from Brand Nu Laboratories, Meriden, Connecticut can also be added to dissolve various resins to form film carrier coatings. In some cases, silanes (eg Dow-Corning Z-6040 available from Dow-Corning Corporation, Midland, Michigan) can be added to improve the adhesion between the filler and the resin interface.

The volume composition of the particles ranges from about 10 to 80% by volume with respect to the total volume of the electrically insulating layer. The preferred particle volume of the electrically insulating layer disclosed herein is about 39%. The size of each particle is in the range of about 200 Å to 35 μm, and the preferred size is about 10 μm. The above scope does not limit the present invention, and it is permitted to use other things in the present invention. Other thermally conductive and electrically insulating fillers can also be used to improve heat transfer to the ambient environment.

Such particle fillers include aluminum oxide, 92% alumina, 96% alumina, aluminum nitride, silicon nitride, silicon carbide, beryllium oxide, boron nitride, diamond powder (manufactured by either high pressure or plasma CVD steps). Is done. Particularly preferred fillers are aluminum oxide and aluminum nitride due to their high thermal conductivity.

Preferred fillers are, in some cases, Dow-Corning's γ-amino-propyl-triethoxysilane (A1100), or β- (3,4-epoxy-cyclohexyl) ethyltrimethoxysilane (A186), or γ-glycidylpropyl. It can also be pretreated with a coupling agent such as trimethoxysilane (Z6040). The amount of coupling agent has been found to be sufficient at about 0.25 wt% of Phila. The amount can be determined by the weight loss of the filler treated with the coupler after firing. The amount should not exceed several monolayers. The particles used reinforce the final layer compared to resin materials that do not contain it.

More importantly, the particles allow the finished composite structure to have a relatively low isotropic expandability with a thermal expansion range of 20-25 ppm (part of a million) / ° C. In addition, the particles provide breakage and fatigue resistance, relatively low hygroscopicity and a rough surface texture, making it sufficiently easy to then plate (especially with copper) through holes and other formed, such as the outer surface. To do. Therefore, the product manufacturer can adjust the CTE by adding a predetermined volume ratio of particles. Next, the relative CTE value of the electrically insulating layer formed by using the above resin material and the corresponding weight% of the identified particles are shown in Table 1 below.

<tables num="1"><img file="JP2005294829A_D0001.tif" /></tables> When making through holes in the above materials (eg, using the lasers below in general), even if such hole patterns are concentrated at high density, after plating (making them conductive), electrical short circuits in the holes will occur. It is known that it does not occur. That is, the plating material (generally copper) does not undergo migration between through holes that may occur when glass fiber or other fibrous material is used.

Electrically insulating layers manufactured using the above materials have major electrical, thermal, physical properties and thermal expansion as shown in Table 2 below, as defined by physical modeling and process development analysis. Has sex.

<tables num="2"><img file="JP2005294829A_D0002.tif" /></tables> In one embodiment of the invention, a total of 10,000 holes can be drilled within a square inch of the electrically insulating layer, which is a high density that can be achieved using the proprietary disclosures herein. It represents an extreme example of the hole pattern of. Pattern densities in the range of about 5,000 to 10,000 holes / square inch can be easily achieved using the disclosures of the present invention. As described above, a laser, particularly a YAG laser, is preferably used for such drilling, and in one embodiment of the present invention, it can be provided in the electrically insulating layer at about 50 through holes / sec.

As will be further appreciated from the contents of this specification, the particular use of the circuit board formed herein is part of a chip carrier, PCB or other electronic packaging product as manufactured and sold by the assignee of the invention. .. A specific example is a chip carrier sold under the name Hyper-BGA Chip Carrier (Hyper-BGA is Endicott Interconnect). Technologies, Inc. (registered trademark). The invention is, of course, not limited to chip carriers or even high level PCBs. Such multiple circuit boards (also called "cores", in certain cases are called "power cores" if the cores contain one or more power surfaces and function primarily in this capability) are final. It can be incorporated into such carriers or PCBs, depending on the operating requirements desired for the product. As described below, the "core" is easily "stacked" with other layers, including conductors and insulating materials, and joined together (preferably using existing PCB stacking steps) to form a multilayer carrier or multilayer PCB. .. The laminate thus formed is further subjected to another step including an existing photolithographic step, and a circuit pattern is formed on the outer conductive layer thereof. As described below, such an external circuit pattern includes a conductive pad, on which a conductor such as a solder ball is placed, and if necessary, other components such as semiconductor chips, PCBs and chip carriers. The structure can be connected to.

Therefore, the original disclosure content of the present invention can be applied to a large number of electronic packaged products. Importantly, the present invention allows the incorporation of circuit boards with high-density through-hole patterns and interconnect functions (eg, high-density "cores") within a larger multi-layer structure. The other layer parts do not have such density and operational capabilities. Thus, most of the structure can be manufactured in "standard" multilayer products and the unique subcomponents disclosed herein can simply be added as part of the existing "standard" process. When the circuit board core is placed inside, it allows for high density connections between other low density parts of the multi-layer product, at least in part of which can give the product the unique features of the invention.

As shown in FIG. 1, the first preferred step of forming a circuit board that includes an electrically insulating layer as disclosed herein includes mating the multilayer members 11, 11'. Each member preferably comprises a relatively thin layer 13 of insulating material having the composition defined herein, and a conductive layer 15 (preferably copper) on it. Each layer 13 is preferably about 1 to 4 mils (1/1000 inch) in thickness (T2), more preferably 2 mils (0.002 inch). Each conductive layer has a thinner thickness (T1), ranging in thickness from only about 0.25 to 1.5 mils. The preferred thickness is 0.5 mil. Each electrically insulating layer containing a resin as part of its composition is preferably conventionally known as a "stage B" state.

Laminated members 11, 11'are aligned and joined to each other using an existing PCB laminating process. In one example, the total pressure used was about 400 lbs per square inch (psi), the temperature was about 188 ° C, and the time was about 90 minutes. The result is an outer conductive layer 15, each of substantially the same thickness as above, but with a common intermediate electrical insulating layer 13'with a compressed thickness of about 4.2 mils, resulting in a final total substrate thickness. A laminated substrate 21 (Fig. 2) with a (T3) of about 5.6 mils is obtained. The intermediate electrical insulating layer 13'as a result of such lamination is technically referred to here as the "C stage" state. This board can further serve to form the base of the circuit board as defined herein and, as further defined, can serve as the "core" board for thicker multilayer products such as PCBs or chip carriers.

In FIG. 3, substrate 21 (not shown on a larger scale than FIGS. 1 and 2 for illustration) is subjected to an existing photolithographic step here to "circuit" the outer conductive layer 15. That is, the layer 15 is treated using a known process to form a desired pattern on it. The pattern includes at least some openings 17 in each layer, which are aligned relative to each other as shown. Further, it is also within the scope of the present invention to provide another circuit shape such as a line or pad 19 in one or both layers. When the substrate 21 acts as a "power core", the layer 15 generally only includes an opening 19 within it. However, if one or both layers 15 function as another capability, eg, a signal layer, other patterns can be provided. Therefore, the pattern of FIGS. 3 (and 4-6) does not limit the scope of the invention.

In FIG. 4, the substrate 21 is shown to include another layer 31 of insulating material on either side thereof, each layer preferably containing a thin conductive layer (eg, copper) on it. In one example of the invention, the layers 31 and 33 are each made of the same material and thickness as the layers 13 and 15 of FIG. 1 and are laminated onto the substrate 21 using a conventionally known laminating process. Other acceptable layers 13 include non-woven reinforcements based on duPont's Thermot aramid fiber matte paper. DriClad resin can also be applied to Thermomount using standard impregnation methods used in the manufacture of prepregs (DriClad is a registered trademark of Endicott Interconnect Technologies, Inc., which is a resin product for PCBs and chip carriers. As part of some of the product line, it forms part of the electrical insulation layer sold by this company). Other suppliers of resin-formed Thermot include Shin-Kobe Electrical Machinery Co., Ltd., in Japan products, and Arlon. Includes Arlon, 55-LM manufactured by Corporation, Engineered Laminates and Coatings Division in East Providence, Rhode Island. After stacking, each conductive layer 33 was "individualized" to include a plurality of openings 41 within it and placed adjacent to it (but separated by an intermediate layer 31) as shown in FIG. ) Align with each opening 17 in the conductive layer 15.

It should be noted that at least one opening 41 is aligned with respect to the corresponding opening 17, but the other probably smaller openings 41 are not so aligned and layer 15 (if one is so formed). ) May be aligned with other parts of the circuit formed above. Through the formed openings 41, through holes are made in the structure of FIG. 5 using a laser of the above type. The laser can make through holes throughout the thickness of the structure of FIG. 5 wherever there is a pair of aligned openings 17 and a corresponding aligned openings 41, as shown in FIG. .. In one embodiment, a total of 10,000 holes, each with a diameter of only about 2 mils, can be placed within each square inch of the structure in these aligned directions. This also represents a high density pattern that can be achieved using the disclosures of the present invention.

In addition to this high density pattern of through holes 51 that penetrate the entire thickness of the structure of FIG. 5, shallower throughs that reach only the conductive layer 15 at the same time as the formation of the holes 51, as shown in FIG. A hole 53 can also be formed. The purpose of these latter holes is, for example, to eventually form an electrical connection to layer 15 with a conductive layer 33 from one predetermined signal line to the other, again where layer 15 is the signal propagation. Although it is assumed to function as a conductive surface, versatility can be added by the present invention if necessary. Layer 15 can function as a ground plane and can be grounded if necessary. In addition, through-holes 51 can be provided through the entire thickness of the structure (see FIG. 6), and if layer 15 includes such lines or is completely signal plane, then (adjacent) signal lines or layers. It is also possible to connect an external signal layer 33 or the like to a predetermined internal signal line or layer in the structure. The through holes 51, 53 are arranged together with the conductive material (if necessary), and the preferred material is copper with a thickness of only about 0.5 to 0.75 mil. The preferred plating process may be electroplating or electroless plating and is determined by the plating equipment available for such plating. Electrolytic and electroless plating of through holes is well known (except for the relatively small diameters disclosed herein) and therefore does not need further explanation.

Further, in FIG. 6, another electric insulating layer 71 (broken line) is formed on both sides of the structure having through holes formed therein, and another conductor layer 73 (also broken line) is formed on each electric insulating layer. Can be seen. This adds some additional electrical insulating and conductive layers to the structure of FIG. 6 and is a larger multilayer final product such as a PCB or laminated chip carrier with more layers than shown in FIGS. 3-6. Is shown to be able to be configured. Each of these other layers can also preferably be formed from an electrically insulating structure as disclosed herein. Further, in a larger and thicker structure, the "core" of a plurality of internal circuit boards as shown in FIG. 6 (or even FIG. 3) is incorporated, and the disclosure contents of the present invention are provided at a plurality of positions inside the core. The final structure provided can be provided. To this end, both examples of the additional layers of FIGS. 3 and 4-6 can be considered such "cores".

FIG. 7 shows an example of an electrical assembly 81 that can be formed using the circuit boards disclosed herein. As mentioned above, each substrate formed according to the disclosures herein can also be used within a larger substrate of a known type, such as a PCB, chip carrier or the like. Figure 7 shows these two larger components, one with the chip carrier 83 and the other with the PCB 85. Obviously, the PCB85 is placed in an electrical component (not shown) such as a personal computer, mainframe, server, etc. and electrically connected to it. As shown, the chip carrier 83 is generally placed on a lower substrate such as a PCB 85 and electrically connected to it. Such a carrier also generally has a semiconductor chip 87 arranged on it and is electrically connected to the carrier. In the embodiment of FIG. 7, the connections between the chip and the carrier and between the carrier and the PCB are achieved using solder balls 89, 89', respectively. Such connections have been known in the past and need no further explanation. The importance of FIG. 7 shows how to use one or more circuit boards 91 (broken line) formed in the chip carrier 83 and PCB85 using the electrically insulating structure of the present invention and forming a part thereof. It is that you are. Two substrates 91 are shown for use within the PCB 85 and only one is shown within the carrier 83. As mentioned above, the invention is not limited to the numbers shown. For example, a highly preferred disclosure of the invention can be provided to a PCB using three or more substrates 91, each of which constitutes a "core" (eg, "power core") of a particular circuit within the PCB. ..

At this time, what is considered to be a preferred embodiment of the invention is shown and described, but various modifications and modifications are made without departing from the scope of the invention, as defined in the appended claims. It is clear to those skilled in the art that it can be done.

<figref num="1">FIG. 5 is a partially enlarged cross-sectional view showing the first steps used to produce a circuit board suitable for use with an electrically insulating layer formed from a composition according to a preferred embodiment of the invention.</figref><figref num="2">It is a partially enlarged sectional view which shows the 2nd step of manufacturing the circuit board.</figref><figref num="3">It is a partially enlarged sectional view which shows the 3rd step of manufacturing the circuit board.</figref><figref num="4">It is a partially enlarged sectional view which shows the 4th step of manufacturing the circuit board.</figref><figref num="5">It is a partially enlarged sectional view which shows the 5th step of manufacturing the circuit board.</figref><figref num="6">It is a partially enlarged sectional view which shows the sixth step of manufacturing the circuit board.</figref><figref num="7">It is a front view of the electrical assembly which assembled the circuit board shown in FIG. 1 and FIG.</figref>

Code description

11, 11 Laminated members 13, 13 (Electrical insulation) layer 15 Conductive layer 17 Opening 19 Lines and pads 21 Substrate 31, 33 Layer 41 Opening 51 Through hole 53 Shallow through hole 71 Electrical insulating layer 73 Conductive Layer 81 Electrical assembly 83 Chip carrier 85 PCB 87 Semiconductor chip 89, 89'Handa ball 91 Circuit board