Memory cell having electric field programmable memory element and operating method therefor

The present invention relates to memory cells, arrays, and / or devices, and methods of controlling and / or operating memory cells, arrays, and / or devices, and more specifically, in one embodiment, memory cells. And for arrays and / or devices that contain multiple such memory cells. Here, each of the memory cells contains an electric field programmable thin film that stores charges that represent the data state.

There are many different types and / or forms of memory cells, arrays, and devices. Such devices generally have two different types: volatile (eg, dynamic random access memory (DRAM) and static random access memory (SRAM)), and non-volatile (eg, dynamic random access memory (DRAM) and static random access memory (SRAM)). For example, it can be classified into read-only memory (ROM), electrically programmable read-only memory (EPROM), and electrically erasable and programmable read-only memory (EEPROM). Typical memory cells, arrays, and devices are typically manufactured on a one-plane approach and are now manufactured from inorganic materials such as single crystal and polycrystalline silicon. (See, for example, Patent Document 1 and Patent Document 2).

Devices containing such memory cells have been technically and commercially successful, but have many drawbacks. Among these drawbacks are, for example, complex architectures, density constraints, and relatively high manufacturing costs. In addition, some volatile types of memory devices must incorporate a "refresh" circuit to re-store information on a steady / periodic basis. This can raise issues related to heat dissipation, timing, and power consumption. Moreover, although some degree of integration density can be achieved, such devices tend to be limited or limited in terms of memory cell size.

For example, in normal DRAM, memory cells are access transistors, typically made on the surface of single crystal silicon wafers, and, for example, dielectrics (such as oxides, nitrides, or combinations thereof). Consists of a capacitor containing two silicon base conductors separated by. Capacitors store charges that represent a bistable memory state. The access transistor acts as a switch that controls the charging and discharging of the capacitor, as well as the reading and writing of the logical state to the capacitor (ie, charging or discharging the capacitor). Traditional techniques use the stack and / or trench capacitor approach. In that case, the capacitors are partially placed above and / or below the access transistors to reduce the two-dimensional area occupied by the memory cells. Therefore, traditional DRAMs that use 1-transistor, 1-capacitor memory cells tend to be limited or limited in terms of memory cell size and single-plane layout.

Non-volatile semiconductor devices avoid certain problems commonly associated with volatile semiconductor devices, but often result in complex cell and circuit design, data storage capacity, capacity, and /. Alternatively, it has the disadvantage of reducing density. (See, for example, Patent Document 1 and Patent Document 3). As complexity increases, production costs often increase. For example, in a conventional EEPROM, a memory cell contains a transistor with multiple gates, the gates being placed on a single crystal semiconductor substrate and separated by a thin insulator with a highly controlled thickness. Will be done. Specifically, the control gate is placed above the floating gate, and the floating gate is placed above the channel region within the semiconductor substrate. Floating gates typically include a heavy-doped silicon or metal layer (eg, aluminum) and are separated from the channel region via a highly controlled thin insulator. The insulator tends to deteriorate with use / time.

In addition to ubiquitous inorganic crystalline semiconductor-based devices, alternative electronic memories that use bistable elements that are converted between high-impedance and low-impedance states by applying current or other types of inputs to the device. And there is a switching device. In electronic memory and switching devices, organic and inorganic thin film semiconductor materials, such as amorphous chalcogenide semiconductor organic charge transfer complex thin films, such as copper-7,7,8,8-tetracyanoquinodimethane (Cu-TCNQ). ) Thin films, and certain inorganic oxides in organic matrices may be used. It should be noted that these materials have been proposed as potential candidates for non-volatile memory.

Some volatile and non-volatile memory devices have been realized using a variety of bistable materials. However, many currently known bistable thin films have a non-homogeneous multilayer composite structure produced by a vapor deposition method. Deposition methods are expensive and often difficult to control. Moreover, these bistable thin films do not provide an opportunity to produce thin films in conformal to planar shapes. Bistable thin films made using polymer matrices and particulate matter are generally non-homogeneous and are therefore unsuitable for making submicrometer and nanometer scale electronic memories and switching devices. In addition, standard industrial methods allow controllable production of other bistable thin films, but their work requires hot melting and annealing at grid intersections. Such thin films generally have trouble with thermal management, have high power consumption requirements, and provide only a small difference between the "conducting" and "non-conducting" states. Moreover, since such thin films operate at high temperatures, it is difficult to design stack device structures that allow for high density memory storage.

<patcit num="1"><text>U.S. Patent Application Publication No. 2004/0135193</text></patcit><patcit num="2"><text>U.S. Pat. No. 6,710,384</text></patcit><patcit num="3"><text>U.S. Patent Application Publication No. 2004/0136239</text></patcit><patcit num="4"><text>US Provisional Patent Application No. 60 / 556,246 "Memory Devices based on Electric Field Programmable Films", filed March 24, filed March 24, 2004, 2004)</text></patcit><patcit num="5"><text>International Publication No. 2004070789 Pamphlet "Rewritable Nano-Surface Organic Electrical Bistable Devices"</text></patcit><patcit num="6"><text>U.S. Patent Application Publication No. 2004/0165462</text></patcit><patcit num="7"><text>U.S. Pat. No. 6,785,163</text></patcit><nplcit num="1"><text>Nature Material (2204) 3 (12), 918-922, entitled Programmable Polymer Thin Film and Non-Volatile Memory Device </text></nplcit><nplcit num="2"><text>Applied Physics Letters (2003), 82 (9), 1419-1421, entitled Nonvolatile Electrical Bistability of Organic / Metal-Nanocluster / Organic System </text></nplcit>

<p> Therefore, one of the drawbacks of conventional memory cells, arrays, and / or devices that use field programmable bistable thin films is that of conventional memory cells, arrays, and / or devices that use conventional bistable thin films. There is a need for improved memory cells, arrays, and / or devices that overcome some, and / or all. Improved memory cells, arrays, and / or to provide field programmable bistable thin films that include or are suitable for a variety of substrates and a variety of definable shapes, including single-plane and / or multi-plane architectures. There is a need for a device.</p><p> In addition, there is a need for memory cells, arrays, and / or devices that use field programmable bistable thin films that can be easily manufactured using conventional integrated circuit manufacturing techniques. In addition, the need for memory cells, arrays, and / or devices that provide field programmable bistable thin films that are relatively cheaper (eg, on a bit-by-bit basis) than traditional memory cells, arrays, and / or devices. Exists. In addition, memory cells, arrays, and / or devices that provide field programmable bistable thin films with embedded logic or other circuits that require fewer integration steps and / or masks to manufacture. There is a need for cells, arrays, and / or devices.</p>

<p> In the first aspect, a memory cell having at least a first data state and a second data state is disclosed. This memory cell includes a semiconductor transistor (eg, a P-channel or N-channel transistor) and an electric field programmable bistable element connected to the semiconductor transistor. In one embodiment, the semiconductor transistor comprises first and second regions, each region having an impurity that provides a first conductive form. The semiconductor transistor further includes a body region disposed between the first region and the second region. The body region contains impurities that provide a second conductive form (where the second conductive form is different from the first conductive form). The gate is spaced from the body area and electrically coupled to the body area.</p><p> An electric field programmable bistable element in a memory cell includes first and second electrodes, as well as at least one electric field programmable thin film located between the first and second electrodes. Here, the first data state of the memory cell represents the first resistance of the electric field programmable thin film, and the second data state represents the second resistance of the electric field programmable thin film.</p><p> In one embodiment, the first electrode is connected to the first region, which is the drain region of the transistor. In another embodiment, the first electrode is connected to a second region, which is the source region of the transistor. In yet another embodiment, the first electrode is connected to the gate of the semiconductor transistor.</p><p> The first electrode may be located in the first region of the semiconductor transistor. In addition, the first electrode is located over the first region of the semiconductor transistor and can extend (either above or below) over at least a portion of the gate. In fact, the first electrode can be at least a portion of the first region of the semiconductor transistor.</p><p> In one embodiment of this aspect of the invention, the first electrode is located above the gate of the semiconductor transistor. In another embodiment, the first electrode is the gate of the semiconductor transistor.</p><p> In other embodiments, memory cells (having at least a first data state and a second data state) are disclosed. This memory cell includes a transistor and a plurality of electric field programmable bistable elements connected to the transistor. In one embodiment, the semiconductor transistor comprises first and second regions, each region having an impurity that provides a first conductive form. The semiconductor transistor further includes a body region disposed between the first region and the second region. The body region contains impurities that provide a second conductive form (where the second conductive form is different from the first conductive form). The gates are spaced from the body area and electrically coupled to the body area. It should be noted that the semiconductor transistor may be a P-channel or N-channel transistor.</p><p> Memory cells of this aspect further include first and second electric field programmable bistable elements connected to semiconductor transistors. Each electric field programmable bistable element comprises a first electrode, a second electrode, and at least one electric field programmable thin film located between the first and second electrodes. The electric field programmable thin film contains at least two resistance states, including a first resistance state and a second resistance state.</p><p> In the memory cell of this embodiment, the electric field programmable thin film of the first electric field programmable bistable element is in the first state, and the electric field programmable thin film of the second electric field programmable bistable element is in the second state. At one point, it is in the first data state. A memory cell is when the electric field programmable thin film of the first electric field programmable bistable element is in the second state and the electric field programmable thin film of the second electric field programmable bistable element is in the first state. It is in the second data state.</p><p> In one embodiment of this embodiment, the first region is the drain region of the semiconductor transistor and the first electrode of the first electric field programmable bistable element is connected to the drain region. In another embodiment, the second region is the source region of the semiconductor transistor and the first electrode of the first electric field programmable bistable element is connected to the source region.</p><p> Further, in one embodiment, the first electrode of the first electric field programmable bistable element is located in the first region of the semiconductor transistor. In another embodiment, the first electrode of the first electric field programmable bistable element is located above the first region of the semiconductor transistor and extends over the gate of the semiconductor transistor. The first electrode may further be part of a first region of the semiconductor transistor.</p><p> Memory cells can contain third and fourth data states. In this regard, the memory when the electric field programmable thin film of the first electric field programmable bistable element is in the first state and the electric field programmable thin film of the second electric field programmable bistable element is in the first state. -The cell is in the third data state. When the electric field programmable thin film of the first electric field programmable bistable element is in the second state and the electric field programmable thin film of the second electric field programmable bistable element is in the second state, the memory cell is in the second state. It is in the data state of 4.</p><p> In yet another embodiment, the memory cell having at least the first and second data states comprises a plurality of semiconductor transistors and a plurality of electric field programmable bistable elements. The memory cell contains a first semiconductor transistor having first and second regions, each of which has impurities that provide a first conductive form. The first semiconductor transistor further includes a body region disposed between the first region and the second region, and the body region contains impurities that provide a second conductive type (where, the second The conductive type of is different from the first conductive type). The gate is spaced from the body region of the first semiconductor transistor and is electrically coupled to the body region.</p><p> The memory cell further includes a first electric field programmable bistable element connected to the first semiconductor transistor. The electric field programmable bistable element includes first and second electrodes, as well as at least one electric field programmable thin film located between the first and second electrodes. The electric field programmable thin film contains at least two resistance states, including a first resistance state and a second resistance state.</p><p> Further, the memory cell of this embodiment includes a second semiconductor transistor. The second semiconductor transistor includes first and second regions having impurities that provide the first conductive type, and a body region arranged between the first region and the second region. The body region contains impurities that provide a second conductive form (where the second conductive form is different from the first conductive form). The gate is spaced from the body region of the second semiconductor transistor and is electrically coupled to the body region.</p><p> The memory cell of this embodiment further includes a second electric field programmable bistable element connected to the second semiconductor transistor. The second electric field programmable bistable element includes the first and second electrodes, as well as at least one electric field programmable thin film located between the first and second electrodes. The electric field programmable thin film of the second electric field programmable element includes at least two resistance states including a first resistance state and a second resistance state.</p><p> When the electric field programmable thin film of the first electric field programmable bistable element is in the first state and the electric field programmable thin film of the second electric field programmable bistable element is in the second state, the memory cell is in the second state. It is in the data state of 1. When the electric field programmable thin film of the first electric field programmable bistable element is in the second state and the electric field programmable thin film of the second electric field programmable bistable element is in the first state, the memory cell is in the first state. It is in the data state of 2.</p><p> It should be noted that when the electric field programmable thin film of the first electric field programmable bistable element is in the second state and the electric field programmable thin film of the second electric field programmable bistable element is in the second state. The memory cell is in the third data state. Further, when the electric field programmable thin film of the first electric field programmable bistable element is in the first state and the electric field programmable thin film of the second electric field programmable bistable element is in the first state, the memory cell. Is in the fourth data state.</p><p> In one embodiment, the first semiconductor transistor is an N-channel transistor and the second transistor is a P-channel transistor. In other embodiments, the first semiconductor transistor is an N-channel transistor and the second transistor is an N-channel transistor. In yet another embodiment, the first semiconductor transistor is a P-channel transistor and the second transistor is a P-channel transistor.</p><p> In one embodiment, the first electrode of the first electric field programmable bistable element is connected to the first region of the first semiconductor transistor. This first region is the drain region of the first semiconductor transistor. In another embodiment, the first electrode of the first electric field programmable bistable element is connected to the second region of the first semiconductor transistor. This second region is the source region of the first semiconductor transistor. In yet another embodiment, the first electrode of the first electric field programmable bistable element is connected to the gate of the first semiconductor transistor.</p><p> The first electrode of the first electric field programmable bistable element may be located above the first region of the first semiconductor transistor. In addition, the first electrode of the first field programmable bistable element may be located above the first region of the semiconductor transistor and extend (either above or below) over at least a portion of the gate. In fact, the first electrode of the first electric field programmable bistable element may be at least a portion of the first region of the semiconductor transistor.</p><p> In one embodiment of this embodiment, the first electrode of the first electric field programmable bistable element is located above the gate of the first semiconductor transistor. In another embodiment, the first electrode of the first electric field programmable bistable element is the gate of the first semiconductor transistor.</p><p> The accompanying drawings are referenced in the course of the detailed description below. These drawings show different aspects of the invention and, where appropriate, reference numerals indicating similar structures, components, materials, and / or elements in different drawings are similarly coded. It is understood that various combinations of structures, components, substances, and / or elements are conceivable and fall within the scope of the present invention, except as specifically indicated.</p>

In a first aspect, a memory cell with an access transistor and an electric field programmable bistable element is disclosed. Access transistors are gates, sources coupled to electric field programmable bistable or multi-stable devices (hereinafter collectively referred to as "electric field programmable bistable elements" unless otherwise stated otherwise). , Or a MOSFET transistor having a drain region (N-channel or P-channel). Access transistors facilitate selective and controllable programming and readout of field programmable bistable elements.

In one embodiment, the electric field programmable bistable element provides two or more different resistance properties. Each resistance characteristic represents one data state (eg, analog or digital state). The electric field programmable bistable element may include one or more electric field programmable thin films including an electron donor and / or an electron acceptor and / or an electron donor acceptor complex. The complex may be located between two or more electrodes.

The electric field programmable bistable element provides a resistor to the current flow that represents the data state of the memory cell. An electric field programmable bistable element is programmed into one of the data states by inducing an electric field by applying an appropriate voltage to at least one electrode. That is, due to this electric field, for example, the electron donor and / or the electron acceptor and / or the electron donor acceptor in the complex exchanges, aligns, rearranges, aligns, or rearranges charges to indicate one of the data states. Arrange.

The electric field programmable bistable element may use one or more electric field programmable thin films described and exemplified in documents such as Patent Document 4, Patent Document 5, Non-Patent Document 1 and Non-Patent Document 2. .. These references can be referenced for the typical manufacturing process of electric field programmable thin films.

Referring to FIGS. 1A-1C, the memory cell 10 of the first aspect of the present invention includes an access transistor 12 and an electric field programmable bistable element 14. The access transistor 12 includes a gate 16, a source 18, and a drain 20. In an exemplary embodiment, the body region is located between the source 18 and the drain 20 and is spaced from the gate 16. The gate 16 is electrically coupled, for example, directly, capacitively, and / or inductively to the body region of the access transistor 12.

In some embodiments, the gate 16 of the access transistor 12 is connected to the signal line 22. The signal line 22 provides a control signal to the access transistor 12 to facilitate reading or writing data from the electric field programmable bistable element 14. (See, for example, Figures 1A and 1C). In this regard, the control signal applied to the signal line 22 controls the "on" and "off" states of the transistor 12.

In another embodiment, the gate 16 is connected to an electric field programmable bistable element 14 (see, eg, FIG. 1B). The electric field programmable bistable element 14 is connected to the gate 16 of the access transistor 12. In this embodiment, the signal applied to the signal line 22 is applied directly to the electric field programmable bistable element 14 to facilitate reading or writing data from the electric field programmable bistable element 14.

The source 18 of the access transistor 12 is connected to an electric field programmable bistable element 14 to allow data to be read or written from the electric field programmable bistable element 14 (see FIG. 1A). In some embodiments, the source 18 of the access transistor 12 is connected to the signal line 24. The signal line 24 provides, for example, a reference voltage to memory cell 10. (See, for example, Figures 1B and 1C).

With reference to FIGS. 1A and 1C, in certain embodiments, the drain 20 of the access transistor 12 is connected to the sense / program signal line 26. The sense / program signal line 26 is selectively and controllably connected to a read / write circuit (not shown). In another embodiment, the drain 20 is connected to an electric field programmable bistable element 14. The electric field programmable bistable element 14 is connected to the sense / program signal line 26. (See, for example, Figure 1C). In the embodiments of FIGS. 1A-1C, the data state (ie, the resistance to the current flow presented by the electric field programmable bistable element 14) is stored in memory cell 10 via the sense / program signal line 26. Or read from there.

Note that the access transistor 12 can be a symmetric or asymmetric device. If the access transistors 12 are symmetrical, the source 18 and drain 20 are essentially interchangeable. However, if the access transistor 12 is an asymmetric device, the source 18 or drain 20 of the access transistor 12 has different electrical, physical, doping concentration and / or doping profile properties. Therefore, the source or drain regions of asymmetric devices are typically not interchangeable.

As described above, the electric field programmable bistable element 14 may be one or more electric field programmable thin films described and exemplified in Patent Document 4 of the electric field programmable thin film. In one embodiment, the field programmable bistable element 14 provides non-destructive readout and includes bistable switching or bistable resistance properties. Further, the electric field programmable bistable element 14 provides a non-volatile memory cell in that the data state of the memory cell is maintained in the electric field programmable bistable element 14 in the absence of power.

Referring to FIG. 2, in one exemplary embodiment, when a first voltage is applied to the electric field programmable bistable element 14, the electric field programmable bistable element 14 is programmed into the first data state ( Thereby, it presents the first resistance characteristic). (See point 28 in Figure 2). When a second voltage is applied to the field programmable bistable element 14, is the field programmable bistable element 14 programmed into the second data state (thus exhibiting a second resistance characteristic)? "Erase" the first data state. (See point 30 in Figure 2). The electric field programmable bistable element 14 is maintained in the second data state (has a second resistance characteristic) until the first voltage is applied again to the electric field programmable bistable element 14. (See point 28).

In the first data state, the field programmable bistable element 14 provides a relatively low resistance to the current flow, and in the second data state, the field programmable bistable element 14 provides a relatively high resistance to the current flow.

There are many materials and techniques for making a memory cell 10 that includes an access transistor 12 and an electric field programmable bistable element 14. For example, if the substrate is a bulk silicon wafer, the access transistor 12 has source 18 (with first conductivity type impurities), drain 20 (with first conductivity type impurities), and Includes body region (with second conductivity type impurities). The gate 16 (conductive type material, eg, metal, metal compound, or heavy-doped polysilicon) is electrically bonded (eg, directly, capacitively, and / or inductively) to the body region. The access transistor 12 may be manufactured using conventional materials and conventional semiconductor manufacturing techniques.

Alternatively, the substrate may be a silicon on insulator (SOI) type wafer, where the access transistor 12 is a partially depleted (PD) transistor, a fully depleted (FD) transistor, or a multigate transistor. It can be (for example, a double or triple gate) and / or a fin-type field effect transistor (Fin-FET). In these embodiments, the access transistor 12 may be further manufactured using conventional materials and conventional semiconductor manufacturing techniques.

Transistors 12 may also be manufactured from or present in polysilicon or amorphous silicon. In this way, a three-dimensional array of memory in which one or more layers can contain transistors (in addition to or on behalf of the substrate) may be manufactured. (See, for example, layer 68 in Figures 23A-23C). In fact, it may be advantageous to recrystallize the polysilicon layer disposed on the substrate in order to improve the operating characteristics of the transistors arranged or manufactured within the polysilicon layer. In this way, a three-dimensional array of memory can include one or more single crystal silicon or semiconductor layers (in addition to or on behalf of the substrate), such layers in which. It has transistors that are arranged or manufactured.

It should be noted that the transistor 12 may be made of any semiconductor material, organic or inorganic, as described below. Such semiconductor materials include, for example, silicon carbide, gallium arsenide, or pentacene. Transistors may be operated in depletion mode or enhancement mode. Transistors may also be manufactured with or without junctions. All methods of manufacturing the transistor 12 (and the material used therein), whether currently known or later developed, are intended to be within the scope of the present invention.

The electric field programmable bistable element 14 may be manufactured, for example, using any of the electric field programmable thin films described in the references described above.

In addition to material and manufacturing techniques, memory cells 10 may be arranged in a number of layouts and configurations. For example, referring to FIGS. 3A-3C, the memory cell 10 schematically shown in FIG. 1A may be manufactured using different materials, techniques, and layouts. Specifically, with reference to FIGS. 3A and 4, in one embodiment, the memory cell 10 is manufactured in and / or on the bulk semiconductor wafer 32. As mentioned above, the access transistor 12 may be manufactured from and using well-known or conventional materials and techniques.

After the access transistor 12 was manufactured, the contacts 34 and 36, as well as the sense / program signal line 26, were made of conventional well-known materials (eg aluminum or highly doped polysilicon) and conventional deposition, lithography, etc. And may be formed and / or patterned using etching techniques. After that (or at the same time as the formation of the sense / program signal line 26), the electrode 38a of the electric field programmable bistable element 14 may be formed and / or patterned. Electrodes 38a are made of conductive materials (eg, heavy-doped semiconductors (eg, polysilicon) or metals, such as aluminum, chromium, gold, silver, molybdenum, platinum, palladium, tungsten, titanium, and / or copper). It may be there. Electrodes 38a may be deposited, formed, and / or patterned using conventional or well-known manufacturing techniques.

The electric field programmable thin film 40 may then be deposited on the electrode 38a using any of the techniques described in Patent Document 4 of the electric field programmable thin film. After that, the electrode 38b can be deposited. As with electrode 38a, electrode 38b, a conductive type of material (e.g., heavily doped semiconductor (e.g., polysilicon) or metal, e.g., aluminum, chromium, gold, silver, molybdenum, platinum, palladium, Tan Gusuten, It may be titanium and / or copper). Electrodes 38b may be deposited, formed, and / or patterned using conventional manufacturing techniques.

Therefore, in this embodiment, the electric field programmable bistable element 14 includes an electric field programmable thin film 40 disposed between the electrodes 38a and 38b. The contact 34 connects the electric field programmable bistable element 14 (and in particular the electrode 38a) to the source region 18 of the access transistor 12. The contacts 34 and electrodes 38a facilitate good electrical connections and provide low resistance to the electrical path between the field programmable thin film 40 and, for example, the source region 18 of the access transistor 12.

It may be advantageous to use materials and manufacturing techniques that reduce and / or minimize the impact on the physical and electrical properties of the electric field programmable thin film 40. In this regard, when manufacturing electrodes 38b (and electrodes 38a), it is advantageous to use materials and techniques that do not impact (or damage) the electrical and physical properties of the electric field programmable thin film 40. is there. For example, the use of materials (eg, aluminum) that are deposited and / or formed using temperatures below the thermal budget of the electric field programmable thin film 40 is that after the deposition / application of the electric field programmable thin film 40. It will ensure electrical and / or physical integrity.

It should be noted that each electrode 38 may be manufactured, deposited, and / or formed from the same or different material using the same or different manufacturing techniques. In one embodiment, the thermal budget uses a first technique and a first material that requires higher temperature production, deposition, and / or formation to produce, deposit, and / or electrode 38a. Allows to form. After the electric field programmable thin film 40 is provided, the electrode 38b is manufactured using a second technique and / or a second material that can be manufactured, deposited, and / or formed at a relatively lower temperature. It may be deposited and / or formed. In this way, after the electrodes 38b are deposited / applied, the electrical and / physical integrity of the electric field programmable thin film 40 is improved or maintained.

In other embodiments, each of the electrodes 38a and 38b may contain material that provides different electrical properties. In this regard, the electrode 38a may be made of a material having a different work function than the material of the electrode 38b. In this way, the electric field programmable bistable element 14 can include an asymmetric response or behavior.

Further, in order to improve the current capacity of the electric field programmable bistable element 14, it may be advantageous to provide the electric field programmable bistable element 14 having a large area. Therefore, the electric field programmable bistable element 14 may be located above the access transistor and extended over the significant portion of the gate 16. In this way, the electrical properties of the electric field programmable bistable element 14 are improved without having a significant impact (if any) on the overall dimensions of the memory cells 10.

Referring to FIG. 3B, in another embodiment, the electric field programmable thin film 40 is placed directly above the source region 18 of the access transistor 12. In this embodiment, the source region 18 further functions or acts as an electrode of the electric field programmable bistable element 14. Therefore, this embodiment can provide a relatively more compact layout that uses fewer manufacturing steps as compared to the layout of FIG. 3A. Further, this embodiment provides an electric field programmable thin film 40 with a relatively large thickness. This can improve the uniformity of the electrical properties of the electric field programmable bistable element 14 between the memory cells 10.

Further, in another exemplary embodiment, with reference to FIG. 3C, the electrode 38a may be formed and / or patterned such that it is in direct contact with the source region 18 and extends over the gate 16. In this embodiment, the memory cells 10 in the array have greater consistency in terms of electrical performance / response of the field programmable bistable element 14 (than in the embodiments of FIGS. 3A and 3B). Can be done. Such consistency is due, for example, to the relatively large surface area and relatively large thickness of the electric field programmable thin film 40, which can be easily manufactured and controlled to a given specification.

It should be noted that the layouts of FIGS. 3A-3C are equally applicable to the memory cells 10 schematically shown in FIG. 1C. In this regard, the electric field programmable bistable element 14 is connected to the drain region 20 of the access transistor 12. For the sake of brevity, those explanations are not repeated. An embodiment of memory cell 10 with an electric field programmable bistable element 14 connected to gate 16 of the access transistor 12 (schematically shown in FIG. 1B) further uses different materials, techniques, and layouts. May be manufactured using. For example, referring to FIG. 5A, in one embodiment, memory cells 10 are manufactured in and / or on bulk semiconductor wafers 32. The access transistor 12 may be manufactured using well-known or conventional materials and techniques.

After manufacturing (or at the same time as manufacturing) the access transistor 12, contacts 34 and 36, signal line 24, and sense / programming signal line 26 are conductive material (eg, aluminum or highly doped polysilicon). It may be manufactured from and formed and / or patterned using conventional deposition, lithography, and etching techniques. The electrode 38a of the electric field programmable bistable element 14 is then subjected to a conductive material (eg, heavy-doped semiconductor (eg, polysilicon)) or metal, such as aluminum, chromium, gold, silver, molybdenum, platinum, palladium, It may be formed and / or patterned from tungsten, titanium, and / or copper). Electrodes 38a may be deposited, formed and / or patterned using conventional or well known manufacturing techniques.

The electric field programmable thin film 40 may then be deposited on the electrode 38a using any of the techniques described in Patent Document 4 of the electric field programmable thin film. Next, the electrode 38b is deposited. Like the electrode 38a, the electrode 38b may be a conductive material. Electrodes 38b may be deposited, formed, and / or patterned using conventional manufacturing techniques.

Thus, in this embodiment, the electric field programmable bistable element 14 includes an electric field programmable thin film 40 that is located on top of the access transistor 12 and is located between the electrodes 38a and 38b. The electrical contact connects the field programmable bistable element 14 (and in particular the electrode 38a) to the gate 16 of the access transistor 12.

As mentioned above, the manufacturing steps following the deposition and formation of the field programmable thin film 40 should use materials and manufacturing techniques that reduce and / or minimize the impact on the physical and electrical properties of the field programmable thin film 40. Can be advantageous. In this regard, using materials (eg, aluminum) and techniques for making electrodes 38b (deposition and / or forming techniques that use temperatures below the thermal budget of the electric field programmable thin film 40) is an electric field program. After deposition / application of the possible thin film 40, the impact on the electrical and / or physical integrity of the electric field programmable thin film 40 is minimized.

Further, as mentioned above, each electrode 38 may be manufactured, deposited, and / or formed from the same or different material using the same or different manufacturing techniques. In one embodiment, the thermal budget uses a first technique and a first material that requires higher temperature production, deposition, and / or formation to produce, deposit, and / or electrode 38a. It may be possible to form. After providing the electric field programmable thin film 40, the electrode 38b uses a second technique and / or a second material that facilitates production, deposition, and / or formation at relatively lower temperatures. , Manufactured, deposited, and / or formed. Thus, after deposition / application of electrode 38b, the electrical and / or physical integrity of the electric field programmable thin film 40 can be improved or maintained.

Referring to FIG. 5B, in another embodiment the electric field programmable thin film 40 is placed directly on the gate 16 of the access transistor 12. In this embodiment, the gate 16 further functions as an electrode of the electric field programmable bistable element 14.

Simply put, contacts 34 and 36 may be formed after manufacturing the access transistor 12. The electric field programmable thin film 40 may then be deposited, formed, and / or patterned on the gate 16 using, for example, any of the techniques described in the references described above.

Signal line 24 and sense / program signal line 26 are deposited, formed, and / or deposited from a conductive material (eg, aluminum or highly doped polysilicon) using conventional deposition, lithography, and etching techniques. Alternatively, it may be patterned. The electrode 38 can then (or at the same time) be deposited. It may be advantageous to use materials and techniques that maintain the physical and electrical integrity of the field programmable thin film 40 during the deposition, formation, and / or patterning process. As mentioned above, the electrode 38 is a conductive material (eg, heavy-doped semiconductor (eg, polysilicon) or metal (eg, aluminum, chromium, gold, silver, molybdenum, platinum, palladium, tungsten, titanium, and /). Or copper)).

It should be noted that the embodiment of FIG. 5B provides a more compact layout of memory cells 10 while using fewer manufacturing steps than memory cells 10 of FIG. 5A. Further, the embodiment of FIG. 5B can facilitate the realization of an electric field programmable thin film 40 with a relatively large thickness. This can improve the consistency and / or uniformity of the bistable electrical properties of the electric field programmable thin film 40 in the memory cells 10 of the memory array.

Read, write, and / or erase operations may be performed by controlling the amplitude and timing of the voltage applied to the access transistor 12 and the field programmable bistable element 14. For example, referring to FIGS. 6A and 7A, the signal line 22 is selected via the memory cell selection circuit 42, thereby making the access transistor 12 movable or first "on" and electroprogrammable bistable. When the element 14 is electrically coupled to the sense / program signal line 26 (via the access transistor 12), the data state of the memory cell 10 can be read. (See 50 in Figure 7A). Note that if memory cell 10 is one of many or more memory cells in a memory array, the memory cell selection circuit 42 may be a conventional wordline decoder / driver. is there. In fact, any wordline decoder / driver, whether currently known or later developed, is intended to be within the scope of the present invention.

A sense amplifier 44 (eg, a conventional cross-coupled sense amplifier) is connected to the sense / program signal line 26 to detect the data state of memory cell 10. In this regard, in one embodiment, the sense amplifier 44 detects the data state of memory cell 10 by comparing the voltages applied to the inputs 44a and 44b. The voltage applied to the input 44a of the sense amplifier 44 largely depends on the resistance characteristics of the electric field programmable bistable element 14 (which is pre-programmed as described below). The voltage applied to input 44b depends on the reference voltage provided or output by reference circuit 46.

In one embodiment, the reference circuit 46 may be a voltage reference or a current source. If the reference circuit 46 is a current source, the output current of the current source provides the appropriate voltage or current to the input 44b of the sense amplifier 44, which detects the data state of the field programmable bistable element 14. To enable. That is, in one embodiment, the amount of current output is between the amount of current equal to the high and low data states of the electric field programmable bistable element 14. In a preferred embodiment, the amount of current is approximately equal to half the sum of the amounts of current equal to the high and low data states of the electric field programmable bistable element 14.

In other embodiments, the reference circuit 46 includes at least two reference memory cells (not shown), each reference memory cell comprising a reference access transistor and a reference electric field programmable bistable element. In this embodiment, one of the reference memory cells is programmed to the high data state and one of the reference memory cells is programmed to the low data state. Reference circuit 46, in one embodiment, provides input 44b with a voltage approximately equal to half the sum of the two reference memory cells. The memory cell 10 is read by coupling the electric field programmable bistable element 14 to the input 44a and the reference voltage generated by the reference circuit 46 to the input 44b.

See above to track and / or process changes in memory cell characteristics due to changes in operating conditions (eg, temperature and / or power fluctuations) or manufacturing conditions (eg, wafer film thickness fluctuations). It may be advantageous to use a memory cell configuration.

Therefore, the circuits used to read the data state of memory cell 10 (eg, sense amplifier 44 and reference circuit 46) use voltage or current sense techniques to capture the data state stored in memory cell 10. Sense. Such circuits and circuit configurations are well known in the art. (See, for example, Patent Document 6 and Patent Document 7). In fact, any circuit or architecture for sensing, sampling, detecting, or determining the data state of memory cell 10, whether currently known or later developed, is within the scope of the invention. Intended to be.

The reference voltage circuit 48 may, in one embodiment, be a circuit that provides a stable reference voltage (eg, ground potential or zero volt). In other embodiments, the reference voltage circuit provides a constant control signal with well-defined voltage levels and timing characteristics.

Note that a path gate and / or column switch circuit (not shown) is used to selectively connect the access transistor 12 (field programmable bistable element 14) to the sense amplifier 44 to memory. -It is possible to facilitate and / or realize the operation of reading the data state of the cell 10.

With reference to FIGS. 6B and 7B, the data state of memory cell 10 couples the field programmable bistable element 14 to the sense / program signal line 26 and is suitable for the field programmable thin film of the field programmable bistable element 14. It may be programmed by applying a high voltage. In this regard, the memory cell selection circuit 42 applies a sufficiently high voltage (for N-channel devices) to the signal line 22 (see 50 in FIG. 7B) to access the access transistor 12 (ie, ie). , Turn on the forward bias transistor 12). In this way, the electric field programmable bistable element 14 is electrically coupled to the sense / program signal line 26.

While the access transistor 12 is "on", the programming circuit 52 applies an appropriate voltage to store either logic high or logic low. In this regard, referring to FIG. 2, when a voltage difference of about 4.5 volts is provided or applied to the electric field programmable thin film 40, the electric field programmable bistable element 14 stores the logical height. (See Figure 7B). In contrast, providing or applying a voltage difference of about 2 volts to the field programmable thin film eliminates the logic height, which causes the field programmable bistable element 14 to store the logic low. (See Figure 7C and / or Figure 7D). The 2 volt voltage difference may be provided by controlling the voltage applied to the control signal lines 24 and 26.

Note that a path gate and / or column switch circuit (not shown) is used to selectively connect the access transistor 12 to the programming circuit 52, facilitating the programming operation of memory cell 10. And / or what can be achieved. In addition, a switch (eg, a transistor, etc.) can be used to connect the reference voltage circuit to the signal line 24 of the selected / addressed memory cell 10.

There are many different techniques (and circuits for doing so) to achieve erase and write operations. All such techniques and circuits, whether known or later developed, are intended to fall within the scope of the invention. For example, the programming circuit 52 may be a switch with one "terminal" coupled to ground or reference (eg, implemented by a transistor). In this way, the reference voltage circuit 48 can be programmed (erased or written) by applying an appropriate voltage to the control signal line 24.

The memory cell 10 is often used or implemented in a memory array 56 having a plurality of memory cells 10. Referring to FIG. 8A, in one embodiment, memory cells 10aa-10xx are located at the intersection of the matrix in rows 58a-58x and columns 60a-60x. Peripheral circuitry 62 (eg, clock alignment circuit, address Decoding, word line drivers, row drivers, output drivers, sense amplifiers, and reference voltage circuits) can be included. Note that with reference to FIG. 8B, the memory device can include multiple memory arrays (or sub-arrays), such as arrays 56a-56d. In fact, the memory cells 10aa-10xx of the memory array 56 may be arranged or configured in any architecture or layout. Such architectures or layouts, whether known or later developed, include, for example, arrays, subarrays, and addressing architectures or layouts.

In another aspect, the invention comprises multiple memory cells, each memory cell having a unique, different and / or separate electric field programmable bistable element and a common access transistor. In this aspect of the invention, the electric field programmable bistable elements of the memory cell "share" the access transistor. That is, multiple memory cells include a common access transistor and unique, different and / or separate electric field programmable bistable elements.

Referring to FIG. 9, in one embodiment, one access transistor 12 is coupled to a plurality of electric field programmable bistable elements 14a-14n. Each of the electric field programmable bistable elements 14a-14n stores individually addressable data. In this regard, by controlling the voltage levels of signal lines 22, 24a-24n, and 26, data states can be individually written and read (sequentially or) to the field programmable bistable elements 14a-14n. In parallel).

The plurality of memory cells 10a to 10n in FIG. 9 may be manufactured using a number of techniques. In addition, memory cells 10a-10n may include a number of different configurations and layouts. For example, referring to FIGS. 10A and 10B, in at least one embodiment, the electric field programmable bistable elements 14a-14c may be arranged on top of the access transistor 12 in a stack array. In this way, the density of memory devices including this aspect of the invention can be increased.

Specifically, continuing with reference to FIG. 10A, memory cells 10a-10c include field programmable bistable elements 14a-14c and shared or common access transistors 12, respectively. Electric field programmable bistable element 14a is electrode 38a₁~ 38a₂Includes an electric field programmable thin film 40a placed between. Electrode 38a₁Is electrically connected to the source 18 of the access transistor 12 via the contact 34. Electrode 38a₂Is connected to signal line 24a (not shown). In fact, in one embodiment, the electrode 38a₂Is the signal line 24a.

Electric field programmable bistable element 14b, electrode 38b₁And 38b₂Includes an electric field programmable thin film 40b placed between and. Conductive via V1 to source 18 of access transistor 12 electrode 38b₁(Electrode 38a)₁And via contact 34). Electrode 38b₂Is connected to signal line 24b (not shown).

Similarly, the electric field programmable bistable element 14c has an electrode 38c.₁And 38c₂Includes an electric field programmable thin film 40c placed between and. Conductive vias to source 18 of access transistor 12 electrode 38c₁(Electrode 38a)₁And 38b₁, Conductive via V1, and via contact 34). Electrode 38c₂Is connected to signal line 24c (not shown).

Note that in one embodiment, the electrode 38a₁, 38b₂, 38c₂Can be signal lines 24a to 24c, respectively.

With reference to FIG. 10B, in this aspect of the invention, other exemplary layouts of memory cells 10 include a denser configuration than shown in FIG. 10A. In this regard, the field programmable bistable elements 14a and 14b "share" the electrode 38ab. Similarly, the field programmable bistable elements 14c and 14d "share" the electrode 38cd. In this way, less manufacturing processes and materials can be used to provide a more compact and dense memory array. It should be noted that all layouts of memory cells 10 in this aspect of the invention are intended to fall within this scope of the invention, whether known or later developed.

Therefore, referring to FIGS. 10A, 11A, and 11B, memory cells 10a-10c in this aspect of the invention include a stacked layout configuration. That is, the access transistor 12 is arranged in the substrate 32, and the electric field programmable bistable elements 14a to 14c are arranged in the layers 64a to 64c of the memory array 56, respectively. Each layer 64a-64c of the memory array 56 has multiple memory cells 10aa-10xx with access transistors 12 and field programmable bistable elements 14 of layer 64 located in or on board 32. Including. (See Figure 11B).

It should be noted that, as mentioned above, the transistors 12 may be manufactured, formed, arranged, and / or placed in different (eg, "higher") planes or layers with respect to the single crystal substrate. is there. In this regard, the transistor 12 may be manufactured from or in polysilicon, amorphous silicon, or other non-crystalline material. In this situation, a three-dimensional array of memory may be manufactured in which one or more layers can contain access transistors (and / or peripheral circuits) (in addition to or on behalf of the board). (See, for example, layer 68 in Figures 23A-23C). Thus, the field programmable bistable element 14 may be formed, placed, and / or placed in layers or planes above and / or below such transistors. In addition, the transistor 12 is an electric field programmable twin formed, placed, and / or placed in a layer or plane above and / or below the layer and / or plane on which the transistor 12 is formed, placed, and / or placed. It may be associated with the stabilizer 14. (See, for example, Figure 23B and Figure 23C).

The memory cells 10 of the three-dimensional array 56 of the memory of FIGS. 11A and 11B may be arranged or configured in any architecture or layout, whether known or later developed. For example, the orientation of subarrays and / or subarray sections can be three-dimensional or two-dimensional (either vertical or horizontal). In this way, the orientation of the sub-array and / or sub-array section may be chosen to improve addressing, read, write, and / or erase operations, eg, to occur.

In addition, the orientation of the sub-array and / or sub-array section may be chosen to minimize peripheral circuitry. For example, a subarray may be defined as a vertical plane perpendicular to the surface of the substrate 32, and peripheral circuits can be located in most areas of the substrate 32 and consume that area.

The write or programming operation of memory cells 10a-10n applies a control voltage to the access transistors 12 and signal lines 24a-24n, which activates or turns on the access transistors 12 and is an electric field programmable bistable element 14. It is executed by storing the appropriate data state. Referring to FIG. 12A, the data state of the memory cell 10a is, for example, the electric field programmable bistable element 14a coupled to the sense / program signal line 26 and the electric field programmable bis through the programming circuit 52 and the reference voltage circuit 48. It may be programmed by applying an appropriate voltage to the field programmable thin film of stabilizer 14a. In this regard, the memory cell selection circuit 42 activates or turns on the access transistor 12 by applying an appropriate positive voltage to the signal line 22 (in the case of an N-channel transistor). In this way, the electric field programmable bistable element 14a is electrically coupled to the sense / program signal line 26.

The programming circuit 52 then applies the appropriate voltage (in relation to the voltage applied to the signal line 24 by the reference voltage circuit 48) while the access transistor 12 is "on" and is field programmable bistable. Either logical high or logical low is stored in the element 14a. For example, in one embodiment (see, for example, the current-voltage characteristics of the exemplary thin film in FIG. 2), providing or applying a voltage difference of approximately 4.5 volts to the electric field programmable thin film of the field programmable bistable element 14a The logical height is memorized. In contrast, providing or applying a voltage difference of about 2 volts to the field programmable thin film of the field programmable bistable element 14a erases the logic height, thereby storing the logic low. The 2 volt voltage difference may be provided by applying the appropriate voltage to the control signal lines 24 and 26. (See, for example, Figure 7C and Figure 7D).

Referring to FIG. 12B, in one embodiment, the data state of the memory cell 10a is obtained by moving the access transistor 12 or by first "turning on" the signal line 22 via the memory cell selection circuit 42. Is read (by applying a control signal to). It electrically couples the field programmable bistable element 14a (via the access transistor 12) to the sense / program signal line 26. Note that the reference voltage (eg, ground) is applied to the signal line 24a by the reference voltage circuit 48.

As mentioned above, the sense amplifier 44 (eg, a conventional cross-coupled sense amplifier) is connected to the sense / program signal line 26 to detect the data state of the memory cell 10. For the sake of brevity, those explanations are not repeated but summarized. The sense amplifier 44 may be a voltage or current based amplifier. The sense amplifier 44 detects the data state of memory cell 10a by comparing the voltages or currents applied to the inputs 44a and 44b. For example, the voltage applied to the input 44a of the sense amplifier 44 is highly dependent on the resistance characteristics of the electric field programmable bistable element 14a. The voltage applied to input 44b depends on the reference voltage, which is the output of reference circuit 46.

Note that a path gate and / or column switch circuit (not shown) is used to selectively connect the access transistor 12 (field programmable bistable element 14a) to the sense amplifier 44 and memory. It is possible to facilitate and / or realize the reading operation of the data state of the cell 10a.

As mentioned above, many different techniques (and circuits that implement such techniques) are used to perform read, write, and / or erase operations for memory cells 10a-10n in this aspect of the invention. ) Exists. All such techniques, and circuits for them, whether known or later developed, are intended to fall within the scope of the present invention.

Further, as mentioned above, memory cells 10a-10n may include a number of different configurations and layouts. In fact, the field programmable bistable elements 14a-14c may include different electrical properties, such as different "on" and / or "off" resistors, write and / or erase voltages. In this regard, in one embodiment, the sizes of the electric field programmable bistable elements 14a-14c can be different to provide different responses to a given control signal. In this way, the data states of the field programmable bistable elements 14a-14c may be read faster and / or simultaneously (compared to sequential read / write / erase embodiments). This is because, for example, the responses of the memory cells 10 including the electric field programmable bistable elements 14a-14c are different. Therefore, with reference to FIGS. 12A and 12B, the control signal lines 24a-24n can be used to write the data state to memory cells 10a-10n.

Referring to FIGS. 12C and 12D, when reading the data state of memory cells 10a-10n, the control signal lines 24a-24n are placed at the same or similar voltage levels (eg, shorted together) and the transistor 12 is Turned on, the resulting current or voltage is read by a number of sense amplifiers 44a-44n with different reference inputs 46a-46n, as shown in Figure 12C, and the result is a data output line (output A-~. Can be placed in N) or, as shown in Figure 12D, the resulting current or voltage can be read by an analog-to-digital converter (ADC) and the result can be placed in the data output line (outputs A-N). These and other methods can identify a large number of voltage (or current) signals or levels output by memory cells 10a-10n. Therefore, the data states stored in the plurality of memory cells 10 may be read out simultaneously or sequentially.

The memory cells 10a-10n in this embodiment of the present invention are, for example, the memory cells 10 described and illustrated in FIGS. 1A-1C, 2, 3A-3C, 4, 5A, and 5B. May be manufactured using the same techniques and materials as previously described with respect to. For the sake of brevity, those explanations are not repeated.

Further, the memory cells 10a to 10n in this embodiment of the present invention may be arranged in the configuration of the memory cells 10 of FIGS. 1A to 1C (described and exemplified above). For example, referring to FIG. 13, the electric field programmable bistable elements 14a-14n may be connected to the gate 16. It should be noted that the transistor 12 and the electric field programmable bistable elements 14a-14n of this embodiment are combined to form a logical OR or logical NOR configuration. In this embodiment, memory cells 10a-10n can further use a stacked layout configuration. In that case, the access transistor 12 is placed in or on the substrate 32, the field programmable bistable elements 14a-14n are placed in layers of the field programmable thin film 40, and these layers are located in the access transistor 12 (and the substrate). It is placed on top of 32). (See Figure 14A and Figure 14B). Therefore, each layer 64a-64n of the electric field programmable thin film 40 "effectively" contains a plurality of memory cells 10 (in combination with the access transistor 12), and the access transistor 12 is in the substrate 32 or Placed on top, the field programmable bistable element 14 is placed in layer 64. (See, for example, Figure 11B, Figure 14A, and Figure 14B).

The memory cells 10a-10n of FIG. 13 may be programmed by selectively controlling the voltage applied to the electric field programmable thin film 40 of the electric field programmable bistable element 14. In this regard, the memory cell selection circuit 42 applies a control signal to the signal lines 22a-22n to program (and store) the data state (or stored information) of the field programmable bistable elements 14a-14n. (Reading) is facilitated. Specifically, referring to FIGS. 15A and 15B, memory cell 10 is selected by applying a first control signal (having a predetermined voltage level) to one or more signal lines 22a-22n. Is programmed. A second control signal (having a predetermined voltage level) is applied to the node 66 by the programming circuit 52. Referring to FIG. 2, in one embodiment, the memory cell selection circuit 42 and the programming circuit 52 apply appropriate voltages to one or more selected memory cells with high or low logic. Remember one. In this regard, when a voltage difference of about 4.5 volts is provided or applied to the electric field programmable thin film 40, the logical height is stored in the electric field programmable bistable element 14. In contrast, providing or applying a voltage difference of about 2 volts to the field programmable thin film eliminates the logic height, thereby storing the logic low in the field programmable bistable element 14. The 2 volt voltage difference may be provided by applying the appropriate voltage to the control signal lines 24 and 26. Note that memory cells 10a-10n may be programmed in series or in parallel.

The data state stored in the memory cells 10a to 10n of FIG. 13 selects or makes the memory cells 10a to 10n movable by the control signal applied to the signal line 22 by the memory cell selection circuit 42, and the access transistor 12 It may be read by sensing the current or voltage response of. Specifically, referring to FIG. 15C, in one embodiment, for example, the data state of the memory cell 10a is read by applying a read voltage to the signal line 22a via the memory cell selection circuit 42. May be done. The memory cell selection circuit 42 gates the access transistor 12 to a voltage that represents the data state stored in the electric field programmable bistable element 14a (ie, due to the resistance characteristics of the previously programmed electric field programmable thin film). Apply to 16. The voltage at gate 16 of the access transistor 12 determines the operating characteristics of the access transistor 12, which is applied and sensed to the sense amplifier 44 (via node 44a).

The sense amplifier 44 (eg, a conventional cross-coupled sense amplifier) detects the data state of memory cell 10. In this regard, in one embodiment, the sense amplifier 44 detects the data state of memory cell 10 by comparing the voltages applied to the inputs 44a and 44b. The voltage applied to the input 44a of the sense amplifier 44 depends, at least in large part, on the resistance characteristics of the electric field programmable bistable element 14a, the impact of which depends on the operating characteristics of the access transistor 12. The voltage applied to the input 44b depends on the reference voltage, which is the output of the reference circuit 46.

As mentioned above, the reference circuit 46 may be a voltage reference or a current source, and the reference voltage circuit 48 is, in one embodiment, a stable reference voltage (eg, an N-channel transistor in this embodiment). It may be a circuit that provides a stable and highly controllable positive voltage to turn on or move the transistor 12. For the sake of brevity, those explanations are not repeated here.

It should be noted that the circuits used to read the data state of memory cells 10a-10n (eg, sense amplifier 44 and reference circuit 46) may use well-known circuits, configurations, and techniques. is there. Any circuit, architecture, or technique that senses, samples, detects, or determines the data state of memory cells 10a-10n, whether known or later developed, is within the scope of the invention. Intended to enter.

Note that a path gate and / or column switch circuit (not shown) is used to selectively connect the access transistor 12 (field programmable bistable element 14a) to the sense amplifier 44 and memory. The operation of reading the data state of cell 10 may be facilitated and / or realized.

In another aspect, the invention includes a differential memory cell having a plurality of memory cells configured to store complementary data states. In this regard, referring to FIG. 16, differential memory cell 100 includes first memory cell 10a and second memory cell 10b, where first memory cell 10a is second memory cell 10b. Maintains a complementary state to. Each of the memory cells 10a and 10b includes an access transistor 12 and an electric field programmable bistable element 14. Therefore, when programmed, one of the memory cells (eg, 10a) stores the logical low and the other memory cell (10b in this example) stores the logical high.

Memory cells 10a and 10b of differential memory cell 100 are manufactured, configured, and / or controlled as described and illustrated with respect to any embodiment of the aspects of the invention described herein. You can. In addition, memory cells 10a and 10b may include layouts as described and illustrated for any embodiment of the aspects of the invention described herein. (See, for example, Figures 18A-18C). For the sake of brevity, their details, descriptions, and examples are not repeated.

Simply put, the data state of a two-transistor differential memory cell 100 is read by sampling, sensing, measuring, and / or detecting the logical state stored in each cell 10 of the differential memory cell 100. It may be issued and / or determined. That is, the memory cell 100 may be read by sampling, sensing, measuring, and / or detecting the difference in resistance values stored or presented in the field programmable bistable elements 14a and 14b. In the first logical state of memory cell 100, memory cell 10a stores the logical low and memory cell 10b stores the logical high. In contrast, in the second logical state of differential memory cell 100, memory cell 10a stores the logical height and memory cell 10b stores the logical low. Differences in resistance values may be sampled, sensed, measured, and / or detected using current or voltage based techniques.

Continuing with reference to FIGS. 16 and 17A, the state of differential memory cell 100 may be read and / or determined by the sense amplifier (comparator) 44. The sense amplifier 44 may be a voltage or current comparator (eg, a cross-coupled sense amplifier). In this regard, the sense amplifier 44 compares the current or voltage (this depends on the resistance value stored or presented in the field programmable bistable elements 14a and 14b). The current or voltage sensed by the sense amplifier 44 represents different logical states stored in memory cells 10a and 10b.

Therefore, the differential memory cell 100 of this aspect of the invention may include some advantages over the memory cell 10 of another aspect of the invention. Among these advantages are, for example, (i) the logical state is determined by the difference between the states of memory cells 10a and 10b, so the read operation is not sensitive to fluctuations in the value of the binary state, (ii) eg. , The reference circuit 46 of FIG. 6 is not always necessary, (iii) the differential memory cell 100 may contain a larger read window (eg, compare with the memory cells described with respect to FIGS. 1A-1C). And) is included.

Referring to FIG. 17B, in one embodiment, while the access transistors 12a and 12b are on, the programming circuit 52 applies the appropriate voltage (sequentially or simultaneously) and is either logically high or logically low. Remember one. In this regard, referring to FIG. 2, providing or applying a voltage difference of about 4.5 volts to the electric field programmable thin film 40 stores a logical height in the electric field programmable bistable element 14. In contrast, providing or applying a voltage difference of about -2 volt to an electric field programmable thin film eliminates the logic height, thereby storing the logic low in the field programmable bistable element 14. This may be provided by applying such a voltage difference to the electric field programmable bistable element 14 via the control signal lines 24 and 26.

In one embodiment, memory cells 10a and 10b have the same or similar properties. If the memory cells 10a and 10b are designed to have the same or similar properties, it may be advantageous to place the memory cells 10a and 10b physically or spatially close together. Thus, during manufacturing, memory cells 10a and 10b are manufactured with little or no process variation and therefore (i) access transistors 12a and 12b of memory cells 10a and 10b are identical, respectively. Or it will have similar electrical, physical, doping concentration and / or profile properties, and (ii) the field programmable bistable elements 14a and 14b of memory cells 10a and 10b will be the same or similar electrical, respectively. Comes to have properties. In fact, memory cells 10a and 10b of memory cell 100 will change in the same or similar manner with respect to temperature and time.

A memory device can include an array of differential memory cells 100 (ie, multiple memory cells arranged in an iterative pattern). (See, for example, Figure 22A and Figure 22B). Memory cells 100 may be arranged in an array in many different ways. For example, memory cell 100 may be manufactured in a stack configuration with a plurality of layers 64. Each of the layers comprises an electric field programmable bistable element coupled to a "shared" or common access transistor previously described with respect to a second aspect of the invention. (See Figure 22A). In this embodiment, each layer of the electric field programmable thin film 40 "effectively" contains a plurality of memory cells 100aa to 100xx (in combination with the shared access transistor 12), where the access transistor 12 is the substrate 32. Placed in or on top of, the field programmable bistable element 14 is placed in one of a plurality of layers 64.

In one embodiment, the differential memory cell 100 may include a first memory cell comprising an access transistor and an electric field programmable bistable element located on the first layer 64a. The memory cell 100 may include a second memory cell comprising the same access transistor and an electric field programmable bistable element located on the second layer 64b. (See, for example, the layouts in Figures 10A, 10B, 14A, and 14B). In this way, the memory cells of the differential memory cell 100 are spatially placed in close proximity to each other. This can minimize, reduce, or eliminate environmental (ie, temperature) and / or process variability between the first and second memory cells. This is because each memory cell contains a common access transistor and the field programmable bistable element of the differential memory cell 100 is located on the adjacent layer 64.

In another embodiment, the differential memory cell 100 is a first memory cell comprising (1) an access transistor and an electric field programmable bistable element located in the first layer of the electric field programmable thin film. , (2) A second memory cell comprising an access transistor adjacent to the access transistor of the first memory cell and an electric field programmable bistable element located in the first layer of the electric field programmable thin film. Can include. In this way, the memory cells of the differential memory cell 100 are spatially placed in close proximity to each other. This can minimize, reduce, or eliminate environmental (ie, temperature) and / or process variability between the components of the first and second memory cells, as described above.

Further, as mentioned above, the transistor 12 may be manufactured, formed, arranged, and / or installed in a different (eg, "higher") plane or layer than the substrate 32. In this regard, the transistor 12 may be manufactured from or within them from polysilicon, amorphous silicon, or other non-crystalline material. In this situation, a three-dimensional array of memory can be manufactured in which one or more layers (in addition to or on behalf of the substrate) can contain transistors. (See, for example, layer 68 in Figures 23A-23C). Thus, the field programmable bistable element 14 may be formed, arranged, and / or installed in layers or planes above and / or below such transistors. (See, for example, Figure 23B and Figure 23C).

In fact, it would be advantageous to recrystallize the polysilicon layer placed on the substrate in order to improve the operating characteristics of the transistors placed or manufactured in the polysilicon layer. In this way, a three-dimensional array of memory can include one or more single crystal silicon or semiconductor layers (in addition to or on behalf of the substrate), with transistors in such layers. Placed or manufactured.

Note that the memory cell 100 of the memory device may also be manufactured in a non-stacked configuration. In the non-stack configuration, the field programmable bistable elements located on a single layer 64 are coupled to the associated access transistors located on the substrate 32. (See Figure 22B).

All layout configurations of access transistors associated with field programmable bistable elements are intended to be within the scope of the present invention, whether known or later developed. (See, for example, Figures 16 and 18A-18C). For example, in one layout, memory cells 10a and 10b are configured to have separate sense lines 24a and 24b, respectively. (Compare Figure 16 with Figure 18A).

In other embodiments, differential memory cells can include multiple memory cells, which include one access transistor and two or more electric field programmable bistable elements 14. It is configured to store complementary data states. In this regard, referring to FIG. 19, differential memory cell 100 includes first memory cell 10a and second memory cell 10b, where first memory cell 10a is second memory cell 10b. Maintains a complementary state to. Memory cells 10a and 10b "share" the access transistor 12. In addition, each of the memory cells 10a and 10b includes field programmable bistable elements 14a and 14b, respectively.

It should be noted that the differential memory cell 100 of FIG. 19 presents a denser or more compact memory cell than the memory cell 100 shown in FIG. 16 (due to the sharing of access transistors). ).

Continuing with reference to FIG. 19, memory cells 10a and 10b of differential memory cell 100 are manufactured, configured, and / or as described and illustrated with respect to embodiments of any aspect of the invention. It may be controlled. In addition, memory cells 10a and 10b may include layouts and configurations as described and illustrated with respect to embodiments of any aspect of the invention described herein. (See, for example, Figures 9-18C). In this regard, the field programmable bistable elements 14a and 14b may be connected to the gate 16, drain 20 or to source 18 as illustrated in FIG. For the sake of brevity, their details, descriptions, and examples are not repeated.

The description of read, program, and erase operations for differential memory cell 100 in FIG. 16 applies equally to differential memory cell 100 shown in FIG. For the sake of brevity, those explanations are not repeated, but are briefly summarized.

With reference to FIG. 20A, the data state of one transistor differential memory cell 100 shall sample, sense, measure, and / or detect the logical state stored in each memory cell 10a and memory cell 10b. May be read and / or determined by. That is, the memory cell 100 may be read by sampling, sensing, measuring, and / or detecting the difference in resistance values stored or presented in the field programmable bistable elements 14a and 14b. In this regard, in one embodiment, the control signal line 22 is raised to Vpp (via the memory selection circuit 42) and the control signal line 24 is maintained at 0V. 0V is the common voltage and / or reference voltage (via reference voltage circuit 48) (see, for example, Figure 7A). Differences in resistance values may be sampled, sensed, measured, and / or detected using current or voltage based techniques (via the sense amplifier 44). Note that in the first logical state of memory cell 100, memory cell 10a stores the logical low and memory cell 10b stores the logical high. In contrast, in the second logical state of differential memory cell 100, memory cell 10a stores the logical height and memory cell 10b stores the logical low.

Referring to FIG. 20B, in one embodiment, the data state of one transistor differential memory cell 100 turns access transistor 12 "on" (via memory selection circuit 42 and reference voltage circuit 48). Sequentially or simultaneously, appropriate voltages may be applied to the control signal lines 26a and 26b (via programming circuit 52) and programmed and / or erased by storing either logic high or logic low. For example, applying V + to gate 16 of transistor 12 (via memory selection circuit 42) and applying 0V or common voltage to source 18 (via reference voltage circuit 48) while applying 4.5V to signal line 26a. The logic height is stored in the differential memory cell 100 in response to the application and the application of 2.5V to the signal line 26b. In contrast, V + is applied to gate 16 of transistor 12 (via memory selection circuit 42), 0V is applied to source 18 (via reference voltage circuit 48), and 2.5V is applied to signal line 26a. Then, in response to applying 4.5V to the signal line 26b, the logic low is stored in the differential memory cell 100.

Again, the description of the read, program, and erase operations of the differential memory cell 100 of FIG. 16 is equally applicable to the differential memory cell 100 illustrated in FIG.

In another aspect, the invention includes complementary memory cells, the complementary memory cells having N-channel and P-channel memory cells, storing at least four different data states. .. In this regard, referring to FIGS. 21A-21C, the complementary memory cell 200 is a first memory cell 10a having an N-channel access transistor 12a and a field programmable bistable element 14a, and a P-channel. Includes a second memory cell 10b with an access transistor 12b and an electric field programmable bistable element 14b. In this embodiment, the gates 16a and 16b of the N-channel access transistor 12a and the P-channel access transistor 12b are connected and / or controlled together by a common signal (word) line 22, respectively.

Memory cells 10a and 10b of complementary memory cells 200 are manufactured, configured, and / or controlled as described and illustrated with respect to embodiments of any aspect of the invention described herein. May be done. In addition, memory cells 10a and 10b may include layouts as described and illustrated for embodiments of any aspect of the invention described herein. For the sake of brevity, their details, descriptions and examples are not repeated.

Simply put, the data state of a two-transistor complementary memory cell 200 is to sample, sense, measure, and / or detect the logical state stored in each memory cell 10 of the complementary memory cell 200. May be read and / or determined by. That is, the complementary memory cell 200 may be read by sampling, sensing, measuring, and / or detecting the difference in resistance values stored or presented in the field programmable bistable elements 14a and 14b.

The state of complementary memory cells 200 may be read and / or determined by a sense amplifier (comparator). The sense amplifier may be a voltage or current type comparator (eg, a cross-coupled sense amplifier). In this regard, the sense amplifier delivers the current or voltage of one of the memory cells 12a or 12b, which depends on the resistance value stored or presented in the field programmable bistable elements 14a and 14b (eg,). Compare with the reference voltage or current (provided via reference circuit 46). The current or voltage sensed by the sense amplifier 44 represents different logical states stored in memory cells 10a and 10b.

Specifically, the memory cell 10a may be read by raising the applied Vpp to the gate of the access transistor 12a (via the control signal line 22) and turning the transistor 12a "on". In this way, the resistance of the electric field programmable thin film 14a may be sensed by the sense amplifier 44. Memory cells 12b may be read by applying a low voltage (eg, 0 volt or ground / common) to the gate of access transistor 12b to turn transistor 12b on. In this way, the resistance of the electric field programmable thin film 14b may be sensed by the sense amplifier 44.

The state of complementary memory cells 200 is a programming circuit by applying an appropriate voltage to store either logical high or logical low while one of the access transistors 12a and 12b is "on". May be written or erased by 52. In this regard, the control signal line 22 is raised to Vpp to "on" the access transistor 12a and provide or apply a voltage difference of approximately 4.5 volts to the field programmable thin film 40 so that the logic height is field programmable. It may be stored in the bistable element 14a (see Figure 2). In contrast, providing or applying a reverse voltage difference of approximately 2 volts to the field programmable thin film 14a (while the transistor 12a is "on") eliminates the logic height, thereby field programmable bistable. The logic low is stored in the element 14a. The 2 volt voltage difference may be provided by controlling the voltage applied to the control signal lines 24 and 26.

A sufficiently low voltage (eg, 0 volt) is applied to the gate 16b of the access transistor 12b (via the control signal line 22) to "on" the access transistor 12b and about 4.5 volt to the field programmable thin film 40. The logical height may be stored in the field programmable bistable element 14b by providing or applying a voltage difference of. (See Figure 2). Alternatively (while transistor 12b is "on"), a logic low is stored in the field programmable bistable element 14b by providing or applying a voltage difference of approximately 2 volts to the field programmable thin film 14b. May be done (or the logical height may be erased). As mentioned above, the 2 volt voltage difference may be provided by controlling the voltage applied to the control signal lines 24 and 26.

Similar to the memory device having an array of differential memory cells 100 described above, the memory device includes an array of complementary memory cells 200 (ie, multiple memory cells arranged in an iterative pattern). It's fine. (See, for example, Figure 22C and Figure 22D). Complementary memory cells 200 may be arranged in an array in many different ways. For example, complementary memory cells 200 may be manufactured in a stack configuration with multiple layers 64. Each of the plurality of layers 64 includes an electric field programmable bistable element coupled to the corresponding access transistor, as previously described with respect to the second aspect of the invention. (See Figure 22C). In this embodiment, each layer of the electric field programmable thin film 40 "effectively" contains a plurality of memory cells 200aa-200xx (together with the access transistor 12) and the access transistor 12 (N channel). And the P channel) are located in or on the substrate 32, and the field programmable bistable element 14 is located in one of multiple layers 64.

Further, as mentioned above, the transistor 12 may be manufactured, formed, arranged, and / or placed on a different (eg, "higher") plane or layer than the substrate 32. In this regard, the transistor 12 may be manufactured from or within them from polysilicon, amorphous silicon, or other non-crystalline material. In this situation, a three-dimensional array of memory can be manufactured in which one or more layers (in addition to or on behalf of the substrate) can contain transistors. (See, for example, layer 68 in Figures 23A-23C). Thus, the field programmable bistable element 14 may be formed, placed, and / or installed in layers or planes above and / or below such transistors. In addition, N-channel access transistors are manufactured in one or more layers (eg, substrate 32, or above or below substrate 32) and one or more different layers (eg, substrate 32, etc.). Or it would be advantageous to manufacture the P-channel access transistor in (above or below) the substrate 32.

Note that the memory cell 200 of the memory device may be manufactured in a non-stacked configuration. In the non-stack configuration, the field programmable bistable elements located in a single layer 64 are coupled to the associated access transistors located in the substrate 32. (See Figure 22D). All layout configurations of access transistors (either N-channel or P-channel access transistors) associated with field programmable bistable elements, whether known or later developed, are presented in this book. Intended to be within the invention. (See, for example, Figures 21A-21E).

Although certain embodiments, features, substances, configurations, attributes, and advantages of the present invention have been described and exemplified, many other, different and / or similar embodiments, features, substances of the present invention. It should be understood that the composition, attributes, structure, and advantages are apparent from the description, illustration, and claim. Accordingly, the embodiments, features, substances, configurations, attributes, structures, and advantages of the present invention described and exemplified herein are not exhaustive and such other similar and different of the present invention. It should be understood that the above embodiments, features, substances, configurations, attributes, structures, and advantages fall within the scope of the present invention.

For example, the electric field programmable thin film 40 of memory cell 10 (and memory cell 100) described above can include a plurality of thin films. That is, the electric field programmable thin film 40 can include two separate / layered electric field programmable thin films described in Patent Document 4 of the electric field programmable thin film.

Further, a significant portion of this description includes details directed to N-channel access transistors (eg, erase, write, and read voltages), but the invention described herein (and embodiments thereof). Is fully applicable to P-channel access transistors. In addition, the circuits around the memory array (eg, word line decoders / drivers and comparators not illustrated here) may include P-channel and / or N-channel transistors. Voltages that control such transistors are well known in the art in the light of this disclosure. Therefore, for the sake of brevity, those explanations are not repeated.

Moreover, as mentioned above, there are many different techniques (and circuits that implement such techniques) that read and write data from memory cells 10 and 100. All such techniques, and circuits for them, whether known or later developed, are intended to fall within the scope of the present invention. For example, by including a separate word signal line 22, a read and write operation or a read and erase operation is sequentially performed on the electric field programmable bistable elements 14a and / or 14b of the memory cells 100 of FIGS. 17A and 17B. Or it may be run in parallel (and independently).

As mentioned above, transistors and electrodes may be manufactured using standard manufacturing techniques (eg, spin-on, sputtering, deposition, and photolithography). However, non-standard manufacturing techniques may also be used. Such non-standard or non-conventional techniques would be advantageous in creating, providing, and / or forming electrically programmable thin films and electrode structures. For example, nano-imprinting, patch die coating, slot or protrusion coating, slide or cascade coating, curtain coating, roll coating, eg knife over roll (doctor blade) coating, forward and reverse. Directional roll coating, gravure coating, dip coating, spray coating, meniscus coating, spin coating, brush coating, air knife coating, silk screen printing process, electrostatic printing process, heat Printing processes, inkjet printing processes, direct transfer, eg laser-assisted excision from carriers, self-assembly or direct growth, electrolytic deposition, non-electrolytic deposition, electrolytic polymerization, CVD, MOCVD, and PVD are electrodes and / or Electrode programmable thin films are all techniques that are advantageously deposited, formed, structured, patterned, and / or provided.

Further structuring or patterning of electrode and / or field programmable thin films is by lift-off techniques or patterning by chemical, physical, electrical, or photoresolved etching, removal, or ablation (eg, laser ablation). Realized and / or may be obtained. In fact, the types, composition, deposition, formation, structuring, patterning, and modification of electrodes, electrode materials, and electric field programmable thin films may affect the performance of the resulting device. Therefore, from a performance and reliability standpoint, it is best to choose from a range of electrode materials, such as organic, inorganic, organic metals, metals, metal oxides, nitrides, chalcogenides, pnictides, and semiconductors. It would be advantageous.

Further, for example, by chemically modifying the surfaces of (1) electrodes, electric field programmable thin films, or both, and / or (2) physically the surfaces of the electrodes, electric field programmable thin films, or both. By modifying and / or (3) one or more additional layers that modify the physical properties of the contact between the electrode and the field programmable thin film, such as the coupling layer, diffusion barrier, and / or buffer layer. By introducing and / or introducing one or more additional layers that modify the electrical properties of the contact between the electrode and the field programmable thin film, eg, a layer of metal or metal oxide with a particular work function. By doing so, it may be advantageous to modify, adjust, and / or control the interface between the electrodes and the field programmable thin film in one or more ways.

In addition, field programmable thin films and / or electrodes add additional materials, such as flow and wet aids, adhesion promoters, and / or anticorrosive agents, to improve, improve, and / or modify certain properties of the interface. It may be incorporated. Material selection and modification may favor properties such as chemical, physical, mechanical, thermal, or electrical compatibility, thereby improving device performance.

As mentioned above, the transistor 12 may be manufactured from or in any semiconductor material. Such semiconductor materials include, for example, silicon carbide, gallium arsenide, or organic materials, such as pentacene. (See, for example, layer 68 in Figures 23A-23C). All methods of making the transistor 12 (and the material used therein), whether known or later developed, are intended to fall within the scope of the present invention. For example, transistor 12 may be manufactured in polysilicon or amorphous silicon. Such a configuration can facilitate a three-dimensional array of memory in which one or more layers (in addition to or on behalf of the substrate) placed on the substrate 32 can contain transistors 12. In fact, it may be advantageous to recrystallize the polysilicon layer placed on the substrate 32 in order to improve the operating characteristics or density of the transistors 12 placed or manufactured in the polysilicon layer. I don't know.

In addition, in other embodiments, a plurality of thin single crystal wafers can be coupled to provide a three-dimensional array of multiple memories. A three-dimensional array of such memories has transistors arranged or manufactured in the "top" layer of the "board" or in a layer spaced from the "board". Field programmable bistable elements 14 (electrode 38 and field programmable) in or between such thin single crystal wafers (including N-channel and / or P-channel transistors) to provide a three-dimensional array of memory. (Including thin film 40) can be placed.

It should be further noted that the term "circuit" is, in particular, a single component or multiple components that are active and / or passive and are combined together to provide or perform the desired function. It can mean (whether or not it is an integrated circuit type). The term "circuit" specifically refers to a circuit (whether in integrated circuit form or not), a group of such circuits, a processor, processor realization software, or a circuit (whether in integrated circuit form or not). Can mean a combination of, a group of such circuits, a processor and / or processor implementation software, a processor and circuit, and / or a processor and circuit implementation software. The term "data" can mean, in particular, a current or voltage signal, whether in analog or digital form. The term "measurement" specifically means sampling, sense, inspection, detection, monitoring, and / or capture. Terms such as "sampling" or "sample" can mean, in particular, recording, measuring, detecting, monitoring, and / or sensing.

<figref num="1A">An exemplary schematic of a memory cell embodiment, the embodiment comprising an access transistor and an electric field programmable bistable thin film device according to aspects of the present invention.</figref><figref num="1B">An exemplary schematic of a memory cell embodiment, the embodiment comprising an access transistor and an electric field programmable bistable thin film device according to aspects of the present invention.</figref><figref num="1C">An exemplary schematic of a memory cell embodiment, the embodiment comprising an access transistor and an electric field programmable bistable thin film device according to aspects of the present invention.</figref><figref num="2">FIG. 5 is a graph of current / voltage switching characteristics of an electric field programmable bistable thin film device including an exemplary electric field programmable bistable thin film according to one embodiment of the present invention.</figref><figref num="3A">FIG. 5 is a cross-sectional view of an exemplary layout of a memory cell according to an embodiment of one embodiment of the present invention, wherein the electric field programmable bistable thin film device is the source of the access transistor shown in the schematic of FIG. 1A. Note that FIG. 3A is a cross-sectional view coupled to the drain region and cut along the dot line AA in FIG.</figref><figref num="3B">FIG. 5 is a cross-sectional view of an exemplary layout of a memory cell according to an embodiment of one embodiment of the present invention, wherein the electric field programmable bistable thin film device is the source of the access transistor shown in the schematic of FIG. 1A. It is sectional drawing connected to the drain region.</figref><figref num="3C">FIG. 5 is a cross-sectional view of an exemplary layout of a memory cell according to an embodiment of one embodiment of the present invention, wherein the electric field programmable bistable thin film device is the source of the access transistor shown in the schematic of FIG. 1A. It is sectional drawing connected to the drain region.</figref><figref num="4">FIG. 5 is a plan view of an exemplary layout of memory cells schematically represented in FIG. 1A.</figref><figref num="5A">A cross-sectional view of an exemplary layout of a memory cell, in which an electric field programmable bistable thin film device is coupled to the gate of an access transistor shown in the schematic of FIG. 1B according to certain embodiments of the present invention. Is.</figref><figref num="5B">A cross-sectional view of an exemplary layout of a memory cell, in which an electric field programmable bistable thin film device is coupled to the gate of an access transistor shown in the schematic of FIG. 1B according to certain embodiments of the present invention. Is.</figref><figref num="6A">It is an exemplary schematic of a memory cell of one embodiment of the invention combined with a read or sense amplifier and a memory cell selection circuit according to an embodiment of the invention.</figref><figref num="6B">It is an exemplary schematic of a memory cell (schematically shown in FIG. 1A) of one embodiment of the invention combined with a programming circuit and a memory cell selection circuit according to an embodiment of the invention.</figref><figref num="7A">It is a figure which shows the exemplary waveform of the control signal for reading the data state stored in the memory cell (schematically shown in FIG. 1A) of the embodiment of the present invention according to the embodiment of the present invention.</figref><figref num="7B">FIG. 5 shows an exemplary waveform of a control signal for writing a stored data state in a memory cell (schematically shown in FIG. 1A) according to an embodiment of the invention.</figref><figref num="7C">It is a figure which shows the exemplary waveform of the programming control signal for erasing the data state of the memory cell (schematically shown in FIG. 1A) of embodiment of this invention according to embodiment of this invention.</figref><figref num="7D">It is a figure which shows the exemplary waveform of the programming control signal for erasing the data state of the memory cell (schematically shown in FIG. 1A) of embodiment of this invention according to embodiment of this invention.</figref><figref num="8A">FIG. 6 is a block diagram of a memory array including peripheral circuits and a plurality of memory cells according to one embodiment of the present invention.</figref><figref num="8B">FIG. 6 is a schematic block diagram of a memory array containing a plurality of subarrays according to certain embodiments of the present invention.</figref><figref num="9">Schematic representation of a plurality of memory cells including access transistors shared by a plurality of electric field programmable bistable thin film devices according to one embodiment of another aspect of the invention, each electric field programmable bistable thin film. It is a schematic diagram in which an element is coupled to the source or drain region of a control transistor.</figref><figref num="10A">FIG. 9 is a cross-sectional view of a plurality of exemplary layouts of the memory cells of FIG. 9, wherein a plurality of electric field programmable bistable thin film devices are arranged in a plurality of stack layers according to an embodiment of the present invention. It is a cross-sectional view coupled to the source or drain region of.</figref><figref num="10B">FIG. 9 is a cross-sectional view of a plurality of exemplary layouts of the memory cells of FIG. 9, wherein a plurality of electric field programmable bistable thin film devices are arranged in a plurality of stack layers according to an embodiment of the present invention. It is a cross-sectional view coupled to the source or drain region of.</figref><figref num="11A">FIG. 6 is a schematic block diagram of a memory array having multiple stack layers of electric field programmable thin films according to certain embodiments of the present invention.</figref><figref num="11B">FIG. 6 is a block diagram of a memory array that "effectively" contains multiple memory cells in each layer of the memory array according to one embodiment of the invention.</figref><figref num="12A">FIG. 5 is a diagram schematically showing an exemplary embodiment of the memory cell programming circuit of FIG. 9 according to an embodiment of an embodiment of the present invention.</figref><figref num="12B">FIG. 5 is a diagram schematically showing an exemplary embodiment of a memory cell read or sense circuit of FIG. 9 according to an embodiment of an embodiment of the present invention.</figref><figref num="12C">Two diagrams schematically illustrating an exemplary embodiment of a memory cell read or sense circuit of FIG. 9 according to an embodiment of an embodiment of the present invention.</figref><figref num="12D">Two diagrams schematically illustrating an exemplary embodiment of a memory cell read or sense circuit of FIG. 9 according to an embodiment of an embodiment of the present invention.</figref><figref num="13">A schematic representation of a plurality of memory cells including access transistors shared by a plurality of electric field programmable bistable thin film devices, wherein the electric field programmable bistable thin film device according to another embodiment of another aspect of the present invention. It is a schematic diagram which is stacked in a plurality of layers and coupled to the gate of a control transistor.</figref><figref num="14A">FIG. 13 is a cross-sectional view of a plurality of exemplary layouts of the memory cells of FIG. 13, wherein a plurality of electric field programmable bistable thin film devices are stacked in multiple layers and the gate of an access transistor according to an embodiment of the present invention. It is sectional drawing which is connected to.</figref><figref num="14B">FIG. 13 is a cross-sectional view of a plurality of exemplary layouts of the memory cells of FIG. 13, wherein a plurality of electric field programmable bistable thin film devices are stacked in multiple layers and the gate of an access transistor according to an embodiment of the present invention. It is sectional drawing which is connected to.</figref><figref num="15A">FIG. 5 is a diagram schematically showing an exemplary embodiment of the memory cell programming circuit of FIG. 13 according to an embodiment of an embodiment of the present invention.</figref><figref num="15B">FIG. 5 is a diagram schematically showing an exemplary embodiment of the memory cell programming circuit of FIG. 13 according to an embodiment of an embodiment of the present invention.</figref><figref num="15C">FIG. 5 is a diagram schematically showing an exemplary embodiment of a memory cell read or sense circuit of FIG. 13 according to an embodiment of an embodiment of the present invention.</figref><figref num="16">A schematic representation of a differential memory cell that includes first and second memory cells, wherein each of the first and second memory cells is an access transistor and according to certain embodiments of other aspects of the invention. It is a schematic diagram which has an electric field programmable bistable thin film element.</figref><figref num="17A">FIG. 5 is a diagram schematically showing an exemplary embodiment of a memory cell read or sense circuit of FIG. 16 according to an embodiment of an embodiment of the present invention.</figref><figref num="17B">FIG. 5 is a diagram schematically showing an exemplary embodiment of the memory cell programming circuit of FIG. 16 according to an embodiment of an embodiment of the present invention.</figref><figref num="18A">Schematic representation of other embodiments of differential memory cells, including first and second memory cells, respectively, according to certain embodiments of other aspects of the invention. Is a schematic diagram having an access transistor and an electric field programmable bistable thin film device.</figref><figref num="18B">Schematic representation of other embodiments of differential memory cells, including first and second memory cells, respectively, according to certain embodiments of other aspects of the invention. Is a schematic diagram having an access transistor and an electric field programmable bistable thin film device.</figref><figref num="18C">Schematic representation of other embodiments of differential memory cells, including first and second memory cells, respectively, according to certain embodiments of other aspects of the invention. Is a schematic diagram having an access transistor and an electric field programmable bistable thin film device.</figref><figref num="19">Schematic of another embodiment of a differential memory cell, including first and second memory cells, wherein the first and second memory cells share an access transistor according to another aspect of the invention. It is a schematic diagram.</figref><figref num="20A">FIG. 5 is a diagram schematically showing an exemplary embodiment of a memory cell read or sense circuit of FIG. 19 according to an embodiment of an embodiment of the present invention.</figref><figref num="20B">FIG. 5 is a diagram schematically showing an exemplary embodiment of a memory cell programming or erasing circuit of FIG. 19 according to an embodiment of an embodiment of the present invention.</figref><figref num="21A">According to certain embodiments of other aspects of the invention, a first memory cell with an N-channel access transistor and an electric field programmable bistable film element, and a P-channel access transistor and an electric field programmable bistable thin film. FIG. 6 is a schematic representation of a complementary (dual or multi-bit) memory cell containing a second memory cell having an element.</figref><figref num="21B">According to certain embodiments of other aspects of the invention, a first memory cell with an N-channel access transistor and an electric field programmable bistable film element, and a P-channel access transistor and an electric field programmable bistable thin film. FIG. 6 is a schematic representation of a complementary (dual or multi-bit) memory cell containing a second memory cell having an element.</figref><figref num="21C">According to certain embodiments of other aspects of the invention, a first memory cell with an N-channel access transistor and an electric field programmable bistable film element, and a P-channel access transistor and an electric field programmable bistable thin film. FIG. 6 is a schematic representation of a complementary (dual or multi-bit) memory cell containing a second memory cell having an element.</figref><figref num="21D">According to certain embodiments of other aspects of the invention, a first memory cell with an N-channel access transistor and an electric field programmable bistable film element, and a P-channel access transistor and an electric field programmable bistable thin film. FIG. 6 is a schematic representation of a complementary (dual or multi-bit) memory cell containing a second memory cell having an element.</figref><figref num="21E">According to certain embodiments of other aspects of the invention, a first memory cell with an N-channel access transistor and an electric field programmable bistable film element, and a P-channel access transistor and an electric field programmable bistable thin film. FIG. 6 is a schematic representation of a complementary (dual or multi-bit) memory cell containing a second memory cell having an element.</figref><figref num="22A">For example, a schematic block diagram of a memory array containing a plurality of differential memory cells of FIGS. 16 and 18A-18C, wherein the memory array is a plurality of field programmable thin films according to one embodiment of the present invention. It is a block diagram containing a stack layer of, and "effectively" containing a plurality of memory cells in each layer of the memory array.</figref><figref num="22B">For example, a block diagram of a memory array containing multiple differential memory cells of FIGS. 16 and 18A-18C, wherein the memory array is one of the electric field programmable thin films according to one embodiment of the present invention. It is a block diagram including a layer.</figref><figref num="22C">For example, a schematic block diagram of a memory array containing a plurality of complementary memory cells of FIGS. 19A-19C, wherein the memory array is a plurality of stack layers of field programmable thin films according to one embodiment of the present invention. It is a block diagram containing a plurality of memory cells "effectively" in each layer of the memory array.</figref><figref num="22D">For example, a block diagram of a memory array containing a plurality of complementary memory cells of FIGS. 19A-19C, wherein the memory array contains one layer of an electric field programmable thin film according to one embodiment of the present invention. It is a block diagram.</figref><figref num="23A">FIG. 6 illustrates a three-dimensional array of exemplary memory according to one embodiment of the invention, in which access transistors are manufactured in one or more layers (in addition to or on behalf of a substrate). It is a diagram in which an electric field programmable bistable element can be formed, placed, and / or placed on a layer or plane above and / or below an access transistor.</figref><figref num="23B">FIG. 6 illustrates a three-dimensional array of exemplary memory according to one embodiment of the invention, in which access transistors are manufactured in one or more layers (in addition to or on behalf of a substrate). It is a diagram in which an electric field programmable bistable element can be formed, placed, and / or placed on a layer or plane above and / or below an access transistor.</figref><figref num="23C">FIG. 6 illustrates a three-dimensional array of exemplary memory according to one embodiment of the invention, in which access transistors are manufactured in one or more layers (in addition to or on behalf of a substrate). It is a diagram in which an electric field programmable bistable element can be formed, placed, and / or placed on a layer or plane above and / or below an access transistor.</figref>

Code description

10, 10a, 10b, 10c, 10d, 10n, 10aa, 10xx Memory cells 12, 12a, 12b Access transistors 14, 14a, 14b, 14c, 14d, 14n Electromagnetic programmable bistable elements 16 16a, 16b Gate region 18 18a, 18b Source area 20, 20a, 20b Drain area 22, 22a, 22b, 22i, 22n Signal line 24, 24a, 24b, 24i, 24n Control signal line 26, 26a, 26b, 26i Sense / program signal line, control signal Lines 28, 30 points 32 Bulk semiconductor wafers 34, 36 Contacts 38, 38a, 38b, 38c, 38d, 38a1, 38a2, 38b1, 38b2, 38c1, 38c2, 38ab, 38cd Electrodes 40, 40a, 40b, 40c, 40d Programmable thin film 42 Memory cell selection circuit 44 Sense amplifier 44a, 44b Input 44n Sense amplifier 46, 46a, 46n Reference circuit 48 Reference voltage circuit 52 Programming circuit 56, 56a, 56b, 56c, 56d Memory Array 58a, 58x Rows 60a, 60x, 60a1, 60a2, 60x1, 60x2 Columns 62 Peripheral Circuits 64 Layout, Layers 64a, 64b, 64c, 64d, 64e, 64f, 64g, 64h Layout, Layer 66 Nodes 68, 68a, 68b Layers 100, 100aa, 100xx Differential memory cells 200, 200aa, 200xx Complementary memory cells