Semiconductor device

The present invention relates to a semiconductor device capable of wireless communication.

Semiconductor devices such as ID chips that can send and receive data wirelessly are being put to practical use in various fields, and the market is expected to expand further as a new form of communication information terminal. ID chips are also called wireless tags, RFID (Radio frequency identification) tags, and IC tags, and a type having an antenna and an integrated circuit formed by using a semiconductor substrate has been put into practical use at present. There is.

<p> By the way, the ID chip may be a case where an integrated circuit and an antenna formed separately are connected later, or a case where the integrated circuit and an antenna are continuously formed (integrally formed) on the same substrate.</p><p> In the case of an ID chip in which an integrated circuit and an antenna formed separately are connected later, defects are likely to occur at the connection point between the integrated circuit and the antenna, and it is difficult to increase the yield. Furthermore, it is assumed that the ID chip can be attached to a flexible material (flexible material) such as paper or plastic depending on the application. Therefore, even if the integrated circuit and the antenna are well connected, stress may be applied to the substrate on which the integrated circuit is formed during use. Therefore, there is a problem that the connection portion is liable to be defective due to stress and the reliability is low.</p><p> On the other hand, in the case of an ID chip in which an integrated circuit and an antenna are integrally formed, unlike the case where they are formed separately, defects in connection points are unlikely to occur. However, when trying to secure the number of ID chips obtained from one substrate, the area for forming the antenna is naturally limited. Therefore, it is difficult to increase the size of the antenna, and it is difficult to form an antenna having a high gain.</p><p> Further, the semiconductor substrate generally used for forming an integrated circuit has a drawback of poor flexibility and low mechanical strength. However, by reducing the area of the integrated circuit itself, the machine can be used. It is possible to improve the target strength to some extent. However, in this case, it becomes difficult to secure the circuit scale and the use of the ID chip is limited, which is not preferable. Therefore, if it is important to secure the circuit scale of the integrated circuit, it is not appropriate to blindly reduce the area of the integrated circuit.</p><p> In view of the above problems, an object of the present invention is to provide an ID chip capable of increasing the gain of an antenna and increasing the mechanical strength of an integrated circuit without suppressing the circuit scale. Furthermore, the present invention relates to packaging materials, tags, certificates, banknotes and securities using the ID chip.</p>

<p> The semiconductor device of the present invention has an integrated circuit in which a semiconductor element formed of a thin-film semiconductor film is used, and an antenna connected to the integrated circuit. The semiconductor device of the present invention includes a wireless chip, and the wireless chip further includes an ID chip. It is desirable that the antenna is integrally formed with the integrated circuit because the mechanical strength of the semiconductor device can be increased. Moreover, the antenna used in the present invention has a conducting wire wound in a circular or spiral shape, and fine particles made of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer containing (dispersed) fine particles using a soft magnetic material is arranged between the conducting wires.</p><p> In the present invention, an insulating film is formed so as to cover the conductive wires, and an insulating layer containing (dispersed) fine particles using a soft magnetic material is arranged between the conductive wires so as to sandwich the insulating film. It may have been done.</p><p> Further, in the present invention, the insulating layer may be formed so as to cover the conducting wire.</p><p> The integrated circuit and the antenna may be formed directly on the substrate, or may be peeled off after being formed on the substrate and attached to a separately prepared substrate. The integrated circuit is bonded by providing a metal oxide film between the highly heat-resistant substrate and the integrated circuit, weakening the metal oxide film by crystallization, peeling off the integrated circuit, and bonding the integrated circuit. A method of separating and bonding the substrate and the integrated circuit by providing a release layer between the and the integrated circuit and removing the release layer by irradiation or etching of laser light, and a highly heat-resistant substrate on which the integrated circuit is formed. Various methods can be used, such as a method of separating the integrated circuit from the substrate and bonding the integrated circuit by mechanically deleting the integrated circuit or removing the integrated circuit by etching with a solution or gas.</p><p> Further, the integrated circuits may be laminated to increase the circuit scale and the capacity of the memory by laminating the separately manufactured integrated circuits. Since the integrated circuit is dramatically thinner than the ID chip made of a semiconductor substrate, the mechanical strength of the ID chip can be maintained to some extent even if a plurality of integrated circuits are stacked. For the connection between the stacked integrated circuits, a known connection method such as a flip chip method, a TAB (Tape Automated Bonding) method, or a wire bonding method can be used.</p><p> Further, the present invention also includes packaging materials, tags, certificates, banknotes and securities using the above ID chip. In the present invention, the packaging material corresponds to a support that can be molded or molded to wrap an object such as a wrap, a PET bottle, a tray, and a capsule. Further, in the present invention, a tag corresponds to a tag having information on an object to which the tag is attached, such as a tag, a price tag, and a name tag. Further, in the present invention, a certificate corresponds to a document proving the fact such as a copy of a family register, a resident's card, a passport, a driver's license, an ID card, a membership card, a credit card, a cash card, a prepaid card, a medical examination ticket, and a commuter pass. Further, in the present invention, securities correspond to securities indicating property rights under private law, such as bills, checks, freight exchange certificates, ship currency securities, warehouse receipts, stock certificates, bonds, gift certificates, and mortgage securities.</p>

<p> The soft magnetic material is a magnetic material having a high magnetic permeability and a small coercive force. Therefore, by arranging the soft magnetic material between the conductors, it is possible to suppress the generation of eddy currents in the conductors included in the conductors due to the magnetic flux intersecting the plane including the antenna. Therefore, the loss of the magnetic flux intersecting the plane including the antenna can be reduced, and the mutual inductance of the antenna can be increased. Therefore, the gain of the antenna can be increased while ensuring the mechanical strength of the ID chip.</p><p> Further, by forming an insulating layer containing a soft magnetic material so as to cover the conducting wire, it is possible to suppress the magnetic flux generated in the antenna from being lost by the conductor arranged in the vicinity of the conducting wire. In particular, when a conductor is used on the surface of the object to which the ID chip is attached, the conductor can be used by attaching the ID chip so that an insulating layer containing a soft magnetic material is arranged between the antenna and the surface. The loss of magnetic flux can be prevented.</p><p> Further, by integrally forming the integrated circuit and the antenna, the wiring for connecting the integrated circuit and the antenna can also be formed on the substrate in the process of manufacturing the integrated circuit. Therefore, it is possible to suppress the occurrence of connection failure when forming the ID chip. Further, when a flexible substrate is used, it is possible to suppress connection defects caused by stress applied to the substrate, which leads to improvement in reliability.</p><p> Further, since an integrated circuit is formed by using a semiconductor element formed of a thin-film semiconductor film, it is possible to use a flexible substrate, and the area is not as small as that of an integrated circuit using a semiconductor substrate. In both cases, high mechanical strength can be obtained. Therefore, the mechanical strength of the integrated circuit can be increased without suppressing the circuit scale, and the range of applications of the ID chip can be further expanded.</p>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, those skilled in the art can easily understand that the present invention can be carried out in many different modes, and that the forms and details thereof can be variously changed without departing from the spirit and scope of the present invention. Will be done. Therefore, the interpretation is not limited to the description of the present embodiment.

The configuration of the semiconductor device such as the ID chip of the present invention will be described with reference to FIG. FIG. 1 (A) shows a form of the ID chip of the present invention in a perspective view. Further, FIG. 1 (B) shows a cross-sectional view of the ID chip shown in FIG. 1 (A) in A-A'. 100 corresponds to an integrated circuit, 101 corresponds to an antenna, and the antenna 101 is electrically connected to the integrated circuit 100. 102 corresponds to a substrate, 103 corresponds to a cover material, and the integrated circuit 100 and the antenna 101 are sandwiched between the substrate 102 and the cover material 103.

Although FIG. 1B shows a TFT (thin film transistor) 104 as an example of the semiconductor element included in the integrated circuit 100, the semiconductor element used in the integrated circuit 100 is not limited to the TFT. For example, in addition to TFT, a storage element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitance element, an inductor, or the like can be used. The antenna 101 is formed on the interlayer insulating film 111 that covers the TFT.

Further, in the ID chip of the present invention, an insulating layer 106 is formed between the conducting wires 105 constituting the antenna 101. Further, in the present invention, as shown in FIG. 1 (B), the insulating layer 106 may be formed not only between the conducting wires 105 but also so as to cover the conducting wires 105.

Next, an enlarged view of the cross section of the ID chip surrounded by the broken line 107 in FIG. 1 (B) is shown in FIG. 1 (C). As the insulating layer 106, an insulator 110 in which fine particles 108 of a soft magnetic material are dispersed is used. An organic resin such as polyimide, epoxy, acrylic, or polyamide can be used for the insulator 110. Further, in addition to the above organic resin, an inorganic resin, for example, a resin containing a Si-O-Si bond formed by using a siloxane-based material as a starting material (hereinafter, referred to as a siloxane-based resin) can be used. The siloxane-based resin may have at least one of hydrogen, an alkyl group, and an aromatic hydrocarbon as a substituent in addition to hydrogen.

Further, if it is possible to include a soft magnetic material, an inorganic insulating film such as silicon oxide, silicon nitride oxide, or silicon nitride can also be used as the insulator 110.

Further, as the soft magnetic material used for the fine particles 108, for example, Fe, Co, Ni, or an alloy using any one or more of these, as well as 3Y₂O₃ 5Fe₂O₃(YIG), Fe₂O₃, Fe-Si-Al alloy, Fe-Cr alloy, FeP alloy, Ni or Ni-Fe alloy with one or more of Mo, Cu, Cr, Nb added to Permalloy alloy. Further, as the soft magnetic material, soft ferrite typified by Mn-Zn ferrite can also be used.

Further, as shown in FIG. 1 (C), the ID chip of the present invention has an insulating film for electrically separating the conductive wires 105 from each other between the insulating layer 106 and the conductive wire 105 (hereinafter referred to as an insulating film for separation). 109 may be formed. When the content of the soft magnetic material in the insulating layer 106 is high, the separating insulating film 109 is an effective means for electrically separating the conducting wires 105 from each other.

Although FIG. 1 shows an example in which the cover material 103 is used to increase the mechanical strength of the ID chip, the ID chip of the present invention does not necessarily have to use the cover material 103. For example, the mechanical strength of the ID chip may be increased by covering the integrated circuit 100 and the antenna 101 with a resin or the like. Further, the mechanical strength of the ID chip may be increased by controlling the thickness of the insulating layer 106.

Further, the integrated circuit 100 and the antenna 101 may be directly formed on the substrate 102 as long as the heat resistant temperature of the substrate 102 is such that it can withstand the heat treatment in the manufacturing process of the integrated circuit 100. However, when a substrate having inferior heat resistance such as a plastic substrate is used as the substrate 102, the integrated circuit 100 and the antenna 101 may be attached to the substrate 102 after forming an integrated circuit on the substrate having heat resistance. good.

Further, the conductor 105 used in the antenna 101 is made of, for example, a metal such as Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, Al, Fe, Co, Zn, Sn, Ni, or a metal compound. A conductive material having one or more can be used. The lead wire 105 can be formed by using, for example, a printing method, a photolithography method, a plating method, a vapor deposition method, a droplet ejection method, or the like. The droplet ejection method means a method of ejecting droplets containing a predetermined composition from pores to form a predetermined pattern, and the inkjet method and the like are included in the category. Further, the printing method includes a screen printing method, an offset printing method and the like.

Further, in FIG. 1C, although the conductor 105 is formed of a single-layer conductive film, it may be formed by using a plurality of conductive films.

In FIG. 2A, after forming the patterned first conductor 201, the second conductor 202 is formed so as to cover the first conductor 201, and the first conductor 201 and the second conductor 202 are formed. A cross-sectional view of the conductor 105 when used as the conductor 105 is shown. In FIG. 2A, the first conductor 201 is formed of Ni using a photolithography method, and then the second conductor 202 is formed of Cu using an electroless plating method so as to cover the first conductor 201. Form. The first conductor 201 can be formed by using a printing method, a vapor deposition method, a droplet ejection method, or the like in addition to the photolithography method. The second conductor 202 can be formed by using an electroplating method, a droplet ejection method, or the like in addition to the electroless plating method.

The materials used for the first conductor 201 and the second conductor 202 are not limited to the configuration shown in FIG. 2 (A). Further, FIG. 2A shows a configuration in which the first conductor 201 is covered with the second conductor 202, but the second conductor 202 covering the first conductor 201 is a single layer. Not necessarily. A second conductor 202 in which a plurality of layers are laminated may cover the first conductor 201.

FIG. 2B shows a cross-sectional view of the conductor 105 when a plurality of conductive films are laminated and then patterned by a photolithography method to form the conductor 105. In FIG. 2B, the second conductor 204 formed of Al is formed so as to be laminated on the first conductor 203 formed of Ti.

The materials used for the first conductor 203 and the second conductor 204 are not limited to the configuration shown in FIG. 2 (B). Further, FIG. 2B shows a configuration in which the first conductor 203 and the second conductor 204 are laminated, but the conductor 105 is formed so that three or more layers of conductors are laminated. Is also good.

Further, as shown in FIG. 2 (B), after forming a plurality of laminated conductors, as shown in FIG. 2 (A), another conductor covers the plurality of laminated conductors to form a conductor. You may try to form 105.

The insulating layer 106 does not necessarily have to cover the lead wire 105, and may be formed at least in contact with the lead wire 105. FIG. 2C shows a cross-sectional view of the conducting wire 105 when the insulating layer 106 is selectively formed between the conducting wires 105. The insulating layer 106 can be formed by using a droplet ejection method, a printing method, or the like. In the case of FIG. 2C, it is desirable to form the protective film 205 so as to cover the conducting wire 105 and the insulating layer 106 after forming the conducting wire 105 and the insulating layer 106. The protective film 205 can be formed of an insulating film using an inorganic resin such as an organic resin or a siloxane-based resin.

The separating insulating film 109 can also be formed by using a vacuum vapor deposition method, a sputtering method, a CVD method, or the like, but can be selectively formed by using a droplet ejection method, a printing method, or the like. is there.

FIG. 3A shows an example in which the separation insulating film 301 is selectively formed so as to cover the lead wire 105 by using the droplet ejection method. In the case of FIG. 3A, an inorganic resin such as an organic resin or a siloxane-based resin can be used as the separating insulating film 301. In the case of FIG. 3A as well, as shown in FIG. 3B, the insulating layer 302 may be selectively formed between the conducting wires 105.

Further, an insulating film such as a silicon nitride film or a silicon oxide film having a high barrier property may be formed between the lead wire 105 and the interlayer insulating film 111. FIG. 3C shows a cross-sectional view of the conductive wire 105 when an insulating film 303 such as a silicon nitride film or a silicon nitride film having a high barrier property is formed between the conductive wire 105 and the interlayer insulating film 111. .. By forming the insulating film 303 having a high barrier property, for example, when a metal such as Cu that adversely affects the characteristics of the semiconductor element is used for the lead wire 105, the metal is prevented from diffusing toward the semiconductor element. It can be suppressed.

Further, even when a metal that adversely affects the characteristics of the semiconductor element is used not only for the metal used for the lead wire 105 but also for the fine particles in the insulating layer 106, the metal diffuses toward the semiconductor element. It can be suppressed. In particular, the separating insulating film 304 formed so as to cover the lead wire 105 and the interlayer insulating film 111 is formed in the insulating layer 106 by forming the insulating film 304 having a high barrier property such as a silicon nitride film or a silicon nitride oxide film. It becomes possible to further suppress the metal used in the fine particles of silicon from diffusing toward the semiconductor element.

Next, a detailed method for manufacturing the ID chip of the present invention will be described. In the present embodiment, the isolated TFT is shown as an example of the semiconductor element, but the semiconductor element used in the integrated circuit is not limited to this, and any circuit element can be used.

First, as shown in FIG. 4 (A), the release layer 501 is formed on the first substrate 500 having heat resistance. As the first substrate 500, for example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Further, a metal substrate including a stainless steel substrate or a semiconductor substrate may be used. A substrate made of a flexible synthetic resin such as plastic generally tends to have a lower heat resistant temperature than the above substrate, but can be used as long as it can withstand the processing temperature in the manufacturing process. ..

As the release layer 501, a layer containing silicon as a main component, such as amorphous silicon, polycrystalline silicon, single crystal silicon, and microcrystalline silicon (including semi-amorphous silicon), can be used. The release layer 501 can be formed by using a sputtering method, a reduced pressure CVD method, a plasma CVD method, or the like. In this embodiment, amorphous silicon having a film thickness of about 50 nm is formed by a reduced pressure CVD method and used as a release layer 501. The release layer 501 is not limited to silicon, and may be formed of a material that can be selectively removed by etching. The film thickness of the release layer 501 is preferably 10 to 100 nm. For semi-amorphous silicon, it may be 30 to 50 nm.

Next, a base film 502 is formed on the release layer 501. The base film 502 is provided to prevent alkali metals such as Na and alkaline earth metals contained in the first substrate 500 from diffusing into the semiconductor film and adversely affecting the characteristics of semiconductor elements such as TFTs. The base film 502 also has a role of protecting the semiconductor element in the subsequent step of peeling the semiconductor element. The base film 502 may be a single layer or a laminate of a plurality of insulating films. Therefore, it is formed by using an insulating film such as silicon oxide, silicon nitride, or silicon nitride, which can suppress the diffusion of alkali metal or alkaline earth metal into the semiconductor film.

In the present embodiment, the SiON film having a film thickness of 100 nm, the SiNO film having a film thickness of 50 nm, and the SiON film having a film thickness of 100 nm are laminated in this order to form the base film 502. , Not limited to this. For example, instead of the lower SiON film, a siloxane resin having a film thickness of 0.5 to 3 μm may be formed by a spin coating method, a slit coater method, a droplet ejection method, a printing method, or the like. Also, instead of the SiNO film in the middle layer, a silicon nitride film (SiNx, Si)₃N₄Etc.) may be used. Also, instead of the upper SiON film, SiO₂A membrane may be used. Further, each film thickness is preferably 0.05 to 3 μm, and can be freely selected from the range.

Alternatively, the base film 502 is a SiON film or SiO.₂Membranes, siloxane-based resin membranes, and SiO₂The films may be sequentially laminated to form.

Here, the silicon oxide film is SiH.₄And O₂, TEOS (Tetraethoxysilane) and O₂It can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECR CVD, etc. using a mixed gas such as The silicon nitride film is typically SiH.₄And NH₃It can be formed by plasma CVD using a mixed gas of. The silicon oxide film (SiOxNy: x&gt; y) and the silicon nitride film (SiNxOy: x&gt; y) are typically SiH.₄And N₂It can be formed by plasma CVD using a mixed gas of O.

Next, the semiconductor film 503 is formed on the base film 502. It is desirable that the semiconductor film 503 is formed without exposing it to the atmosphere after forming the base film 502. The film thickness of the semiconductor film 503 is 20 to 200 nm (preferably 40 to 170 nm, preferably 50 to 150 nm). The semiconductor film 503 may be an amorphous semiconductor, a semi-amorphous semiconductor, or a polycrystalline semiconductor. Further, as the semiconductor, not only silicon but also silicon germanium can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%.

The semiconductor film 503 may be crystallized by a known technique. Known crystallization methods include a laser crystallization method using laser light and a crystallization method using a catalytic element. Alternatively, a crystallization method using a catalytic element and a laser crystallization method can be used in combination. When a substrate having excellent heat resistance such as quartz is used as the first substrate 500, a thermal crystallization method using an electric heating furnace, a lamp annealing crystallization method using infrared light, and a crystal using a catalyst element. A crystallization method that combines any of the crystallization methods with high-temperature annealing at about 950 ° C may be used.

For example, when laser crystallization is used, prior to laser crystallization, the semiconductor film 503 is thermally annealed at 500 ° C. for 1 hour in order to increase the resistance of the semiconductor film 503 to the laser. Then, by using a solid-state laser capable of continuous oscillation and irradiating the laser light of the second to fourth harmonics of the fundamental wave, a crystal having a large particle size can be obtained. For example, typically Nd: YVO₄It is desirable to use the second harmonic (532 nm) or third harmonic (355 nm) of the laser (primary wave 1064 nm). Specifically, continuous oscillation YVO₄The laser beam emitted from the laser is converted into harmonics by a nonlinear optical element to obtain a laser beam with an output of 10 W. Then, preferably, it is formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated to the semiconductor film 503. The power density at this time is 0.01 to 100 MW / cm²Degree (preferably 0.1-10 MW / cm²)is required. Then, the scanning speed is set to about 10 to 2000 cm / sec, and irradiation is performed.

Further, the laser crystallization may be performed by setting the oscillation frequency of the laser beam for pulse oscillation to 10 MHz or more and using a frequency band significantly higher than the commonly used frequency band of several tens of Hz to several hundreds of Hz. It is said that the time from irradiating the semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens of nsec to several hundred nsec. Therefore, by using the above frequency, it is possible to irradiate the laser beam of the next pulse from the time when the semiconductor film is melted by the laser beam to the time when it is solidified. Therefore, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, it is possible to form an aggregate of crystal grains having a width of 10 to 30 μm in the scanning direction of the contained crystal grains and a width of about 1 to 5 μm in the direction perpendicular to the scanning direction. By forming single crystal grains elongated along the scanning direction, it is possible to form a semiconductor film having almost no grain boundaries at least in the TFT channel direction.

The laser crystallization may be performed by irradiating the laser beam of the fundamental wave of continuous oscillation and the laser beam of the harmonic of continuous oscillation in parallel, or the laser beam of the fundamental wave of continuous oscillation and the harmonic of pulse oscillation. The laser beam of the wave may be irradiated in parallel.

The laser beam may be irradiated in an atmosphere of an inert gas such as a rare gas or nitrogen. As a result, it is possible to suppress the roughness of the semiconductor surface due to laser light irradiation, and it is possible to suppress the variation in the threshold value caused by the variation in the interface state density.

By irradiating the laser beam described above, the semiconductor film 503 having higher crystallinity is formed. The polycrystalline semiconductor may be formed in advance by a sputtering method, a plasma CVD method, a thermal CVD method, or the like.

Further, although the semiconductor film 503 is crystallized in the present embodiment, the process may proceed to the process described later without crystallizing the amorphous silicon film or the microcrystalline semiconductor film. A TFT using an amorphous semiconductor or a microcrystalline semiconductor has an advantage that the cost can be suppressed and the yield can be increased because the number of manufacturing steps is smaller than that of the TFT using a polycrystalline semiconductor.

Amorphous semiconductors can be obtained by glow discharge decomposition of silicified gas. As a typical silicified gas, SiH₄, Si₂H₆Can be mentioned. This silicified gas may be diluted with hydrogen, hydrogen and helium before use.

The semi-amorphous semiconductor is a film containing a semiconductor having an intermediate structure between an amorphous semiconductor and a semiconductor having a crystal structure (including a single crystal and a polycrystal). This semi-amorphous semiconductor is a semiconductor having a stable third state from the viewpoint of free energy, is a crystalline semiconductor having short-range order and lattice strain, and has a particle size of 0.5 to 20 nm and is non-single. It is possible to disperse and exist in a crystalline semiconductor. The Raman spectrum of the semi-amorphous semiconductor is 520 cm.^-1Diffraction peaks (111) and (220), which are said to be derived from the Si crystal lattice, are observed in X-ray diffraction. It also contains at least 1 atomic% or more of hydrogen or halogen to terminate unbonded hands (dangling bonds). Here, for convenience, such a semiconductor is referred to as a semi-amorphous semiconductor (SAS). Further, by adding rare gas elements such as helium, argon, krypton, and neon to further promote the lattice strain, the stability is increased and a good semi-amorphous semiconductor can be obtained.

Further, SAS can be obtained by glow discharge decomposition of a silicified gas. As a typical silicified gas, SiH₄And also Si₂H₆, SiH₂Cl₂, SiHCl₃, SiCl₄, SiF₄Etc. can be used. In addition, it is easy to form SAS by diluting this siliceous gas with hydrogen or a gas obtained by adding one or more rare gas elements selected from helium, argon, krypton, and neon to hydrogen. Can be. It is preferable to dilute the silicified gas in the range of 2 to 1000 times the dilution rate. Furthermore, in the silicified gas, CH₄, C₂H₆Carbide gas such as GeH₄, GeF₄Germaniumized gas, such as F₂The energy bandwidth may be adjusted to 1.5 to 2.4 eV or 0.9 to 1.1 eV by mixing the above.

For example, SiH₄To H₂When using gas with the addition of, or SiH₄To F₂When a TFT is made using the formed semi-amorphous semiconductor, the subthreshold coefficient (S value) of the TFT is 0.35 V / dec or less, typically 0.25 to 0.09 V / dec. Carrier mobility 10 cm²Can be / Vsec. When, for example, a 19-stage ring oscillator is formed by the TFT using the semi-amorphous semiconductor, the oscillation frequency can be 1MH or more, preferably 100MHz or more at a power supply voltage of 3 to 5V. Further, at a power supply voltage of 3 to 5 V, the delay time per stage of the inverter can be 26 ns, preferably 0.26 ns or less.

Next, as shown in FIG. 4 (B), the semiconductor film 503 is patterned to form island-shaped semiconductor films 504 to 506. Then, the gate insulating film 507 is formed so as to cover the island-shaped semiconductor films 504 to 506. The gate insulating film 507 can be formed by using a plasma CVD method, a sputtering method, or the like, and a film containing silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxide nitride is formed as a single layer or laminated. In the case of laminating, for example, it is preferable to have a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film from the substrate side.

Next, as shown in FIG. 4C, gate electrodes 510 to 512 are formed. In the present embodiment, Si, WN, and W doped with impurities that impart n-type are formed so as to be laminated in order by a sputtering method, and then etching is performed using the resist 513 as a mask to perform gate electrodes 510 to 512. To form. Of course, the material, structure, and manufacturing method of the gate electrodes 510 to 512 are not limited to this, and can be appropriately selected. For example, a laminated structure of Si and NiSi (nickel silicide) doped with impurities that impart n-type, a laminated structure of Si and WSix doped with impurities that impart n-type, TaN (tantalum nitride) and W ( It may be a laminated structure of (tungsten). Further, it may be formed in a single layer by using various conductive materials.

Further, a mask such as SiOx may be used instead of the resist mask. In this case, a step of patterning to form a mask (called a hard mask) of SiOx, SiON, etc. is added, but since the mask film loss during etching is less than that of the resist, the gate electrodes 510 to 512 having a desired width are added. Can be formed. Further, the gate electrodes 510 to 512 may be selectively formed by using the droplet ejection method without using the resist 513.

As the conductive material, various materials can be selected depending on the function of the conductive film. Further, when the gate electrode and the antenna are formed at the same time, the material may be selected in consideration of their functions.

The etching gas used for etching and forming the gate electrode is CF.₄, Cl₂, O₂Mixed gas and Cl₂Gas was used, but it is not limited to this.

Next, as shown in FIG. 4 (D), the island-shaped semiconductor film 505, which is a p-channel TFT, is covered with the resist 514, and the gate electrodes 510 and 512 are used as masks on the island-shaped semiconductor films 504 and 506. Doping the mold-imparting impurity element (typically P (phosphorus) or As (arsenic)) to a low concentration (first doping step). The condition of the first doping step is the dose amount: 1 × 10¹³~6×10¹³/cm², Acceleration voltage: 50 ~ 70keV, but not limited to this. In this first doping step, doping is performed through the gate insulating film 507, and a pair of low-concentration impurity regions 516 and 517 are formed on the island-shaped semiconductor films 504 and 506. The first doping step may be performed without covering the island-shaped semiconductor film 505, which is a p-channel TFT, with a resist.

Next, as shown in FIG. 4 (E), after removing the resist 514 by ashing or the like, a new resist 518 is formed so as to cover the island-shaped semiconductor films 504 and 506 which are n-channel TFTs, and a gate is formed. Using the electrode 511 as a mask, the island-shaped semiconductor film 505 is doped with an impurity element (typically B (boron)) that imparts p-type to a high concentration (second doping step). The condition of the second doping step is the dose amount: 1 × 10¹⁶~3×10¹⁶/cm², Acceleration voltage: 20 ~ 40keV. By this second doping step, doping is performed through the gate insulating film 507, and a pair of p-type high-concentration impurity regions 519 are formed on the island-shaped semiconductor film 505.

Next, as shown in FIG. 5A, the resist 518 is removed by ashing or the like, and then the insulating film 520 is formed so as to cover the gate insulating film 507 and the gate electrodes 510 to 512. In this embodiment, SiO with a film thickness of 100 nm₂The film is formed by the plasma CVD method. Then, the insulating film 520 and the gate insulating film 507 are partially etched by the etchback method, and the sidewalls 522 to 524 are formed so as to be in contact with the side walls of the gate electrodes 510 to 512 as shown in FIG. 5 (B). Form self-aligned (self-aligned). CHF as the etching gas₃And He mixed gas is used. The process of forming the sidewall is not limited to these.

If an insulating film is also formed on the back surface of the first substrate 500 when the insulating film 520 is formed, the insulating film formed on the back surface should be selectively etched and removed using a resist. You can do it. In this case, the insulating film formed on the back surface may be removed by etching together with the insulating film 520 and the gate insulating film 507 when the sidewalls 522 to 524 are formed by the etchback method.

Next, as shown in FIG. 5 (C), a resist 525 is newly formed so as to cover the island-shaped semiconductor film 505 that becomes a p-channel TFT, and the gate electrodes 510 and 512 and sidewalls 522 and 524 are masked. As a result, an impurity element (typically P or As) that imparts n-type is doped at a high concentration (third doping step). The condition of the third doping step is the dose amount: 1 × 10¹³~5×10¹⁵/cm², Acceleration voltage: 60 ~ 100keV. By this third doping step, a pair of n-type high-concentration impurity regions 527 and 528 are formed on the island-shaped semiconductor films 504 and 506.

The sidewalls 522 and 524 function as a mask when doping impurities that later impart a high concentration of n-type to form a low-concentration impurity region or a non-doped offset region under the sidewalls 522 and 524. is there. Therefore, in order to control the width of the low-concentration impurity region or the offset region, the conditions of the etchback method when forming the sidewalls 522 and 524 or the film thickness of the insulating film 520 are appropriately changed, and the sidewalls 522 and 524 are formed. Just adjust the size.

Next, after removing the resist 525 by ashing or the like, the impurity region may be thermally activated. For example, after forming a 50 nm SiON film, heat treatment may be performed at 550 ° C. for 4 hours in a nitrogen atmosphere.

Further, after forming a SiNx film containing hydrogen to a film thickness of 100 nm, heat treatment is performed at 410 ° C. for 1 hour in a nitrogen atmosphere to hydrogenate the island-shaped semiconductor films 504 to 506. You may. Alternatively, a step of hydrogenating the island-shaped semiconductor films 504 to 506 may be performed by performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing hydrogen. Further, as another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. By this hydrogenation step, the dangling bond can be terminated by thermally excited hydrogen. Further, even if a defect is formed in the semiconductor film by bending the second substrate 548 after bonding the semiconductor element on the flexible second substrate 548 in a later step, hydrogenation causes the semiconductor element. The concentration of hydrogen in the semiconductor film is 1 x 10¹⁹~1×10²²atoms / cm³Preferably 1x10¹⁹~5×10²⁰atoms / cm³Therefore, the defect can be terminated by hydrogen contained in the semiconductor film. Further, in order to terminate the defect, halogen may be contained in the semiconductor film.

The n-channel type TFT529, the p-channel type TFT530, and the n-channel type TFT531 are formed by the series of steps described above. In the above-mentioned manufacturing step, a TFT having a channel length of 0.2 μm to 2 μm can be formed by appropriately changing the conditions of the etchback method or the film thickness of the insulating film 520 and adjusting the size of the sidewall. In the present embodiment, TFT529 to 531 have a top gate structure, but a bottom gate structure (reverse stagger structure) may be used.

Further, after this, a passivation film for protecting TFT 529 to 531 may be formed. As the passivation film, it is desirable to use silicon nitride, silicon nitride oxide, aluminum nitride, aluminum oxide, silicon oxide or the like, which can prevent the invasion of alkali metals and alkaline earth metals into TFT529 to 531. Specifically, for example, a SiON film having a film thickness of about 600 nm can be used as the passivation film. In this case, the hydrogenation treatment step may be performed after the SiON film is formed. In this way, a three-layer insulating film of SiON, SiNx, and SiON is formed on TFT529 to 531, but the structure and material thereof are not limited to these. By using the above configuration, TFT529 to 531 is covered with the base film 502 and the passivation film, so that alkali metals such as Na and alkaline earth metals diffuse into the semiconductor film used in the semiconductor element, and the semiconductor It is possible to prevent adverse effects on the characteristics of the element.

Next, as shown in FIG. 5 (D), the first interlayer insulating film 533 is formed so as to cover the TFTs 529 to 531. As the first interlayer insulating film 533, a heat-resistant organic resin such as polyimide, acrylic, or polyamide can be used. In addition to the above organic resins, low dielectric constant materials (low-k materials), resins containing Si-O-Si bonds (hereinafter, also referred to as siloxane-based resins) and the like can be used. The skeleton structure of siloxane is formed by the combination of silicon (Si) and oxygen (O). As these substituents, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. Moreover, you may use a fluoro group as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent. The first interlayer insulating film 533 is formed by spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, depending on the material. , Knife coater, etc. can be adopted. Further, an inorganic material may be used, in which case silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), PBSG (phosphorus glass), BPSG (boron phosphorus glass), alumina film or the like is used. be able to. The first interlayer insulating film 533 may be formed by laminating these insulating films.

Further, in the present embodiment, the second interlayer insulating film 534 is formed on the first interlayer insulating film 533. As the second interlayer insulating film 534, a film having carbon such as DLC (diamond-like carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride film, or the like can be used. As a forming method, a plasma CVD method, an atmospheric pressure plasma, or the like can be used. Alternatively, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, resist or benzocyclobutene, a siloxane resin or the like may be used.

The first interlayer insulating film 533 or the first interlayer insulating film 533 or the first interlayer insulating film 533 or the second interlayer insulating film 534 and the conductive material constituting the wiring to be formed later are stressed by the difference in the coefficient of thermal expansion. In order to prevent the second interlayer insulating film 534 from peeling or cracking, a filler may be mixed in the first interlayer insulating film 533 or the second interlayer insulating film 534.

Next, as shown in FIG. 5 (D), contact holes are formed in the first interlayer insulating film 533 and the second interlayer insulating film 534 to form wirings 535 to 539 connected to TFTs 529 to 531. The gas used for etching when opening contact holes is CHF.₃A mixed gas of and He was used, but the present invention is not limited to this. In this embodiment, the wirings 535 to 539 are formed of Al. Wiring 535 to 539 may have a five-layer structure of Ti, TiN, Al-Si, Ti, and TiN, and may be formed by a sputtering method.

By mixing Si in Al, it is possible to prevent the occurrence of hillock in the resist bake during wiring patterning. Further, instead of Si, about 0.5% Cu may be mixed. Further, by sandwiching the Al-Si layer with Ti or TiN, the hillock resistance is further improved. At the time of patterning, it is desirable to use the above hard mask made of SiON or the like. The wiring material and the forming method are not limited to these, and the material used for the gate electrode described above may be adopted.

Wiring 535 and 536 are in the high-concentration impurity region 527 of the n-channel type TFT529, wiring 536 and 537 are in the high-concentration impurity region 519 of the p-channel type TFT530, and wiring 538 and 539 are in the high-concentration impurity region of the n-channel type TFT531. It is connected to 528 respectively.

Next, as shown in FIG. 5 (E), a third interlayer insulating film 540 is formed on the second interlayer insulating film 534 so as to cover the wirings 535 to 539. The third interlayer insulating film 540 has an opening such that a part of the wiring 535 is exposed. The third interlayer insulating film 540 can be formed by using an organic resin film, an inorganic insulating film, or a siloxane-based insulating film. For an organic resin film, for example, acrylic, polyimide, polyamide or the like can be used, and for an inorganic insulating film, silicon oxide, silicon nitride or the like can be used. The mask used to form the opening can be formed by a droplet ejection method or a printing method. Further, the third interlayer insulating film 540 itself can be formed by a droplet ejection method or a printing method.

Next, the antenna 541 is formed on the third interlayer insulating film 540. For the antenna 541, use a conductive material having one or more metals and metal compounds such as Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, Al, Fe, Co, Zn, Sn, and Ni. Can be done. And the antenna 541 is connected to the wiring 535. In FIG. 5 (E), the antenna 541 is directly connected to the wiring 535, but the ID chip of the present invention is not limited to this configuration. For example, the antenna 541 and the wiring 535 may be electrically connected by using a separately formed wiring.

The antenna 541 can be formed by using a printing method, a photolithography method, a plating method, a vapor deposition method, a droplet ejection method, or the like. In the present embodiment, the antenna 541 is formed of a single-layer conductive film, but it is also possible to form an antenna 541 in which a plurality of conductive films are laminated.

By using the printing method and the droplet ejection method, it is possible to form the antenna 541 without using an exposure mask. Further, unlike the photolithography method, the droplet ejection method and the printing method do not waste the material that is removed by etching. Further, since it is not necessary to use an expensive mask for exposure, the cost required for manufacturing the ID chip can be suppressed.

When the droplet ejection method or various printing methods are used, for example, conductive particles obtained by coating Cu with Ag can also be used. When the antenna 541 is formed by the droplet ejection method, it is desirable that the surface of the third interlayer insulating film 540 is subjected to a treatment that enhances the adhesion of the antenna 541.

Specifically, as a treatment for enhancing the adhesion, for example, a method of adhering a metal or a metal compound capable of enhancing the adhesion of the conductive film or the insulating film by catalytic action to the surface of the third interlayer insulating film 540. A method of adhering an organic insulating film, metal, or metal compound having high adhesion to the formed conductive film or insulating film to the surface of the third interlayer insulating film 540, which is large on the surface of the third interlayer insulating film 540. Examples thereof include a method in which plasma treatment is performed under atmospheric pressure or reduced pressure to modify the surface. In addition to titanium and titanium oxide, 3d transition elements such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, and Zn are examples of metals having high adhesion to the conductive film or insulating film. Can be mentioned. Further, examples of the metal compound include the above-mentioned metal oxides, nitrides, and oxynitrides. Examples of the organic insulating film include polyimide and siloxane resin.

When the metal or metal compound attached to the third interlayer insulating film 540 is conductive, its sheet resistance is controlled so as not to interfere with the normal operation of the antenna. Specifically, the average thickness of the conductive metal or metal compound is controlled to be, for example, 1 to 10 nm, or the metal or metal compound is partially or wholly insulated by oxidation. You can do it. Alternatively, the adhered metal or metal compound may be selectively removed by etching except for the region where the adhesion is desired to be improved. Further, the metal or the metal compound may not be adhered to the entire surface of the substrate in advance, but may be selectively adhered only to a specific region by using a droplet ejection method, a printing method, a sol-gel method or the like. The metal or the metal compound does not have to be in the form of a completely continuous film on the surface of the third interlayer insulating film 540, and may be in a dispersed state to some extent.

After the antenna 541 is formed, the separation insulating film 542 is formed so as to cover the antenna 541 as shown in FIG. 6 (A). An organic resin, an inorganic insulating film, a siloxane-based resin, or the like can be used as the separation insulating film 542. Specific examples of the inorganic insulating film include a DLC film, a carbon nitride film, a silicon oxide film, a silicon oxide film, a silicon nitride film, and AlN._XMembrane or AlN_XO_YA membrane or the like can be used. Further, for example, a film in which a carbon nitride film and silicon nitride are laminated, a film in which polystyrene is laminated, or the like may be used as the separation insulating film 542. In this embodiment, a silicon nitride film is used as the separating insulating film 542.

Next, as shown in FIG. 7 (C), the protective layer 543 is formed so as to cover the separating insulating film 542. The protective layer 543 uses a material that can protect the TFTs 529 to 531 and the wirings 535 to 539 when the release layer 501 is later removed by etching. For example, the protective layer 543 can be formed by applying an epoxy-based, acrylate-based, or silicon-based resin soluble in water or alcohol to the entire surface.

In this embodiment, a water-soluble resin (manufactured by Toa Synthetic: VL-WSHL10) is applied by a spin coating method to a film thickness of 30 μm, exposed for 2 minutes for temporary curing, and then exposed to ultraviolet rays on the back surface. The protective layer 543 is formed by exposing for a total of 12.5 minutes, 2.5 minutes from the surface and 10 minutes from the surface. When a plurality of organic resins are laminated, the organic resins may be partially dissolved at the time of coating or firing depending on the solvent used, or the adhesion may become too high. Therefore, when an organic resin soluble in the same solvent is used for both the separating insulating film 542 and the protective layer 543, the separating insulating film 542 should be covered so that the protective layer 543 can be smoothly removed in a later step. Inorganic insulating film (SiN)_XMembrane, SiN_XO_YMembrane, AlN_XMembrane, or AlN_XO_YIt is preferable to form a film).

Next, as shown in FIG. 6 (B), a groove 546 is formed to separate the ID chips from each other. The groove 546 may have a depth such that the release layer 501 is exposed. Dicing, scribing, photolithography and the like can be used to form the groove 546. If it is not necessary to separate the ID chip formed on the first substrate 500, it is not always necessary to form the groove 546.

Next, as shown in FIG. 6C, the release layer 501 is removed by etching. In the present embodiment, fluorine halide is used as the etching gas, and the gas is introduced from the groove 546. In this embodiment, for example, ClF₃Using (chlorine trifluoride), temperature: 350 ° C, flow rate: 300sccm, atmospheric pressure: 8 × 10²Pa (6Torr), time: 3 hours. Also, ClF₃A gas obtained by mixing nitrogen with the gas may be used. ClF₃By using a halogen fluoride such as the above, the release layer 501 is selectively etched, and the first substrate 500 can be separated from the TFTs 529 to 531. The halogen fluoride may be either a gas or a liquid.

Next, as shown in FIG. 7 (A), the peeled TFTs 529 to 531 are attached to the second substrate 548 using the adhesive 547. The adhesive 547 uses a material capable of adhering the second substrate 548 and the base film 502. As the adhesive 547, for example, various curable adhesives such as reaction-curable adhesives, thermosetting adhesives, photocurable adhesives such as ultraviolet curable adhesives, and anaerobic adhesives can be used.

As the second substrate 548, for example, a glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or an organic material such as flexible paper or plastic can be used. Alternatively, a flexible inorganic material may be used as the second substrate 548. As the plastic substrate, ARTON (manufactured by JSR) made of polynorbornene with a polar group can be used. In addition, polyester typified by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide. (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin and the like can be mentioned. The second substrate 548 preferably has a high thermal conductivity of about 2 to 30 W / mK in order to diffuse the heat generated in the integrated circuit.

Next, as shown in FIG. 7 (A), the insulating layer 549 is formed so as to cover the separating insulating film 542. The insulating layer 549 uses an insulator 550 in which fine particles 551 formed of a soft magnetic material are dispersed. An organic resin such as polyimide, epoxy, acrylic, or polyamide can be used for the insulator 550. In addition to the above organic resin, an inorganic resin such as a siloxane-based material can be used. As the substituent of the siloxane-based resin, an organic group containing at least hydrogen (for example, an alkyl group, an aromatic hydrocarbon, etc.) is used. Alternatively, a fluoro group may be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent.

As the soft magnetic material used for the fine particles 551, for example, Fe, Co, Ni, or an alloy using any one or more of these, as well as 3Y₂O₃ 5Fe₂O₃(YIG), Fe₂O₃, Fe-Si-Al alloy, Fe-Cr alloy, FeP alloy, Ni or Ni-Fe alloy with one or more of Mo, Cu, Cr, Nb added to Permalloy alloy. Further, as the soft magnetic material, soft ferrite typified by Mn-Zn ferrite can also be used.

It is desirable to appropriately adjust the concentration and specific surface area of the fine particles 551 depending on the soft magnetic material used. If the concentration of the soft magnetic material is too high, the resistance of the insulating layer 549 decreases, causing a loss of magnetic flux due to eddy current, and it is difficult to increase the inductance. On the contrary, even if the concentration of the soft magnetic material is too low, the magnetic permeability of the entire insulating layer 549 is too low, and it is difficult to increase the inductance of the antenna 541. Further, if the specific surface area of the fine particles 551 is too small, the diameter of the fine particles 551 becomes too large, and it becomes difficult to uniformly disperse the fine particles 551 between the conducting wires constituting the antenna 541. On the contrary, if the specific surface area of the fine particles 551 is too large, the fine particles 551 tend to aggregate, which also makes it difficult to uniformly disperse the fine particles 551 between the conducting wires. Fe as a soft magnetic material₂O₃When using, for example, the specific surface area of fine particles 551 is 50 to 300 m.²The insulating layer 549 can be formed so that the concentration is 40 to 50 mol% at / g.

Next, the adhesive 552 is applied on the insulating layer 549, and the cover material 553 is attached. As the cover material 553, the same material as that of the second substrate 548 can be used. The thickness of the adhesive 552 may be, for example, 10 to 200 μm.

Further, as the adhesive 552, a material capable of adhering the cover material 553 and the insulating layer 549 is used. As the adhesive 552, for example, various curable adhesives such as reaction-curable adhesives, thermosetting adhesives, photocurable adhesives such as ultraviolet curable adhesives, and anaerobic adhesives can be used.

In the present embodiment, the cover material 553 is attached to the insulating layer 549 by using the adhesive 552, but the present invention is not limited to this configuration. By using a resin having a function as an adhesive for the insulator 550 of the insulating layer 549, the insulating layer 549 and the cover material 553 can be directly bonded to each other.

Further, in the present embodiment, as shown in FIG. 7B, an example in which the cover material 553 is used is shown, but the present invention is not limited to this configuration. For example, the process may be completed up to the process shown in FIG. 7 (A).

The ID chip is completed through each of the above steps. By the above manufacturing method, a dramatically thin integrated circuit having a total film thickness of 0.3 μm or more and 3 μm or less, typically about 2 μm, can be formed between the second substrate 548 and the cover material 553. The thickness of the integrated circuit includes not only the thickness of the semiconductor element itself but also the thickness of various insulating films and interlayer insulating films formed between the adhesive 547 and the adhesive 552, and does not include the antenna. .. In addition, the area occupied by the integrated circuit of the ID chip is 5 mm square (25 mm).²) Below, more preferably 0.3 mm square (0.09 mm)²) ~ 4mm square (16mm)²) Can be.

By locating the integrated circuit in the center between the second substrate 548 and the cover material 553, the mechanical strength of the ID chip can be increased. Specifically, assuming that the distance between the second substrate 548 and the cover material 553 is d, the distance x between the center in the thickness direction of the integrated circuit and the second substrate 548 becomes the following equation 1. It is desirable to control the thickness of the adhesive 547 and the adhesive 552 so as to satisfy the formula shown.

<maths num="1"><img file="JP2005294818A_D0001.tif" /></maths>

Further, preferably, the thicknesses of the adhesive 547 and the adhesive 552 are controlled so as to satisfy the formula shown in Equation 2 below.

<maths num="2"><img file="JP2005294818A_D0002.tif" /></maths>

In addition, as shown in FIG. 8, the distance (t) from the island-shaped semiconductor film of the TFT to the underlying film underneath in the integrated circuit._under) And the distance from the island-shaped semiconductor film to the upper third interlayer insulating film 540 (t)._over) May be equal or substantially equal, and the thickness of the base film 502, the first interlayer insulating film 533, the second interlayer insulating film 534, or the third interlayer insulating film 540 may be adjusted. By arranging the island-shaped semiconductor film in the center of the integrated circuit in this way, the stress on the semiconductor layer can be relaxed and the occurrence of cracks can be prevented.

Further, in the present embodiment, the insulating layer is only formed so as to cover the antenna, but the present invention is not limited to this configuration. An insulating layer in which a soft magnetic material is dispersed may be formed between the antenna and the second substrate. In FIG. 17, a third interlayer insulating film 1704 is formed on the second interlayer insulating film 1701, and the third interlayer insulating film 1704 has two layers of insulating films 1702 and 1703 laminated in this order. The cross-sectional view of the ID chip is shown in the case where the ID chip is formed in. The antenna 1705 is formed on the third interlayer insulating film 1704. Among the insulating films 1702 and 1703, the insulating film 1703 closest to the antenna 1705 is dispersed with fine particles formed of a soft magnetic material. Therefore, in FIG. 17, the insulating film 1703 corresponds to the insulating layer of the present invention. Further, in the ID chip shown in FIG. 17, the antenna 1705 is covered with the separating insulating film 1706, and the insulation in which fine particles formed of the soft magnetic material are dispersed so as to cover the antenna 1705 and the separating insulating film 1706. Layer 1707 is formed.

The separating insulating film 1706 does not necessarily have to be provided. Further, the insulating layer 1707 may be formed only between the conducting wires constituting the antenna 1705. Further, an insulating film for separation may be formed between the insulating film 1703 and the antenna 1705.

As shown in FIG. 17, by forming the insulating film 1703 that functions as an insulating layer, the gain of the antenna can be further increased.

In the present embodiment, a method of providing a release layer between the first substrate 500 having high heat resistance and the integrated circuit and removing the release layer by etching to separate the substrate from the integrated circuit has been described. The method for producing the ID chip of the present invention is not limited to this configuration. For example, a metal oxide film may be provided between the substrate having high heat resistance and the integrated circuit, and the metal oxide film may be fragile by crystallization to peel off the integrated circuit. Alternatively, a release layer using an amorphous semiconductor film containing hydrogen is provided between the highly heat-resistant substrate and the integrated circuit, and the release layer is removed by irradiation with laser light to separate the substrate from the integrated circuit. You may. Alternatively, the integrated circuit may be separated from the substrate by mechanically removing the highly heat-resistant substrate on which the integrated circuit is formed or removing it by etching with a solution or gas.

When an organic resin is used for the adhesive 547 in contact with the base film 502 in order to ensure the flexibility of the ID chip, by using a silicon nitride film or a silicon nitride film as the base film 502, the organic resin can be changed to Na, etc. It is possible to prevent the alkali metal and the alkaline earth metal from diffusing into the semiconductor film.

Further, the surface of the object has a curved surface, so that the second substrate 548 of the ID chip bonded to the curved surface is bent so as to have a curved surface drawn by the movement of the generatrix such as a conical surface or a pillar surface. In this case, it is desirable to align the direction of the bus with the direction in which the carriers of TFT529 to 531 move. With the above configuration, even if the second substrate 548 is bent, it is possible to suppress the influence on the characteristics of TFT 529 to 531. In addition, by setting the ratio of the area occupied by the island-shaped semiconductor film in the integrated circuit to 1 to 30%, even if the second substrate 548 bends, the characteristics of TFT 529 to 531 will be affected. It can be suppressed more.

The frequencies of radio waves generally used in ID chips are often 13.56MHz and 2.45GHz, and it is very important to form an ID chip so that radio waves of that frequency can be detected in order to improve versatility. Is.

Further, the ID chip of the present embodiment has an advantage that radio waves are less likely to be shielded than an ID chip formed by using a semiconductor substrate, and the signal can be prevented from being attenuated by the shielding of radio waves. Therefore, since it is not necessary to use a semiconductor substrate, the cost of the ID chip can be significantly reduced. For example, when using a silicon substrate with a diameter of 12 inches and 730 x 920 mm²Compare with the case of using the glass substrate of. The area of the former silicon substrate is about 73000 mm²However, the area of the latter glass substrate is about 672000 mm.²The glass substrate is equivalent to about 9.2 times that of the silicon substrate. The area of the latter glass substrate is about 672000 mm²Then, ignoring the area consumed by the division of the substrate, it is calculated that about 672,000 1 mm square ID chips can be formed, which is about 9.2 times the number of the silicon substrate. And the capital investment for mass production of ID chips is 730 x 920 mm.²Since the number of steps is smaller when the glass substrate is used than when the silicon substrate with a diameter of 12 inches is used, the amount can be reduced to one-third. Further, in the present invention, the glass substrate can be reused after the integrated circuit is peeled off. Therefore, even considering the cost of compensating for the damaged glass substrate and cleaning the surface of the glass substrate, the cost can be significantly reduced as compared with the case of using the silicon substrate. Even if the glass substrate is discarded without being reused, it is 730 x 920 mm.²Since the cost of the glass substrate is about half that of a silicon substrate with a diameter of 12 inches, it can be seen that the cost of the ID chip can be significantly reduced.

Therefore, 730 x 920 mm²It can be seen that the price of the ID chip can be reduced to about 1/30 when the glass substrate of No. 1 is used as compared with the case where the silicon substrate with a diameter of 12 inches is used. Since the ID chip is expected to be used for disposable purposes, the ID chip of the present invention, which can significantly reduce the cost, is very useful for the above-mentioned use.

In the present embodiment, an example in which the integrated circuit is peeled off and attached to a flexible substrate has been described, but the present invention is not limited to this configuration. For example, when a substrate having a heat resistant temperature that can withstand heat treatment in the process of manufacturing an integrated circuit, such as a glass substrate, is used, it is not always necessary to peel off the integrated circuit. 9 (A) and 9 (B) show a cross-sectional view of an ID chip formed by using a glass substrate.

In the ID chip shown in FIG. 9A, a glass substrate is used as the substrate 570, and TFTs 571 to 573 are formed directly on the substrate 570 without being peeled off. Specifically, it is formed so that the substrate 570 and the substrate film 574 are in contact with each other without sandwiching an adhesive between the TFTs 571 to 573 and the substrate 570. Note that FIG. 9B corresponds to a cross-sectional view of the ID chip in which the cover material 575 is attached to the ID chip shown in FIG. 9A.

A configuration of a semiconductor device such as an ID chip when the wiring connected to the TFT and the antenna are formed together by patterning the conductive film will be described with reference to FIG. 10 (A). FIG. 10A shows a cross-sectional view of the ID chip of this embodiment.

In FIG. 10A, the TFT 1401 includes an island-shaped semiconductor film 1402, a gate insulating film 1403 in contact with the island-shaped semiconductor film 1402, and an island-shaped semiconductor film 1402 with the gate insulating film 1403 sandwiched between them. It has an overlapping gate electrode 1404. The TFT 1401 is covered with a first interlayer insulating film 1405 and a second interlayer insulating film 1406. In this embodiment, the TFT 1401 is covered with two interlayer insulating films, a first interlayer insulating film 1405 and a second interlayer insulating film 1406, but this embodiment is not limited to this configuration. The TFT1401 may be covered with a single-layer interlayer insulating film, or may be covered with three or more layers of interlayer insulating film.

The wiring 1407 formed on the second interlayer insulating film 1406 is formed on the island-shaped semiconductor film 1402 via the contact holes formed in the first interlayer insulating film 1405 and the second interlayer insulating film 1406. It is connected.

An antenna 1408 is formed on the second interlayer insulating film 1406. The wiring 1407 and the antenna 1408 can be formed together by forming a conductive film on the second interlayer insulating film 1406 and patterning the conductive film. By forming the antenna 1408 together with the wiring 1407, the number of ID chip manufacturing steps can be reduced.

A separation insulating film 1409 is formed so as to cover the antenna 1408, and an insulating layer 1410 is further formed so as to cover the antenna 1408 and the separation insulating film 1409. The insulating layer 1410 does not necessarily have to cover the entire antenna 1408, and may be formed so as to be arranged between the conducting wires constituting the antenna 1408.

Further, in FIG. 10A, the insulating layer 1410 is selectively formed in the region where the antenna 1408 is formed, but this embodiment is not limited to this configuration. The insulating layer 1410 may be formed so as to cover the wiring 1407. However, in this case, it is desirable that the separating insulating film 1409 is formed so as to cover the wiring 1407.

Next, with reference to FIG. 10B, the configuration of the ID chip when the gate electrode of the TFT and the antenna are formed together by patterning the conductive film will be described. FIG. 10B shows a cross-sectional view of the ID chip of this embodiment.

In FIG. 10B, the TFT 1411 has an island-shaped semiconductor film 1412, a gate insulating film 1413 overlapping the island-shaped semiconductor film 1412, and an island-shaped semiconductor film 1412 with the gate insulating film 1413 sandwiched between them. It has an overlapping gate electrode 1414. An antenna 1418 is formed on the gate insulating film 1413. The gate electrode 1414 and the antenna 1418 can be formed together by forming a conductive film on the gate insulating film 1413 and patterning the conductive film. By forming the antenna 1418 together with the gate electrode 1414 with the same material, the number of ID chip manufacturing steps can be reduced.

An insulating layer 1420 is formed so as to cover the antenna 1418. The insulating layer 1420 does not necessarily have to cover the entire antenna 1418, and may be formed so as to be arranged between the conducting wires constituting the antenna 1418.

Further, although FIG. 10B shows a configuration in which the insulating film for separation is not formed, the present invention is not limited to this configuration. An insulating film for separation may be formed between the antenna 1418 and the insulating layer 1420.

In this example, an example in which the integrated circuit is peeled off and attached to a separately prepared substrate has been described, but the present invention is not limited to this configuration. For example, when a substrate having a heat resistant temperature that can withstand heat treatment in the process of manufacturing an integrated circuit, such as a glass substrate, is used, it is not always necessary to peel off the integrated circuit. In addition, this embodiment can be used freely in combination with other embodiments or examples.

In this embodiment, one form of a functional configuration of the semiconductor device such as the ID chip of the present invention will be described with reference to FIG.

In FIG. 11, 900 corresponds to an antenna and 901 corresponds to an integrated circuit. Further, 903 corresponds to the capacitance formed between both terminals of the antenna 900. The integrated circuit 901 includes a demodulation circuit 909, a modulation circuit 904, a rectifier circuit 905, a microprocessor 906, a memory 907, and a switch 908 for applying load modulation to the antenna 900. The memory 907 is not limited to one, and may be a plurality, and SRAM, flash memory, ROM, FRAM (registered trademark), or the like can be used.

The signal sent as a radio wave from the reader / writer is converted into an AC electric signal by electromagnetic induction at the antenna 900. The demodulation circuit 909 demodulates the AC electric signal and transmits it to the microprocessor 906 in the subsequent stage. Further, in the rectifier circuit 905, a power supply voltage is generated using an AC electric signal and supplied to the microprocessor 906 in the subsequent stage. The microprocessor 906 performs various arithmetic processes according to the input signal. The memory 907 stores programs, data, and the like used in the microprocessor 906, and can also be used as a work area during arithmetic processing.

Then, when data is sent from the microprocessor 906 to the modulation circuit 904, the modulation circuit 904 can control the switch 908 and apply load modulation to the antenna 900 according to the data. The reader / writer can receive the load modulation applied to the antenna 900 by radio waves, and as a result, can read the data from the microprocessor 906.

The ID chip shown in FIG. 11 merely shows one embodiment of the present invention, and the present invention is not limited to the above configuration. The ID chip of the present invention does not necessarily have to have the microprocessor 906. Further, the signal transmission method is not limited to the electromagnetic coupling method as shown in FIG. 11, and an electromagnetic induction method may be used.

This embodiment can be carried out in any combination with other embodiments or examples.

In this embodiment, the configuration of the TFT used in the semiconductor device such as the ID chip of the present invention will be described.

FIG. 12A shows a cross-sectional view of the TFT of this embodiment. 701 corresponds to an n-channel TFT, and 702 corresponds to a p-channel TFT. A more detailed configuration will be described by taking the n-channel TFT701 as an example.

The n-channel type TFT 701 has an island-shaped semiconductor film 705 used as an active layer, and the island-shaped semiconductor film 705 has two impurity regions 703 used as a source region or a drain region and the two impurity regions 703. It has a channel forming region 704 sandwiched between the two impurity regions 703 and two LDD (Lightly Doped Drain) regions 710 sandwiched between the two impurity regions 703 and the channel forming region 704. Further, the n-channel type TFT 701 has a gate insulating film 706 covering the island-shaped semiconductor film 705, a gate electrode 707, and two sidewalls 708 and 709 formed of the insulating film.

In this embodiment, the gate electrode 707 has two layers of conductive films 707a and 707b, but the present invention is not limited to this configuration. The gate electrode 707 may be formed of one layer of conductive film or may be formed of two or more layers of conductive film. The gate electrode 707 overlaps with the channel forming region 704 of the island-shaped semiconductor film 705 with the gate insulating film 706 in between. Further, the sidewalls 708 and 709 overlap with the two LDD regions 710 of the island-shaped semiconductor film 705 with the gate insulating film 706 in between.

The sidewall 708 can be formed, for example, by etching a silicon oxide film having a thickness of 100 nm, and the sidewall 709 can be formed, for example, by etching an LTO film (Low Temperature Oxide) having a thickness of 200 nm. .. In this embodiment, the silicon oxide film used for the sidewall 708 is formed by the plasma CVD method, and the LTO film used for the sidewall 709 is formed by the reduced pressure CVD method. Nitrogen may be mixed in the silicon oxide film, but the number of nitrogen atoms is smaller than the number of oxygen atoms.

The impurity region 703 and the LDD region 710 form sidewalls 708 and 709 after doping the island-shaped semiconductor film 705 with n-type impurities using the gate electrode 707 as a mask, and the islands serve as the sidewalls 708 and 709 masks. By doping the semiconductor film 705 in the shape of an n-type impurity, it can be produced separately.

The p-channel type TFT 702 has almost the same configuration as the n-channel type TFT 701, but differs only in the configuration of the island-shaped semiconductor film 711 of the p-channel type TFT 702. The island-shaped semiconductor film 711 does not have an LDD region, but has two impurity regions 712 and a channel forming region 713 sandwiched between the two impurity regions 712. The impurity region 712 is doped with p-type impurities. Note that FIG. 12A shows an example in which the p-channel type TFT702 does not have an LDD region, but the present invention is not limited to this configuration. The p-channel type TFT 702 may have an LDD region.

FIG. 12 (B) shows the case where the sidewall is a single layer in the TFT shown in FIG. 12 (A). The n-channel type TFT721 and the p-channel type TFT722 shown in FIG. 12B have single-layer sidewalls 728 and 729, respectively. The sidewalls 728 and 729 can be formed, for example, by etching a silicon oxide film having a film thickness of 100 nm. In this embodiment, the silicon oxide film used for the sidewall 728 is formed by the plasma CVD method. Nitrogen may be mixed in the silicon oxide film, but the number of nitrogen atoms is smaller than the number of oxygen atoms.

Next, Fig. 12 (C) shows the configuration of the bottom gate type TFT. 741 corresponds to an n-channel TFT and 742 corresponds to a p-channel TFT. A more detailed configuration will be described by taking the n-channel TFT741 as an example.

In FIG. 12C, the n-channel TFT 741 has an island-shaped semiconductor film 745, and the island-shaped semiconductor film 745 has two impurity regions 743 used as a source region or a drain region, and the two. It has a channel forming region 744 sandwiched between the impurity regions 743 and two LDD (Lightly Doped Drain) regions 750 sandwiched between the two impurity regions 743 and the channel forming region 744. Further, the n-channel type TFT 741 has a gate insulating film 746, a gate electrode 747, and a channel protective film 748 formed of the insulating film.

The gate electrode 747 has a gate insulating film 746 in between and overlaps the channel forming region 744 of the island-shaped semiconductor film 745. The gate insulating film 746 is formed after the gate electrode 747 is formed, and the island-shaped semiconductor film 745 is formed after the gate insulating film 746 is formed. Further, the channel protective film 748 overlaps with the gate insulating film 746 with the channel forming region 744 in between.

The channel protection film 748 can be formed, for example, by etching a silicon oxide film having a film thickness of 100 nm. In this embodiment, the silicon oxide film used for the channel protection film 748 is formed by the plasma CVD method. Nitrogen may be mixed in the silicon oxide film, but the number of nitrogen atoms is smaller than the number of oxygen atoms.

In the impurity region 743 and LDD region 750, an n-type impurity is doped into an island-shaped semiconductor film 745 using a mask formed by a resist, and then a channel protective film 748 is formed, and the island-shaped semiconductor film 748 is formed as an island-shaped mask. By doping the semiconductor film 745 of No. 745 with n-type impurities, it can be produced separately.

The p-channel type TFT742 has almost the same configuration as the n-channel type TFT741, but differs only in the configuration of the island-shaped semiconductor film 751 of the p-channel type TFT742. The island-shaped semiconductor film 751 does not have an LDD region, but has two impurity regions 752 and a channel formation region 753 sandwiched between the two impurity regions 752. The impurity region 752 is doped with p-type impurities. Note that FIG. 12C shows an example in which the p-channel type TFT 742 does not have an LDD region, but the present invention is not limited to this configuration. The p-channel type TFT 742 may have an LDD region. Further, the n-channel TFT741 does not have to have an LDD region. In addition, this embodiment can be used freely in combination with other embodiments or examples.

In this embodiment, a method of manufacturing a semiconductor device such as a plurality of ID chips using a large substrate will be described.

First, the integrated circuit 401 and the antenna 402 are formed on a heat-resistant substrate, then peeled off and bonded to a separately prepared substrate 403 using an adhesive 404 as shown in FIG. 13 (A). Note that FIG. 13A shows a state in which the integrated circuit 401 and the antenna 402 are attached to the substrate 403 one by one, but the present invention is not limited to this configuration. The set of the integrated circuit 401 and the antenna 402 may be peeled off from the substrate in a state of being connected to each other and bonded to the substrate 403 at once.

Next, as shown in FIG. 13B, the cover material 405 is attached to the substrate 403 so as to sandwich the integrated circuit 401 and the antenna 402 between them. At this time, the adhesive 406 is applied on the substrate 403 so as to cover the integrated circuit 401 and the antenna 402. By attaching the cover material 405 to the substrate 403, the state shown in FIG. 13 (C) can be obtained. In FIG. 13C, the integrated circuit 401 and the antenna 402 are shown so as to be seen through the cover material 405 in order to clarify the positions of the integrated circuit 401 and the antenna 402.

Next, as shown in FIG. 13 (D), by dicing or scribing, to separate the integrated circuit 401 and the antenna 402 to one another in Rukoto to complete the ID chip 407.

An ID chip using a glass substrate can be called an IDG chip (Identification Glass Chip), and an ID chip using a flexible substrate can be called an IDF chip (Identification Flexible Chip).

This example can be carried out in combination with Examples 1 to 3.

In this embodiment, the shape of the groove formed when a plurality of integrated circuits formed on one substrate are peeled off will be described. FIG. 14A shows a top view of the substrate 603 in which the groove 601 is formed. Further, FIG. 14 (B) shows a cross-sectional view taken along the line A-A'of FIG. 14 (A).

The integrated circuit 602 is formed on the release layer 604, and the release layer 604 is formed on the substrate 603. The groove 601 is formed between the integrated circuits 602 and has a depth such that the release layer 604 is exposed. Also, in this embodiment, the plurality of integrated circuits 602 are partially but not completely separated by a groove 601.

Next, FIGS. 14 (C) and 14 (D) show the state after the etching gas is poured from the grooves 601 shown in FIGS. 14 (A) and 14 (B) and the release layer 604 is removed by etching. .. FIG. 14 (C) corresponds to a top view of the substrate 603 in which the groove 601 is formed, and FIG. 14 (D) corresponds to a cross-sectional view taken along the line A-A'of FIG. 14 (C). It is assumed that the etching of the release layer 604 has proceeded from the groove 601 to the region shown by the broken line 605 by etching. As shown in FIGS. 14 (C) and 14 (D), the release layer 604 was etched by separating the plurality of integrated circuits 602 by the groove 601 in a state where they were partially connected to each other rather than completely. It is possible to prevent each integrated circuit 602 from moving without being supported later.

After forming the state shown in FIGS. 14 (C) and 14 (D), a tape to which the adhesive is attached, a substrate, or the like is separately prepared, and the integrated circuit 602 is peeled off from the substrate 603. Then, the plurality of integrated circuits 602 separated from the substrate 603 are attached to a separately prepared substrate before or after being separated from each other.

In this embodiment, an example of a method for manufacturing a semiconductor device such as an ID chip is shown, and the method for manufacturing a semiconductor device of the present invention is not limited to the configuration shown in this embodiment.

This embodiment can be carried out in any combination with other embodiments or examples.

When a flexible substrate is used, the semiconductor device such as the ID chip of the present invention is suitable for bonding to a flexible object or a curved object. Further, if a memory such as a ROM in which data cannot be rewritten is formed in the integrated circuit of the ID chip of the present invention, it is possible to prevent forgery of the object to which the ID chip is attached. Further, for example, using the ID chip of the present invention for a food product whose commercial value is greatly influenced by the production area, the producer, etc. is useful for preventing camouflage of the production area, the producer, etc. at a low cost.

Specifically, the ID chip of the present invention can be used by being attached to a tag having information on an object, such as a tag, a price tag, or a name tag. Alternatively, the ID chip itself of the present invention may be used as a tag. Also, for example, it is attached to a certificate equivalent to a document certifying the fact, such as a copy of a family register, resident's card, passport, driver's license, ID card, membership card, certificate, credit card, cash card, prepaid card, medical examination ticket, commuter pass. You may. Further, for example, it may be attached to securities corresponding to securities indicating property rights under private law, such as bills, checks, freight exchange certificates, ship currency receipts, warehouse receipts, stock certificates, bonds, gift certificates, and mortgage securities.

FIG. 15 (A) shows an example of check 1301 to which the ID chip 1302 of the present invention is attached. In FIG. 15 (A), the ID chip 1302 is mounted inside the check 1301, but it may be exposed to the front. When the ID chip of the present invention uses a flexible substrate, it has an advantage that it is not easily broken by stress even if it is attached to the flexible check 1301.

FIG. 15B shows an example of a passport 1304 to which the ID chip 1303 of the present invention is attached. In FIG. 15B, the ID chip 1303 is attached to the cover of passport 1304, but may be attached to another page of passport 1304. When the ID chip of the present invention uses a flexible substrate, it has an advantage that it is not easily broken by stress even if it is attached to the cover of the flexible passport 1304.

FIG. 15C shows an example of the gift certificate 1306 to which the ID chip 1305 of the present invention is attached. The ID chip 1305 may be formed inside the gift certificate 1306, or may be formed so as to be exposed on the surface of the gift certificate 1306. When the ID chip of the present invention uses a flexible substrate, it has an advantage that it is not easily broken by stress even if it is attached to the flexible gift certificate 1306.

An ID chip using an integrated circuit having a TFT is inexpensive and thin. Therefore, the ID chip of the present invention is suitable for applications where it is finally thrown away by consumers. In particular, when used for a product in which a price difference of several yen or several tens of yen greatly affects sales, the packaging material having an inexpensive and thin ID chip of the present invention is very useful. The packaging material corresponds to a support that can be molded or molded to wrap an object such as a wrap, a PET bottle, a tray, or a capsule.

FIG. 16A shows how the packaging material 1308 to which the ID chip 1307 of the present invention is attached wraps the lunch box 1309 for sale. By recording the price of the product in the ID chip 1307, the price of the lunch box 1309 can be settled at the register that functions as a reader / writer. Furthermore, it is possible to easily manage the inventory of products and the expiration date of products.

Further, for example, it is possible to attach the ID chip of the present invention to the label of the product and use the ID chip to manage the distribution of the product.

As shown in FIG. 16 (B), the ID chip 1311 of the present invention is attached to a support such as a product label 1310 whose back surface has adhesiveness. Then, the label 1310 to which the ID chip 1311 is attached is attached to the product 1312. The identification information about the product 1312 can be read wirelessly from the ID chip 1311 attached to the label 1310. Therefore, the ID chip 1311 facilitates product management in the distribution process. When the ID chip of the present invention uses a flexible substrate, it has an advantage that it is not easily broken by stress even if it is attached to the flexible label 1310. Therefore, the label 1310 using the ID chip of the present invention is suitable for being attached to an object having a curved surface.

For example, when a writable non-volatile memory is used as the memory of the integrated circuit in the ID chip 1311, the distribution process of the product 1312 can be recorded. In addition, by recording the process at the production stage of the product, it becomes easy for the wholesaler, the retailer, and the consumer to grasp the place of origin, the producer, the date of manufacture, the processing method, and the like.

This embodiment can be implemented in any combination with other embodiments or configurations of the embodiments.

<figref num="1">A perspective view and a cross-sectional view of the ID chip of the present invention.</figref><figref num="2">Sectional drawing of the antenna which the ID chip of this invention has.</figref><figref num="3">Sectional drawing of the antenna which the ID chip of this invention has.</figref><figref num="4">The figure which shows the manufacturing method of the ID chip of this invention.</figref><figref num="5">The figure which shows the manufacturing method of the ID chip of this invention.</figref><figref num="6">The figure which shows the manufacturing method of the ID chip of this invention.</figref><figref num="7">The figure which shows the manufacturing method of the ID chip of this invention.</figref><figref num="8">The figure which shows the manufacturing method of the ID chip of this invention.</figref><figref num="9">The figure which shows the manufacturing method of the ID chip of this invention.</figref><figref num="10">Sectional drawing of the ID chip of this invention.</figref><figref num="11">The block diagram which shows one form of the functional structure of the ID chip of this invention.</figref><figref num="12">Sectional drawing of the TFT which the ID chip of this invention has.</figref><figref num="13">The figure which shows the method of manufacturing a plurality of integrated circuits used for the ID chip of this invention using a large-sized substrate.</figref><figref num="14">The figure which shows the shape of the groove formed at the time of peeling a plurality of integrated circuits formed on one substrate.</figref><figref num="15">The figure which shows the usage method of the ID chip of this invention.</figref><figref num="16">The figure which shows the usage method of the ID chip of this invention.</figref><figref num="17">Sectional drawing of the ID chip of this invention.</figref>

Code description

100 Integrated circuit 101 Antenna 102 Board 103 Cover material 104 TFT105 Lead wire 106 Insulation layer 107 Dashed line 108 Fine particles 109 Separation insulating film 110 Insulator 111 Interlayer insulating film