Semiconductor device and manufacturing method therefor

The present invention relates to a semiconductor device having a memory transistor on a substrate and a method for manufacturing the same.

In recent years, the number of semiconductor storage devices such as computers having a non-volatile semiconductor storage element for storing data and programs has increased. A semiconductor storage device generally identifies the location of a memory transistor by a memory cell array having a plurality of memory transistors (also called memory cell transistors) in which data is stored, a circuit for writing, erasing, or reading, and an address signal. It consists of a decoder. Since the elements constituting each of these circuits have different characteristics required for each, the configuration also differs accordingly.

EEPROM (Electric Erasable Programmable Read Only Memory) and flash memory (flash memory) are known as representative memories of semiconductor non-volatile memory. Among these memories, when a memory transistor having a floating gate electrode is used, it is necessary to make the tunnel oxide film between the semiconductor layer of the memory transistor and the floating gate electrode as thin as possible. This is because the tunnel oxide film must be thin enough to allow the tunnel current to flow. In addition to the floating gate electrode and the tunnel oxide film, the memory transistor is composed of two gate electrodes and two insulating films because it has a control gate electrode and an insulating film sandwiched between the control gate electrode and the floating gate electrode. ing.

Since the transistors constituting the decoder are required to operate at high speed, it is desirable that the gate insulating film is a thin film.

On the other hand, in a circuit that writes, erases, and reads, in terms of its operation, the transistors that make up the circuit are subject to a high voltage that is as high as the voltage applied to the memory transistor. It is necessary to thicken the gate insulating film.

As described above, the semiconductor storage device is manufactured by integrating elements having different configurations.

As a related technology, there is a technology for manufacturing an active matrix substrate in which a pixel unit, a drive circuit unit, and a memory unit are integrally formed on the same substrate. In this case as well, transistors having different configurations are integrated on the active matrix substrate. Is made. Specifically, in order to manufacture a transistor having a structure corresponding to each function, the gate insulating film of the transistor in the memory portion is made thinner than the film thickness of the gate insulating film in the pixel portion and the drive circuit portion. (See Patent Document 1 above).<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2000-356788</text></patcit>

<p> When a semiconductor storage device is manufactured on the same substrate by integrating transistors having different configurations as described above, elements with a thick gate insulating film, elements with a thin gate insulating film, elements with one gate electrode, two elements, etc. coexist, so naturally. The number of steps tended to increase. Further, if the elements having different configurations are manufactured and then connected to each other by wiring, the number of steps can be shortened, but there is a problem that the semiconductor storage device becomes large.</p><p> Therefore, an object of the present invention is to provide a semiconductor device in which elements having different configurations are manufactured on the same substrate while shortening the number of steps, and a manufacturing process thereof.</p>

<p> In order to solve the above problems, the semiconductor device of the present invention includes a first active layer, a first gate insulating film on the first active layer, a floating gate electrode on the first gate insulating film, and a floating gate. It has a first transistor having a second gate insulating film on the electrode and a control gate electrode on the second gate insulating film, and also has a second active layer and gate insulation on the second active layer. It has a film and a second transistor having a gate electrode on the gate insulating film, the first transistor and the second transistor are provided on the same substrate, and the gate insulating film of the second transistor is the lower gate insulating film. It has a film and an upper gate insulating film, the lower gate insulating film of the second transistor is formed from the same layer as the first gate insulating film, and the upper gate insulating film is formed from the same layer as the second gate insulating film. It is characterized by being.</p><p> Further, the semiconductor device of the present invention includes a first active layer, a first gate insulating film on the first active layer, a floating gate electrode on the first gate insulating film, and a second gate on the floating gate electrode. A first transistor having an insulating film and a control gate electrode on the second gate insulating film, a second active layer, a gate insulating film on the second active layer, and a gate electrode on the gate insulating film. The first transistor and the second transistor are provided on the same substrate, and the gate electrode of the second transistor has a lower gate electrode and an upper gate electrode. The lower gate electrode of the transistor 2 is formed from the same layer as the floating gate electrode, and the upper gate electrode is formed from the same layer as the control gate electrode.</p><p> Further, the first active layer, the first gate insulating film on the first active layer, the floating gate electrode on the first gate insulating film, the second gate insulating film on the floating gate electrode, and the second gate. A first transistor having a control gate electrode on an insulating film, a second active layer, a gate insulating film on the second active layer, and a second transistor having a gate electrode on the gate insulating film. , A third active layer, a gate insulating film on the third active layer, and a third transistor having a gate electrode on the gate insulating film, and these first to third transistors are the same. Provided on the substrate, the gate insulating film of the third transistor has a lower gate insulating film and an upper gate insulating film, and the lower gate insulating film of the third transistor is the gate insulating film of the first gate and the second transistor. It is formed from the same layer as the film, the upper gate insulating film is formed from the same layer as the second gate insulating film, and the gate electrode of the second transistor has a lower gate electrode and an upper gate electrode, and the second transistor. The lower gate electrode of the above is formed from the same layer as the floating gate electrode, and the upper gate electrode is formed from the same layer as the control gate electrode and the gate electrode of the third transistor.</p><p> It is characterized in that the gate electrode of the second transistor is routed by using the upper gate electrode formed from the same layer as the control gate electrode of the first transistor.</p><p> The active layer is characterized by being a crystalline semiconductor film or a microcrystalline semiconductor film.</p><p> In the semiconductor device of the present invention, the first insulating film is formed on the active layer of the first transistor and the active layer of the second transistor, the first conductive film is formed on the first insulating film, and the first conductive film is formed. By selectively etching, the first conductive film on the active layer of the second transistor is removed to expose the first insulating film on the active layer of the second transistor, and the etched first conductive film is exposed. By forming a second insulating film on the film and the exposed first insulating film, forming a second conductive film on the second insulating film, and etching the second conductive film, the gate electrode of the second transistor and By forming the control gate electrode of the first transistor, etching the second conductive film, etching the second insulating film, etching the second insulating film, and then etching the etched first conductive film. , The floating gate electrode of the second transistor is formed, the gate insulating film of the second transistor is composed of the first insulating film and the second insulating film, and the first transistor and the second transistor are provided on the same substrate. It is characterized by being.</p><p> In the semiconductor device of the present invention, the first insulating film is formed on the active layer of the first transistor and the active layer of the second transistor, the first conductive film is formed on the first insulating film, and the first conductive film is formed. By forming a second insulating film on top and selectively etching the second insulating film, the second insulating film on the active layer of the second transistor is removed, and the second insulating film is on the active layer of the second transistor. The upper part of the second transistor is formed by exposing the first conductive film, forming the second conductive film on the etched second insulating film and the exposed first conductive film, and etching the second conductive film. The gate electrode and the control gate electrode of the first transistor are formed, and the lower gate electrode of the second transistor and the floating gate electrode of the first transistor are formed by etching the first conductive film, and the first transistor is formed. And the second transistor are characterized in that they are provided on the same substrate.</p><p> In the semiconductor device of the present invention, a first insulating film is formed on the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor, and the first conductive film is formed on the first insulating film. The first conductive film on the active layer of the third transistor is removed by forming the first conductive film and selectively performing the first etching on the first conductive film to remove the first conductive film on the active layer of the third transistor. To expose the insulating film, form a second insulating film on the first etched first conductive film and the exposed first insulating film, and selectively perform the second etching on the second insulating film. Removes the second insulating film on the active layer of the second transistor to expose the first conductive film on the active layer of the second transistor, and exposes the second etched second insulating film. By forming a second conductive film on the first conductive film and performing a third etching on the second conductive film, the control gate electrode of the first transistor, the upper gate electrode of the second transistor, and the third conductive film are formed. By forming the gate electrode of the transistor of the above, performing the fourth etching on the second etched second insulating film, and performing the fifth etching on the first etched first conductive film. The floating gate electrode of the first transistor and the lower gate electrode of the second transistor are formed, and the gate insulating film of the third transistor is composed of the first insulating film and the second insulating film, and the first transistor and the second transistor are formed. The third transistor is provided on the same substrate.</p><p> The first etching is characterized in that a pattern of a first conductive film covering the active layer of the first transistor and a pattern of the first conductive film covering the active layer of the second transistor are formed. ..</p><p> The floating gate electrode is made of a tantalum nitride film or a tantalum film, and the control gate electrode is made of a tungsten film.</p><p> In the present specification, a memory element having a floating gate electrode is sandwiched between a memory transistor, a transistor having a two-layer gate insulating film as a high withstand voltage transistor, and a first gate insulating film of the memory transistor (between the floating gate electrode and the active layer). A transistor having a gate insulating film having a film thickness similar to that of the gate insulating film) is called a high-speed transistor. The memory transistor can write and read information, and in some cases, the written information can be erased. The high-voltage transistor is a transistor that is subjected to a high voltage as high as the voltage applied to the memory transistor, and has a thick gate insulating film that is not destroyed even if a high voltage is applied. A high-speed transistor is a transistor that operates at high speed and constitutes a peripheral circuit such as a decoder.</p><p> In the present specification, the semiconductor storage device means a device having at least a memory transistor. Further, in the present specification, the semiconductor device means a device having at least a semiconductor storage device.</p>

<p> The present invention suppresses an increase in the number of steps by efficiently manufacturing other high-speed transistors and high-voltage transistors in accordance with memory transistors having a large number of steps during element formation among the transistors constituting the semiconductor device. , A low-cost semiconductor device can be manufactured on the same substrate. In addition, the following effects can be exhibited.</p><p> The first and second insulating films corresponding to the first and second gate insulating films of the memory transistor are laminated to form a gate insulating film of a high withstand voltage transistor having a thick film thickness. As a result, the gate insulating film of the high withstand voltage transistor can be formed without increasing the number of steps. Further, since the gate insulating film of the high withstand voltage transistor can be formed by laminating layers of different materials, a transistor having a desired capacitance and high withstand voltage can be formed.</p><p> Further, the first and second conductive films on which the floating gate electrode and the control gate electrode of the memory transistor are formed are laminated to form the gate electrode of the high-speed transistor. Thereby, the gate electrode of the high-speed transistor can be formed without increasing the number of steps. Further, since the gate electrode of the high-speed transistor can be processed into various shapes, a low-concentration impurity region can be provided outside the channel region called a low-concentration drain (LDD) structure. This low-concentration impurity region is called an LDD region, and in particular, a structure (GOLD (Gate-drain Overlapped LDD) structure) in which the LDD region overlaps with the gate electrode via a gate insulating film can be formed. By adopting such a structure, the withstand voltage of the transistor can be improved and the reliability can be improved.</p><p> Further, since the gate electrode of the high-speed transistor has two layers, a gate electrode material having an optimum work function as a gate electrode and a low resistance gate electrode material for routing can be combined to form a gate electrode. Therefore, a high-speed transistor having a low resistance and a desired threshold value can be obtained, and the range of materials used as a gate electrode is widened.</p><p> Further, according to the present invention, the etching of the conductive film and the insulating film, which is performed after the second conductive film is formed, can be etched by using the same resist mask for each transistor. That is, since it is not necessary to newly form a resist mask each time etching is performed, the resist mask can be formed only once and the process can be shortened. Specifically, in the memory transistor, etching for forming the control gate electrode and the floating gate electrode and etching of the second insulating film can be performed with one resist mask. In the high withstand voltage transistor, the etching for forming the gate electrode and the etching of the second insulating film can be performed by one resist mask. In a high-speed transistor, etching for forming upper and lower gate electrodes can be performed with one resist mask.</p><p> Further, the first conductive film is etched to expose the first insulating film on the active layer of the high withstand voltage transistor, and the pattern of the first conductive film (lower part) is placed on the active layer of the high-speed transistor and the active layer of the memory transistor. A film to be a gate electrode and a film to be a floating gate electrode) are formed respectively. At that time, in order to make the film to be the lower gate electrode and the film to be the floating gate electrode one size larger than the active layer of the high-speed transistor and the active layer of the memory transistor, the first step is to prevent plasma damage occurring in the subsequent steps. It is possible to prevent the gate insulating film of a thin film made of an insulating film.</p>

Hereinafter, the best mode for carrying out the invention will be described with reference to the drawings. However, those skilled in the art can easily understand that the present invention can be carried out in many different modes, and that the forms and details thereof can be variously changed without departing from the spirit and scope of the present invention. Will be done. Therefore, the present invention is not construed as being limited to the description of the present embodiment. Further, common parts in each drawing are designated by the same reference numerals, and detailed description thereof will be omitted.

(Embodiment 1) FIGS. 1 to 3 are diagrams showing a manufacturing process of a semiconductor storage device according to the present invention.

Examples of the substrate 101 of FIG. 1A include a quartz substrate, a ceramics substrate, a plastic substrate, a stainless steel substrate, a synthetic resin substrate, a flexible substrate, and the like. When these substrates are used, if an undercoat film (not shown) in contact with the substrate is required, it may be appropriately used, and in the present specification, the substrate on which the undercoat film is formed is also referred to as a substrate.

A semiconductor film is formed in contact with the substrate 101. As the semiconductor film to be formed, it is desirable to use a crystalline semiconductor obtained by crystallizing an amorphous semiconductor film formed by a film forming method such as a reduced pressure thermal CVD method, a plasma CVD method or a sputtering method by a laser crystallization method. .. Further, a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film formed by the film forming method by a solid phase growth method by heat treatment is used, or a crystalline semiconductor film crystallized by laser irradiation after heat treatment is used. May be used. Also, silane (SiH)₄) May be a crystalline semiconductor film obtained by laser-crystallizing a microcrystalline semiconductor film formed from). A microcrystalline semiconductor film may be used. The semiconductor material applied here includes silicon (Si), germanium (Ge), silicon germanium alloy, and silicon carbide, and compound semiconductor materials such as gallium arsenide can also be used. In this embodiment, a crystalline silicon film is formed as a semiconductor film. Further, a semiconductor film may be formed by using an SOI (Silicon on Insulator) substrate.

Then channel doping is performed to control the threshold. In this embodiment, the acceleration voltage is 25 kV and the material gas is B.₂H₆It is done using.

Next, the semiconductor film is patterned to form the active layers 102 to 104. The active layer 102 is a semiconductor layer constituting a high-speed transistor, the active layer 103 is a semiconductor layer constituting a high withstand voltage transistor, and the active layer 104 is a semiconductor layer constituting a memory transistor. A silicon oxide film is formed on these active layers as the first insulating film 105. When the silicon oxide film is used as the gate insulating film, there is an advantage that the interface level between the gate insulating film and the silicon film of the active layer is lowered. Further, since the first insulating film 105 functions as a gate insulating film for high-speed transistors and as a first gate insulating film which is a tunnel oxide film for memory transistors, the thinner the film, the higher the speed operation becomes and the easier it is for tunnel current to flow. Become. Therefore, any method may be used as long as the first insulating film 105 can be formed thinly, but if it is a heat-resistant substrate such as a quartz substrate, a thermal oxide film that can be formed uniformly thin is suitable. The film thickness of the first insulating film 105 is 1 to 100 nm, preferably 1 to 10 nm.

Subsequently, the first conductive film 106 is formed on the first insulating film 105 (FIG. 1 (A)). As the first conductive film 106, for example, a metal film or a semiconductor film doped with impurities can be used, and any film having conductivity may be used. When a semiconductor film is used, there are crystalline semiconductor films and microcrystalline semiconductor films, and the semiconductor materials and film forming methods thereof can be considered to be the same as those of the above-mentioned semiconductor films on which the active layers 102 to 104 are formed. In this embodiment, a tantalum nitride (TaN) film or a tantalum (Ta) film is used as the first conductive film 106. After that, the first conductive film 106 is etched to form a film 107 that becomes a lower gate electrode of the high-speed transistor and a film 108 that later becomes a floating gate electrode. At the same time, the first conductive film on the active layer 103 of the high withstand voltage transistor is removed, and the first insulating film under the first conductive film is exposed (FIG. 1 (B)).

At this time, it is desirable to use a material having a sufficiently large etching selectivity with the first insulating film 105 as the material of the first conductive film 106. For example, when the first conductive film 106 is a tantalum nitride film or a tantalum film and the first insulating film 105 is a silicon oxide film, Cl is used as the etching gas.₂By using the above, the etching selectivity of the first conductive film 106 with respect to the first insulating film can be set to 10 or more, and over-etching of the exposed first insulating film 105 can be prevented.

In addition, if the film thickness of the first conductive film 106 is reduced, the etching time of the first conductive film is shortened, so that overetching of the first insulating film 105 on the active layer 103 can be suppressed. Further, when the film thickness of the first conductive film is thin, the film coverage of the second insulating film to be formed next is also improved, and the underlying step is formed in the etching of the control gate electrode formed on the upper part of the second insulating film. The impact is reduced. From the above, the film thickness of the first conductive film 106 is preferably 5 to 100 nm, preferably 5 to 20 nm.

FIG. 1C is a top view showing the positional relationship between the active layers 102 to 104 of FIG. 1B, the film 107 serving as the lower gate electrode and the film 108 serving as the floating gate electrode above the active layers 102 to 104. The film 107 serving as the lower gate electrode is etched into a shape that is one size larger in both vertical and horizontal directions than the shape of the active layer 102. As a result, the active layer 102 of the high-speed transistor and the first insulating film portion of the high-speed transistor (gate insulating film of the high-speed transistor) are covered with the film 107 that serves as the lower gate electrode. This is to prevent the first insulating film portion of the high-speed transistor (the portion that functions as the gate insulating film of the high-speed transistor) from plasma damage in the plasma process that is performed later. In addition, the gate insulating film of a high-speed transistor is very thin, and even a small amount of damage tends to cause defects in the film, so it is very useful to prevent plasma damage.

Like the film 107 that becomes the lower gate electrode, the film 108 that becomes the floating gate electrode is also etched into a shape that is one size larger in both vertical and horizontal directions than the shape of the active layer 104, and the active layer 104 of the memory transistor and the first insulating film of the memory transistor are etched. The portion (the portion that functions as the first gate insulating film of the memory transistor) is covered with the film 108 that serves as the floating gate electrode. As a result, the first insulating film 105 can be prevented from plasma damage, and defects generated in the first gate insulating film can be suppressed. If there is a defect in the first gate insulating film even at one place, all the charge accumulated in the floating gate electrode leaks from the defect, which greatly affects the charge retention characteristics of the memory transistor. I don't need it.

Further, the length in the channel width direction (longitudinal direction in FIG. 1C) of the film 108 is maintained as it is even after the etching for forming the floating gate electrode, which is performed later. Therefore, since the area of the large floating gate electrode can be maintained, lengthening the channel width direction of the membrane 108 is effective for optimizing the charge injection / erasing efficiency during the operation of the memory transistor.

Next, a second insulating film 109 is formed on the film 107 that serves as the lower gate electrode, the film 108 that serves as the floating gate electrode, and the exposed first insulating film (lower gate insulating film) (FIG. 1 (D)). Then, in order to remove the second insulating film that is unnecessary only for the high-speed transistor, the second insulating film on the film 107 is removed by etching to expose the film 107 (FIG. 1 (E)). The second insulating film does not have to be the same material as the first insulating film, but in this embodiment, a silicon oxide film is used. CHF is used as an etching method for this second insulating film.₃By performing plasma etching using gas, the selectivity of tantalum nitride or tantalum of the first conductive film and the silicon oxide film of the second insulating film can be made 10 or more. Further, even in the case of wet etching using hydrofluoric acid, the selection ratio with tantalum nitride or tantalum can be sufficiently large. Here, since the gate insulating film of the high-speed transistor is covered with the film 107 which is the lower gate electrode, the plasma damage due to the removal of the second insulating film is not received.

In this embodiment, the same silicon oxide film as the first insulating film is used as the second insulating film, but a silicon nitride film having a higher dielectric constant than the silicon oxide film or a film containing a silicon nitride film (SiO).₂/ SiN / SiO₂) May be used. This is because when a silicon nitride film having a larger dielectric constant than the silicon oxide film is formed as a second insulating film, a high withstand voltage transistor having a desired capacitance and a gate insulating film having a desired film thickness can be produced. ..

For example, it is assumed that the first and second insulating films are formed of a silicon oxide film to increase the film thickness of the silicon oxide film which is the gate insulating film of a high withstand voltage transistor. Then, the transistor is generally designed to have a desired capacitance, but from C = ε × S / d (C: capacitance, ε: permittivity, S: electrode area, d: film thickness), it is dielectric. When the rate ε and the electrode area S are constant, the capacitance C becomes small. However, if the second conductive film to be laminated is a film having a dielectric constant ε larger than that of the silicon oxide film of the first conductive film, the film thickness can be increased without changing the capacitance as a transistor. It is possible to manufacture a high withstand voltage transistor in which both the capacitance and the thickness of the gate insulating film are desired values. That is, by having a gate insulating film having a laminated structure, a transistor having a desired capacitance and high withstand voltage can be obtained.

Then, as shown in FIG. 2A, the second conductive film 110 is formed on the film 107 and the second insulating film 109 which are the lower gate electrodes. The second conductive film 110 may be a film having conductivity as in the first conductive film, and a tungsten (W) film is used in this embodiment.

Next, a resist is formed on the second conductive film 110 to form resist masks 111 to 113. The second conductive film 110 is etched by using resist masks 111 to 113 to form an upper gate electrode 114 of a high-speed transistor, a gate electrode 115 of a high withstand voltage transistor, and a control gate electrode 116 of a memory transistor. Etching of tungsten film is CF₄, Cl₂, O₂Or SF₆, Cl₂, O₂The selection ratio of the first conductive film with the tantalum nitride film or the tantalum film can be 5 or more (Fig. 2 (B)).

At this time, the wiring is also routed using the second conductive film. Here, if the first conductive film is used for routing, as described above, the first conductive film must be thinly formed, so that the wiring resistance cannot be reduced. Therefore, it is desirable to route the wiring using a second conductive film having no particular limitation on the film thickness. In particular, tungsten, which is the second conductive film material, has a resistance value about 1/10 lower than that of tantalum nitride or tantalum, which is the first conductive film material, and is therefore most suitable for wiring.

Further, the first and second conductive films may be formed from the same material, but if they are formed from different materials, they have the following effects. Generally, the threshold value of a transistor is controlled by forming a gate electrode using a gate electrode material having an optimum work function. However, some gate electrode materials have an optimum work function but high resistance, and in that case, they are not suitable for wiring, so they are difficult to use as gate electrode materials. In such a case, if the gate electrode has two layers, a material having an optimum work function can be used for the lower gate electrode, and a material having a low resistance can be used for the upper gate electrode. Therefore, it can be used as a gate electrode material. The range of materials that can be produced is expanded, and as a whole, a high-speed transistor having a low resistance and a desired threshold value can be obtained.

Next, the second insulating film is etched using the resist masks 112 and 113 (FIG. 2 (C)). At this time, CHF₃By performing dry etching using the above, the etching rate of the silicon oxide film, which is the second insulating film, can be increased 10 times or more with respect to the tantalum nitride or tantalum of the film 108, which is the floating gate electrode. A similar etching rate can also be obtained by wet etching using hydrofluoric acid. Therefore, in the etching, there is almost no difference in film thickness between the film 107 as the lower gate electrode and the film 108 as the floating gate electrode, so that the etching of the films 107 and 108, which is the next step, can be completed within the same time. This can prevent overetching of the first insulating film. By the etching, patterns 117 and 118 composed of the second insulating film are formed. The pattern 117 functions as the upper gate insulating film of the high withstand voltage transistor, and the pattern 118 functions as the second gate insulating film of the memory transistor. The silicon oxide film, which is the second insulating film, is a floating gate electrode material and has a sufficient etching selectivity with tantalum nitride or tantalum. The first insulating film residual film after etching can be aligned with a high-speed transistor and a memory transistor without etching 105.

Next, the film 107 as the lower gate electrode and the film 108 as the floating gate electrode are etched with the resist masks 111 and 113 to form the lower gate electrode 119 and the floating gate electrode 120 of the high-speed transistor (FIG. 2). (D)). Etching of the tantalum nitride or the films 107 and 108 made of tantalum is Cl as an etching gas.₂Can be used to make the selectivity of the first insulating film with the silicon oxide film 10 or more. Therefore, even if there is a film thickness difference between the film 107 which is the lower gate electrode and the film 108 which is the floating gate electrode and one of the first insulating films is over-etched, the absolute amount is not large, so that it is practical. It doesn't matter.

After removing the resist masks 111 to 113, impurity elements are doped into the active layers 102 to 104 to form a source region and a drain region in each active layer (FIG. 2 (E)). The first gate insulating film of the high withstand voltage transistor may be etched to some extent during the etching of the first conductive film in FIG. 1 (B), but the film thickness is almost the same as that of the first gate insulating film of the memory transistor. It is the same as the film thickness of. Therefore, doping can be performed on all the transistors at once through the first insulating film having the same film thickness, and the transistors can be separately produced while suppressing the increase in the doping process.

As described above, when the formation of the impurity region is completed, a cap film made of a 50 nm silicon oxide film is formed so as to cover the upper gate electrode 114, the gate electrode 115, and the control gate electrode 116 made of the second conductive film of each transistor. Then, the impurity elements are activated by heat treatment, laser annealing, lamp annealing, or the like. Next, a 100 nm film of a silicon nitride film containing hydrogen is formed in the film, and heat treatment for hydrogenation is performed. By this heat treatment, hydrogen released from the silicon nitride film terminates defects such as dangling bonds existing in the first and second insulating films and each active layer, and reduces the interface state at the interface of the film. To do.

Next, the silicon oxide film is formed again on the silicon nitride film to complete the interlayer insulating film 121 composed of the silicon oxide film, the silicon nitride film, and the silicon oxide film. Although the interlayer insulating film 121 having a flat surface is shown in FIG. 3A, it does not have to be flat. Further, the interlayer insulating film may be formed of a single layer of a silicon nitride film, a silicon oxide film, a silicon oxide film, an organic resin film, or a laminated film obtained by combining them. When multiple layers of wiring are provided on the interlayer insulating film, it is desirable to use a flattening film having a flat surface as the interlayer insulating film. After that, a contact hole reaching the active layers 102 to 104 and a contact hole reaching the control gate electrode 116 are formed in the interlayer insulating film 121 (FIG. 3A).

Next, a conductive film of a metal such as an aluminum film or copper is formed and patterned to form wirings 122 to 127 connecting to the source region and drain region of the active layers 102 to 104, and wiring 128 connecting to the control gate electrode 116. (Fig. 3 (B)). The semiconductor storage device is completed by the above steps.

Through the above steps, a memory transistor having a floating gate electrode, a high withstand voltage transistor on which a gate insulating film is laminated, and a high-speed transistor having a gate insulating film having the same thickness as the tunnel oxide film of the memory transistor are placed on the same substrate. It can be manufactured by a manufacturing method that is efficient and reduces the number of steps.

The gate insulating film of the high withstand voltage transistor produced in this step has a film thickness of approximately the sum of the first gate insulating film and the second gate insulating film of the memory transistor. Since the gate insulating film of the high withstand voltage transistor need not be destroyed by the voltage applied to the memory transistor, it is equal to or larger than the thickness of the first gate insulating film of the memory transistor, preferably the film thickness of the first gate insulating film and the second. It is preferable to have a film thickness that is the sum of the film thickness of the gate insulating film.

Further, by optimizing the size of the floating gate electrode of the memory transistor, the charge injection / erasing efficiency during the operation of the memory transistor is optimized.

In this manufacturing process, both the memory transistor and the high-speed transistor can form the gate insulating film of the high-speed transistor and the first gate insulating film of the memory transistor, which are required to have the highest characteristics, from the same first insulating film. , There is an advantage that the film thickness can be shared.

In this embodiment, the manufacturing process of simultaneously forming a high-speed transistor, a high-voltage transistor, and a memory transistor on the same substrate has been introduced, but the present invention is not limited to this, and two types of transistors such as a memory transistor and a high-speed transistor and a memory transistor and a high-voltage transistor are introduced. May be combined and formed on the same substrate at the same time.

(Embodiment 2) FIG. 4 is a diagram showing a manufacturing process of the semiconductor storage device according to the present invention. In FIG. 4, the same reference numerals are used for the parts corresponding to those in FIGS. 1 to 3, and the description of the first embodiment is referred to as a detailed description thereof.

As the substrate 401 in FIG. 4, a semiconductor substrate made of single crystal silicon is used, but a semiconductor film may be formed by using an SOI (Silicon on Insulator) substrate. Next, channel doping is performed to control the threshold. In this embodiment, B is used as the material gas at an acceleration voltage of 25 kV.₂H₆It is done using.

Next, device separation is performed by a known isolation technique such as the LOCOS method (selective oxidation method) or the STI method (Shallow Trench Isolation) to form active layers 402 to 404 on the surface of the semiconductor substrate. The active layer 402 is a semiconductor layer constituting a high-speed transistor, the active layer 403 is a semiconductor layer constituting a high withstand voltage transistor, and the active layer 404 is a semiconductor layer constituting a memory transistor. Next, thermal oxidation is performed to form a thermal oxide film in contact with the semiconductor substrate to form the first insulating film 405. Since the thermal oxide film can be formed thinly and uniformly, it is most suitable as the first insulating film (Fig. 4 (A)). However, the first insulating film may be formed by using other film forming methods, not limited to the thermal oxide film.

Subsequently, a tantalum nitride (TaN) film or a tantalum film (Ta) is formed on the first insulating film as the first conductive film 106. Then, etching is performed to form a film 107 as a lower gate electrode and a film 108 as a floating gate electrode to expose the first insulating film on the active layer 403 (FIG. 4 (B)). Next, a silicon oxide film is formed as a second insulating film 109 on the film 107 as the lower gate electrode, the film 108 as the floating gate electrode, and the exposed first insulating film. After forming the second insulating film 109, only the second insulating film on the film 107, which is the lower gate electrode, is removed by etching (FIG. 4 (C)).

Then, as shown in FIG. 4D, a second conductive film 110, which is a tungsten (W) film, is formed on the film 107 and the second insulating film 109, which are the lower gate electrodes.

Next, after forming a resist on the second conductive film 110, resist masks 111 to 113 are formed. The second conductive film 110, the second insulating film 109, the film 107 as the lower gate electrode, and the film 108 as the floating gate electrode are etched in order using resist masks 111 to 113 to form the gate electrode of each transistor (FIG. 4 (E)).

Next, after removing the resist masks 111 to 113, the active layer is doped with an impurity element to form a source region and a drain region (FIG. 4 (F)). After that, the impurity elements are activated by heat treatment, laser annealing, lamp annealing and the like.

The subsequent steps are completed by forming an interlayer insulating film, forming a contact hole, and forming wiring to be connected to each semiconductor layer and the control gate electrode, as in FIG.

Through the above steps, a memory transistor having a floating gate electrode, a high withstand voltage transistor on which a gate insulating film is laminated, and a high-speed transistor having a gate insulating film having the same thickness as the tunnel oxide film of the memory transistor are placed on the same substrate. It can be manufactured by a manufacturing method that is efficient and reduces the number of steps.

In this embodiment, the manufacturing process of simultaneously forming a high-speed transistor, a high-voltage transistor, and a memory transistor on the same substrate has been introduced, but the present invention is not limited to this, and two types of transistors such as a memory transistor and a high-speed transistor and a memory transistor and a high-voltage transistor are introduced. May be combined and formed on the same substrate at the same time.

A method for manufacturing a semiconductor storage device in which a memory transistor is an N-channel transistor, a high-speed transistor is a P-channel or N-channel transistor, and a high-voltage transistor is a P-channel or N-channel transistor will be described. In addition, various examples of the present invention will be shown in the following Examples 1 to 4 with reference to the drawings. In each drawing, the parts common to the above-described embodiments are designated by the same reference numerals, and the description of the first embodiment will be described in detail. Refer to.

Since this embodiment is the same manufacturing process as in FIGS. 1 (A) to 2 (D) described above until the gate electrodes and the like of each element are formed, FIG. 5 is used for the steps after FIG. 2 (D). This will be described below.

FIG. 5 (A) shows a state in which the resist mask shown in FIG. 2 (D) is removed from each gate electrode of the high-speed transistor, the high withstand voltage transistor, and the memory transistor. The resist masks 501a and 501b are newly formed here. Then, an impurity element that imparts n-type is added to form impurity regions 502a, 502b, 503a, 503b, 504a, and 504b that exhibit n-type. As the n-type impurity element, an element belonging to Group 15 can be typically used, typically phosphorus or arsenic (Fig. 5 (B)).

The impurity regions 502a, 502b, 503a, 503b, 504a, and 504b are the source region and drain region of the N-channel type high-speed transistor, the source region and drain region of the N-channel high withstand voltage transistor, and the N-channel type memory transistor, respectively. Source area and drain area. The impurity region formed here contains 1 × 10 n-type impurity elements.²⁰~1×10²¹atoms / cm³(Typically 2x10²⁰~5×10²¹atoms / cm³) Concentration. In this specification, an impurity region containing an n-type impurity element is defined as an n-type impurity region.

After forming the n-type impurity region, the resist masks 501a and 501b are peeled off by wet etching to newly form resist masks 505a to c. Then, a p-type impurity element (boron in this example) is added to form impurity regions 506a, 506b, 507a, and 507b containing boron at a high concentration (Fig. 5 (C)). In this example, diborane (B)₂H₆) By the ion doping method using 3 × 10²⁰~3×10²¹atoms / cm³(Typically 2x10²⁰~5×10²¹atoms / cm³) Concentrates to form an impurity region containing boron. These impurity regions are the source region and drain region of the P-channel type high-speed transistor, and the source region and drain region of the P-channel type high withstand voltage transistor. In this specification, the impurity region containing the p-type impurity element is defined as the p-type impurity region.

After forming an impurity region in the active layer of each transistor by the above steps, the resist masks 505a to 505c are peeled off by wet etching. After that, the impurity region is activated to form the interlayer insulating film 121. Next, the interlayer insulating film 121 is etched to form a contact hole, and the n-type impurity region or the p-type impurity region of each transistor, 502a, 502b, 503a, 503b, 506a, 506b, 507a, 507b, and the memory transistor, Wiring 508 to 516 connected to the control gate electrode is formed (Fig. 5 (D)). As the wiring material, the same wiring material as that described in the first embodiment is used. The semiconductor storage device is completed by the above steps. Note that this embodiment can also be applied to a method for manufacturing a semiconductor storage device using the semiconductor substrate shown in FIG.

A method of manufacturing a semiconductor storage device having an LDD structure in which a high-voltage transistor and a high-speed transistor have an LDD region of a low-concentration impurity region will be described. Since this embodiment is the same manufacturing process as in FIGS. 1 (A) to 2 (D) described above until the gate electrode of each transistor is formed, FIGS. 6 and 7 are shown for the steps after FIG. 2 (D). It will be described below in use.

The resist mask shown in FIG. 2D is removed from each gate electrode of the high-speed transistor, high-voltage transistor, and memory transistor to form new resist masks 601a to 601a to d. Then, an impurity element that imparts n-type is added to form n-type impurity regions 602a and 602b in the active layer of the memory transistor (FIG. 6 (A)). As the n-type impurity element, an element belonging to Group 15 is typically used, and phosphorus or arsenic is typically used.

The n-type impurity regions 602a and 602b are the source region and the drain region of the N-channel type memory transistor, respectively. The n-type impurity element formed here contains 1 × 10 n-type impurity elements.²⁰~1×10²¹atoms / cm³(Typically 2x10²⁰~5×10²¹atoms / cm³) Concentration.

After forming the n-type impurity regions 602a and 602b, the resist masks 601a to 601a to d are peeled off by wet etching, and then the resist mask is covered so as to cover the P-channel type high-speed transistor, the P-channel type high withstand voltage transistor, and the memory transistor. Form 603a ~ c. Then, an n-type impurity element is added to form n-type impurity regions 604a, 604b, 605a, and 605b containing the n-type impurity element (phosphorus) at a low concentration (FIG. 6 (B)). The n-type impurity regions 604a, 604b, 605a, and 605b thus formed are typically 1 × 10.¹⁶~5×10¹⁸atoms / cm³(Typically 3x10¹⁷~3×10¹⁸atoms / cm³) To add n-type impurity elements.

Next, the resist masks 603a to 603a to c are peeled off by wet etching, then the resist masks 606a to 606a to c are formed, and an impurity element that imparts p-type is added to the p-type impurity region 607a containing boron at a low concentration. It forms 607b, 608a, and 608b (Fig. 6 (C)). These p-type impurity regions are 1 × 10¹⁶~5×10¹⁸atoms / cm³Boron (B) is added so as to contain an impurity element that imparts p-type at a certain concentration.

Then, the resist masks 606a to 606a to c are peeled off by wet etching to form the silicon oxide film 701 on the entire surface (FIG. 7 (A)). Then, the silicon oxide film 701 is etched back to form sidewalls 702a to e on the side surfaces of each gate electrode (FIG. 7 (B)). At this time, the first insulating film 105 is exposed to dry etching together with the silicon oxide film 701, but the portion directly below each gate electrode that actually functions as the gate insulating film is protected by the gate electrode, resulting in plasma damage. There is no need to worry about receiving it.

Next, in order to add a high concentration of phosphorus, the P-channel type high-speed transistor, high withstand voltage transistor, and memory transistor are covered with resist masks 703a to 703. Then add phosphorus and 1x10²⁰~1×10²¹atoms / cm³(Typically 2x10²⁰~5×10²¹atoms / cm³) Concentrates to form an n-type impurity region containing n-type impurity elements. By adding this impurity element, a source region 704a and a drain region 704b of an N-channel high-speed transistor, LDD regions 704c and 704d which are low-concentration impurity regions, and a channel formation region 704e are formed. In addition, source regions 705a and drain regions 705b, LDD regions 705c and 705d, and channel formation regions 705e of the N-channel high withstand voltage transistor are formed (FIG. 7 (C)).

Next, the resist masks 703a to 703c are peeled off by wet etching to form the resist masks 706a to c. Then, add p-type impurity element, 3 × 10²⁰~3×10²¹atoms / cm³A p-type impurity region is formed so as to contain boron at the concentration of. As a result, the source region 707a and drain region 707b, the LDD region 707c and 707d, and the channel formation region 707e of the P-channel type high-speed transistor are formed. In addition, source regions 708a and drain regions 708b, LDD regions 708c and 708d, and channel formation regions 708e of the P-channel type high withstand voltage transistor are formed (FIG. 7 (D)).

Through the above steps, high-speed transistors and high-voltage transistors other than memory transistors can be made into an LDD structure. After FIG. 7 (D), the resist masks 706a to 706 are removed, and the process is completed in the same manner as in FIG. 5 (D). In the configuration of this embodiment, the withstand voltage of the transistor can be improved by adopting the LDD structure, and the single-channel effect can be suppressed when the miniaturization progresses and the single-channel effect occurs. Note that this embodiment can also be applied to a method for manufacturing a semiconductor storage device using the semiconductor substrate shown in FIG.

In this embodiment, a method for manufacturing a semiconductor storage device having an LDD structure or a GOLD structure will be described by a method different from that in the second embodiment. Since this embodiment is the same manufacturing process as in FIGS. 1 (A) to 2 (A) until the second conductive film is formed, FIGS. 8 and 9 are used for the steps after FIG. 2 (A). Will be described below. In the present specification, the region where the LDD region overlaps with the gate electrode via the gate insulating film is called a Lov region (first LDD region), and the region where the LDD region does not overlap with the gate electrode via the gate insulating film is called Loff. It is called a region (second LDD region).

After forming the second conductive film 110, the silicon oxide film 801 is formed on the second conductive film. Then, a resist is deposited on the silicon oxide film 801 and patterned to form resist masks 802a to e (FIG. 8 (A)). Using this resist mask 802a to e, the silicon oxide film 801 of the lower layer is etched to form the silicon oxide film 803a to e, and then the second conductive film 110 is etched to form the upper gate electrodes 804a and 804b with high withstand voltage. The gate electrodes 804c and 804d of the transistor and the control gate electrodes 804e are formed. Further, the second insulating film 109 is etched with the resist masks 802c to e to form the upper gate insulating films 805a and 805b of the high withstand voltage transistor and the second gate insulating film 805c of the memory transistor. Next, using the resist masks 802a, 802b, and 802e, the films 107a and 107b to be the lower gate electrodes and the film 108 to be the floating gate electrodes are etched to form the lower gate electrodes 806a and 806b and the floating gate electrodes 806c. (Fig. 8 (B)).

From the formation of the resist masks 802a to e shown in FIG. 8A to the state shown in FIG. 8B, all the etching of each film is performed using any of the resist masks 802a to e.

After removing the resist masks 802a to 802a, new resist masks 807a and 807b are formed to cover the high-speed transistor and the high withstand voltage transistor of the P-type channel. Next, an impurity element that imparts n-type is added to form n-type impurity regions 808a to f. The concentration of the n-type impurity region of the n-type impurity region 808a to f is 1 × 10.²⁰~1×10²¹atoms / cm³(Typically 2x10²⁰~5×10²¹atoms / cm³). As the n-type impurity element, an element belonging to Group 15 can be typically used, typically phosphorus or arsenic (Fig. 8 (C)).

Next, the resist masks 807a to 807a to b are peeled off by wet etching to form resist masks 901a to 901a to c. In this state, an impurity element that imparts p-type is added at a high concentration to form p-type impurity regions 902a to d. The p-type impurity region 902a ~ d is 3 × 10²⁰~3×10²¹atoms / cm³Impurity elements are added so as to contain p-type impurity elements at the concentration of. Boron can be used as the p-type impurity element (Fig. 9 (A)).

Then, the resist masks 901a to 901c are peeled off by wet etching. Next, using the silicon oxide films 803a to 803a to e as a mask, the upper gate electrodes 804a and 804b, the gate electrodes 804c and 804d of the high withstand voltage transistor, and the control gate electrode 804e are isotropically etched to reduce the side surfaces and reduce the width. The upper gate electrodes 903a and 903b, the gate electrodes 903c and 903d of the high withstand voltage transistor, and the control gate electrode 903e are formed (Fig. 9 (B)). Next, the silicon oxide films 803a to 803a to e are removed to form resist masks 904a and 904b that cover the high-speed transistor and high-voltage transistor of the P-type channel. Then, an impurity element that imparts n-type is added to form source regions 905a and drain regions 905b, Lov regions 905c and 905d, and channel formation regions 905e of the N-channel type high-speed transistor. Further, the source region 906a and drain region 906b, the Loff region 906c and 906d, and the channel formation region 906e of the N-channel type high withstand voltage transistor are formed. The Lov regions 905c and 905d and the Loff regions 906c and 906d are typically 1 × 10.¹⁶~5×10¹⁸atoms / cm³(Typically 3x10¹⁷~3×10¹⁸atoms / cm³) N-type impurity element is added (Fig. 9 (C)).

Next, the resist masks 904a and 904b are peeled off by wet etching to form resist masks 907a to 907a. Then, a p-type impurity element is added at a low concentration to form a p-type impurity region. Low-concentration p-type impurity region is 1 × 10¹⁶~5×10¹⁷atoms / cm³Boron (B) is added so as to contain impurity elements at a certain concentration. As a result, the source region 908a and drain region 908b, the Lov region 908c and 908d, and the channel formation region 908e of the P-channel type high-speed transistor were formed. In addition, source regions 909a and drain regions 909b, Loff regions 909c and 909d, and channel formation regions 909e of the P-channel type high withstand voltage transistor were formed.

Through the above steps, the high-speed transistor has a GOLD structure and the high-voltage transistor has an LDD structure. Then, the resist masks 907a to 907a to c are peeled off by wet etching, and then the process is completed in the same manner as in FIG. 5 (D). Further, if the upper gate electrodes 903a and 903b are used as masks and the lower gate electrodes 806a and 806b of the high-speed transistor are etched so as to have the same gate electrode length as the upper gate electrode, the high-speed transistor has an LDD structure having an Loff region.

Since a transistor having good withstand voltage can be obtained from the LDD structure and a transistor having good reliability can be obtained from the GOLD structure, a structure suitable for the situation may be used. Note that this embodiment can also be applied to a method for manufacturing a semiconductor storage device using the semiconductor substrate shown in FIG.

This embodiment describes a method for manufacturing a semiconductor storage device in which a high-speed transistor and a high-voltage transistor have a low-concentration impurity region. Since this embodiment is the same manufacturing process as those in FIGS. 1 (A) to 2 (A) until the second conductive film is formed, FIGS. 10 and 11 are used for the steps after FIG. 2 (A). Will be described below.

After depositing the resist on the second conductive film, the resist masks 1001a to e are formed. Then, the first etching process for forming the electrode is performed. An ICP (Inductive Coupled Plasma) etching apparatus is used for etching. For the first etching process, CF is used as the etching gas.₄, Cl₂, O₂Is added. The etching pressure is 1.3 Pa, and 800 W of plasma generation power and 300 W of substrate bias power are supplied. By this etching, the second conductive film becomes a tapered pattern 1002a to e (FIG. 10 (A)).

Next, the silicon oxide film of the second insulating film 109 is applied to CHF.₃The second etching process is performed by taper etching using gas. As a result, the second insulating film is processed into the tapered upper gate insulating films 1003a and 1003b and the tapered second gate insulating film 1003c (Fig. 10 (B)).

Next, as a third etching process, CF the etching gas is used.₄, Cl₂The first conductive layer, tantalum nitride or tantalum, is etched by switching to. The etching conditions at this time are as follows: an etching pressure of 1.3 Pa, a power for plasma generation of 500 W, and a power for a substrate bias of 10 W are supplied. As described above, the tapered lower gate electrodes 1004a and 1004b and the floating gate electrode 1004c can be formed (FIG. 10 (C)).

Next is SF for etching gas₆, Cl₂, O₂Anisotropic etching of tapered patterns 1002a to e is performed using. The etching pressure is 1.9 Pa, and 500 W of plasma generation power and 3 W of substrate bias power are supplied. By this anisotropic etching, the ends of the tapered patterns 1002a to e are the lower gate electrodes 1004a and 1004b, the floating gate electrodes 1004c and the tapered upper gate insulating films 1003a and 1003b, and the tapered second gate insulating film 1003c. Retreat inward (Fig. 11 (A)).

After removing the resist masks 1001a to e, the resist masks 1101a and 1101b are formed on the P-channel type transistor to form 1 × 10¹⁹~5×10²¹/cm³Ion implantation at the phosphorus concentration of. As a result, in the N-channel type high-speed transistor, the source region 1102a and the drain region 1102b, the Lov region 1102c and 1102d, and the channel formation region 1102e are formed at the same time. In the N-channel type high withstand voltage transistor, the source region 1103a and the drain region 1103b, the Loff region 1103c and 1103d, and the channel formation region 1103e are formed at the same time. In the memory transistor, the source region 1104a and the drain region 1104b, the Lov region 1104c and 1104d, and the channel formation region 1104e are formed at the same time (FIG. 11 (B)).

Next, the resist masks 1101a and 1101b are peeled off by wet etching. Next, resist masks 1105a to 1c are formed so as to cover the N-channel type transistor and the memory transistor, and 1 × 10¹⁹~5×10²¹/cm³Ion implantation at the impurity concentration (boron) of. As a result, in the P-channel type high-speed transistor, the source region 1106a and the drain region 1106b, the Lov region 1106c and 1106d, and the channel formation region 1106e are formed. In the P-channel type high withstand voltage transistor, a source region 1107a and a drain region 1107b, a Loff region 1107c and 1107d, and a channel formation region 1107e are formed (FIG. 11 (C)).

After that, the resist masks 1105a to 1105a to c are peeled off by wet etching, and then the process is the same as in FIG. 5 (D) to complete the process. Further, if the tapered portion of the lower gate electrode of the high-speed transistor is etched using the upper gate electrode as a mask, an LDD structure having an Loff region can be formed. In this embodiment, the Loff region and the Lov region can be formed together with the source and drain regions by injecting the impurity element once. In addition, the configuration of this embodiment can suppress the single-channel effect when miniaturization progresses and the single-channel effect occurs. Note that this embodiment can also be applied to a method for manufacturing a semiconductor storage device using the semiconductor substrate shown in FIG.

FIG. 12 shows a typical block diagram of a non-contact type IC card or ID tag having a built-in CPU (Central Processing Unit) as a semiconductor device using the semiconductor storage device of the present invention. In the figure, the semiconductor device 1201 has an integrated circuit 1211 built-in, and the integrated circuit 1211 has a power supply circuit 1203, a clock generation circuit 1204, a data demodulation modulation circuit 1205, a CPU1207, an interface (denoted as IF) 1208, and a non-volatile memory (denoted as IF). Notated as NVM) It is composed of 1209 and SRAM1210. A volatile memory such as DRAM may be used instead of the SRAM 1210.

In this embodiment, the memory transistor constituting the semiconductor storage device of the present invention is used as the non-volatile memory 1209. Further, when a high-speed operation transistor is required as a transistor constituting the clock generation circuit 1204, the data demodulation modulation circuit 1205, the CPU1207, the interface 1208, and the SRAM 1210, in the process of manufacturing the high-speed transistor constituting the semiconductor storage device of the present invention. , Can be manufactured at the same time as the semiconductor storage device of the present invention. When a high withstand voltage transistor is required as a transistor constituting the power supply circuit 1203, it can be manufactured at the same time as the semiconductor storage device of the present invention in the process of manufacturing the high withstand voltage transistor constituting the semiconductor storage device of the present invention. From the above, an integrated circuit can be efficiently manufactured on the same substrate.

Further, since the manufacturing process is simplified and the semiconductor storage device of the present invention that can be manufactured at low cost can be applied to the non-volatile memory 1209, it is possible to provide the semiconductor device 1201 that realizes cost reduction and miniaturization. ..

The integrated circuit 1211 is formed on a glass substrate, a flexible substrate, or a semiconductor substrate. The antenna 1202 may be formed on the same substrate as the integrated circuit 1211 in the semiconductor device, or may be formed on the protective layers above and below the integrated circuit. As described above, when the antenna is formed on the same substrate as the integrated circuit 1211, a method of forming a composition using nanoparticles by a printing method (droplet ejection method or screen printing method) can also be used.

Further, the semiconductor device may electrically connect the integrated circuit 1211 provided with only the connection terminal with the antenna and the antenna 1202 made of copper, aluminum, or the like by using an anisotropic conductive film or the like.

The size of the integrated circuit 1211 is 5 mm square or less, preferably 0.3 mm to 4 mm square, and the protective layers above and below the integrated circuit 1211 are larger than the size of the semiconductor device.

This embodiment can be used in combination with Examples 1 to 2 and Examples 1 to 4.

A typical block diagram of a non-contact RFID (Radio Frequency Identification) tag having the semiconductor storage device of the present invention is shown in FIG. FIG. 13 shows a configuration having a simple function of reading fixed data such as authentication data. In the figure, the RFID tag 1301 is an antenna 1302, a high frequency circuit 1303, a power supply circuit 1304, a reset circuit 1305, a clock generation circuit 1306, a data demodulation circuit 1307, a data modulation circuit 1308, a control circuit 1309, and a non-volatile memory (denoted as NVM). ) It is composed of 1310 and ROM1311.

In this embodiment, the memory transistor constituting the semiconductor storage device of the present invention is used as the non-volatile memory 1310. Further, when a transistor having high speed operation is required as a transistor constituting the high frequency circuit 1303, the reset circuit 1305, the clock generation circuit 1306, the data demodulation circuit 1307, the data modulation circuit 1308, the control circuit 1309, and the ROM 1311, the present invention is used. It can be manufactured at the same time in the manufacturing process of high-speed transistors constituting the semiconductor storage device. When a high withstand voltage transistor is required as a transistor constituting the power supply circuit 1304, it can be manufactured at the same time as the semiconductor storage device of the present invention by the process of manufacturing the high withstand voltage transistor constituting the semiconductor storage device of the present invention. From the above, it is possible to efficiently manufacture RFID tags on the same substrate.

Further, since the manufacturing process is simplified and the semiconductor storage device of the present invention that can be manufactured at low cost can be applied to the non-volatile memory 1310, it is possible to realize cost reduction and miniaturization even for the RFID tag 1301.

Further, all the circuits shown in FIG. 13 are formed on a glass substrate, a flexible substrate, or a semiconductor substrate. The antenna 1302 may be formed on the glass substrate, the flexible substrate, or the semiconductor substrate, or may be outside the substrate and connected to the semiconductor integrated circuit inside the substrate.

The high frequency circuit 1303 is a circuit that receives an analog signal from the antenna 1302 and outputs an analog signal received from the data modulation circuit 1308 from the antenna 1302. The power supply circuit 1304 is a circuit that generates a constant power supply from the received signal, the reset circuit 1305 is a circuit that generates a reset signal, the clock generation circuit 1306 is a circuit that generates a clock signal, and the data demodulation circuit 1307 extracts data from the received signal. The circuit and data modulation circuit 1308 are circuits that generate an analog signal to be output to the antenna based on the digital signal received from the control circuit or change the antenna characteristics, and the analog section is composed of the above circuits.

On the other hand, the control circuit 1309 receives the data extracted from the received signal and reads the data. Specifically, the address signals of the non-volatile memory 1310 and ROM 1311 are generated, the data is read, and the read data is sent to the data modulation circuit. The digital unit is composed of the above circuits.

This embodiment can be used in combination with Examples 1 to 2 and Examples 1 to 4.

The usage pattern of the ID tag described in Examples 5 and 6 will be described. In this embodiment, a card equipped with the ID tags of Examples 5 and 6 (hereinafter referred to as an IDF card) will be used for description.

In FIG. 14A, an IDF chip 1402 and an antenna 1403 having identification information are provided on the insulating substrate 1401.

Then, as shown in FIG. 14 (B), the first film 1404 and the second film 1405 are bonded together to complete the IDF card 1406. At this time, the IDF chip may be arranged at the center of the card to be mounted, and the periphery of the IDF chip may be formed so as to be covered with the base material of the article, the first and second films in the present embodiment. As a result, the mechanical strength of the IDF chip can be increased. Specifically, the position where the IDF chip is sandwiched (center of the IDF chip): X is (1/2) x D-30 μm &lt;X &lt;(1/2) x D + 30 μm, where D is the thickness of the card. It is recommended to arrange so as to satisfy.

Further, in the present embodiment, the case where the IDF chip in which the antenna is formed on the substrate is used has been described, but the case where the IDF chip in which the antenna is mounted may be used, and the IDF chip satisfies the above position. preferable.

A case where the semiconductor storage device of the present invention is made into a chip and incorporated inside the device assuming a specific application will be described with reference to FIG. In this embodiment, an example of being packaged and implemented by BGA (ball grid array) technology will be described.

As shown in FIG. 15A, the semiconductor storage device 1501 separated from the substrate on which a plurality of semiconductor storage devices of the present invention are manufactured is attached to a substrate 1502 such as a resin substrate. Further, the semiconductor storage device 1501 is wire-bonded to the lead frame 1504 by a wire 1503 made of a gold wire and sealed with a resin 1505. A solder ball terminal 1506 is formed on the opposite side of the resin substrate to which the semiconductor storage device 1501 is attached. Chips packaged in this way are mounted on a particular device via solder ball terminals 1506.

Since the semiconductor storage device of the present invention can be manufactured on the same substrate, a large number of memory chips can be manufactured at one time by manufacturing a plurality of semiconductor storage devices as in the present embodiment and then separating them.

A case where the non-volatile memory, which is an example of the semiconductor storage device of the present invention, is applied to a system LSI integrated on one chip will be described.

The system LSI is an LSI that is incorporated inside a device that is intended for a specific application and constitutes a system that controls the device and processes data. It has a wide variety of uses, and examples thereof include mobile phones, PDAs, DSCs, televisions, printers, fax machines, game consoles, car navigation systems, and DVD players.

Figure 16 shows an example of a system LSI. The system LSI typically consists of a CPU core 1601, a flash memory 1604, a clock controller 1603, a main memory 1602, a memory controller 1605, an interrupt controller 1606, an I / O port 1607, and the like. Of course, the system LSI shown in FIG. 16 is a simplified example, and in an actual system LSI, a wide variety of circuit designs are performed depending on the application.

A memory transistor constituting the semiconductor storage device of the present invention can be used for the flash memory 1604. As the main memory 1602, for example, SRAM or DRAM can be used. By using the semiconductor storage device of the present invention as the flash memory of the system LSI, the cost of the system LSI can be reduced and the size can be reduced.

Further, when a transistor having high speed operation is required as a transistor constituting the CPU core 1601, the clock controller 1603, the main memory 1602, the memory controller 1605, the interrupt controller 1606, and the I / O port 1607, the semiconductor storage device of the present invention is used. It can be manufactured in the same manner as the manufacturing of the high-speed transistor constituting the above. This makes it possible to efficiently manufacture other circuits as well as the semiconductor device on the same substrate.

This embodiment can be used in combination with Examples 1 to 2 and Examples 1 to 4. Further, in the eighth embodiment, the semiconductor storage device is made into a chip, but in the present embodiment as well, the system LSI may be packaged and mounted in the same manner.

In this embodiment, an example in which the semiconductor storage device of the present invention is attached or manufactured on the same substrate as the panel will be described with reference to FIGS. 17 and 18.

FIG. 17A shows an example in which the semiconductor storage device of the present invention is provided on the same substrate as the pixel unit 1701. The substrate 1702 may be any substrate or a glass substrate. 1703 is a memory unit, 1704 is a gate side drive circuit, 1705 is a source side drive circuit, and 1706 is an external input terminal. A cross-sectional view taken along the line A-A'of FIG. 17 (A) is shown in FIG. 17 (B). A pixel unit 1701 and a gate-side drive circuit 1704 are formed on the substrate 1702, and the pixel unit 1701 is formed by a plurality of pixels including a current control thin film transistor 1710 and a pixel electrode 1711 electrically connected to its drain. To. Further, the gate-side drive circuit 1704 is formed by using a CMOS circuit 1712 in which an n-channel thin film transistor and a p-channel FET are complementarily combined.

The pixel electrode 1711 functions as a cathode of the EL element. Further, a light emitting layer and a hole injection layer are formed on the pixel electrode 1711. Further, an anode of the EL element, a passivation film, and the like are formed on the anode. The memory unit 1703 is formed by a high-speed transistor 1721, a high withstand voltage transistor 1722, and a memory transistor 1723.

The memory unit 1703 and the drive circuit or pixel unit are electrically connected via the connection wiring 1714, and further via the anisotropic conductive film 1716 and the electrode pad 1717. More specifically, the wiring portion of the high-speed transistor of the semiconductor storage device is electrically connected to the drive circuit or the pixel portion.

1718 is the cover material, 1719 is the first seal material, 1720 is the second seal material, and there is a filler between the inner cover material 1718 surrounded by the first seal material 1719 and the substrate 1702 (not shown). Is provided.

FIG. 17B shows an example in which the semiconductor storage device is turned upside down and attached to the substrate 1702, but the substrate 1702 and the substrate on which the semiconductor storage device is formed may be adhered without being turned upside down. Further, although the EL display device has been described in this embodiment, it goes without saying that the semiconductor storage device can be provided on the same substrate as the liquid crystal panel and can be applied to the liquid crystal display device.

From the above, the semiconductor storage device of the present invention can be provided as the memory of the pixel portion, and a display device including a small memory can be provided at low cost.

FIG. 18 shows an example in which the memory unit is provided on the same substrate on which the pixel unit and the drive circuit are provided. In FIG. 18, the parts common to those in FIG. 17 are designated by the same reference numerals, and detailed description thereof will be omitted. Although not shown in FIG. 18, the wiring of the high-speed transistor and the peripheral drive circuit of the memory unit are electrically connected by the wiring directly connected to the source region and the drain region of each transistor. Therefore, the drive circuit unit and the memory unit can be connected more easily than in the case of FIG. In the configuration of FIG. 18, since all can be manufactured on the same substrate at the same time, a display device smaller and lower cost than the configuration described in FIG. 17 can be obtained, and the manufacturing process can be simplified.

Various semiconductor devices can be completed using the present invention. Examples thereof include personal digital assistants (electronic organizers, mobile computers, mobile phones, etc.), video cameras, digital cameras, personal computers, television receivers, projection display devices, and the like. An example of them is shown in the figure. Refer to Examples 8 to 10 for a method of mounting or arranging the semiconductor storage device of the present invention on the device shown in FIG.

FIG. 19A is an example of completing a television receiver by applying the present invention, and is composed of a housing 2401, a support base 2402, a display unit 2403, and the like. By providing the semiconductor storage device of the present invention, a low-cost television receiver can be provided.

FIG. 19B is an example of completing a video camera by applying the present invention, and is composed of a main body 2411, a display unit 2412, an audio input unit 2413, an operation switch 2414, a battery 2415, an image receiving unit 2416, and the like. .. By providing the semiconductor storage device of the present invention, a low-cost video camera can be provided.

FIG. 19C is an example of completing a notebook-type personal computer by applying the present invention, and is composed of a main body 2421, a housing 2422, a display unit 2423, a keyboard 2424, and the like. By providing the semiconductor storage device of the present invention, a low-cost personal computer can be provided.

FIG. 19 (D) is an example of completing a PDA (Personal Digital Assistant) by applying the present invention, and is composed of a main body 2431, a stylus 2432, a display unit 2433, an operation button 2434, an external interface 2435, and the like. By providing the semiconductor storage device of the present invention, a low-cost PDA can be provided.

FIG. 19 (E) is an example in which the sound reproduction device is completed by applying the present invention. Specifically, it is an in-vehicle audio device, which is composed of a main body 2441, a display unit 2442, operation switches 2443, 2444, and the like. Has been done. By providing the semiconductor storage device of the present invention, a low-cost sound reproduction device can be provided.

FIG. 19 (F) is an example of completing a digital camera by applying the present invention. Main body 2451, display unit (A) 2452, eyepiece unit 2453, operation switch 2454, display unit (B) 2455, battery 2456. It is composed of such as. By providing the semiconductor storage device of the present invention, a low-cost digital camera can be provided.

FIG. 19 (G) is an example of completing a mobile phone by applying the present invention, and is composed of a main body 2461, a voice output unit 2462, a voice input unit 2463, a display unit 2464, an operation switch 2465, an antenna 2466, and the like. There is. By providing the semiconductor storage device of the present invention, a low-cost mobile phone can be provided.

The device shown here is only an example, and is not limited to these applications.

This embodiment can be used in combination with Examples 1 to 2, Examples 1 to 4, and 8 to 10.

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Code description

101 Substrate 102 Active layer 103 Active layer 104 Active layer 105 First insulating film 106 First conductive film 107 Film 107a Film 108 Film 109 Second insulating film 110 Second conductive film 111 Resist mask 112 Resist mask 114 Upper gate electrode 115 Gate electrode 116 Control gate electrode 117 Pattern 118 Pattern 119 Lower gate electrode 120 Floating gate electrode 121 Interlayer insulating film 122 Wiring 128 Wiring