Semiconductor device and its manufacturing method

The present invention relates to a semiconductor device and a method for manufacturing the same.

In a semiconductor device having two or more types of convex protrusions, it may be desired to form a side wall portion by allowing a side wall material to remain only on the side surface of a part of the protrusions. The FinFET shown in FIG. 1 shows an example of a semiconductor device in which a side wall portion is formed separately at a protrusion portion.

In the semiconductor device shown in FIG. 1, a gate electrode 10 is provided as a second protrusion on an embedded insulating film 8 formed from a BOX (Buried Oxide), and a source / drain is provided as the first protrusion. Fin12 is provided. A SiN hard mask 11 is provided on the upper side of the gate electrode 10, and a SiN hard mask 13 is provided on the upper side of the Fin 12.

However, when the side wall portion is formed in the side wall leaving step, there is a problem that the side wall portion is formed in all of the protrusions. That is, in the semiconductor device shown in FIG. 1, as shown in FIG. 2, it is necessary to form the side wall portion 14 on the side wall portion of the gate electrode 10. However, if the side wall portion 14 is formed on the gate electrode 10, the side wall portion 16 is inevitably formed on the Fin 12.

If the side wall portion 16 is formed in the Fin 12 in this way, when the ion is driven into the Fin 12 in order to form the source region / drain region in the Fin 12, the ion can not be driven from the side wall of the Fin 12. For this reason, ion injection was performed from above Fin12.

FIG. 3 is a diagram showing a cross section taken along the line AA'in FIG. As shown in FIG. 3, when ions are implanted into Fin12 from above, it becomes impossible to form a uniform source region / drain region 18 in the depth direction of Fin12. If a uniform source / drain region 18 cannot be formed in the depth direction, the distance L1 between the source region and the drain region at the upper part of Fin12 and the distance L2 between the source region and the drain region at the lower part of Fin12 are different. Will end up. In addition, a high parasitic resistance R is generated in the source / drain region 18 at the bottom of Fin12. For this reason, there has been a problem that the driving ability of the transistor is deteriorated.

However, if the side wall portion 14 is not formed, there arises a problem that the source / drain regions 18 are bonded to each other when heat diffusion is performed after ion implantation is performed in Fin 12 to form the source / drain region 18. Further, if the side wall portion 14 is not formed, when silicide 19 is formed on the upper part of the source / drain region 18, the silicide 19 formed in the source / drain region 18 and the silicide formed in the gate electrode 10 are coupled. There is also the problem of doing so.

Further, there is known a technique of forming a pattern finer than the limit of photolithography by using the side wall portion formed in the side wall leaving step as an etching pattern. Such a process is called a side wall pattern transfer process, and is disclosed in, for example, Non-Patent Document 1.<nplcit num="1"><text>Yang-Kyu Choi, Tsu-Jae King, Chenming Hu, "A Spacer Patterning Technology for Nanoscale CMOS", IEEE Transactions on Electron Devices, Vol. 49, No.3, March 2002, pp.436-441</text></nplcit>

<p> The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a high driving ability and a method for manufacturing the same. Another object of the present invention is to enable the simultaneous formation of a fine pattern and a large pattern by using side wall pattern transfer and photolithography.</p>

<p> In order to solve the above problems, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a convex first protrusion and a first method so that the surface is located at a position higher than the first protrusion. It is characterized by including a step of forming a film 1, a step of forming a mask portion on the first film, and a step of etching the first film using the mask portion as a mask. And.</p><p> The semiconductor device according to the present invention has a convex semiconductor portion having a source region formed on one side and a drain region formed on the other side, and a convex semiconductor portion between the source region and the drain region. A gate electrode formed via a gate insulating film, a lower side wall portion formed below the side wall portion of the gate electrode, and a lower side wall portion formed on the side wall portion of the gate electrode. The upper side wall portion is characterized by having an upper side wall portion formed of a member different from the member constituting the lower side wall portion.</p>

<p> According to the present invention, it is possible to provide a semiconductor device having a high driving ability and a method for manufacturing the same. In addition, a fine pattern and a large pattern can be formed at the same time by using side wall pattern transfer and photolithography.</p>

[First Embodiment] First, the basic concept of the present invention will be described by taking the first embodiment as an example. As shown in FIG. 4, a convex protrusion 102 is formed on the embedded insulating film 100. The protrusion 102 is a device component in the present embodiment. Subsequently, a film 104 having a certain thickness is formed on the film with a film thickness thinner than the height of the protrusion 102. However, the film 104 does not necessarily have to have a film thickness thinner than the height of the protrusion 102. Then, the entire surface is anisotropically etched, and only the thickness of the film 104 is etched. Then, as shown in FIG. 5, the material of the film 104 remains on the side wall portion of the protrusion 102, and the side wall portion 106 is formed.

On the other hand, as shown in FIG. 6, a film 110 is formed on the embedded insulating film 100 on which the protrusion 102 is formed with a film thickness thicker than the height of the protrusion 102. That is, the film 110 is formed so that the surface of the film 110 is higher than the protrusion 102. After that, the film 110 is flattened. Then, the entire surface is anisotropically etched, and only the thickness of the film 110 on the insulating film 100 is etched. Then, as shown in FIG. 7, the film 110 does not remain on the side wall portion of the protrusion 102, and the side wall portion is not formed. In this embodiment, this property is applied.

8 and 9 are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present embodiment. As shown in FIG. 8, the first protrusion 120 and the second protrusion 122 are formed on the embedded insulating film 100. However, the second protrusion 122 is formed to be higher than the first protrusion 120. The first protrusion 120 and the second protrusion 122 are examples of device components in the present embodiment.

Next, the first film 124 is formed on the entire surface, and is flattened and etched back. However, the thickness of the first film 124 after etching back is made thicker than the height of the first protrusion 120 and thinner than the height of the second protrusion 122. In other words, the surface of the first film 124 is set to be higher than the first protrusion 120 and lower than the second protrusion 122. Therefore, the top of the first protrusion 120 does not protrude from the first film 124, but the top of the second protrusion 122 protrudes from the surface of the first film 124.

Next, by forming the second film 125 as a whole and performing anisotropic etching on the entire surface, the second film 125 remaining on the side wall portion of the second protrusion 122 is the first side wall portion 126. To form. In order to prevent the first film 124 from being etched during this total anisotropic etching, the material of the second film 125 is selected to have a high etching selectivity with respect to the material of the first film. It is desirable to do. The first side wall portion 126 corresponds to the mask portion in the present embodiment.

Next, as shown in FIG. 9, the first film 124 is anisotropically etched using the first side wall portion 126 as a mask. As a result, the first film 124 remains on the side surface portion of the second protrusion 122, and the second side wall portion 128 is formed. However, the first film 124 does not remain on the side wall portion of the first protrusion 120, and the side wall portion is not formed.

As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, the side wall portions 126 and 128 are formed only on the side surface portion of the high protrusion 122, and the side wall portion is formed on the side surface portion of the lower protrusion 120. No part is formed. Therefore, in a semiconductor device having two or more types of protrusions that are device components, a side wall portion can be formed only on a side surface portion of a specific protrusion. That is, it is possible to cover and protect only the side surface portion of the specific protrusion portion with the side wall portion.

This means that the side surface of the protrusion other than the specific protrusion can be exposed, and various processing can be performed in the subsequent steps.

[Second Embodiment] The second embodiment is an application of the above-mentioned first embodiment to a FinFET which is an example of a convex semiconductor portion. More details will be described below.

10 to 20 are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the present embodiment. As shown in FIG. 10, an SOI substrate having an SOI thickness of about 50 nm to 100 nm is prepared. In the present embodiment, a SOI substrate is prepared in which a BOX (Buried Oxide) is used as the embedded insulating film 200 on the semiconductor substrate and a silicon film 202 having a diameter of 50 nm to 100 nm is formed on the BOX (Buried Oxide). Subsequently, a SiN hard mask 204 having a size of about 70 nm is formed, and two Fin 206s are formed by patterning and RIE. In the present embodiment, the width of this Fin 206 is about 10 nm.

Next, as shown in FIG. 11, a gate insulating film (not shown) is formed on the side surface of Fin206, and then the first layer of gate polysilicon 208 is formed. In the present embodiment, the gate polysilicon 208 is formed with a film thickness of about 300 nm. Since this gate polysilicon 208 is formed on the step of Fin206, a large step is formed on the surface thereof.

Next, as shown in FIG. 12, the gate polysilicon 208 is flattened by CMP (Chemical Mechanical Polishing) and etched back until the SiN hard mask 204 is exposed. Subsequently, as shown in FIG. 13, the second layer of gate polysilicon 210 is formed. In the present embodiment, the gate polysilicon 210 is formed with a film thickness of about 50 nm. Here, the gate polysilicon 208 and the gate polysilicon 210 are combined to form the gate polysilicon 212.

Next, as shown in FIG. 14, a SiN hard mask 214 is formed on the gate polysilicon 212. In the present embodiment, the SiN hard mask 214 is formed with a film thickness of about 100 nm. Subsequently, a resist is applied and patterned on the SiN hard mask 214 to form a gate pattern 216.

Next, as shown in FIG. 15, the SiN hard mask 214 is etched by RIE using the gate pattern 216 as a mask, and then the gate pattern 216 is removed. Subsequently, the SiN hard mask 214 is used as a mask to etch the gate polysilicon 212. As a result, the gate electrode 218 is formed from the gate polysilicon 212.

Next, as shown in FIG. 16, an insulating film 220 made of a material (for example, TEOS) that forms a side wall portion on the side wall portion of the gate electrode is formed over the entire surface higher than the height of the gate electrode 218 and is flat. To become. Subsequently, as shown in FIG. 17, the insulating film 220 is etched back to expose the SiN hard mask 214 on the gate electrode 218.

Next, as shown in FIG. 18, an insulating film (for example, SiN) is formed, and the insulating film (for example, SiN) is etched back to form the first side wall portion 222. Although the first side wall portion 222 is actually formed around the entire circumference of the SiN hard mask 214, the first side wall portion formed in the short side direction of the SiN hard mask 214 is formed in FIG. 18 and below for the sake of clarity. 222 is omitted and shown.

Next, as shown in FIG. 19, the insulating film 220 remaining on the side wall portion of the gate electrode 218 by etching the insulating film 220 with RIE using the first side wall portion 222 and the SiN hard mask 214 as masks. Therefore, the second side wall portion 224 is formed. For this purpose, it is desirable that the insulating film 220 has a high etching selectivity with respect to the first side wall portion 222 and the SiN hard mask 214.

Next, as shown in FIG. 20, SiN-RIE is performed to remove the SiN hard mask 204 on Fin206 by etching. Subsequently, the side surface of Fin206 is doped to form a source / drain region, and the formed source / drain region is subjected to a silicide. Doping to the side surface of Fin206 can be performed by oblique ion implantation, plasma doping, or solid layer diffusion. Further, as the silicide material, for example, NiSi can be used.

FIG. 21 is a cross-sectional view taken along the line BB'in FIG. 20 after silicide. As shown in FIG. 21, the first side wall portion 222 and the second side wall portion 224 are formed only on the side wall portion of the gate electrode 218, and are not formed on the side wall portion of the Fin 206. Therefore, the Fin 206 can be doped from the side surface to form the source diffusion layer region 230 on one side of the Fin 206 and the drain diffusion layer region 230 on the other side of the Fin 206, and the Silicide 232 is attached to the side surface. Can be attached.

When doping from the side, the distance L1 between the source and drain regions above Fin206 and the distance L2 between the source and drain regions below Fin206 are substantially equal, in the depth direction of Fin206. A uniform source / drain region 230 can be formed. That is, the effective channel length can be made uniform in the depth direction of Fin206. Further, since sufficient doping and silicidation can be performed down to the lower part of Fin206, the parasitic resistance R can be reduced and the driving ability of the transistor can be improved.

[Third Embodiment] FIG. 22 is a cross-sectional view for explaining the semiconductor device according to the third embodiment, and is a diagram corresponding to FIG. 21 in the above-described second embodiment. Explaining only the part different from the second embodiment described above, as shown in FIG. 22, in the present embodiment, only VDD300 is attached without forming an impurity diffusion layer in the source / drain region. That is, a FinFET having a Schottky junction source / drain structure is formed. Other than that, the manufacturing process and structure are the same as those in the second embodiment described above.

According to the present embodiment, the first side wall portion 222 and the second side wall portion 224 are formed on the side surface portion of the gate electrode 218, but the side wall portion is not formed on the side surface portion of the Fin 206. Therefore, the silicide 300 can be attached to the side wall surface of the Fin 206. As a result, a uniform Schottky source / drain region can be formed in the depth direction of Fin206. That is, the distance L1 between the Schottky source area and the Schottky drain area at the upper part of Fin206 and the distance L2 between the Schottky source area and the Schottky drain area at the lower part of Fin206 can be made substantially equal. it can. That is, the effective channel length can be made uniform in the depth direction of Fin206.

Further, since the low resistance Silicide 300 is formed in the lower part of the Schottky source / drain region, the parasitic resistance R is reduced and the driving ability of the transistor can be improved.

In order to reduce the Schottky contact resistance, it is desirable to use a material having a small Schottky barrier as the material of VDD300. For example, in the case of an n-type MOS transistor, ErSi or the like having a work function smaller than the median of the bandgap may be used as the material of the silicide 300, and the silicide 300 may be formed of ErSi. In the case of a p-type MOS transistor, Pt or the like having a work function larger than the median of the band gap may be used as the material of the silicide 300, and the silicide 300 may be formed by PtSi.

[Fourth Embodiment] FIG. 23 is a cross-sectional view illustrating the semiconductor device according to the fourth embodiment. As shown in FIG. 23, also in the present embodiment, the first side wall portion 222 and the second side wall portion 224 are formed on the side surface portion of the gate electrode 218 as in the second embodiment described above. However, the side wall portion is not formed on the side surface portion of Fin206.

However, in the present embodiment, after forming the impurity diffusion layer as the source / drain region, the source / drain portion is lifted by, for example, epitaxial growth. That is, since the upper surface and the side surface of the Fin 206 are exposed, the epitaxial silicon portion 400 can be formed on the upper surface and the side surface of the Fin 206 by epitaxial growth. After forming the epitaxial silicon portion 400, impurity ion implantation or silicid formation may be further performed, if necessary.

According to the method for manufacturing a semiconductor device according to the present embodiment, since the side wall portion is not formed on the side surface portion of Fin206, the epitaxial silicon portion 400 can be formed by epitaxial growth. Then, by forming the epitaxial silicon portion 400, the parasitic resistance R in the source / drain region is reduced, so that the driving ability of the transistor can be improved.

[Fifth Embodiment] FIGS. 24 to 26 are sectional views illustrating a manufacturing process of the semiconductor device according to the fifth embodiment. Up to FIG. 24, the manufacturing process is the same as that of the second embodiment described above. That is, the first side wall portion 222 and the second side wall portion 224 are formed on the side surface portion of the gate electrode 218, but the side wall portion is not formed on the side surface portion of the Fin 206.

Subsequently, as shown in FIG. 25, SiN-RIE is performed to remove the SiN hard mask 204 on the Fin 206 and the SiN hard mask 214 on the gate electrode 218. Subsequently, in order to form the source / drain region, impurity diffusion layers are formed on the left and right ends of Fin206 by doping.

Next, as shown in FIG. 26, the source / drain portion of Fin206 and the gate electrode 218 are all silicidized into metal source / drain and metal gate electrodes, respectively. The gate electrode 218 is formed to be very thin, and the lower portion thereof is an embedded insulating film 200. Since the embedded insulating film 200 is not silicidal in the first place, the gate electrode 218 is the gate electrode 218 in the present embodiment. It can be silicid to the lower end.

According to the present embodiment, the first side wall portion 222 and the second side wall portion 224 are formed on the side surface portion of the gate electrode 218, but the side wall portion is not formed on the side wall portion of the Fin 206. Silicide can be formed on the side surface. Therefore, the parasitic resistance R in the source / drain region is reduced, and the driving ability of the transistor can be improved. In addition, since all the polysilicon that constitutes the gate electrode 218 can be silicidized to form a metal gate, the threshold value of the completely depleted transistor (FinFET) can be controlled, and a high driving force can be realized at a low voltage. it can.

The present invention is not limited to the above embodiment and can be variously modified. For example, as shown in FIG. 27, a FinFET may be formed on the silicon substrate 600 by the manufacturing process of each of the above-described embodiments. In this case, Fin206 may be formed by etching the silicon substrate 600, and STI (Shallow Trench Isolation) may be formed between Fin206s from a silicon oxide film 602 or the like.

Further, in the above-described embodiment, FinFET has been described as an example of the semiconductor device to which the present invention is applied, but the present invention can also be applied to other types of semiconductor devices.

[Sixth Embodiment] When the side wall pattern transfer process is used for forming Fin (convex silicon region, active area) and gate electrode, the line is finer than the limit of photolithography. It is possible to form a pattern with a small edge roughness (LER: Line Edge Roughness). Hereinafter, the manufacturing process will be described in order.

First, as shown in FIG. 28, a silicon nitride film 612 is formed on the semiconductor substrate 610 via a thin oxide film (not shown). In the present embodiment, the thickness of the silicon nitride film 612 is, for example, 100 nm. Subsequently, an amorphous silicon layer 614 is formed on the silicon nitride film 612 with a thickness of, for example, about 150 nm. Subsequently, a resist pattern having a width of about 0.1 μm is formed on the amorphous silicon layer 614 by photolithography, and the amorphous silicon layer 614 is etched by RIE using this resist pattern as a mask. As a result, the dummy pattern 616 is obtained.

Next, as shown in FIG. 29, a TEOS having a thickness of about 40 nm is formed on the TEOS, and then etched back with RIE on the entire surface to form a side wall portion 620 on the side surface portion of the dummy pattern 616.

Next, as shown in FIG. 30, the dummy pattern 616 formed of amorphous silicon is removed by etching, leaving the side wall portion 620 formed of TEOS on the silicon nitride film 612.

Next, as shown in FIG. 31, an anti-reflective coating (ARC) 622 for preventing the reflection of light is formed on the film. Subsequently, a photoresist is formed on the antireflection film 622, and the photoresist is patterned using photolithography to form a resist pattern 624. In the present embodiment, the width of the resist pattern 624 is formed to be thicker than the width of the side wall portion 620. As disclosed in Non-Patent Document 1 described above, the resist pattern 624 and the side wall portion 620 may have a portion that overlaps with each other.

Next, as shown in FIG. 32, the silicon nitride film 612 is etched by RIE using the resist pattern 624 and the side wall portion 620 as masks. Subsequently, the side wall portion 620 and the resist pattern 624 are removed by wet etching or the like.

Next, as shown in FIG. 33, the silicon nitride film 612 is thinned by wet etching such as hot phosphoric acid. Next, as shown in FIG. 34, the semiconductor substrate 610 is processed by RIE.

In this way, the pattern transfer of the side wall portion 620 can form a pattern that is finer than the limit of photolithography and has a small line edge roughness (LER). The reason for the reduction in LER is that the line width of the pattern on the side wall 620 is determined by the thickness that forms the TEOS.

However, as can be seen from FIGS. 31 and 32, when the resist pattern 624 is formed by using the antireflection film 622, the antireflection film 622 remains on the side surface of the side wall portion 620, and the thin side wall portion 620 made with great care There is a problem that the line pattern becomes thick. On the other hand, if light is diffusely reflected during photolithography, the shape of the resist pattern 624 is disturbed, which hinders miniaturization. Therefore, it is difficult to omit the antireflection film 622 in order to miniaturize the resist pattern 624.

[7th Embodiment] Therefore, in the 7th embodiment, the line pattern of the side wall portion 620 is prevented from being thickened by the antireflection film 622.

First, as shown in FIG. 35, in the present embodiment, the insulating film 702 is formed on the semiconductor substrate 700 made of silicon. This insulating film is, for example, a silicon oxide film (SiO).₂).

Next, a silicon nitride film 704 is formed on the insulating film 702. In the present embodiment, the thickness of the silicon nitride film 704 is, for example, 100 nm. The reason why the insulating film 702 of the silicon oxide film is formed between the semiconductor substrate 700 and the silicon nitride film 704 is to relax the stress by interposing the insulating film 702 of the silicon oxide film. This silicon nitride film 704 corresponds to the second film in the present embodiment.

Subsequently, an amorphous silicon layer 706 is formed on the silicon nitride film 704, for example, at about 150 nm. Subsequently, a resist pattern having a width of about 0.1 μm is formed on the amorphous silicon layer 706 by photolithography, and the amorphous silicon layer 706 is etched by RIE using this resist pattern as a mask. As a result, a dummy pattern 708 is obtained.

Next, as shown in FIG. 36, a TEOS having a thickness of about 40 nm is formed on the TEOS, and then etched back with RIE on the entire surface to form a side wall portion 710 on the side surface portion of the dummy pattern 708.

Next, as shown in FIG. 37, the dummy pattern 708 formed of amorphous silicon is removed by etching, leaving the side wall portion 710 formed of TEOS on the silicon nitride film 704. This side wall portion 710 corresponds to the first protrusion in the present embodiment.

Next, as shown in FIG. 38, a material (for example, amorphous silicon) different from the side wall portion 710 formed from TEOS is deposited and flattened by CMP (Chemical Mechanical Polishing) to form a base film 712. To form. This base film 712 corresponds to the first film in the present embodiment.

Next, as shown in FIG. 39, an antireflection film (ARC: Anti Reflective Coating) 714 that prevents light reflection is formed on the base film 712. Subsequently, a photoresist is formed on the antireflection film 714, and the photoresist is patterned by photolithography to form a resist pattern 716. In the present embodiment, the width of the resist pattern 716 is formed to be thicker than the width of the side wall portion 710. This resist pattern 716 corresponds to the mask portion in this embodiment.

Next, as shown in FIG. 40, the undercoat film 712 is etched by RIE using this resist pattern 716 as a mask. At this time, the side wall portion 710 formed earlier is exposed. Then, the resist pattern 716 is removed.

Next, as shown in FIG. 41, the silicon nitride film 704 is etched by RIE using both the side wall portion 710 and the base film 712 as masks. Subsequently, the side wall portion 710 and the base film 712 are removed by wet etching or the like. When the side wall portion 710 of TEOS is removed by wet etching such as HF, the insulating film 702 is also etched.

Next, as shown in FIG. 42, the silicon nitride film 704 is thinned by wet etching such as hot phosphoric acid. Next, as shown in FIG. 43, the semiconductor substrate 700 is processed by RIE.

As described above, according to the present embodiment, the pattern transfer of the side wall portion 710 formed by TEOS enables fine processing below the limit of photolithography, and line edge roughness (LER: line edge roughness). ) Can form a small silicon pattern.

Further, even when the resist pattern 716 is formed by photolithography using the antireflection film 714, the antireflection film 714 does not remain on the side surface of the side wall portion 710, so that the pattern width of the side wall portion 710 becomes thick. It can be avoided.

[Eighth Embodiment] In the present embodiment, after the side wall portion 710 is formed, the amorphous silicon dummy pattern 708 is not removed, but the second amorphous silicon is overlapped with each other. Is different from. Hereinafter, the manufacturing process will be described in order.

As shown in FIG. 44, in the present embodiment, the insulating film 702 is formed on the semiconductor substrate 700 made of silicon. This insulating film is, for example, a silicon oxide film (SiO).₂).

Next, a silicon nitride film 704 is formed on the insulating film 702. In the present embodiment, the thickness of the silicon nitride film 704 is, for example, 100 nm. Subsequently, an amorphous silicon layer 706 is formed on the silicon nitride film 704, for example, at about 150 nm. Subsequently, a resist pattern having a width of about 0.1 μm is formed on the amorphous silicon layer 706 by photolithography, and the amorphous silicon layer 706 is etched by RIE using this resist pattern as a mask. As a result, a dummy pattern 708 is obtained.

Next, as shown in FIG. 45, a TEOS having a thickness of about 40 nm is formed on the TEOS, and then etched back with RIE on the entire surface to form a side wall portion 710 on the side surface portion of the dummy pattern 708.

Next, as shown in FIG. 46, a material (for example, amorphous silicon) different from the side wall portion 710 formed from TEOS is deposited on these side wall portions 710 and the dummy pattern 708, and flattened by CMP. The base film 712 is formed by the formation.

Next, as shown in FIG. 47, an antireflection film (ARC: Anti Reflective Coating) 714 that prevents light reflection is formed on the base film 712. Subsequently, a photoresist is formed on the antireflection film 714, and the photoresist is patterned by photolithography to form a resist pattern 716. In the present embodiment, the width of the resist pattern 716 is formed to be thicker than the width of the side wall portion 710.

Next, as shown in FIG. 48, the base film 712 is etched by RIE using this resist pattern 716 as a mask. By this etching, the dummy pattern 708 is also removed, and the side wall portion 710 formed earlier is exposed. Since the following manufacturing process is the same as that of the seventh embodiment described above, the description thereof will be omitted.

As described above, also in the present embodiment, the pattern transfer of the side wall portion 710 formed by TEOS enables fine processing below the limit of photolithography, and line edge roughness (LER). Small silicon pattern can be formed.

Further, since the dummy pattern 708 located between the side wall portions 710 is removed together with the base film 712 by one RIE, the number of steps in the manufacturing process can be reduced and the cost can be reduced. it can.

[9th Embodiment] This embodiment is different from the 8th embodiment described above in that a stopper portion for polishing is formed on the surface of the dummy pattern 708 of amorphous silicon. Hereinafter, the manufacturing process will be described in order.

As shown in FIG. 49, in the present embodiment, the insulating film 702 is formed on the semiconductor substrate 700 made of silicon. This insulating film is, for example, a silicon oxide film (SiO).₂).

Next, a silicon nitride film 704 is formed on the insulating film 702. In the present embodiment, the thickness of the silicon nitride film 704 is, for example, 100 nm. Subsequently, an amorphous silicon layer 706 is formed on the silicon nitride film 704, for example, at about 150 nm. Subsequently, a silicon nitride film 720 is formed on the amorphous silicon layer 706. In the present embodiment, the silicon nitride film 720 is formed, for example, at about 50 nm.

Next, a resist pattern having a width of about 0.1 μm is formed on the silicon nitride film 720 by photolithography, and the silicon nitride film 720 and the amorphous silicon layer 706 are etched by RIE using this resist pattern as a mask. .. As a result, the stopper portion 722 is obtained from the silicon nitride film 720, and the dummy pattern 708 is obtained from the amorphous silicon layer 706.

Next, as shown in FIG. 50, a TEOS having a thickness of about 40 nm is formed on the TEOS, and then the entire surface is etched back with RIE to form a side wall portion 710 on the side surface portion of the dummy pattern 708. ..

Next, as shown in FIG. 51, a material (for example, amorphous silicon) different from the side wall portion 710 formed from TEOS is deposited on these side wall portions 710 and the dummy pattern 708, and flattened by CMP. The base film 712 is formed by forming the base film 712. When performing this CMP, the stopper portion 722 acts as a stopper. However, it is desirable to adjust the process so that the film thickness of the silicon nitride film 720 thinned by CMP is about 20 nm or less.

Next, as shown in FIG. 52, the stopper portion 722 thinned by CMP is removed, and an antireflection film (ARC: Anti Reflective Coating) 714 that prevents light reflection is formed on the base film 712. Subsequently, a photoresist is formed on the antireflection film 714, and the photoresist is patterned by photolithography to form a resist pattern 716. In the present embodiment, the width of the resist pattern 716 is formed to be thicker than the width of the side wall portion 710.

Next, as shown in FIG. 53, the undercoat film 712 is etched by RIE using this resist pattern 716 as a mask. By this etching, the dummy pattern 708 is also removed, and the side wall portion 710 formed earlier is exposed. Since the following manufacturing process is the same as that of the seventh embodiment described above, the description thereof will be omitted.

As described above, also in the present embodiment, the pattern transfer of the side wall portion 710 formed by TEOS enables fine processing below the limit of photolithography, and line edge roughness (LER). Small silicon pattern can be formed.

Further, when the base film 712 is flattened by polishing (CMP in this embodiment), the stopper portion 722 functions as a stopper, so that polishing can be easily performed.

[10th Embodiment] In this embodiment, the forming material of the hard mask 704 for silicon processing in the 7th embodiment described above and the forming material of the side wall portion 710 are replaced. Hereinafter, the manufacturing process will be described in order.

As shown in FIG. 54, in the present embodiment, the insulating film 702 is formed on the semiconductor substrate 700 made of silicon. This insulating film is, for example, a silicon oxide film (SiO).₂).

Next, the TEOS film 750 is formed on the insulating film 702. In the present embodiment, the thickness of the TEOS film 750 is, for example, 100 nm. Subsequently, an amorphous silicon layer 706 is formed on the TEOS film 750 at, for example, about 150 nm. Subsequently, a resist pattern having a width of about 0.1 μm is formed on the amorphous silicon layer 706 by photolithography, and the amorphous silicon layer 706 is etched by RIE using this resist pattern as a mask. As a result, a dummy pattern 708 is obtained.

Next, as shown in FIG. 55, a silicon nitride film having a thickness of about 40 nm is formed on the silicon nitride film, and then etched back by RIE on the entire surface to form a side wall portion 752 on the side surface portion of the dummy pattern 708. Form.

Next, as shown in FIG. 56, the dummy pattern 708 formed of amorphous silicon is removed by etching, leaving the side wall portion 752 formed of silicon nitride on the TEOS film 750.

Next, as shown in FIG. 57, a material (for example, amorphous silicon) different from the side wall portion 752 formed of silicon nitride is deposited and flattened by CMP to form the base film 712.

Next, as shown in FIG. 58, an antireflection film (ARC: Anti Reflective Coating) 714 that prevents light reflection is formed on the base film 712. Subsequently, a photoresist is formed on the antireflection film 714, and the photoresist is patterned by photolithography to form a resist pattern 716. In the present embodiment, the width of the resist pattern 716 is formed to be thicker than the width of the side wall portion 710.

Next, as shown in FIG. 59, the undercoat film 712 is etched by RIE using this resist pattern 716 as a mask. At this time, the side wall portion 752 formed earlier is exposed. Then, the resist pattern 716 is removed.

Next, as shown in FIG. 60, the TEOS film 750 is etched by RIE using both the side wall portion 752 and the base film 712 as masks. Subsequently, the side wall portion 752 and the base film 712 are removed by wet etching or the like.

Next, as shown in FIG. 61, the TEOS film 750 is thinned by wet etching such as HF. Next, as shown in FIG. 62, the semiconductor substrate 700 is processed by RIE.

As described above, various combinations of materials of the present invention can be selected. That is, various materials can be combined while ensuring the selection ratio at the time of etching. Further, even when the stopper portion 722 is formed as in the ninth embodiment, various combinations of materials including the stopper portion 722 can be selected.

[11th Embodiment] In the 10th embodiment described above, the undercoat film 712 made of amorphous silicon is formed of an SOG film (coating film). Hereinafter, the manufacturing process will be described in order.

In the present embodiment, the manufacturing process up to FIG. 63 is the same as that of the tenth embodiment described above. Following FIG. 63, in the present embodiment, as shown in FIG. 64, SOG, which is a material different from the side wall portion 752 formed of silicon nitride, is applied. By applying SOG, the surface of SOG is flattened, so this is used as the base film 760.

Next, as shown in FIG. 65, an antireflection film (ARC: Anti Reflective Coating) 714 that prevents light reflection is formed on the base film 760. Subsequently, a photoresist is formed on the antireflection film 714, and the photoresist is patterned by photolithography to form a resist pattern 716. In the present embodiment, the width of the resist pattern 716 is formed to be thicker than the width of the side wall portion 752.

Next, as shown in FIG. 66, the base film 760 is etched by RIE using this resist pattern 716 as a mask. At this time, the side wall portion 752 formed earlier is exposed.

Next, as shown in FIG. 67, the TEOS film 750 is etched by RIE using both the side wall portion 752, the base film 760, and the resist pattern 716 as masks. Subsequently, the side wall portion 752, the base film 760, and the resist pattern 716 are removed by wet etching or the like.

Next, as shown in FIG. 68, the TEOS film 750 is thinned by wet etching such as HF. Next, as shown in FIG. 69, the semiconductor substrate 700 is processed by RIE.

As described above, also in the present embodiment, the pattern transfer of the side wall portion 752 formed by SiN enables fine processing below the limit of photolithography and line edge roughness (LER). Small silicon pattern can be formed.

Further, since the base film 760 is formed by applying SOG which is a liquid, the polishing step for flattening the surface can be omitted.

The present invention is not limited to the above embodiment and can be variously modified. For example, in the above-described embodiment, the semiconductor substrate 700 made of silicon is used, but a germanium substrate or a silicon germanium substrate may be used as the semiconductor substrate.

<figref num="1">A cross-sectional view illustrating a conventional FinFET manufacturing process.</figref><figref num="2">A cross-sectional view illustrating a conventional FinFET manufacturing process.</figref><figref num="3">FIG. 2 is a cross-sectional view taken along the line A-A'in FIG.</figref><figref num="4">FIG. 5 is a cross-sectional view illustrating a step of forming a side wall portion on a side wall portion of a protrusion by a side wall leaving step.</figref><figref num="5">FIG. 5 is a cross-sectional view illustrating a step of forming a side wall portion on a side wall portion of a protrusion by a side wall leaving step.</figref><figref num="6">The cross-sectional view explaining the etching process which does not form the side wall part in the side wall part part of the protrusion part.</figref><figref num="7">The cross-sectional view explaining the etching process which does not form the side wall part in the side wall part part of the protrusion part.</figref><figref num="8">The cross-sectional view explaining the manufacturing process of the semiconductor device in 1st Embodiment.</figref><figref num="9">The cross-sectional view explaining the manufacturing process of the semiconductor device in 1st Embodiment.</figref><figref num="10">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="11">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="12">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="13">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="14">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="15">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="16">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="17">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="18">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="19">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="20">The cross-sectional view explaining the manufacturing process of the semiconductor device in 2nd Embodiment.</figref><figref num="21">FIG. 20 is a sectional view taken along line B-B'in FIG.</figref><figref num="22">Sectional drawing of the semiconductor device which concerns on 3rd Embodiment.</figref><figref num="23">Sectional drawing of the semiconductor device which concerns on 4th Embodiment.</figref><figref num="24">The cross-sectional view explaining the manufacturing process of the semiconductor device in 5th Embodiment.</figref><figref num="25">The cross-sectional view explaining the manufacturing process of the semiconductor device in 5th Embodiment.</figref><figref num="26">The cross-sectional view explaining the manufacturing process of the semiconductor device in 5th Embodiment.</figref><figref num="27">FIG. 5 is a cross-sectional view of a semiconductor device illustrating another modification.</figref><figref num="28">The cross-sectional view explaining the manufacturing process of the semiconductor device in 6th Embodiment.</figref><figref num="29">The cross-sectional view explaining the manufacturing process of the semiconductor device in 6th Embodiment.</figref><figref num="30">The cross-sectional view explaining the manufacturing process of the semiconductor device in 6th Embodiment.</figref><figref num="31">The cross-sectional view explaining the manufacturing process of the semiconductor device in 6th Embodiment.</figref><figref num="32">The cross-sectional view explaining the manufacturing process of the semiconductor device in 6th Embodiment.</figref><figref num="33">The cross-sectional view explaining the manufacturing process of the semiconductor device in 6th Embodiment.</figref><figref num="34">The cross-sectional view explaining the manufacturing process of the semiconductor device in 6th Embodiment.</figref><figref num="35">The cross-sectional view explaining the manufacturing process of the semiconductor device in 7th Embodiment.</figref><figref num="36">The cross-sectional view explaining the manufacturing process of the semiconductor device in 7th Embodiment.</figref><figref num="37">The cross-sectional view explaining the manufacturing process of the semiconductor device in 7th Embodiment.</figref><figref num="38">The cross-sectional view explaining the manufacturing process of the semiconductor device in 7th Embodiment.</figref><figref num="39">The cross-sectional view explaining the manufacturing process of the semiconductor device in 7th Embodiment.</figref><figref num="40">The cross-sectional view explaining the manufacturing process of the semiconductor device in 7th Embodiment.</figref><figref num="41">The cross-sectional view explaining the manufacturing process of the semiconductor device in 7th Embodiment.</figref><figref num="42">The cross-sectional view explaining the manufacturing process of the semiconductor device in 7th Embodiment.</figref><figref num="43">The cross-sectional view explaining the manufacturing process of the semiconductor device in 7th Embodiment.</figref><figref num="44">The cross-sectional view explaining the manufacturing process of the semiconductor device in 8th Embodiment.</figref><figref num="45">The cross-sectional view explaining the manufacturing process of the semiconductor device in 8th Embodiment.</figref><figref num="46">The cross-sectional view explaining the manufacturing process of the semiconductor device in 8th Embodiment.</figref><figref num="47">The cross-sectional view explaining the manufacturing process of the semiconductor device in 8th Embodiment.</figref><figref num="48">The cross-sectional view explaining the manufacturing process of the semiconductor device in 8th Embodiment.</figref><figref num="49">The cross-sectional view explaining the manufacturing process of the semiconductor device in 9th Embodiment.</figref><figref num="50">The cross-sectional view explaining the manufacturing process of the semiconductor device in 9th Embodiment.</figref><figref num="51">The cross-sectional view explaining the manufacturing process of the semiconductor device in 9th Embodiment.</figref><figref num="52">The cross-sectional view explaining the manufacturing process of the semiconductor device in 9th Embodiment.</figref><figref num="53">The cross-sectional view explaining the manufacturing process of the semiconductor device in 9th Embodiment.</figref><figref num="54">FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.</figref><figref num="55">FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.</figref><figref num="56">FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.</figref><figref num="57">FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.</figref><figref num="58">FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.</figref><figref num="59">FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.</figref><figref num="60">FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.</figref><figref num="61">FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.</figref><figref num="62">FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.</figref><figref num="63">The cross-sectional view explaining the manufacturing process of the semiconductor device in 11th Embodiment.</figref><figref num="64">The cross-sectional view explaining the manufacturing process of the semiconductor device in 11th Embodiment.</figref><figref num="65">The cross-sectional view explaining the manufacturing process of the semiconductor device in 11th Embodiment.</figref><figref num="66">The cross-sectional view explaining the manufacturing process of the semiconductor device in 11th Embodiment.</figref><figref num="67">The cross-sectional view explaining the manufacturing process of the semiconductor device in 11th Embodiment.</figref><figref num="68">The cross-sectional view explaining the manufacturing process of the semiconductor device in 11th Embodiment.</figref><figref num="69">The cross-sectional view explaining the manufacturing process of the semiconductor device in 11th Embodiment.</figref>

Code description

100 Embedded insulating film 120 First protrusion 122 Second protrusion 124 First film 125 Second film 126 First side wall 128 Second side wall 700 Semiconductor substrate 702 Insulation film 704 Silicon nitride film 706 Amorphous Silicon layer 708 Dummy pattern 710 Side wall 712 Base film 714 Anti-reflection film 716 Resist pattern