Semiconductor integrated circuit

The present invention relates to a semiconductor integrated circuit provided with a bleeder resistor circuit that can be trimmed from the outside.

Conventionally, a semiconductor integrated circuit provided with a bleeder resistance circuit capable of trimming by a memory as shown in the circuit diagram of FIG. 3 has been known. A write control circuit 102 having a data input terminal 97 and a clock input terminal 96 as input terminals, a plurality of memory cells 103 to which data is written by the output of the write control circuit 102, and a data held by the memory cells 103 are reflected and turned on. The trimming switch 104 is composed of a MOS transistor that switches the off state, the switch control circuit 106 that buffers the output of the memory cell 103 and transmits it to the trimming switch 104, and the bleeder resistance circuit 105 that is trimmed by the trimming switch 104. To. The bleeder resistance circuit 105 is a circuit that changes the overall resistance value by combining the on / off states of the trimming switch 104.

The write control circuit 102 includes a shift register 99 that counts the clock signal input from the clock input terminal 96, and a data register 100 that temporarily holds the trimming data input from the data input terminal 97.

When writing data, the trimming data to be written is serially input to the data input terminal 97 in synchronization with the clock signal input to the clock input terminal 96 . When the clock signal reaches the end of the shift register 99 that counts the clock signal, the write signal is output to the data write control signal node 98, and the trimming data stored in the data register 100 is transferred to the corresponding memory cell in the memory cell 103. Communicate to.

At the time of data reading, the trimming data held in the memory cell 103 is transmitted to the trimming switch 104 via each corresponding switch control circuit 106, and the on / off state is determined.

That is, the bleeder resistance circuit 105 can be trimmed to a desired resistance value by serially inputting a combination of on / off states of the trimming switch 104 that realizes a desired resistance value to the data input terminal 97. (See, for example, Patent Document 1)<patcit num="1"><text>Japanese Patent Application Laid-Open No. 2003-242799 (Page 12, Fig. 1)</text></patcit>

<p> However, in a conventional semiconductor integrated circuit equipped with a trimming bleeder resistor circuit, the number of flip-flop circuits included in the data register 100 increases as the number of trimming data bits increases, and the layout area increases, resulting in a semiconductor. There is a problem that it hinders cost reduction and miniaturization of integrated circuits. Therefore, an object of the present invention is to solve the conventional problems and to provide a semiconductor integrated circuit having a small layout area.</p>

<p> In order to achieve the above object, in a semiconductor integrated circuit provided with a bleeder resistance circuit capable of trimming according to the present invention, serially input trimming data is sequentially written to a plurality of memory cells by a selection signal to bleeder resistance. It is characterized by trimming.</p>

<p> According to the semiconductor integrated circuit provided with the trimming bleeder resistance circuit of the present invention, since a data register for holding the trimming data is not required, it is possible to provide an inexpensive semiconductor integrated circuit with a small layout area. It will be possible.</p>

FIG. 1 is a block diagram of a semiconductor integrated circuit provided with a trimming bleeder resistor circuit of the present invention. A clock input terminal 96, a data input terminal 97, a shift register 99 that creates a selection signal from a clock signal, a write control circuit 110 consisting of a plurality of AND circuits that input trimming serial data and a selection signal, and a write control circuit. A memory cell 103 composed of a plurality of memory cells connected to, a trimming switch 104, a switch control circuit 106 that controls the trimming switch 104 on / off based on the data of the memory cell, and a bleeder resistance circuit 105 that can be trimmed by the trimming switch. Consists of.

The output signal (A1, A2, A3 ... An) of each stage of the shift register 99 is an AND corresponding to the memory cell as a selection signal for selecting the memory cell for performing the data writing operation from the memory cell 103. Input to each circuit 110.

The AND circuit 110 outputs trimming serial data to each memory cell at the timing selected by the selection signal. In this example, all memory cells 103 are initialized to the Low level.

Figure 2 shows the input / output waveform of the write control circuit. clk is the waveform input to the clock input terminal 96, a1 to an are the waveforms of the selection signal, and data is the waveform input to the data input terminal 97.

By inputting the clk signal to the clock input terminal 96, the selection signals a1 to an are output from the shift register 99. The AND circuit 110 outputs a data signal when the selection signal is at a high level, and outputs a low level when the selection signal is at a low level. Therefore, for the memory cell for which the high level of the memory cell 103 is to be given at the time of writing the trimming data, the high level may be given to the data input terminal 97 in synchronization with the timing of the corresponding selection signal of the high level. On the contrary, for the memory cell for which the low level of the memory cell 103 is desired to be given, the low level may be given to the data input terminal 97 in synchronization with the timing of the corresponding selection signal at the high level.

Next, the trimming data of the memory cell 103 turns on / off the trimming switch 104 composed of the MOS totalizer via the switch control circuit 106, and trims the bleeder resistance circuit 105 to a desired resistance value.

A memory electronic switch such as a memory MOS transistor used for a non-volatile memory can also be used for the trimming switch 104 of the embodiment of the present invention. In this case, the on-resistance of the memory electronic switch is set sufficiently smaller than the element resistance of the bleeder resistor 105, and the off resistance of the electronic switch is set sufficiently larger than the element resistance of the bleeder resistor 105. As a result, the memory cell 103 becomes unnecessary, so that the present invention can realize a small circuit.

Although the operation of the embodiment of the present invention using the AND circuit has been described above, the circuit of the present invention is not limited to the AND circuit. Depending on the logical state of the input signal, a NOR circuit or the like can be used. In this case, the same effect can be obtained by changing the logical state of the operation description.

Further, it is clear that the same effect can be obtained for a circuit using EPROM or EEPROM that can hold trimming data even when no power is input to the memory cell 103.

<figref num="1">It is a block diagram of the semiconductor integrated circuit provided with the bleeder resistance circuit which can be trimmed of this invention.</figref><figref num="2">It is an input / output waveform of the write control circuit of the semiconductor integrated circuit of this invention.</figref><figref num="3">It is a block diagram of the semiconductor integrated circuit provided with the conventional trimming bleeder resistance circuit.</figref>

Code description

96 Clock input terminal 97 Data input terminal 98 Data write control signal node 99 Shift register 100 Data register 101 Data register Output bus line 103 Memory cell 104 Trimming switch 105 Breeder resistance 106 Switch control circuit 110 Write control circuit 111 Memory address selection signal node 112 Clock signal waveform 113 Memory address selection signal Waveform 114 Data signal waveform