Method of manufacturing semiconductor device

The present invention relates to a method for manufacturing a semiconductor device.

In recent years, semiconductor devices have been required to be lighter, thinner, shorter, smaller, and have higher performance. In semiconductor devices such as multi-chip packages, wiring density has been increased, logic elements have been miniaturized, and memory capacity has been increased.

As one means for responding to such a demand, it has been attempted to provide a through electrode on a semiconductor substrate to increase the density of wiring. As a conventional through electrode, for example, there is one described in Patent Document 1. The document discloses a semiconductor device having a through electrode having a structure in which an intermediate insulating layer is provided around a through hole penetrating a semiconductor element substrate and a conductive layer is filled inside the intermediate insulating layer. It is said that using this configuration, a plurality of semiconductor device substrates can be laminated three-dimensionally at high density.

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2000-311982</text></patcit>

<p> However, since the through silicon via described in Patent Document 1 has a thick through electrode penetrating the semiconductor element substrate, wiring or the like cannot be provided in the region where the through electrode is formed. For this reason, the degree of integration of wiring and the like is lowered, and there is room for further improvement in terms of increasing the density of wiring. Further, since the through electrode is manufactured after the element is formed, there is a concern that the reliability of the element may be lowered when the through electrode is formed.</p><p> The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a through electrode excellent in performance as an electrode and manufacturing stability.</p>

<p> According to the present invention, a step of forming a first hole on the element forming surface side of a semiconductor substrate, a step of forming a barrier film made of an insulating material on the inner wall of the first hole, and the first step. A step of burying the first metal film so as to embed the inside of the hole, and removing the first metal film formed outside the first hole, and first inside the first hole. A step of forming a plug and a step of selectively removing the semiconductor substrate from the back surface side to form a second hole and exposing a part of the first plug inside the second hole. After the step of selectively adhering the insulating material to the region of the inner surface of the second hole excluding the first plug and the step of adhering the insulating material, at least a part of the exposed barrier film is removed. Then, the step of exposing the first metal film and the step of selectively growing the second metal film so as to fill the inside of the second hole to include a part of the first plug. Provided is a method for manufacturing a semiconductor device, which comprises a step of forming a second plug.</p><p> In the present specification, the element forming surface is the surface of the semiconductor substrate on which the semiconductor element is formed.</p><p> According to this method, a semiconductor device having a through electrode having excellent adhesion between the first plug and the second plug can be stably manufactured by a simple process. In addition, a semiconductor device having excellent insulation on the surface of the second plug can be manufactured by a simple process.</p><p> In the present invention, the first plug includes a first metal film and a barrier film. Further, in the present invention, the first metal film may include a barrier metal film.</p><p> In the method for manufacturing a semiconductor device of the present invention, in the step of forming the second plug, the second metal film is formed so as to fill the inside of the second hole starting from the exposed first metal film. It may include a step of growing. By doing so, the metal film can be more reliably grown in the second hole.</p><p> In the method for manufacturing a semiconductor device of the present invention, the insulating material may be an electrodeposition material. By doing so, the insulating material can be adhered to the inner surface of the second hole except the first plug with higher selectivity.</p><p> In the method for manufacturing a semiconductor device of the present invention, the electrodeposition material may be an electrodeposition polyimide. By doing so, the resistance of the insulating material to the treatment in the subsequent process can be improved. Therefore, it is possible to stably manufacture the semiconductor device with a higher yield.</p><p> In the method for manufacturing a semiconductor device of the present invention, the second hole may be a hole having a larger cross-sectional area than the first hole. By doing so, the cross-sectional area of the first plug can be made smaller than the cross-sectional area of the second plug. Therefore, a part of the first plug can be surely included in the second plug. In addition, a semiconductor device having a high degree of wiring integration can be stably manufactured.</p><p> In the method for manufacturing a semiconductor device of the present invention, a step of forming a metal seed layer on the inner surface of the second hole is included before the step of forming the second plug to form the second plug. The step may include a step of growing the second metal film starting from the seed layer. By growing the second metal film starting from the seed layer, the metal film can be more reliably embedded in the second pore.</p><p> In the method for manufacturing a semiconductor device of the present invention, after the step of forming the second hole and before the step of attaching the insulating material, the first plug on the inner surface of the second hole is removed. The step of selectively forming a metal seed layer in the region and adhering the insulating material may include a step of adhering the insulating material to the seed layer. By doing so, the insulating material can be more stably adhered to the region excluding the first plug on the inner surface of the second hole.</p><p> In the method for manufacturing a semiconductor device of the present invention, the step of forming the first hole is the region of the region where the first hole is formed after the insulating film is formed on the element forming surface side of the semiconductor substrate. A step of selectively removing the insulating film can be included. By doing so, it is possible to stably obtain a semiconductor device having a configuration in which the first plug is connected to the wiring on the upper part of the insulating film.</p><p> In the method for manufacturing a semiconductor device of the present invention, the step of forming the wiring layer includes a step of forming a wiring layer on the insulating film of the semiconductor substrate after the step of forming the first plug. A step of forming a wiring in contact with the first plug may be included. By doing so, it is possible to increase the degree of integration of the wiring in the same layer as the wiring connected to the first plug. Therefore, a semiconductor device having a high degree of wiring integration can be stably manufactured. Further, in the method for manufacturing a semiconductor device of the present invention, a step of forming an upper wiring connected to the wiring may be included in the upper part of the wiring layer. By doing so, it is possible to stably manufacture a multi-layer semiconductor device having a high degree of integration of the upper wiring existing above the wiring layer.</p><p> It should be noted that any combination of these configurations and the conversion of the expression of the present invention between methods, devices and the like are also effective as aspects of the present invention.</p><p> For example, according to the present invention, a penetrating electrode that penetrates a semiconductor substrate, an insulating layer provided on an element forming surface of the semiconductor substrate, and a conductive member provided inside the insulating layer and penetrates the semiconductor substrate. The through electrode has a first conductive plug to be connected to the conductive member and a cross-sectional area provided in the semiconductor substrate and larger than the cross-sectional area of the first conductive plug. Provided is a semiconductor device comprising a second conductive plug including a part of the first conductive plug.</p><p> In the semiconductor device of the present invention, a part of the first conductive plug is included in the second conductive plug. Therefore, the anchor effect is preferably obtained, and the adhesion of these plugs is excellent. In addition, the contact resistance between these plugs is reduced. Further, since the first plug having a small cross-sectional area is arranged on the element forming surface side, the degree of integration of the wiring in the vicinity of the through electrode can be improved. Therefore, the configuration is suitable for miniaturization.</p><p> Further, according to the present invention, the semiconductor substrate, the transistor forming layer provided on the element forming surface of the semiconductor substrate, the wiring layer provided above the transistor forming layer, and the wiring layer provided above the wiring layer are provided. It has an upper wiring layer, a transistor forming layer, and a penetrating electrode penetrating the semiconductor substrate, and the penetrating electrode is provided in the transistor forming layer and is connected to a wiring formed in the wiring layer. It is characterized by having one plug and a second plug formed in the semiconductor substrate, having a cross-sectional area larger than the cross-sectional area of the first conductive plug, and connecting to the first plug. The semiconductor device is provided.</p><p> In the semiconductor device of the present invention, the first conductive plug is connected to the wiring layer coated on the upper wiring layer. Further, the cross-sectional area of the first conductive plug is smaller than the cross-sectional area of the second conductive plug. Therefore, it is possible to improve the degree of integration of wiring and elements in the wiring layer or the layer above it. Therefore, the semiconductor device of the present invention has a configuration suitable for miniaturization.</p><p> In the semiconductor device of the present invention, the second conductive plug and the semiconductor substrate may be in contact with each other via an insulating film. By doing so, it is possible to obtain a structure having excellent manufacturing stability. In addition, the parasitic capacitance can be reduced. For example, in the present invention, the insulating film can be an electrodeposition insulating film.</p><p> Further, in the present invention, the step of embedding the first metal film may include a step of forming a barrier metal film on the inner wall of the first hole. Further, in the present invention, the first metal film can be a laminated film including a barrier metal film. By doing so, it is possible to more reliably suppress the diffusion of the conductive material constituting the first plug onto the semiconductor substrate.</p>

<p> As described above, according to the present invention, there is provided a semiconductor device having a through electrode having excellent performance as an electrode and manufacturing stability. Further, it becomes possible to increase the density of wiring of the semiconductor device.</p>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate in the following description. Further, in the following embodiments, the element forming surface side of the semiconductor substrate is the upper (front) side of the semiconductor device, and the back surface side of the semiconductor substrate is the lower (back) side of the semiconductor device.

(First Embodiment) FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to the present embodiment. The semiconductor device 100 of FIG. 1 has a laminated structure of a silicon substrate 101, an etching stopper film 109, a lowermost layer insulating film 111, and a first wiring layer insulating film 113, and has a silicon substrate 101, an etching stopper film 109, and a lowermost layer insulating film. A through electrode 135 that penetrates the film 111 is provided.

A MOS transistor composed of a diffusion layer 105, a gate electrode 107, and the like and an element separation film 103 are formed on the element forming surface of the silicon substrate 101. The lowermost insulating film 111 is formed so as to embed the MOS transistor and the element separation film 103. An etching stopper film 109 is provided in the lowermost insulating film 111 in contact with the upper surfaces of the silicon substrate 101 and the gate electrode 107. Further, the lowermost insulating film 111 is also provided with a connection plug 123 for connecting to the diffusion layer 105.

The first wiring layer insulating film 113 is provided with a connection plug 122 that electrically connects to the first wiring 121 and the first wiring 121. Further, on the upper part of the connection plug 122, a pad 125 electrically connected to the connection plug 122 and a bump 127 electrically connected to the pad 125 are formed in this order.

The through silicon via 135 has a conductive small-diameter plug 119 and a conductive large-diameter plug 131. The cross-sectional area and diameter of the small-diameter plug 119 are larger than the cross-sectional area and diameter of the connecting plug 123 and smaller than the cross-sectional area and diameter of the large-diameter plug 131, respectively. Further, a protruding portion 141 in which the small diameter plug 119 protrudes from the silicon substrate 101 penetrates the upper surface of the large diameter plug 131.

The diameter of the small diameter plug 119 can be, for example, about 1 to 5 μm. Further, the small diameter plug 119 can be configured to penetrate into the silicon substrate 101 by about 20 to 50 μm. Further, the length of the protruding portion 141 penetrating into the large diameter plug 131 is set to, for example, about 1 to 50 μm. The diameter of the large diameter plug 131 is, for example, about 10 to 1000 μm.

The small-diameter plug 119 penetrates the etching stopper film 109 and the silicon substrate 101 in this order from the upper surface of the lowermost insulating film 111, and the tip thereof is a protruding portion 141 exposed to the outside of the silicon substrate 101. The upper surface of the small-diameter plug 119 is in contact with the first wiring 121 having a bottom surface in the same plane as the bottom surface of the first wiring layer insulating film 113, and an electrical connection is secured. The side surface of the small diameter plug 119 is covered with the SiN film 137 except for the protrusion 141.

Further, the large diameter plug 131 is formed from the back surface of the silicon substrate 101 toward the element forming surface. The upper surface of the large diameter plug 131 is located below the upper surface of the silicon substrate 101. An electrodeposition insulating film 129 is provided on the bottom surface and the side surface of the large-diameter plug 131 and the back surface of the silicon substrate 101. The surface of the large-diameter plug 131 is covered with a plating film 133.

The material of the small diameter plug 119 is not particularly limited, but W can be used, for example. By doing so, diffusion to the silicon substrate 101 is preferably suppressed. The materials of the large-diameter plug 131 and the plating film 133 are not particularly limited, but may be, for example, Ni and Au, respectively.

Next, a method of manufacturing the semiconductor device 100 will be described. 2 (a) to 2 (d) are cross-sectional views schematically showing the manufacturing process of the semiconductor device 100 shown in FIG.

First, the gate electrode 107, the diffusion layer 105, and the element separation film 103 are formed on the silicon substrate 101. The element separation membrane 103 is, for example, STI (shallow trench isolation). Then, the etching stopper film 109 and the lowermost insulating film 111 are laminated in this order on the entire upper surface of the silicon substrate 101.

At this time, as the etching stopper film 109, for example, a SiN film is formed at 50 nm by the plasma CVD method. Further, as the lowermost insulating film 111, for example, SiO₂The film is deposited at 400 nm by the plasma CVD method. Alternatively, as the lowermost insulating film 111, an L-Ox (trademark) film, which is a low dielectric constant interlayer insulating film, is formed at 300 nm by a coating method, and SiO is formed on the upper surface of the L-Ox (trademark) film.₂A laminated film may be formed by forming a film at 100 nm.

Next, the antireflection film and the photoresist are applied in this order on the lowermost insulating film 111, and a resist pattern (not shown) having an opening corresponding to the shape of the small diameter plug 119 is formed by using a photolithography technique. The bottom insulating film 111 is dry-etched using the photoresist film as a mask to open the position where the small-diameter plug 119 is provided. Then, the etching stopper film 109 is etched back by dry etching.

After that, the etching gas is further changed to etch the silicon substrate 101 halfway. For example, etching is performed from the upper surface of the silicon substrate 101 to a depth of 10 μm or more and 50 μm or less. By setting the depth to 10 μm or more, the periphery of the protrusion 141 can be reliably connected to the large diameter plug 131. By setting the thickness to 50 μm or less, the amount of protrusion of the small diameter plug 119 from the element forming surface of the silicon substrate 101 into the silicon substrate 101 can be reduced. Therefore, the opening can be stably formed. The diameter of the opening is selected so that the diameter of the small diameter plug 119 is, for example, about 1 to 5 μm. Then, the photoresist film and the antireflection film or their residues due to etching are removed.

Next, a SiN film 137 is formed by 20 nm on the entire upper surface of the silicon substrate 101 provided with an opening corresponding to the shape of the small diameter plug 119.

Then, an antireflection film and a photoresist are newly applied on the lowermost insulating film 111 in this order, and a resist pattern (not shown) that opens corresponding to the shape of the connection plug 123 is formed by using photolithography technology. .. Using this photoresist film as a mask, the lowermost insulating film 111 is dry-etched to open the position where the connection plug 123 is provided above the diffusion layer 105. Then, the etching stopper film 109 is etched back by dry etching to expose the upper surface of the diffusion layer 105. In this way, holes for forming the small diameter plug 119 and the connection plug 123 are obtained.

Next, a W film is formed as a metal film on the entire upper surface of the silicon substrate 101 by the CVD method. The film thickness of the W film is set so that both of them can be embedded according to the diameters of the connection plug 123 and the small diameter plug 119. For example, the film thickness of W is about 1 μm. Then, the W film and the SiN film 137 on the lowermost insulating film 111 are removed by CMP (Chemical Mechanical polishing). In this way, the small diameter plug 119 and the connection plug 123 are formed at the same time (Fig. 2 (a)).

Next, the first wiring layer insulating film 113 is provided on the entire upper surface of the silicon substrate 101. As shown in FIG. 2B, the first wiring layer insulating film 113 has a configuration in which the wiring insulating film 112 and the plug insulating film 114 are laminated.

First, the entire upper surface of the silicon substrate 101 is covered, and the wiring insulating film 112 forming the lower layer of the first wiring layer insulating film 113 is formed with a film thickness of 300 nm. The wiring insulating film 112 can be, for example, a low dielectric constant film such as an L-Ox film. At this time, a SiCN film as a Cu diffusion prevention film may be provided on the lowermost insulating film 111. Also, SiO on the low dielectric constant film₂The film may be formed at 100 nm. Next, an antireflection film and a photoresist are applied to the entire upper surface of the silicon substrate 101, and a resist pattern for groove wiring is formed on the photoresist by using a photolithography technique. Then, using the photoresist as a mask, the wiring insulating film 112 is etched to form an opening for manufacturing the first wiring 121. Next, the photoresist and the antireflection film are removed by ashing.

Then, a TaN film is formed at 30 nm as a barrier metal film by a sputtering method, and a Cu film for seeding is formed at 100 nm on the TaN film. Next, a Cu film is formed at 700 nm by the electrolytic plating method, and then a metal film to be the first wiring 121 is formed by the CMP method. After that, the Cu film and the barrier metal film on the wiring insulating film 112 are removed in the same manner as when the small diameter plug 119 and the connection plug 123 are formed, and the first wiring 121 is formed.

After that, a plug insulating film 114 forming an upper layer of the first wiring layer insulating film 113 is formed on the wiring insulating film 112 by a normal wiring manufacturing process. A connection plug 122 to be connected to the first wiring 121 is formed in the plug insulating film 114. Then, the pad 125 and the bump 127 to be connected to the connection plug 122 are formed in this order. The material of the pad can be, for example, Al, Cu, Ni, TiN or the like. The material of the bump 127 can be, for example, Au, solder, or the like.

An upper layer such as a predetermined number of wiring layers may be further formed on the first wiring layer insulating film 113.

Next, the adhesive layer 115 is formed on the upper surface of the silicon substrate 101, and the support 117 is attached (FIG. 2 (b)). As the pressure-sensitive adhesive layer 115, for example, an adhesive tape is used. The adhesive tape is composed of a base material and adhesive layers formed on both sides thereof. As the base material constituting the adhesive tape, for example, a polyolefin resin, a polyester resin, or the like is used. Further, as the pressure-sensitive adhesive constituting the pressure-sensitive adhesive tape, for example, an acrylic emulsion-type pressure-sensitive adhesive, an acrylic-based solvent-type pressure-sensitive adhesive, a urethane-based pressure-sensitive adhesive, or the like is used.

The material of the support 117 may be any material having resistance to heat, chemicals, external force, etc. in a process such as thinning of the silicon substrate 101 by backside grinding, which will be described later. For example, quartz or Pyrex ( It can be glass such as (registered trademark). Further, it may be used as a material other than glass. For example, a material such as plastics such as acrylic resin may be used.

Next, the back surface of the silicon substrate 101 is ground. Backside grinding is performed by mechanical polishing. The thickness of the silicon substrate 101 after grinding can be appropriately selected within a range in which the bottom of the small diameter plug 119 is not exposed, and can be, for example, about 50 to 200 μm. Then, an antireflection film and a photoresist are formed on the back surface of the silicon substrate 101 in this order, and a resist pattern (not shown) in which a region for forming the large-diameter plug 131 is opened is formed by using a photolithography technique. The silicon substrate 101 is dry-etched using the photoresist film as a mask, and the opening 139 is provided at a position where the large-diameter plug 131 is to be provided later.

The opening 139 has a shape that faces the element forming surface from the back surface of the silicon substrate 101 and the upper surface is located below the vicinity of the element forming surface of the silicon substrate 101. Further, the opening 139 is provided at the bottom of the protrusion 141, and the upper surface thereof is located above the bottom surface of the small diameter plug 119. A SiN film 137 is provided on the surface of the small diameter plug 119, and the etching conditions for dry etching the silicon substrate 101 described above are set to a condition in which the selection ratio between the silicon film and the SiN film 137 is high. The small diameter plug 119 is not removed when the opening 139 is formed, and the silicon substrate 101 on the outer periphery of the side surface of the small diameter plug 119 is selectively removed. As a result, the opening 139 is formed in a form including the bottom surface of the small diameter plug 119. Further, a part of the small diameter plug 119 is exposed to the outside of the silicon substrate 101, and a protruding portion 141 is formed.

Next, an electrodeposition insulating film 129 is provided on the back surface of the silicon substrate 101 (FIG. 2 (c)). At this time, the electrodeposition insulating film 129 is selectively formed on the back surface of the silicon substrate 101 and the bottom surface and side surfaces of the opening 139. Since the surface of the protrusion 141 is covered with the insulating SiN film 137, the electrodeposition insulating film 129 is not formed on the outside of the small diameter plug 119. The film thickness of the electrodeposited insulating film 129 is, for example, about 0.5 to 5 μm.

The electrodeposited insulating film 129 is, for example, an electrodeposited polyimide film. As the material of the electrodeposited polyimide film, a cationic polyimide electrodeposition coating material or an anionic polyimide electrodeposition coating material can be used. Specifically, for example, Elecoat PI manufactured by Shimizu Co., Ltd. can be used. The material of the electrodeposition insulating film 129 is not limited to polyimide, and other electrodeposition polymer paints such as epoxy-based electrodeposition paints, acrylic-based electrodeposition paints, and fluorine-based electrodeposition paints may be used. Good. By using polyimide as the material of the electrodeposition insulating film 129, the heat resistance of the electrodeposition insulating film 129 can be improved. Therefore, deterioration in the subsequent manufacturing process is suitably suppressed, and a configuration capable of stable manufacturing with a high yield can be obtained.

The electrodeposition insulating film 129 is formed, for example, as follows. The silicon substrate 101 is used as one electrode and is immersed in the liquid of the electrodeposition paint together with the other electrode. Then, a predetermined potential is applied to the silicon substrate 101 and the counter electrode according to the electric charge of the polymer. By doing so, the polymer adheres to the surface of the silicon substrate 101. When a predetermined film thickness is obtained, the silicon substrate 101 is taken out from the paint and washed with water. Then, by firing the silicon substrate 101, an electrodeposition insulating film 129 is formed on the back surface thereof.

Next, the SiN film 137 is etched back. As a result, the SiN film 137 is removed at the tip of the protrusion 141 to expose the surface of the small diameter plug 119. At this time, since the electrodeposited insulating film 129 is formed on the back surface of the silicon substrate 101, the silicon substrate 101 is not removed and the SiN film 137 is selectively removed. In addition, in FIG. 1 and FIG. 2 (d), the configuration in which all the SiN film 137 in the protruding portion 141 is removed is illustrated, but at least a part including the plug bottom of the small diameter plug 119 may be exposed. ..

Next, a Ni film is grown from the exposed portion of the small diameter plug 119 by electroless plating to embed the opening 139, and a bump is integrally formed on the outside of the opening 139. Then, by providing the Au plating film 133 on the surface of the bump, the large diameter plug 131 is formed (FIG. 2 (d)).

At this time, the formation of the large-diameter plug 131 may be divided into a step of embedding the opening 139 on the back surface and a step of forming bumps on the back surface.

Then, by peeling the pressure-sensitive adhesive layer 115 from the element forming surface of the silicon substrate 101, the support 117 is removed, and the semiconductor device 100 shown in FIG. 1 is obtained.

Next, the effect of the semiconductor device 100 shown in FIG. 1 will be described. First, in the semiconductor device 100, the through electrode 135 is composed of two plugs, a small diameter plug 119 and a large diameter plug 131. The protruding portion 141 at the end of the small diameter plug 119 is included in the large diameter plug 131.

FIGS. 3 (a) and 3 (b) are diagrams schematically showing the configuration of a through electrode composed of two plugs having different thicknesses. In each division, the upper view is a cross-sectional view and the lower view is a plan view. FIG. 3A is a diagram showing the configuration of the through silicon via 135 according to the present embodiment. Further, FIG. 3B is a diagram showing a through electrode 235 having a shape in which the small diameter plug 219 and the large diameter plug 231 are connected on a flat surface.

In the configuration shown in Fig. 3 (a), the adhesion between both plugs can be improved by the anchor effect. Therefore, as in the configuration of FIG. 3B, it is possible to have a configuration in which these ends are in close contact with each other as compared with the case where they are simply in contact with each other. Further, the large-diameter plug 131 can be formed by selective growth from the back surface side of the silicon substrate 101. Therefore, the structure is such that the manufacturing process can be simplified. Further, with this configuration, the contact resistance between both plugs can be reduced. Further, the diameter of the plug can be lowered in the vicinity of the wiring to secure a sufficient wiring density, and the diameter of the plug can be increased in the vicinity of the wiring to reduce the electric resistance. Therefore, the electrical characteristics of the semiconductor device 100 can be improved.

Further, as shown in FIG. 3 (c), in the structure in which the through electrode 135 according to the present embodiment is composed of two small diameter plugs 119 and a large diameter plug 131 included in the large diameter plug 131, the anchor Due to the effect, the adhesion of the plug is further improved, and the contact resistance is further reduced.

The small diameter plug 119 does not need to penetrate to the back surface side of the large diameter plug 131. Since the depth of the protruding portion 141 can be made shallow, the small diameter plug 119 can be stably manufactured by embedding.

Further, in the through electrode 135, the diameter of the small diameter plug 119 is smaller than the diameter of the large diameter plug 131. Therefore, the size of the first wiring 121 electrically connected to the small diameter plug 119 can be reduced. Further, the configuration is such that the degree of integration of the elements in the lowest layer insulating film 111 can be improved. Therefore, the configuration is suitable for miniaturization of the entire device.

Further, since the small diameter plug 119 can be molded at the same time as the connection plug 123, the manufacturing process can be simplified and the manufacturing cost can be reduced accordingly. Further, the molding of the small diameter plug 119 has a small influence on the transistor molding process, and the formation of the through electrode 135 causes less damage to the transistor.

Further, in the upper part of the through electrode 135, the small diameter plug 119 is connected to the first wiring 121 in the first wiring layer insulating film 113 which is the lowest layer wiring, and the through electrode 135 projects to the first wiring layer insulating film 113. It is configured not to. Therefore, the wiring density in the first wiring layer insulating film 113 can be improved. Therefore, the installation of the through electrode 135 has a small effect on the circuit configuration, the semiconductor device 100 has a high degree of freedom in selecting the arrangement of elements and wiring, and the dead space of the first wiring layer insulating film 113 is reduced and the first The configuration can be such that the degree of integration of one wiring 121 can be increased.

Further, in the semiconductor device 100, the electrodeposition insulating film 129 is selectively provided in a region excluding the surface of the protrusion 141 on the inner surface of the opening 139. Therefore, since the electrodeposition insulating film 129 can be used as a protective film in the subsequent steps of forming the large diameter plug 131, it is necessary to form a resist pattern for forming the large diameter plug 131 on the back surface of the silicon substrate 101. Absent. Therefore, the large-diameter plug 131 can be stably manufactured by a simple process.

Next, the configuration of the through electrode 135 including the small diameter plug 119 and the large diameter plug 131 will be further described in comparison with the configuration of the conventional through electrode. 4 (a) and 4 (b) are cross-sectional views schematically showing the configuration of the through electrode. FIG. 4A is a diagram schematically showing the configuration of the through silicon via 135 according to the present embodiment. Further, FIG. 4B is a diagram schematically showing the configuration of the conventional through silicon via 235.

As shown in FIG. 4 (b), the conventional through electrode 235 is composed of a single thick plug, and is in contact with the wiring 253 on the upper surface thereof. Therefore, the area of the wiring 253 above the through electrode 235 tends to be relatively large. Further, in the layer of the wiring 253 in contact with the through electrode 235, it was not possible to provide the wiring 254 other than the wiring 253 in contact with the through electrode 235 in the vicinity of the through electrode 235. Therefore, as shown by the arrows in the drawing, it was possible to form the wiring 254 other than the wiring 253 in contact with the through electrode 235 only in the region away from the upper surface of the through electrode 235 and its vicinity. Therefore, there is room for improvement in terms of improving the degree of integration of the wiring 254 other than the wiring 253 that contacts the through electrode 235.

On the other hand, as shown in FIG. 4A, the through silicon via 135 according to the present embodiment is in contact with the wiring 153 on the upper surface of the small diameter plug 119. Therefore, the cross-sectional area of the wiring 153 above the small diameter plug 119 can be reduced. The plug connected to the wiring 153 is a small diameter plug 119. Therefore, as shown by the arrow in the figure, the area where the wiring 154 other than the wiring 153 in contact with the small diameter plug 119 can be formed is wide. Therefore, the degree of integration of the wiring 154 other than the wiring 153 that contacts the small diameter plug 119 can be improved. Further, the diameter of the plug can be reduced in the vicinity of the wiring layer to sufficiently secure the wiring density, and the diameter of the plug can be increased in the vicinity of the wiring layer to reduce the electrical resistance.

Further, the through silicon via 135 of FIG. 4 (a) has a configuration in which a part of the small diameter plug 119 penetrates into the large diameter plug 131 as described above with reference to FIGS. 3 (a) and 3 (b). Therefore, unlike the configuration shown in Fig. 4 (b), even when two plugs are used, the contact resistance between these plugs is sufficiently small when compared with the configuration shown in Fig. 3 (b). It has a structure with excellent characteristics as a through electrode.

Although not shown in FIG. 1, in the semiconductor device 100, the configuration of the upper layer of the first wiring layer insulating film 113 can be appropriately selected according to the device design. A wiring layer or the like may be further laminated on the first wiring layer insulating film 113.

For example, FIG. 5 is a cross-sectional view schematically showing the configuration of a semiconductor device in which wiring layers are laminated. The configuration of the semiconductor device of FIG. 5 is basically the same as that of the semiconductor device 100 shown in FIG. 1, but in addition to the lowermost layer insulating film 111 and the first wiring layer insulating film 113, the silicon substrate 101 is further insulated. Layer 161 and insulating layer 163 are laminated. A wiring 165 and a connection plug 167 are formed on the insulating layer 161. Wiring 169 and connection plug 171 are formed on the insulating layer 163.

As shown in FIG. 5, the through silicon via 135 according to the present embodiment is provided with a small-diameter plug 119 having a small cross-sectional area on the element forming surface side, and this is connected to the first wiring 121 provided in the lower layer in the laminate. are doing. Therefore, the degree of integration of the upper layer wiring can be improved.

Further, FIG. 6 is a cross-sectional view schematically showing another configuration of the semiconductor device in which the wiring layers are laminated. As shown in FIG. 6, since the small diameter plug 119 is connected to the first wiring 121, the degree of freedom in designing the upper layer is superior to that of the first wiring 121. For example, a configuration in which the through electrode 135 is not connected to the bump 127, or a structure in which the through electrode 135 and the bump 127 are connected via a wiring (not shown) without forming the bump 127 directly above the through electrode 135. can do.

Further, in the semiconductor device according to the present embodiment and the following embodiments, as a mode in which a part of the small diameter plug 119 constituting the through electrode 135 is included in the large diameter plug 131, for example, a part of the cross section of the small diameter plug 119 is included. Examples thereof include a mode in which the entire cross section is included and a mode in which the entire cross section is included. 7 (a) and 7 (b) are cross-sectional views schematically showing the configuration of such through silicon via 135. FIG. 7A is a diagram showing a configuration in which the entire cross section of the small diameter plug 119 is included in the large diameter plug 131. Further, FIG. 7B is a diagram showing a configuration in which a part of the cross section of the small diameter plug 119 is included in the large diameter plug 131. The shape of the recess formed in the large-diameter plug 131 differs depending on how the small-diameter plug 119 is encapsulated.

As shown in FIGS. 7 (a) and 7 (b), a plurality of small diameter plugs 119 are included in the large diameter plug 131 by incorporating at least a part of the cross section of the small diameter plug 119 in the large diameter plug 131. It can be configured to be in contact with the surface. Therefore, the adhesion between the small diameter plug 119 and the large diameter plug 131 can be improved as compared with the configuration described above using FIG. 3 (b). Further, as shown in FIG. 7A, the adhesion of the small-diameter plug 119 can be further improved by penetrating the large-diameter plug 131 and including the small-diameter plug 119.

(Second Embodiment) The semiconductor device 100 according to the first embodiment can also be manufactured as follows. Hereinafter, the points different from those of the first embodiment will be mainly described with reference to FIGS. 2 (a) to 2 (d).

First, in the same manner as in the first embodiment, the procedure of providing the electrodeposited insulating film 129 on the back surface of the silicon substrate 101 is performed (FIG. 2 (c)). Next, the SiN film 137 in the protrusion 141 is etched back in the same manner as in the first embodiment.

Then, a metal seed layer is formed on the entire back surface of the silicon substrate 101 provided with the electrodeposition insulating film 129. The metal constituting the seed layer can be, for example, Ni, Ni / Cu, TiN / Ti / Cu, or the like. When a plurality of metals are used for the seed layer, they are indicated as "lower layer / upper layer" or "lower layer / middle layer / upper layer" in order from the layer closest to the silicon substrate 101. Further, the seed layer can be formed by, for example, a sputtering method.

Next, the back surface of the silicon substrate 101 is covered with the opening 139 to form a resist pattern in which a region other than the opening 139 is open. Then, the seed layer is removed by etching. Then, the resist pattern provided on the back surface of the silicon substrate 101 is removed. This forms a seed layer that covers the inner surface of the opening 139.

Then, electrolytic plating of Ni is performed, a plating film 133 of Au is provided on the surface, and a large-diameter plug 131 is obtained. In this way, the semiconductor device according to the present embodiment is obtained.

In the semiconductor device according to the present embodiment, a seed layer is formed on the entire inner wall of the opening 139. Therefore, the large diameter plug 131 can be stably manufactured in the opening 139 without any gap. Further, since the seed layer is provided, the contact resistance between the small diameter plug 119 and the large diameter plug 131 can be suitably reduced. The conductive structure of the through electrode 135 makes it even more excellent. Therefore, the through silicon via 135 has a more reliable configuration. In addition, it has a structure with excellent manufacturing stability.

(Third Embodiment) The semiconductor device 100 according to the first embodiment can also be manufactured as follows. Hereinafter, the points different from those of the first or second embodiment will be mainly described with reference to FIGS. 2 (a) to 2 (d).

First, the above-described procedure is performed using FIGS. 2 (a) and 2 (b) in the same manner as in the first and second embodiments. After forming the adhesive layer 115 on the upper surface of the silicon substrate 101 and attaching it to the support 117 (FIG. 2 (b)), the procedure up to the back surface grinding of the silicon substrate 101 and the formation of the opening 139 is performed.

Next, a seed layer is provided on the back surface of the silicon substrate 101 before the procedure (FIG. 2C) for providing the electrodeposited insulating film 129 on the back surface of the silicon substrate 101. The material of the seed layer is a material having a lower resistance than Si. For example, a metal such as Ni. The film thickness of the seed layer can be, for example, about 0.1 to 2 μm.

The seed layer can be formed by, for example, electroless plating. By using electroless plating, a seed layer can be selectively formed on the back surface of the silicon substrate 101 with respect to the SiN film 137.

After the seed layer is formed, the seed layer is used as a seed, and an electrodeposition insulating film 129 is provided on the back surface of the silicon substrate 101 in the same manner as in the first embodiment (FIG. 2 (c), but the seed layer is not shown). ). Subsequent steps can be performed in the same manner as in the first or second embodiment. In this way, the semiconductor device according to the present embodiment is obtained.

In the semiconductor device according to the present embodiment, a seed layer is formed on the entire back surface of the silicon substrate 101 including the inner wall of the opening 139. By providing a metal seed layer having a resistance lower than that of Si as a base, the electrodeposition insulating film 129 can be uniformly and stably formed. Therefore, the large-diameter plug 131 can be manufactured more stably without forming a resist pattern for forming the large-diameter plug 131 on the back surface of the silicon substrate 101. Further, the large diameter plug 131 and the silicon substrate 101 can be reliably insulated from each other.

The preferred embodiment of the invention has been described above. However, the present invention is not limited to the above-described embodiment, and it goes without saying that a person skilled in the art can modify the above-described embodiment within the scope of the present invention.

For example, in the above embodiments, a silicon substrate is used as the semiconductor substrate, but a compound semiconductor substrate such as a GaAs substrate may be used.

Further, in the above embodiment, W is used as the material of the small diameter plug 119, but another metal having high conductivity may be used. For example, metals such as Cu, Al, and Ni may be used.

Further, in the above embodiment, the configuration in which the small diameter plug 119 constituting the through electrode 135 is connected to the first wiring layer insulating film 113 has been described, but from the first wiring layer insulating film 113 of the second wiring layer or higher. It may be configured to be connected to the upper lower wiring layer.

Further, in the above embodiment, the configuration in which one small diameter plug 119 penetrates into the upper surface of one large diameter plug 131 has been described as an example, but as shown in FIG. 3C, one large diameter plug has been described. It is also possible to configure 131 with two or more small diameter plugs 119 penetrating. By doing so, the electrical contact between the small diameter plug 119 and the large diameter plug 131 can be further ensured.

Further, the case where both the small diameter plug 119 and the large diameter plug 131 constituting the through electrode 135 are cylindrical has been described as an example, but if the small diameter plug 119 is a columnar body penetrating the large diameter plug 131, these shapes will be different. It is not limited to a cylindrical shape. For example, the shape of the small diameter plug 119 or the large diameter plug 131 may be a shape in which the areas of the upper surface and the bottom surface of an elliptical pillar, a prism, or the like are substantially equal. Further, the shape may be a truncated cone, an elliptical truncated cone, or a truncated cone having no tip on the upper surface. Further, the columnar body may have a trench shape extending in one direction.

Further, in the above embodiment, the configuration in which the upper surface of the large-diameter plug 131 is located below the element forming surface of the silicon substrate 101 has been described as an example, but the large-diameter plug 131 is an element from the back surface of the silicon substrate 101. The configuration may be provided over the vicinity of the forming surface. Further, even if the upper surface of the large-diameter plug 131 slightly protrudes from the element forming surface of the silicon substrate 101, the large-diameter plug 131 may be insulated from the upper surface.

Further, in the above embodiment, the pressure-sensitive adhesive layer 115 and the support 117 are peeled off from the element forming surface of the silicon substrate 101, but if necessary, they may be used as they are as a part of the semiconductor device without being peeled off.

<figref num="1">It is sectional drawing which shows typically the structure of the semiconductor device which concerns on this embodiment.</figref><figref num="2">It is sectional drawing explaining the manufacturing process of the semiconductor device of FIG.</figref><figref num="3">It is a figure which shows typically the structure of the through electrode.</figref><figref num="4">It is sectional drawing which shows typically the structure of the through electrode.</figref><figref num="5">It is sectional drawing which shows typically the structure of the semiconductor device which concerns on this embodiment.</figref><figref num="6">It is sectional drawing which shows typically the structure of the semiconductor device which concerns on this embodiment.</figref><figref num="7">It is sectional drawing which shows typically the structure of the through electrode which concerns on this embodiment.</figref>

Code description

100 Semiconductor device 101 Silicon substrate 102 Semiconductor device 103 Element separation film 104 Semiconductor device 105 Diffusion layer 107 Gate electrode 109 Etching stopper film 112 Insulation film for wiring 113 First wiring layer Insulation film 114 Insulation film for plug 115 Adhesive layer 117 Support 119 Small diameter plug 121 First wiring 122 Connection plug 123 Connection plug 125 Pad 127 Bump 129 Electrodeposition insulating film 131 Large diameter plug 133 Plating film 135 Penetrating electrode 137 SiN film 139 Opening 141 Projection 153 Wiring 154 Wiring 161 Insulation layer 163 Insulation Layer 165 Wiring 167 Connection plug 169 Wiring 171 Connection plug