Field effect transistor

The present invention relates to a field effect transistor, and more particularly to a field effect transistor in which a drain electrode, a semiconductor layer, a source electrode, a gate insulating layer and a gate electrode are laminated and a current value is controlled by an electric signal of the gate electrode. In particular, it is suitable for a field effect transistor used as a drive calculation circuit for a computer such as a sheet display.

Field-effect transistors using amorphous silicon (a-Si) or polysilicon (p-Si) for the semiconductor layer have already been put into practical use for active matrix liquid crystal displays or organic EL display devices. FIG. 4 shows an example of the structure of a field effect transistor using a-Si or p-Si. In the field-effect transistor shown in FIG. 4, the source electrode 15 and the drain 14 are arranged in the lateral direction with respect to the substrate 11. That is, the source electrode 15 and the drain electrode 14 are provided separately by the electrically neutral silicon semiconductor layer (channel layer region) 16. The gate electrode 12 is electrically separated from the silicon semiconductor layer 16 by the gate insulating layer 13 and is arranged on the substrate 11.

In recent years, due to growing interest in low-cost manufacturing processes such as printing methods, field-effect transistors using organic materials for forming semiconductor layers have attracted attention. 5 and 6 are examples of element structures of field effect transistors using organic semiconductor materials. As shown in FIG. 5, even when an organic material is used, the source electrode 105 and the drain electrode 104 are arranged in the lateral direction with respect to the doped silicon substrate 101, as in the transistor using the silicon material. Is common. The gate electrode (not shown) is electrically insulated from the organic semiconductor layer 106 by the gate insulating layer 103 and is arranged on the substrate 101.

On the other hand, there is a transistor structure described in Patent Document 1, and in the transistor structure of Patent Document 1, as shown in FIG. 6, the drain electrode 114, the semiconductor layer 116, and the source electrode 115 are sequentially arranged vertically on the substrate 111. It is a laminated one. Here, the gate electrode 112 and the gate insulating layer 113 are both formed on the substrate 111, and specifically, the gate is adjacent to the three layers of the drain electrode 114, the semiconductor layer 116, and the source electrode 115 in the lateral direction. The insulating layer 113 is arranged, and the gate electrode 112 is arranged adjacent to the gate insulating layer 113 in the lateral direction. By using such a laminated element structure, the channel length can be shortened as compared with the horizontal element, so that a sufficient drain current can be obtained even if a relatively high resistance semiconductor material such as an organic semiconductor material is used. As the semiconductor material constituting such an organic semiconductor layer, an organic material such as a π-electron conjugated polymer compound or an aromatic compound is generally used.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2003-110110</text></patcit>

In the above-mentioned field effect transistors, the electric field applied from the gate electrode via the gate insulating layer acts on the semiconductor layer (channel portion) to control the current flowing between the source electrode and the drain electrode. Realizes transistor operation.

Field-effect transistors that use organic materials for the semiconductor layer require a vacuum process such as chemical vapor deposition (CVD) compared to field-effect transistors that use a-Si or p-Si for the semiconductor layer. However, since the device can be manufactured only by a simple process such as a printing method, the manufacturing method is simplified and the manufacturing cost can be reduced. However, a field-effect transistor using an organic material for the semiconductor layer has a lower carrier mobility than a field-effect transistor using a-Si or p-Si for the semiconductor layer, and cannot pass a large current. Therefore, there is a problem that high-speed operation cannot be performed.

Conventionally, in order to solve such a problem, improvement of organic materials has been attempted as one.

In other words, as improvements from the aspect of organic materials, for example, technologies related to molecular design such as technology for controlling the conjugated state of π-conjugated polymers, technology for using molecular electrical conduction anisotropy, and organic by vapor deposition method. A technique for achieving high crystallinity when obtaining a polymer film has been proposed.

On the other hand, it has also been proposed to solve the above problem by improving the element structure. That is, in the electric field effect type transistors shown in FIGS. 4 and 5, a voltage is applied to the gate electrode while a voltage is applied between the source electrode and the drain electrode, and the voltage is applied to the interface between the gate insulating layer and the semiconductor layer. A current is passed between the source electrode and the drain electrode by inducing a channel, and the current (Id) between the source electrode and the drain electrode at this time can be generally expressed by the following equation. .. Id = [W Cox ? ? Vg-Vth]²] / (2 L) (1) Equations Cox,?, Vg and Vth in the formula are as follows. Cox: Gate capacity (F / m)²) ?: Carrier mobility (cm)²/ Vs) Vg: Gate voltage (V) Vth: Threshold voltage (V)

With reference to the above equation (1), in order to improve the transistor performance within the limited transistor dimensions (L: channel length, W: channel width), a higher Id value must be realized. In addition, as other factors for improving the Id value (factors other than channel length L and channel width W), an increase in Cox and ?? can be considered. Conventionally, it has been proposed that the effective Cox is improved by using a material with a high relative permittivity (Patent Document 2), and that the? Is improved by the development of a π-conjugated polymer material (Patent Document 3). However, these can only be realized after material development. Further, in order to obtain a high Id by reducing the channel length L, improvement of the element structure becomes an issue. Here, the channel length L depends on the limit of lithography processing, and in the field effect transistors shown in FIGS. 4 and 5, the value of the channel length L is limited to about 5 to 10? M. On the other hand, by adopting a laminated element structure as shown in Fig. 6, the L value can be reduced to the level of several hundred nm, and the Id value can be obtained several hundred times from the equation (1). Became. However, the average mobility of organic materials is 10.^-3~10^-4(cm²/ Vs) (Best data: 10^-2(cm²/ Vs)), 0.5 ~ 2 (cm) for a-Si²/ Vs), 10 ~ 100 (cm) for p-Si²Since it is / Vs), the mobility of organic materials is tens to hundreds of times smaller than that of a-Si, and thousands of times smaller than that of p-Si. The structure is still inadequate.<patcit num="2"><text>Japanese Unexamined Patent Publication No. 10-270712</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 10-190001</text></patcit>

Further, in the liquid crystal display device, the transistor element as described above has the source electrode connected to the pixel transparent electrode to drive the liquid crystal for each pixel. Here, in each pixel, the region occupied by the pixel transparent electrode is used as a transmission region that can be visually recognized by the viewer, and the existing region such as the gate electrode and the drain electrode is an opaque region. Therefore, when a transistor element in which the source electrode and the drain electrode are arranged in the horizontal direction as shown in FIGS. 4 and 5 is used, the ratio (aperture ratio) occupied by the transmission region of the liquid crystal display device becomes low. Further, even in the case described in Patent Document 1, the three layers of the drain electrode 114, the semiconductor layer 116 and the source electrode 115, the gate insulating layer 113, and the gate insulating layer 113 are arranged in the lateral direction. Therefore, there is a problem that the aperture ratio is low.

<p> The present invention has been made in view of such a problem, and a semiconductor device having a new device structure for shortening the channel length and shortening the channel and improving the actual electric field mobility can be produced in a low-cost manufacturing process. It is an object of the present invention to provide a transistor element that can be manufactured. Another object of the present invention is to provide a transistor element capable of increasing the aperture ratio when used in an active matrix type display such as a TFT liquid crystal display device.</p>

<p> In the present invention, in order to solve the above object, in the field effect transistor element according to the present invention, the first electrode, the semiconductor layer, and the second electrode are sequentially laminated on the substrate so as to surround the periphery of the multilayer portion. An electrically insulating layer is formed on the surface of the electric insulating layer, and a gate electrode is formed on the upper surface of the electrically insulating layer.</p><p> By adopting the above configuration, even if a material having an electric field mobility lower than a-Si or p-Si such as an organic semiconductor material is used, a sufficient drain for driving the TFT liquid crystal display device or the organic EL display device is used. The current (Id) can now be obtained. That is, the channel length can be reduced to the order of nanometers by the structure in which the first electrode, the semiconductor layer, the second electrode, the gate insulating film, and the gate electrode are sequentially laminated on the substrate. It is sufficient that the insulating layer is formed within a range that prevents the gate electrode and the other electrode from being short-circuited, and it is not essential that the insulating layer covers the entire periphery of the multilayer portion.</p><p> Further, according to the above structure, the channel regions of the semiconductor layer can be formed so as to exist at two locations on the left and right along the semiconductor layer stacking direction, and therefore the effective drain current can be improved.</p><p> Further, since the structure is such that the first electrode, the semiconductor layer, the second electrode, the gate insulating film, and the gate electrode are sequentially laminated on the substrate, the opaque region can be reduced when used in a display device. , A sufficient aperture ratio can be obtained. When used in a display device in this way, it is preferable that either the first electrode or the second electrode is connected to the pixel electrode of the surface display device. In particular, it is preferable to adopt a configuration in which pinholes are formed in the gate electrode and the gate insulating film, and the first electrode or the second electrode and the pixel electrode are electrically connected via the pinholes.</p><p> The electrically insulating layer can be a gate insulating layer. Further, the semiconductor layer can be formed from an inorganic material or a low molecular weight or high molecular weight organic material. It is also possible to form the electrically insulating layer from an inorganic material or a low molecular weight or high molecular weight organic material.</p><p> Further, the first electrode, the second electrode, and the drain electrode can be formed of an inorganic material, a low-molecular-weight and high-molecular-weight organic material, and an additive that becomes an appropriate dopand. In addition, each electrode may be composed of the same material, or different materials, that is, one electrode is composed of an inorganic material, and the other material is an appropriate dopand with the above-mentioned low molecular weight and high molecular weight organic materials. It can also be composed of additives.</p><p> Further, the first electrode and the second electrode can be composed of a source electrode and a drain electrode, respectively.</p><p> Here, there are a method of forming the source electrode by a conventional CVD method and processing it by photolithography, and a method of forming it by a printing method such as an inkjet method. Here, it is preferable that a plurality of source electrodes are formed in parallel on the substrate.</p><p> Further, the semiconductor layer may use the CVD method and photolithography as in the source electrode, but the printing method is lower in cost. Here, since the thickness of the semiconductor layer corresponds to the channel length, accurate control is required particularly according to the target channel length. In order to increase the drain current value, it is better to reduce the film pressure, but if it is made too small, the source electrode and the drain electrode may come into contact with each other, so care must be taken. It is preferable that a plurality of semiconductor layers are laminated on one source electrode layer, that is, the semiconductor layer is provided for each pixel.</p><p> Further, the drain electrode can be formed by the same method as the source electrode. It is preferable that the drain electrode is provided for each semiconductor layer, that is, the drain electrode layer is provided for each pixel. Further, it is preferable that the drain electrode layer is electrically connected to the pixel electrode (transparent electrode) of each pixel.</p><p> Further, the gate insulating film can be formed by a combination of a CVD method and a photolithography method, but can also be formed by a printing method. Here, the gate insulating film is formed so as to surround the periphery of the three layers in which the source electrode, the semiconductor layer, and the drain electrode are laminated. The gate insulating film is provided for each pixel in the same manner as the semiconductor layer and the drain electrode layer, that is, the gate insulating film is provided so as not to electrically connect the gate electrode layer to other electrode layers. It is preferable to have.</p><p> Further, the gate electrode can also be formed by two methods, a method of forming by film formation by a CVD method and processing by photolithography, and a method of forming by a solution process such as a printing method. A dual side gate field effect transistor may also be made using a process that includes both a CVD and photolithography process and a solution process. It is preferable that a plurality of the gate electrodes are formed so as to intersect the source electrodes in a plan view at a position where the gate insulating film exists.</p><p> The transistor element described above has a vertical structure, and the channels formed in the semiconductor layer are in the vertical direction with respect to the substrate surface. Therefore, if a cyclic compound in which a π-electron cloud of an aromatic compound-based organic material is formed in the vertical direction is adopted as the semiconductor layer, the element structure is particularly effective for such a cyclic compound.</p><p> Further, in the method for manufacturing a field-effect transistor element according to the present invention, a first electrode, a semiconductor layer, and a second electrode are sequentially laminated on a substrate, and an electrically insulating layer is formed so as to surround the three layers. However, a gate electrode is formed on the upper surface of the electrically insulating layer. This makes it possible to manufacture a field effect transistor element having the above-mentioned advantages.</p><p> When the field effect transistor element is formed on the substrate of a display device such as a liquid crystal display device, a pinhole is formed in the gate electrode and the electrical insulating film, and the first electrode or the first electrode or the first electrode or the electric insulating film is formed through the pinhole. It is preferable to adopt a configuration in which the second electrode and the pixel electrode are electrically connected.</p><p> In the present invention as described above, since the vertical field-effect transistor in which the channel region is formed in the direction perpendicular to the substrate, the channel length is reduced by order as compared with the conventional horizontal element. Therefore, a sufficiently large drain current can be obtained even if a semiconductor material having low mobility is used. Further, in the dual side gate field effect transistor of the present invention, since two channel regions are formed in one layer of the semiconductor layer, a drain current can be obtained more effectively. Further, since the element structure is simple, the transistor can be manufactured with the conventional manufacturing technique and accuracy.</p>

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings. Note that FIG. 1 shows a schematic cross-sectional view of the element structure according to the embodiment of the present invention. FIG. 2 is a diagram illustrating a state in which a CVD method and a photolithography method are used with respect to the manufacturing process according to the embodiment of the present invention. FIG. 3 is a process diagram for manufacturing the manufacturing process according to the embodiment of the present invention by using a solution process such as an inkjet method or a microcontact printing method.

The transistor element of the embodiment of the present invention is a TFT element effectively utilized as a dual side gate transistor, and the TFT element is a source electrode 5 (first electrode) on a substrate as shown in FIG. ), The semiconductor layer 6 (semiconductor region), the drain electrode (second electrode), the gate insulating film, and the gate electrode 2 are sequentially laminated.

A plurality of the source electrodes 5 are formed in parallel on the substrate 1 at the same pitch, and the plurality of source electrodes 5 are arranged between each pixel region. Further, a plurality of the gate electrode layers 2 are formed in parallel at the same pitch so as to be orthogonal to the source electrode 5 in a plan view, and the plurality of gate electrode layers 2 are also arranged between the pixel regions. Has been done. The source electrode 5, the semiconductor layer 6, the drain electrode 4, and the gate insulating film 3 are located at locations where the gate electrode layer 2 and the source electrode 5 are orthogonal to each other in a plan view, and the gate electrode layer 2 and the source electrode are located. It is formed between 5 and 5.

In the TFT element of the present embodiment having the above configuration, a drain current Id flows in a direction orthogonal to the surface of the substrate 1, and a gate electrode provided around an active region (source electrode 5, semiconductor layer 6 and drain electrode 4). The structure is such that an electric field is applied to the semiconductor layer 6 from 2 via the gate insulating layer 3. Here, since the film thickness L of the semiconductor layer 6 laminated on the source electrode 5 can be reduced, the channel length L can be dramatically increased as compared with the conventional one that depends on the processing accuracy of photolithography. A shortened structure can be realized. As a result, the transistor performance, that is, the effective drain current value can be improved. Further, since the structure of the semiconductor element is simple, the manufacturing process can be simplified, and therefore the manufacturing cost of the semiconductor element can be reduced.

Further, in the TFT element of the present embodiment, the gate insulating layer 3 is formed around the active regions of the first electrode (source electrode 5), the semiconductor layer 6 and the second electrode (drain electrode 4), and the gate insulating layer is further formed. A third electrode (gate electrode 2) is provided around 3. That is, the channel regions of the semiconductor layer 6 exist at two locations on the left and right along the semiconductor layer stacking direction. In this way, since the channel regions of the semiconductor layer 6 are formed on both the left and right sides of the semiconductor layer 6, in addition to the effect of shortening the channel length L, the channel regions are also formed at two locations, so that the drain is more effective. An electric current can flow.

Further, by arranging the source electrode 5, the semiconductor layer 6 and the drain electrode 4 at the position where the source electrode 5 and the gate electrode 2 intersect in the plane position, the pixel electrode can be made large. Therefore, The aperture ratio of the display device can be improved.

As disclosed in Patent Document 1, the semiconductor device of the present invention is provided with a buffer layer between the first electrode 5 and the semiconductor layer 6 or between the semiconductor layer 6 and the second electrode 7. It is also a matter that the design can be changed as appropriate. By providing the buffer layer in this way, good electrical contact can be obtained between the first electrode 5, the semiconductor layer 6, and the second electrode 7. The buffer layer is made of a conductive polymer material that can be formed by a solution process such as a printing method or an inkjet method, and is a low molecular weight system often used for organic EL applications in addition to polythiophene and polyphenylene. The conductive material may be formed by a vacuum vapor deposition method. As described above, in the device in which the buffer layer is inserted, the carrier propagates beyond the slight potential difference barrier formed at the interface between the semiconductor layer and the buffer layer, which is particularly effective in reducing the off-current.

The semiconductor preferably includes an acene molecular material composed of naphthalene, anthracene, tetracene, pentacene, and derivatives thereof, a pigment composed of a phthalocyanine compound, an azo compound, a perylene compound and a derivative thereof, and a hydrazone compound. Low molecular weight compounds consisting of diphenylmethane compounds, triphenylmethane compounds, stillben compounds, arylvinyl compounds, pyrazoline compounds, triphenylamine compounds, phenylene derivatives and triarylamine compounds, their derivatives, poly-N-vinylcarbazole, polythiophene, It can be composed of an organic semiconductor material composed of a polymer compound such as polyphenylene, polyphenylene vinylene, polyalkylfluorene, polythionaphthene, polyaniline, polypyrrole and the like. In this way, by using an organic semiconductor material as the material constituting the semiconductor, when a polymer organic semiconductor material is adopted, the solution is formed by a printing method such as an inkjet method or a microcontact printing method. Can be done. Further, when a low molecular weight organic semiconductor material is adopted, the film can be formed by means such as a vacuum vapor deposition method, so that an extremely thin organic semiconductor layer can be formed at low cost.

Further, the semiconductor layer may be made of an inorganic semiconductor material such as silicon such as a-Si or p-Si, or a metal oxide such as zinc oxide or tin oxide. As described above, since the inorganic semiconductor material can be formed into a film by means such as a vacuum vapor deposition method, an extremely thin inorganic semiconductor layer can be manufactured.

Examples of the material of the gate insulating layer include polymers having a hydroxyl group such as polyvinyl alcohol, polyvinyl butyral, phenol resin and novolak resin, polymers having a cyano group such as polyacrylonitrile, and polychloropyrene polyethylene terephthalate and polyoxymethylene. Examples thereof include polymer materials such as polyvinyl chloride, polyfluorinated vinylidene, polymethylmethacrylate, polycarbonate, polyimide, polysulfone, and polyorganosiloxane. Also, not only polymers, but SiO₂, SiN, Al₂O₃, Etc. may be used. It is also possible to stack two or more films as the gate insulating film. Further, after depositing the film using a known film forming method depending on the material such as a vapor deposition method, a sputtering method, a coating method, a printing method or an inkjet method, a gate insulating film having a desired arrangement is formed by a photolithography step and an etching step. It is possible to do.

The first electrode (source electrode), second electrode (drain electrode) and gate electrode are Cr, Al, Ta, Mo, Nb, Cu, Ag, Au, Pt, Pd, In, Ni, Nd and alloys thereof. Inorganic materials such as polysilicon, amorphous silicon, tin oxide, indium oxide, indium tin oxide (ITO), and doped conductive polymers (eg, polyethylene dioxythiophene (PEDOT)). ) And sodium polystyrene sulfonate, etc.) and other organic materials. It is also possible to form the electrode from two or more layers. The electrodes are also formed in a desired arrangement by a photolithography step and an etching step after depositing a film using a known film forming method depending on the material such as a vapor deposition method, a sputtering method, a coating method, a printing method or an inkjet method. be able to.

To explain one embodiment of the method for manufacturing a transistor element of the present invention, first, an electrode film to be the first electrode 5, a semiconductor film to be the semiconductor layer 6, and an electrode film to be the second electrode 4 are vapor-deposited on the substrate 1. Laminate sequentially by law (see Fig. 2 (1)). Then, the first electrode 5, the semiconductor layer 6, and the second electrode 4 having desired shapes are obtained by etching treatment (see FIG. 2 (2)). Next, a gate insulating film 3 is formed around the first electrode 5, the semiconductor layer 6, and the second electrode 4 by, for example, a printing method (see FIG. 2 (3)). Then, the gate electrode 2 is formed on the upper surface of the gate insulating film 3 by, for example, vapor deposition, and then formed into a desired shape by a photolithography step and an etching step (see FIG. 2 (4)).

Further, to explain another embodiment of the method for manufacturing a transistor element of the present invention, first, a bank made of a resist is formed in a tubular shape on a substrate 1 (see FIG. 3 (1)). Then, the first electrode 5, the semiconductor layer 6, and the second electrode 4 are sequentially laminated in this tubular bank (see FIG. 3 (2)). Next, a gate insulating film 3 is formed on the upper surface of the second electrode 4 with the same material as the bank (see FIG. 3 (3)). Then, the gate electrode 2 is formed on the upper surface of the gate insulating film 3 (see FIG. 3 (4)).

(Example 1) Next, as a specific example of the present invention, the following dual side gate transistor will be described below with reference to FIGS. 7 and 8 together with the manufacturing procedure thereof.

First, in this embodiment, a Cr layer 5 is formed on the glass substrate 1 with a film thickness of 50 nm (see FIG. 7 (1)), and an Au layer is formed on the upper surface of the Cr layer 5 with a film thickness of 150 nm. Membrane.

Next, the photoresist is applied onto the Au film by spin coating, and then exposed and developed using a mask having a predetermined pattern. Subsequently, the Au layer and the Cr layer 5 are peeled off, and finally the resist is peeled off by immersing in a NaOH solution to form a source electrode 5 having a desired shape (see FIG. 7 (2)).

Then, banks were formed on all sides of the source electrode 5 (see FIG. 7 (3)). Here, a photoresist containing a volac resin is formed on the substrate 1 by a spin coating method, and the resist film is exposed and developed in a desired pattern to insulate the side of the source electrode 5 with a resist. It forms a layered bank 3. The thickness of bank 3 in the width direction is 200 nm.

Next, a polyhexylthiophene film is formed on the upper part of the source electrode 5 by an inkjet method to form a semiconductor layer 6. The thickness of the semiconductor layer 6 was set to 200 nm. The channel width was set to 20 μm. Further, a film made of PEDOT / PSS (polyethylene dioxythiophene / polystyrene sulfonate) is formed on the upper part of the semiconductor layer 6 by an inkjet method to form a drain electrode 4 (see FIG. 8 (1)).

Then, a photoresist containing a novolak resin is applied to the upper part of the drain electrode 4 by an inkjet method as an insulating layer for avoiding contact between the drain electrode 4 and the gate electrode 2 to form the gate insulating layer 3 (FIG. 8). See (2)).

A Ta film is formed as the gate electrode 2 around the gate insulating layer. The Ta film was formed by the CVD method and the dry etching method (see Fig. 8 (3)).

The characteristics of the dual side gate transistor manufactured by the above steps were evaluated. The source / drain voltage was varied from -20V to 0V and the gate voltage was varied from -20V to 0V. The drain current in this case was 150 μA. From here, the mobility obtained by using the above-mentioned equation (1) is 1 × 10.^-2cm²/ Vs. The on / off ratio is 10⁶It was at the same level as the conventional transistor using a-Si.

(Comparative Example 1) As a comparative example of Example 1, Comparative Example 1 relating to the manufacture of a so-called horizontal field effect transistor having a conventional structure shown in FIG. 6 is shown below. A substrate made of a Si wafer doped with phosphorus at a high concentration is thermally oxidized at 1100 degrees to form a thermal oxide film of 200 nm. Then, Au / Cr films were laminated as source / drain electrodes, and a pattern was formed on these films by photolithography and etching. The channel length was 5 μm and the channel width was 20 μm. Finally, a polyhexylthiophene solution was formed into a film by a spin coating method to prepare a horizontal field effect transistor.

The characteristics of the horizontal field effect transistor manufactured by the above steps were evaluated. The source / drain voltage was varied from -20V to 0V and the gate voltage was varied from -20V to 0V. The drain current in this case was 6 μA. The mobility obtained from this using the above equation (1) is 2 × 10.^-2cm²/ Vs. The on / off ratio is 10⁶It was at the same level as the conventional transistor using a-Si.

When the results of Example 1 and Comparative Example 1 were compared, the carrier mobilities showed different values even though the same polyhexylthiophene was used. Regarding this, in Example 1, PEDOT / PSS is used for the drain electrode, while in Comparative Example 1, Au / Cr is used for both the source / drain electrode, and Example 1 regarding the gate insulating film. This is because an organic polymer material is used, and in Comparative Example 1, a silicon thermal oxide film is used. Due to these factors, in Example 1, although the mobility is about half that of Comparative Example 1, the drain current value of Example 1 is 25 times that of Comparative Example 1. .. On the other hand, regarding the on / off ratio, no difference was observed between Example 1 and Comparative Example 1.

From these results, by using the dual side gate field effect transistor of Example 1, a sufficiently large drain current can be obtained even if a semiconductor material having a low mobility is used, and in particular, a polymer-based organic semiconductor can be obtained. It was confirmed that it is effective as an element.

(Example 2) Next, as a specific example of the present invention, the TFT element used in the following LCD panel will be described below with reference to FIGS. 9 and 10 together with the manufacturing procedure thereof.

First, in the second embodiment, the source electrode 5 is formed on the substrate 1 (see FIG. 9 (1)). The source electrode 5 is formed by forming Cr and Au into a film by a CVD method and then performing photolithography and dry etching. Here, a plurality of source electrodes 5 are formed.

Next, the semiconductor layer 6 is formed by forming a polythiophene film by an inkjet method (see FIG. 9 (2)). Here, a plurality of semiconductor layers 6 are formed on the source electrode 5.

Then, the drain electrode 4 is formed on the upper surface of the semiconductor layer 6 (see FIG. 9 (3)). Here, as with the source electrode 5, Au was formed by a CVD method and formed by photolithography and dry etching.

Next, the gate insulating film 3 is formed around the three laminated layers (see FIG. 9 (4)). Here, using polyvinylphenol, a film was formed by an inkjet method to form a gate insulating film 3 (see FIG. 8 (4)).

Then, the gate electrode 2 is formed so as to pass through the upper surface of the three layers (see FIG. 10 (1)). Here, Al was formed into a film by the CVD method to form the gate electrode 2.

Next, a passivation film is formed. Silicon nitride is deposited by the CVD method (see Fig. 10 (2)). At this time, by performing mask vapor deposition, a pinhole penetrating to the drain electrode 4 was formed on the drain electrode.

Then, an ITO film is formed as a pixel electrode on the upper surface of the passivation film (see FIG. 10 (3)). Here, the transparent electrode was formed by a film formation by a CVD method, and formed by photolithography and wet etching.

<figref num="1">Structure of Dual Side Gate Field Effect Transistor Element of the Present Invention</figref><figref num="2">A process diagram when the dual side gate field effect transistor element of the present invention is manufactured by the CVD method.</figref><figref num="3">A process diagram when the dual side gate field effect transistor element of the present invention is manufactured by a printing method.</figref><figref num="4">Element structure of horizontal field effect transistor when amorphous silicon is used for the semiconductor layer</figref><figref num="5">Element structure of general field effect transistor when organic semiconductor material is used for semiconductor layer</figref><figref num="6">Structure of vertical field effect transistor element</figref><figref num="7">Process diagram of manufacturing a dual side gate field effect transistor element described in Example 1 (cross-sectional view: right, top view: left)</figref><figref num="8">Process diagram of manufacturing a dual side gate field effect transistor element described in Example 1 (cross-sectional view: right, top view: left)</figref><figref num="9">Process diagram of manufacturing a TFT substrate for a liquid crystal display including a dual side gate field effect transistor described in Example 2 (cross-sectional view: right, top view: left)</figref><figref num="10">Process diagram of manufacturing a TFT substrate for a liquid crystal display including a dual side gate field effect transistor described in Example 2 (cross-sectional view: right, top view: left)</figref>

Code description

1, 11, 101, 111 ... Insulating substrate, glass substrate, transparent substrate 2, 12, 102, 112 ... Gate electrode 3, 13, 103, 113 ... Gate insulating layer 4, 14, 104, 114 ... drain electrodes 5, 15, 105, 115 ... source electrodes 6, 16, 106, 116 ... semiconductor layer