Non-volatile semiconductor storage device

The present invention relates to a non-volatile semiconductor storage device, and more particularly to a non-volatile semiconductor storage device suitable for speeding up an erasing operation and improving rewriting resistance.

EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used as a non-volatile semiconductor storage device that can be electrically written and erased. These storage devices (memory) represented by flash memory, which is widely used at present, have a conductive floating gate electrode surrounded by an oxide film and a trapping insulation under the gate electrode of a MOS (Metal Oxide Semiconductor) transistor. It has a film, and the charge accumulation state in the floating gate electrode or the trapping insulating film is used as stored information and read out as the threshold of the transistor. The trapping insulating film refers to an insulating film capable of accumulating electric charges, and an example thereof is a silicon nitride film. By injecting and discharging electric charge into such an electric charge storage region, the threshold value of the MOS transistor is shifted and operated as a storage element. As this flash memory, there is a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film, which will be described in detail later.

In such a memory, by using a silicon nitride film as the charge storage region, 1) the charge is discretely stored, so that the reliability of data retention is excellent as compared with the conductive floating gate film. In addition, 2) because of its excellent data retention reliability, the oxide films above and below the silicon nitride film can be thinned, and the writing / erasing operation can be reduced in voltage.

Further, by using the split gate type cell, 1) hot electrons can be injected into the silicon nitride film by the source side injection method, the electron injection efficiency is excellent, and high-speed and low-current writing is possible. It also has the advantages of 2) that the peripheral circuits can be made smaller because the write / erase operation is easy to control.

Two known memory erasing methods are a tunneling erasing method and a hot hole injection method (hole injection method). For example, Patent Document 1 (Japanese Patent Laid-Open No. 2001-102466) describes a memory cell using a tunneling erasing method, and Patent Document 2 (USP 5,969,383) and Patent Document 3 (USP6,248,633). (Japanese Patent Laid-Open No. 2003-46002), Patent Document 4 (Japanese Unexamined Patent Publication No. 2003-46002) describes a memory cell using the BTBT hot hole injection erasing method.

In the tunneling erasing method, the electrons injected into the silicon nitride film by writing are tunneled by applying an electric field to the oxide film above or below the silicon nitride film, and the electrons are pulled out to the gate electrode or the substrate for erasing. ..

In the other BTBT hot hole injection / elimination method, instead of extracting electrons, holes (holes) having a positive charge are injected to change the threshold value. For hole injection, BTBT, as described in the 2003 IE International Electron Devices Meeting Technical Digest, pp. 157-160 (IEEE International Electron Devices Meeting 2003, pp. 157-160). It is known that reholes are generated by a (Band-To-Band Tunneling) phenomenon and the electric field is accelerated to inject them into an insulating film (see Non-Patent Document 1).<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2001-102466</text></patcit><patcit num="2"><text>USP 5,969,383</text></patcit><patcit num="3"><text>USP 6,248,633</text></patcit><patcit num="4"><text>Japanese Unexamined Patent Publication No. 2003-46002</text></patcit><nplcit num="1"><text>2003 IE International Electron Devices Meeting Technical Digest pp. 157-160 (IEEE International Electron Devices Meeting 2003, pp. 157-160)</text></nplcit>

<p> Comparing the above-mentioned tunnel erasing method with the hole injection method (BTBT hot hole injection method), in the case of the tunneling erasing method, a trade-off relationship between the data retention characteristic and the erasing characteristic can be mentioned as a problem. That is, in order to improve the data retention characteristics, the silicon nitride film itself must be thickened in order to increase the number of oxide films and traps above and below the silicon nitride film that suppresses charge leakage. However, in the erasing operation, it is necessary to tunnel the charge through a thick oxide film, and as a result, the erasing speed becomes slow. Further, in order to improve the erasing speed, it is necessary to increase the erasing voltage, but this increase in the erasing voltage causes the peripheral circuit to become large-scale, which leads to an increase in chip cost. The oxide film on the side where electrons are extracted is limited to a thin film thickness within the range where electron tunneling occurs, and the data retention characteristics are restricted.</p><p> Furthermore, the threshold voltage after erasure cannot be lowered below the initial threshold voltage at which the silicon nitride film is electrically neutral in order to extract and erase the injected electrons during writing. .. If the threshold value cannot be lowered sufficiently, it will not be possible to obtain a large read current, which is disadvantageous in speeding up the read.</p><p> On the other hand, in the case of the hole injection elimination method (BTBT hot hole injection elimination method), the threshold value after elimination can be shifted to the negative side from the initial value. That is, since the positive charge is injected and accumulated in the insulating film by the erasing operation, the threshold value can be set to the negative side lower than the initial value. This makes it possible to allow a large amount of current to flow, which is suitable for high-speed operation of semiconductor circuits. Therefore, in recent years, the hole injection elimination method has attracted attention.</p><p> In the erasing operation by the hole injection erasing method (BTBT hot hole injection erasing method), in the memory cell based on the NMOS, a positive voltage is applied to the source diffusion layer and a negative voltage is applied to the gate electrode, and the end of the source diffusion layer is applied. The holes generated by BTBT can be accelerated by the electric field created by the high voltage applied to the source diffusion layer and the gate electrode, and injected into the silicon nitride film for elimination.</p><p> However, according to the study of the present inventor, when this hole injection elimination method (BTBT hot hole injection elimination method) is used, holes (holes) are injected locally, so that holes accumulate. I found out. Accumulation of this hole causes a problem that the erasing property is deteriorated and the charge holding property is deteriorated.</p><p> The deterioration of the erasing characteristics when the hole injection erasing method is used occurs as follows. By applying a negative potential to the memory gate (MG) and a positive potential to the source (MS), the hot hole during the erasing operation is the end of the source region MS (part b in FIG. 30) as shown in FIG. ), And is injected into the entire area of the nitride film (SIN) facing the silicon substrate. As a result, holes (holes) are accumulated in the nitride film (part c in FIG. 30) directly above the hole generation site (part b in FIG. 30) during the erasing process. Note that FIG. 29 is a cross-sectional view of a main part showing the location of hot electrons generated during writing in the non-volatile semiconductor storage device (flash memory), and schematically shows the state of electron injection into the charge storage portion during writing. FIG. 30 is a cross-sectional view of a main part showing the location of hot holes when erasing the non-volatile semiconductor storage device, and schematically shows the injection state of holes into the charge storage part at the time of erasing. There is. Since each part of the flash memory of FIGS. 29 and 30 has the same reference numerals as the parts corresponding to the embodiments of the present invention described later, the description thereof will be omitted.</p><p> By accumulating these holes, the vertical electric field applied to the insulating film-board interface at the end of the source diffusion layer (MS) is reduced, the amount of holes generated is reduced, and the erasing operation is stopped. Further, when the rewriting is repeated, the amount of holes accumulated in the nitride film above the hole generation site increases, and the generation of holes stops before the electrons injected by writing are completely erased. As a result, there arises a problem that repeated write / erase operations are restricted.</p><p> In addition, the accumulated holes deteriorate the charge retention characteristics. That is, in the writing state, the charged must be retained by the injected electrons. However, as described above, since hole injection by BTBT generates holes at the edge of the source diffusion layer, if holes are excessively accumulated immediately above the diffusion layer, the holes are locally accumulated even in the writing state. Therefore, the threshold change due to the recombination of holes and electrons is observed as deterioration of the retention characteristics.</p><p> An object of the present invention is to improve the performance and reliability of a non-volatile semiconductor storage device.</p><p> Further, an object of the present invention is to eliminate the deterioration of characteristics due to holes accumulated by the erasing operation.</p><p> The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.</p>

<p> A brief description of typical inventions disclosed in the present application is as follows.</p><p> In the present invention, carriers (electrons) having opposite polarities are injected into the carriers (holes) accumulated by the erasing operation to neutralize the charges.</p><p> Further, the non-volatile semiconductor storage device of the present invention comprises (a) the first and second semiconductor regions formed in the semiconductor substrate, and (b) the upper portion of the semiconductor substrate between the first and second semiconductor regions. The first conductor located on the first semiconductor region side and the second conductor located on the second semiconductor region side, and (c) formed between the first conductor and the semiconductor substrate. It has a first insulating film and (d) a second insulating film formed between the second conductor and the semiconductor substrate, and having a charge holding portion inside the second insulating film. In a non-volatile semiconductor storage device that performs (e) an operation of injecting electrons into the charge storage unit and (f) an operation of injecting holes into the charge holding unit, electrons are injected in accordance with the hole injection. By doing so, the charge neutralizing operation is performed.</p><p> Further, the non-volatile semiconductor storage device of the present invention comprises (a) the first and second semiconductor regions formed in the semiconductor substrate, and (b) the upper portion of the semiconductor substrate between the first and second semiconductor regions. A first conductor located on the first semiconductor region side and a second conductor located on the second semiconductor region side, and (c) formed between the first conductor and the semiconductor substrate. A second insulating film formed between the second conductor and the semiconductor substrate, and a second insulating film having a charge storage portion inside the first insulating film. (E) A potential of the first polarity, which is either positive or negative, is applied to the second semiconductor region, and a potential of the second polarity opposite to the first polarity is applied to the second conductor. By applying a potential having the same polarity as the first polarity to the first conductor, erasing is performed by injecting a first carrier having the same polarity as the first polarity into the charge storage portion. ..</p><p> Further, the non-volatile semiconductor storage device of the present invention comprises (a) the first and second semiconductor regions formed in the semiconductor substrate, and (b) the upper portion of the semiconductor substrate between the first and second semiconductor regions. The first conductor and the second conductor formed in the above, (c) the first insulating film formed between the first conductor and the semiconductor substrate, and (d) the second conductor and the above. It is a second insulating film formed between a semiconductor substrate and a second insulating film having a charge storage portion inside the second insulating film, and (e) a current flows between the first and second semiconductor regions. In the flowing state, carriers (holes) generated by the interband tunnel phenomenon are injected into the charge storage portion to eliminate them.</p><p> Further, the non-volatile semiconductor storage device of the present invention comprises (a) the first and second semiconductor regions formed in the semiconductor substrate, and (b) the upper portion of the semiconductor substrate between the first and second semiconductor regions. The first conductor and the second conductor formed in the above, (c) the first insulating film formed between the first conductor and the semiconductor substrate, and (d) the second conductor and the above. A plurality of memory cells having a second insulating film formed between the semiconductor substrate and the second insulating film having a charge storage portion therein are arranged in an array, and (e) the plurality of said ones. Among the memory cells, on the first conductor side of the first line connecting the first conductors of the memory cells arranged in the first direction and the memory cells arranged in the second direction orthogonal to the first direction. It has a plurality of second lines connecting the first semiconductor region located, and (f) is either positive or negative to the first line connected to the selected memory cell among the plurality of memory cells. With a potential of one polarity applied, erasing is performed by injecting a first carrier having the same polarity as the first polarity generated by the interband tunnel phenomenon into the charge storage portion of the selected memory cell. ..</p><p> Further, the non-volatile semiconductor storage device of the present invention comprises (a) the first and second semiconductor regions formed in the semiconductor substrate, and (b) the upper portion of the semiconductor substrate between the first and second semiconductor regions. The first conductor and the second conductor formed in the above, (c) the first insulating film formed between the first conductor and the semiconductor substrate, and (d) the second conductor and the above. A plurality of memory cells having a second insulating film formed between the semiconductor substrate and the second insulating film having a charge storage portion therein are arranged in an array, and (e) the plurality of said ones. Among the memory cells, on the second conductor side of the first line connecting the first conductors of the memory cells arranged in the first direction and the memory cells arranged in the second direction orthogonal to the first direction. It has a plurality of second lines connecting the second semiconductor region located and a third line connecting the first semiconductor region of the memory cells arranged in the first direction, and (f) the plurality of wires. A first line having the same polarity as the first polarity generated by the interband tunnel phenomenon while a positive or negative first polarity potential is applied to the first line connected to the selected memory cell among the memory cells. Erasing is performed by injecting one carrier into the charge storage portion of the selected memory cell.</p><p> Further, the non-volatile semiconductor storage device of the present invention comprises (a) the first and second semiconductor regions formed in the semiconductor substrate, and (b) the upper portion of the semiconductor substrate between the first and second semiconductor regions. A first conductor located on the first semiconductor region side and a second conductor located on the second semiconductor region side, and (c) formed between the first conductor and the semiconductor substrate. A second insulating film formed between the second conductor and the semiconductor substrate, and a second insulating film having a charge storage portion inside the first insulating film. During the writing operation, (e) the positive potential is applied to the second semiconductor, the positive potential is applied to the second semiconductor region, and the positive potential is applied to the first conductor to accumulate the charge. By injecting electrons into the part, (f) a positive potential is applied to the second semiconductor, 0 V or a positive potential lower than that of the second conductor is applied to the second semiconductor region, and the first conductivity is applied. By applying a potential equal to or lower than that of the first semiconductor region to the body, electrons are injected into the charge storage portion.</p><p> Further, the non-volatile semiconductor storage device of the present invention comprises (a) the first and second semiconductor regions formed in the semiconductor substrate, and (b) the upper portion of the semiconductor substrate between the first and second semiconductor regions. A first conductor located on the first semiconductor region side and a second conductor located on the second semiconductor region side, and (c) formed between the first conductor and the semiconductor substrate. A second insulating film formed between the second conductor and the semiconductor substrate, and a second insulating film having a charge storage portion inside the first insulating film. During the erasing operation, (e) a negative potential is applied to the second conductor, a positive potential is applied to the second semiconductor region, and a positive potential is applied to the first conductor to accumulate the charge. By injecting a hole into the portion, (f) a positive potential is applied to the second semiconductor, 0 V or a positive potential lower than that of the second conductor is applied to the second semiconductor region, and the first By applying a potential equal to or lower than that of the first semiconductor region to the conductor, electrons are injected into the charge storage portion.</p>

<p> Among the inventions disclosed in the present application, the effects obtained by typical ones will be briefly described as follows.</p><p> Good element characteristics can be obtained by injecting carriers (electrons) having opposite polarities into the carriers (holes) accumulated by the erasing operation to neutralize the charges.</p><p> In addition, the performance and reliability of the non-volatile semiconductor storage device can be improved. In particular, it is possible to speed up the erasing operation and improve the rewriting resistance. In addition, the reading speed and data retention characteristics can be improved.</p>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiment, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. Further, in the following embodiments, the description of the same or similar parts is not repeated in principle except when it is particularly necessary.

Further, since the present invention mainly uses a trapping insulating film (an insulating film capable of accumulating charges) in the charge storage portion, the following embodiments are based on an NMOS (n-channel MOS) transistor. The explanation will be given based on a memory cell using a trapping insulating film. Further, the polarities (polarity of applied voltage and carrier polarity at the time of writing / erasing / reading) in the following embodiments explain the operation in the case of a memory cell based on an NMOS (n-channel MOS) transistor. In principle, the same operation can be obtained by reversing all the polarities such as the applied potential and the conductive type of the carrier when using a MOSFET (p-channel type MOS) transistor as a basis. it can.

(1) The basic configuration of the non-volatile semiconductor storage device (flash memory) according to the present invention will be described.

FIG. 1 is a cross-sectional view of a main part of the non-volatile semiconductor storage device (flash memory) of the present embodiment.

This flash memory is a split gate type cell using a MONOS film.

As shown in FIG. 1, the memory cell consists of a silicon nitride film (nitride film) SIN (that is, a charge storage part) for accumulating charges, and oxide films (silicon oxide films) BOTOX and TOPOX located above and below it. It is located under the ONO film (ONO) made of laminated film, the memory gate electrode MG made of a conductor such as n-type polysilicon, the selective gate electrode SG made of a conductor such as n-type polysilicon, and the selective gate electrode SG. Gate insulating film SGOX, source region (source diffusion layer, n-type semiconductor region) MS consisting of n-type impurities (introduced semiconductor region (silicon region)) MS, n-type impurities (introduced semiconductor region (silicon region)) It has a drain region (drain diffusion layer, n-type semiconductor region) MD consisting of regions)). The source region MS and the drain region MD are formed in the p-type well region PWEL provided on the p-type silicon substrate (semiconductor substrate) PSUB.

Here, a MOS transistor (MISFET: Metal Insulator Semiconductor Field Effect Transistor) composed of a memory gate electrode MG is referred to as a memory transistor, and a MOS transistor (MISFET: Metal Insulator Semiconductor Field Effect Transistor) composed of a selective gate electrode SG is referred to as a selection transistor. ..

Next, the writing / erasing / reading operation will be described. Here, the injection of electrons into the silicon nitride film SIN is defined as "writing", and the injection of holes is defined as "erasing". Hereinafter, the erasing operation, the writing operation, and the reading operation according to the present embodiment will be described.

(1-1) First, the erasing method will be described. FIG. 2 shows the conditions for applying a voltage to each part of the selected memory cell at the time of writing, erasing, and reading of the present embodiment. Here, in order to give a typical operating voltage condition, a memory cell formed by using a so-called MOSFET 0.25 micron generation process and device technology will be described. That is, the selected transistor having a gate length of 0.2 μm and operating in a 1.5 V system was used. The channel width of the memory cell is 0.25 μm.

As shown in the upper part of the "erasure" column in Fig. 2, at the time of erasure, the voltage Vmg applied to the memory gate electrode MG is -5V, the voltage Vs applied to the source region MS is 7V, and the voltage Vd applied to the drain region MD. Is 0V, and the voltage Vsg applied to the selection gate electrode SG is controlled to be a set value that inverts the channel surface of the selection transistor. For example, when the threshold value (threshold voltage of the selection transistor) is 0.4V, the voltage Vsg of the selection gate electrode SG may be about 0.7V. 0V (V well) is applied to the well.

In this way, at the time of erasing (erasing operation), a positive potential (Vs&gt; 0) is applied to the source region MS, and the potential (positive potential) applied to the source region MS is applied to the memory gate electrode MG. Apply a negative potential (Vmg &lt;0), which is the potential of the opposite polarity, to the selection gate electrode SG, a potential that can invert the channel surface of the selection transistor, here the same potential applied to the source region MS. A positive potential (Vsg&gt; 0), which is a polar potential, is applied. Further, the potential of the drain region MD is lower than the potential of the selection gate electrode SG and the potential of the source region MS (Vd &lt;Vsg, Vd &lt;Vs).

In the erasing method of the present embodiment, holes (holes, carriers of positive polarity) generated in BTBT (Band-To-Band Tunneling) are injected into the silicon nitride film SIN to perform erasing. At the same time (that is, when the holes generated by BTBT are injected into the silicon nitride film SIN and erased), the source-drain (source region MS and drain region MD) is passed through the inversion layer of the selection transistor. Channel current flows between). When a high source potential is applied to the wells, the substrate-well depletion layer width w is w = (2ε) using the one-sided step joint approximation._Siε₀(V_SB+ φ_B) / (Q × N_well))^0.5It grows as expressed as. Where ε_SiAnd ε₀Are the relative permittivity of silicon and the permittivity of vacuum, V, respectively._SBIs source-well bias, φ_BIs the Fermi potential of the well, q is the amount of electron charge, N_wellIs the impurity concentration of the well. Therefore, if the memory gate length is shorter than the depletion layer width w, the depletion layer will grow inside the substrate even if holes are accumulated due to the charge injected into the memory gate and insulating film on the substrate surface. , Carriers inverted and held on the channel surface of the selected transistor can be drifted to the source side. This corresponds to the flow of current due to the short channel effect in the memory transistor section. The electrons (negatively polar carriers) that have entered the electric field region of the source diffusion layer (source region MS) are accelerated and injected into the silicon nitride film (SIN) above the source diffusion layer where holes are accumulated. Therefore, the accumulated holes can be eliminated, the electric field on the substrate surface can be maintained, and the hole generation by BTBT can be sustained. In addition, electrons accelerated by the electric field generate electron-hole pairs by impact ionization, and these secondary carriers are widely injected into the charge holding region, so that erasure can be accelerated. Of course, when looking at the injection as a whole, it is necessary to perform it in a state where the threshold value can be reduced by hole injection as compared with electron injection. For example, when the junction withstand voltage between the source diffusion layer and the well is BVbs, if Vs is brought close to 1V near BVbs at the time of erasing, excessive electron injection occurs, so that the threshold value rises despite the erasing operation. In the present embodiment, holes are referred to as positively polar carriers, and electrons are referred to as negatively polar carriers (carriers having the opposite polarity to holes). And.

In addition, holes generated by BTBT and impact ionization in this operation lower the junction barrier between the drain and well, causing bipolar operation with the drain, well, and source as the emitter, base, and collector, respectively, and consuming a large amount of current. It will be. To prevent this, it is effective to apply a bias in order to keep the joint barrier between the drain and the well high. The erasure settings for erasing in Fig. 2 are shown by applying drain and well (corresponding to the 3rd and 4th stages of the erasing column in Fig. 2, respectively).

Further, the drain application can be automatically limited by the circuit so that the current flowing through the selection transistor does not become too large. That is, it can be automatically controlled in a circuit so that the current value (channel current) flowing between the source region MS and the drain region MD becomes constant. For this automatic limitation, the same circuit as the circuit used when writing the constant channel current described in writing may be used.

When the above voltage (erasing voltage, erasing potential) is applied, as shown in FIG. 30, the voltage applied between the source region MS and the memory gate electrode MG causes BTBT (Band-To-Band) at the end of the source diffusion layer. Holes generated by Tunneling (inter-band tunneling phenomenon) are accelerated by the high voltage applied to the source region MS and the memory gate electrode MG (between) to become hot holes, and become a silicon nitride film SIN. Infused into. The injected holes are trapped in the trap in the silicon nitride film SIN, and the threshold voltage (threshold value, threshold value) of the memory transistor is lowered. The hot hole injection location is not only near the end of the selection gate electrode SG side in the silicon nitride film SIN into which electrons were injected during writing (part a in FIG. 29), but also the nitride film facing the silicon substrate (silicon nitride film). It is injected into the entire area in SIN), and holes are accumulated in the silicon nitride film SIN (part c in Fig. 30) above the hole generation site (near the end of the source region MS, part b in Fig. 30) due to BTBT. To go.

FIG. 31 shows a cross section of a main part of a memory cell of a non-volatile semiconductor storage device (flash memory) schematically showing the movement of electrons when an erasing potential (potential described in the erasing column of FIG. 2) is applied. FIG. 5 is a cross-sectional view corresponding to FIGS. 1, 29 and 30. The electrons flowing through the channel described above are accelerated by a high electric field generated in the channel direction at the end of the source region MS to which a high voltage is applied. Then, when holes are accumulated in the silicon nitride film SIN above the hole generation site (part b in FIG. 30) due to BTBT, these electrons are formed in the vertical direction by the accumulated holes as shown in FIG. It is attracted by the electric field and injected into the hole accumulation part (part c in FIGS. 30 and 31) in the silicon nitride film SIN. Since the electron injection position corresponds to the hole accumulation portion (the c portion in FIGS. 30 and 31) in the silicon nitride film SIN, it becomes the upper silicon nitride film SIN near the end of the source region MS.

That is, during the erasing operation, the holes generated by BTBT as shown in FIG. 30 are injected into the silicon nitride film SIN, and the hole storage portion of the electrons flowing through the channel as shown in FIG. 31 in the silicon nitride film SIN. The injection into will be done at the same time.

By injecting electrons into the hole accumulation portion in this way, the amount of hole accumulation can be reduced, and the decrease in the vertical electric field at the end of the source diffusion layer (source region MS) due to hole accumulation and the amount of hole generation due to BTBT can be reduced. The decrease can be suppressed.

FIG. 3 is a graph showing erasing characteristics. Figure 3 shows the case where the BTBT hot hole elimination method (corresponding to this embodiment) in which a current is passed through the channel is used (shown by a solid line in the graph of FIG. 3), and the BTBT in which no current is passed through the channel. When the hot hole elimination method (corresponding to the comparative example) is used (indicated by the broken line (dotted line) in the graph of Fig. 3), after rewriting once, after rewriting 1000 times, and after rewriting 100,000 times. Erasing characteristics are shown. The horizontal axis of the graph of FIG. 3 corresponds to the erasing time (the application time of the erasing voltage), and the vertical axis of the graph of FIG. 3 corresponds to the threshold voltage (threshold) Vth of the memory transistor.

As can be seen from FIG. 3, when an electric current is passed through the channel during the erasing operation to inject electrons into the hole accumulation portion of the silicon nitride film SIN as in the present embodiment, the decrease in the amount of holes generated by BTBT is suppressed. , The erasing speed is improved as compared with the BTBT hot hole erasing method of the comparative example (conventional) in which no current is passed through the channel during the erasing operation.

In addition, in the comparative example (conventional) BTBT hot hole erasing method in which no current flows through the channel when rewriting (writing and erasing) is repeated, the hole generation site (near the end of the source region MS, part b in FIG. 30). Since the amount of holes accumulated in the nitride film SIN (part c in FIGS. 30 and 31) in the upper part of the above is increasing, the erasing speed is slowed down. In addition, since the generation of holes stops before the electrons (electrons in part a in FIG. 29) injected into the silicon nitride film SIN during writing are completely erased, the threshold voltage that can be lowered by erasing is reduced. It rises (that is, the threshold voltage value after erasing rises as the number of rewrites increases), and the number of rewrites is limited.

On the other hand, as in the present embodiment, when a current (electrons) is passed through the channel during the erasing operation and electrons are injected into the hole accumulation portion (part c in FIGS. 30 and 31) in the silicon nitride film SIN, the hole is formed. Since the accumulated amount can be reduced each time the rewriting is performed, deterioration of the erasing speed due to the rewriting can be suppressed. In addition, there is almost no increase in the threshold voltage that can be lowered by erasing (that is, the threshold voltage value after erasing does not change so much even if the number of rewrites increases), and the number of rewrites can be increased. ..

As described above, if the gate length of the memory gate is shortened, current will flow through the channel even when a negative voltage is applied to the memory gate electrode MG, but the channel region under the memory gate electrode MG will be n-shaped. This also allows current to flow through the channel as well.

It is more preferable that the current flowing through the channel (current value flowing between the source region MS and the drain region MD) at the time of erasing is about 0.1 to 10 μA, which is the same as at the time of writing described later. The power supply circuit can be used effectively by setting the same amount of current as when writing.

Further, the current may not be passed through the channel at the initial stage of the erasing operation, and the current may be passed through the channel after the accumulated amount of the holes increases. That is, a positive potential (for example, 7V) is supplied to the source region MS and a negative potential (for example, -5V) is supplied to the memory gate electrode MG to start injection of holes into the silicon nitride film SIN (at this time, the selection gate electrode SG of the selection gate electrode SG). A positive potential (for example, 0.7V) that inverts the channel surface of the selection transistor on the selection gate electrode SG after a predetermined time has elapsed since the current was not passed through the channel by setting the potential Vsg to 0V. The supply may be started and a current (channel current) may be started to flow between the source region MS and the drain region MD. As a result, the current supply capacity of the power supply circuit can be effectively used by not passing an extra current. This is effective if the current (channel current) starts to flow between the source region MS and the drain region MD after 1 μsec. (1 microsecond) or more has passed since the injection of holes into the silicon nitride film SIN was started. It is even more effective if a current (channel current) is started to flow between the source region MS and the drain region MD after 10 μsec. (10 microseconds) or more has passed since the injection of holes into the silicon nitride film SIN was started. ..

Also in the memory cell according to the present embodiment, by repeating the erasing operation, holes are accumulated in the silicon nitride film SIN (part c in FIGS. 30 and 31) on the source diffusion layer (source region MS), and the charge is retained. The characteristics deteriorate. In order to suppress this deterioration, it is preferable to perform a hole neutralization operation (accumulated hole neutralization operation) in which electrons are tunnel-injected into the hole accumulation portion of the silicon nitride film SIN to neutralize the holes. In this hole neutralization operation, a positive potential is applied to the memory gate MG while keeping the source region MS at the ground potential, so that the hole accumulation portion of the silicon nitride film SIN directly above the source diffusion layer (source region MS) is provided. Electrons are tunnel-injected into (part c of Fig. 30 and Fig. 31). At this time, since the accumulated holes have a strong positive potential, a large electric field can be obtained at the effective interface that controls the tunnel current without applying a large potential to the memory gate electrode MG. The voltage application conditions during the hole neutralization operation are, for example, 10 V for the memory gate electrode MG, 0 V for the source region MS, 0 V for the selective gate electrode SG, and 0 V for the drain region MD.

FIG. 4 shows the charge retention characteristics of the memory cell depending on the presence or absence of the hole neutralization operation in the memory cell in which the writing / erasing operation is repeated using the above erasing method (BTBT hot hole erasing method in which a current is passed through the channel). It is a graph comparing. The graph in Fig. 4 shows the case where the write / erase operation was performed 10,000 times and then the operation for neutralizing the accumulated holes (shown by the solid line in the graph in Fig. 4) and the case where it was not performed (Fig. 4). In the graph of 4, the charge retention characteristics (indicated by the broken line (dotted line)) are shown. The horizontal axis of the graph of FIG. 4 corresponds to the charge holding time (elapsed time after writing), and the vertical axis of the graph of FIG. 4 corresponds to the threshold voltage (threshold) Vth of the memory transistor. As can be seen from FIG. 4, the change amount of the threshold value can be reduced by performing the hole neutralization operation. Although the description is given here using a single memory cell, this accumulated hole neutralization operation can be made more effective in the write and erase operations in the memory array, and the array operation is used for this operation. Will be described later based on.

The above erasing operation can be applied to the case of a memory cell based on an NMOS (n-channel MOS) transistor as described above (in this case, the source region MS and the drain region MD are formed by the n-type semiconductor region). It is more preferable to form a non-volatile semiconductor storage device by a memory cell based on an NMOS (n-channel MOS) transistor as in the present embodiment because a high-performance non-volatile semiconductor storage device can be formed. As another form, in the case of a memory cell based on a MOSFET (p-channel type MOS) transistor (in this case, the source region MS and the drain region MD are formed by the p-type semiconductor region), the application in the above erasing operation is performed. In principle, the same operation can be obtained by reversing all the polarities such as the electric potential and the conductive type of carriers (holes or electrons). That is, in the case of a memory cell based on a MIMO transistor, a negative potential (Vs &lt;0, for example, Vs = -7V) is applied to the source region MS during erasing (erasing operation), and the memory gate electrode MG A positive potential (Vmg&gt; 0, for example Vmg = 5V) is applied to the selection gate electrode SG, and a potential that can invert the channel surface of the selection transistor, here a negative potential (Vsg &lt;0, for example Vsg =-) is applied to the selection gate electrode SG. 0.7V) is applied, and a potential higher than that of the selective gate electrode SG or the source region MS (Vd&gt; Vsg, Vd&gt; Vs, for example, Vd = 0V) is applied to the drain region MD. As a result, the electrons generated in the BTBT are injected into the silicon nitride film SIN and erased, and at the same time, the channel is channeled between the source and drain (between the source region MS and the drain region MD) via the inversion layer of the selection transistor. A current (current formed by the movement of holes) flows, holes that enter the electric field region of the source diffusion layer (MS) are accelerated, and electrons are accumulated in the silicon nitride film (SIN) above the source diffusion layer. The electrons injected into and accumulated can be extinguished.

(1-2) Next, the writing method will be described. The writing method is hot electron writing, which is a so-called source side injection method.

As shown in the upper part of the "write" column in FIG. 2, the voltage Vs applied to the source region MS is 5 V, the voltage Vmg applied to the memory gate electrode MG is 10 V, and the voltage Vd applied to the drain region MD is 10 V at the time of writing. 0V, the voltage Vsg applied to the selection gate electrode SG is controlled so that the channel current at the time of writing becomes a certain set value. The Vsg at this time is determined by the set current value and the threshold value (threshold voltage, threshold value) of the selected transistor. For example, when the set current value is 1 μA, it is about 0.7 V. 0V (V well) is applied to the well.

Under the above voltage conditions, the channel current at the time of writing is set by the voltage Vsg applied to the selection gate electrode SG, but Vsg may be 1.5V and the channel current may be set by Vd. Vd at this time is also determined by the set value of the channel current and the threshold voltage of the selected transistor. For example, when the set current value is 1 μA, it is about 0.8 V (see the lower part of the write column in Fig. 2).

Under the above two conditions, a constant voltage is applied to perform writing, and the current flowing through the channel during writing is determined by the potential difference between the selection gate electrode SG and the drain region MD and the threshold voltage of the selection transistor. If the threshold voltage of the selected transistor varies, the channel current will vary, and the writing speed will vary accordingly. In order to suppress this variation in writing speed, Vd may be automatically controlled in a circuit so that the set channel current is obtained. Publicly known literature The circuit method described on pages 211 to 212 of the 2003 Proceedings of the Institute of Electrical and Electronics Engineers (IEEE) VLSI Circuits Symposium is used to write constant channel currents. Can be done.

The channel current at the time of writing shall be about 0.1 to 10 μA. The writing speed increases in proportion to the channel current, but as the channel current increases, the area of the power supply increases or the number of bits to be written at the same time decreases.

Hot electrons are generated in the channel region (between source and drain) below between the two gate electrodes (MG, SG) and locally hot electrons only on the selected transistor side in the silicon nitride film SIN under the memory gate electrode MG. Is injected (see part a in Figure 29). The injected electrons are trapped in the trap in the silicon nitride film SIN, and as a result, the threshold voltage (threshold, threshold) of the memory transistor rises. The electron distribution has a peak near the end on the SG side of the selective gate electrode in the silicon nitride film SIN.

(1-3) Next, the reading method will be described. There are two types of reading: reading in which the voltage between the source and drain is set in the opposite direction to that in writing, and reading in which the voltage is set in the same direction.

In the case of reverse reading, as shown in the upper part of the Read column in FIG. 2, the voltage Vd applied to the drain region MD is 1.5V, the voltage Vs applied to the source region MS is 0V, and the selection gate electrode SG is applied. Read out with the voltage Vsg set to 1.5V and the voltage Vmg applied to the memory gate electrode MG set to 1.5V.

In the case of reading in the same direction, as shown in the lower part of the Read column in FIG. 2, the voltage Vd applied to the drain region MD and the voltage Vs applied to the source region MS are exchanged to be 0V and 1.5V, respectively.

The voltage Vmg applied to the memory gate electrode MG at the time of reading is set between the threshold voltage of the memory transistor in the writing state and the threshold voltage of the memory transistor in the erasing state. When the threshold voltages in the write state and the erase state are set to 5V and -2V, respectively, the Vmg at the time of reading is an intermediate value between the two. By setting it to an intermediate value, even if the threshold voltage in the write state drops by 2 to 3 V or the threshold voltage in the erase state rises by 2 to 3 V during data retention, the write state and erase state can be discriminated. The margin of data retention characteristics can be widened. If the threshold voltage of the memory cell in the erased state is sufficiently low, Vmg at the time of reading may be set to 0V. By setting Vmg at the time of reading to 0V, it is possible to avoid reading disturb, that is, fluctuation of the threshold voltage due to voltage application to the memory gate.

(2) Next, the memory operation when an array is configured with a plurality of memory cells will be described.

FIG. 5 is a circuit diagram showing a non-volatile semiconductor memory array of the present embodiment. For simplicity, only 2x4 memory cells are shown.

As shown in the figure, the selection gate line (word line) SGL0 to SGL3 connecting the selection gate electrode SG of each memory cell, the memory gate line MGL0 to MGL3 connecting the memory gate electrode MG, and two adjacent memory cells share. The source lines SL0 and SL1 connecting the source area MS extend parallel to each other in the X direction.

Further, the bit lines BL0 and BL1 connecting the drain area MD of the memory cell extend in the Y direction, that is, in the direction orthogonal to the selection gate line SGL and the like.

It should be noted that these wirings extend in the above direction not only on the circuit diagram but also on the layout of each element and wiring (the same applies to FIGS. 9, 10 and 13). Further, the selection gate wire SGL or the like may be composed of the selection gate electrode SG, or may be composed of wiring connected to the selection gate SG.

Although omitted in FIG. 5, a boost driver consisting of a high-voltage MOS transistor is connected to the source line SL and the memory gate line MGL in order to apply a high voltage during writing / erasing. Also, since only a low voltage of about 1.5V is applied to the selected gate line SGL, a high-speed boost driver with low withstand voltage is connected. 16 memory cells, 32 or 64 memory cells are connected to one local bit line, the local bit line is connected to the global bit line via a MOS transistor that selects the local bit line, and the global bit line is Connected to a sense amplifier.

6 and 7 show the voltage conditions applied to each wiring during writing, erasing, and reading in the memory array of FIG. 6 and 7 show the conditions for setting the channel current at the time of writing / erasing with the potential of the selected gate line SGL and the potential of the bit line BL, respectively, and of the channel current shown in FIG. When setting is performed with the voltage Vsg of the selected gate electrode SG (first stage in the "erasure" column of Fig. 2) and when the setting is performed with the voltage Vd of the drain area MD (second stage of the "erasure" column of Fig. 2). Corresponds to.

(2-1) First, the array operation of writing under the voltage conditions shown in FIG. 6 will be described. In order to perform writing, it is a necessary condition that a current flows through the channel, that is, the selection transistor is in the ON state.

The write conditions shown in FIG. 6 are the conditions when the memory cell BIT1 shown in FIG. 5 is selected. The selected gate line boosts SGL0 from 0V to around 0.7V, the bit line steps only BL0 from 1.5V to 0V, 5V for the source line SL0 to which the selected cell is connected, and 10V for the memory gate line MGL0. Is applied. As a result, only in the memory cell BIT1 shown in FIG. 5, the potential of the selection gate line SGL becomes larger than the potential of the bit line BL, the selection transistor is turned on, and the writing condition shown in FIG. 2 is satisfied and writing is performed. ..

At this time, a potential of 0.7V is also applied to the selection gate electrode SG such as the other memory cell BIT2 connected to the selection gate line SGL0 to which the selection cell BIT1 is connected, but the potential is connected to the other memory cell. By applying a potential (0.7V) or higher (1.5V in FIG. 6) of the selection gate line SGL0 or higher to the bit line BL1 or the like, the selection transistor is turned off in the other memory cells, and writing is performed. I can't.

FIG. 6 shows the operating conditions when the channel current at the time of writing is set by the potential of the selected gate line SGL, but even when the potential of the bit line BL, that is, the drain region MD shown in FIG. 7 is set, the selected cell BIT1 If the selected gate lines SGL0 and bit line BL0 of are set to 1.5V and 0.8V, respectively, and the selected gate lines SGL1 to 3 and bit lines BL1 that are not connected to the selected cell BIT1 are set to 0V and 1.5V, respectively, only the selected cell BIT1 is used. The potential of the selected gate line SGL becomes larger than the potential of the bit line BL, and the same writing operation is possible.

(2-2) Next, the erasing operation under the voltage conditions shown in FIG. 6 will be described. In Fig. 6, when erasing the memory cell WORD1 connected to one word line (upper part of the "Erase" column in Fig. 6) and erasing all cells in Fig. 5 connected to multiple word lines. Two conditions are shown for the case (lower part of the "Erase" column in Fig. 6). In the former case, the time for erasing all cells becomes long, but the area of the power supply circuit can be reduced. In the latter case, on the contrary, the area of the power supply circuit becomes large, but the erasing time can be shortened.

When erasing the memory cell WORD1 connected to one word line of the former, the selection gate line SGL0 is boosted from 0V to around 0.7V with all bit lines BL in the state of 0V, and the source to which the selection cell is connected. Apply 7V to line SL0 and -5V to memory gate line MGL0. As a result, in the memory cell WORD1 shown in FIG. 5, the potential of the selected gate line SGL becomes larger than the potential of the bit line BL, the selected transistor is turned on, and the erasing condition shown in FIG. 2 is satisfied, and erasing is performed. Be struck. At this time, BTBT hot hole elimination is performed in the memory cell WORD2 that shares the source line (SL0) with the memory cell WORD1 so that no current flows through the channel. Next to the memory cell WORD1, the BTBT hot hole is erased with the current flowing through the channel for the memory cell WORD2.

When erasing all cells (memory cells) in Fig. 5 connected to the latter multiple word line, the bit line BL is all 0V and the selection gate line SGL to which the selection cell is connected is all around 0V to 0.7V. 7V and -5V should be applied to all the source line SL and memory gate line MGL to which the selected cell is connected.

The above are the operating conditions when the channel current at the time of erasing is set by the potential of the selected gate line SGL, but the selected cell is connected even when the potential of the bit line BL, that is, the drain region MD shown in FIG. 7 is set. If the selected gate line SGL is 1.5V, the selected gate lines SGL1 to 3 to which the selected cell is not connected are set to 0V, and all the bit lines BL are set to 0.8V, the potential of the selected gate line SGL is set only in the selected cell BIT1. Is larger than the potential of the bit line BL, and the erasing operation in which the channel current is passed is possible.

(2-3) Next, the read conditions of the memory array will be described. In the case of reading as well, it is a necessary condition that the selection transistor is in the ON state as in the case of writing / erasing, and the reading cell is selected by the selection gate line SGL and the bit line BL.

In the case of reading, the voltage between the source and drain may be in the opposite direction to that in writing / erasing, or in the same direction.

In the former case, the potentials of the selected gate line SGL0 and the bit line BL0 connected to the selected cell BIT1 are 1.5 V, the potentials of the selected gate lines SGL1 to 3 and the bit line BL1 not connected to the selected cell are 0 V, and the source line. The potentials of SL0 and SL1 are all set to 0V.

In the latter case, the potentials of the selected gate line SGL0 and the bit line BL0 connected to the selected cell BIT1 are 1.5 V and 0V, respectively, and the potentials of the selected gate lines SGL1 to 3 and the bit line BL1 not connected to the selected cell. Are 0V and 1.5V, respectively, and the potentials of the source lines SL0 and SL1 are all 1.5V.

The potential of the memory gate line MGL should be 1.5 V applied only to the line MGL0 to which the selected cell is connected in order to obtain a larger read current. Under the read voltage conditions shown in FIGS. 6 and 7, the memory cell BIT1 of FIG. 5 is read in both the reverse direction and the same direction.

(2-4) Next, a method of carrying out the hole neutralization operation by tunnel electron injection described above in the memory array will be described. The hole neutralization operation by tunnel electron injection can be performed during the writing operation or the erasing operation.

FIG. 8 shows an example of the voltage application timing at which the hole neutralization operation is performed by tunnel electron injection during the writing operation. In section 1, the memory cells BIT1 and BIT3 satisfy the write voltage conditions shown in FIG. 6 and are written (injecting electrons into the silicon nitride film SIN on the source side). On the other hand, in the memory cells BIT4 and BIT5 in which writing is not performed, a high electric field is applied between the memory gate and the source by lowering the potential of the source to 0V, and a hole neutralization operation is performed by tunnel electron injection. In section 1, in memory cells BIT1 and BIT3, the potential of the source line SL0 is higher than that of the source line SL1 of memory cells BIT4 and BIT5, so the electric field between the memory gate and the source is lowered by that amount, and the memory cell. Tunnel injection like BIT4 and BIT5 is not performed (only source side injection is performed). Similarly, in section 2, the memory cells BIT4 and BIT5 satisfy the write voltage conditions shown in FIG. 6 and are written (source-side injection). On the other hand, in the memory cells BIT1 and BIT3 in which writing is not performed, a high electric field is applied between the memory gate and the source by lowering the potential of the source to 0V, and a hole neutralization operation is performed by tunnel electron injection. In section 2, in the memory cells BIT4 and BIT5, the potential of the source line SL1 is higher than that of the source line SL0 of the memory cells BIT1 and BIT3, so that the electric field between the memory gate and the source is lowered by that amount, and the memory cell. Tunnel injection like BIT1 and BIT3 is not performed (only source side injection is performed). By performing the hole neutralization operation by the above tunnel electron injection, the charge retention characteristics can be improved as shown in FIG. That is, good charge retention characteristics can be obtained by performing the writing operation in two stages: an electron injection operation for source side injection (when writing is selected) and a hole neutralization operation for tunnel injection (when writing is not selected). Can be done.

The applied voltage condition during hole neutralization operation is lower than 0V or memory gate wire (memory gate electrode MG) at the source wire (source region MS) by applying a positive potential to the memory gate wire (memory gate electrode MG). A positive potential may be applied. Further, a potential equal to or lower than that of the bit wire (drain region MD) may be applied to the selective gate wire (selective gate electrode SG). In the example shown in FIG. 8, the memory gate electrode MG is 10V, the source region MS is 0V, the selection gate electrode SG is 0V, and the drain region MD is 0V.

The hole neutralization operation by tunnel electron injection during the writing operation has been described above, but this hole neutralization operation can also be performed during the erasing operation. In the hole neutralization operation during the erasing operation, a positive potential is applied to the memory gate line (memory gate electrode MG) in the non-selected memory cell for erasing, and 0V is applied to the source line (source region MS), as in the writing operation. Alternatively, a positive potential lower than that of the memory gate wire (memory gate electrode MG) may be applied. Further, a potential equal to or lower than that of the bit wire (drain region MD) may be applied to the selective gate wire (selective gate electrode SG).

(2-5) In (2-1) and (2-2) above, the write / erase operation in which a constant voltage is applied was explained, but the channel current at the time of write / erase is controlled in a circuit so as to be constant. The method of writing / erasing will be described. FIG. 9 shows an example of a circuit configuration that realizes the writing / erasing operation of this constant channel current. A mirror circuit composed of a MOSFET transistor is provided at one end of bit lines BL0 and BL1, and a mirror circuit composed of an NMOS is provided at the other end.

Here, the erasing operation performed by passing a constant channel current through the memory cell represented by WORD1 will be described.

First, the voltage shown in FIG. 7 is applied except for the bit lines BL0 and BL1, and the current I1 is passed through the constant current source CCS1 and the current I2 larger than the current I1 is passed through the constant current source CCS2. Here, when the bit line selection switching transistors BS0 and BS1 of all the bit lines BL0 and BL1 to which the selection cell WORD1 is connected are turned on, the NMOS transistors MN0 and MN1 are connected from the bit line to the ground by the principle of the mirror circuit. The current I2 flows in the direction, and the current I1 flows in the direction of entering the bit line in the MOSFETs MP0 and MP1. The current of the difference between I2 and I1 is supplied to the bit line only through the memory cell WORD1 in which the selection transistor is on among the memory cells connected to the bit line. That is, the current Ip (= I2-I1) flows through the channel of the selected cell BIT1. In this way, by setting the difference between I2 and I1 to the channel current value at the time of erasing and inverting the switching transistor for bit line selection, the current can be passed through the channel for erasing.

In the writing operation as well, the erasing can be performed by passing a current through the channel as in the erasing operation. For writing, the writing cell can be selected depending on whether or not a channel current is passed, so only the bit line selection switching transistor of the bit line to which the memory cell to be written is connected needs to be turned on. By doing so, for the bit wire to which the selected cell is not connected, the potential of the bit wire rises to 1.5 V above the potential of the selected transistor (1.5 V for SG0, 0 V for SG1 to SG3) via the MOSFET transistor. The selection transistors of all memory cells connected to BL1 are turned off, and writing of non-selection cells can be prohibited. If the potential of BL1 drops from 1.5V due to a bit wire junction leak or the like, the selection transistor of the memory cell indicated by BIT2 is turned on, a current flows through the channel, and weak writing is performed. This weak writing can be prevented by supplying a current through the MOSFET transistor MP1 in the mirror circuit.

When erasing memory cells connected to multiple word lines (for example, n × m memory cells) at the same time, the bit line selection switching transistors of all the bit lines to which the selected cells are connected are turned on, and a constant current source is used. Make the difference between the current I2 of CCS2 and the current I1 of the constant current source CCS1 equal to the product of the channel current Ip at the time of erasing and several m of memory cells connected to the bit line, that is, I2-I1 = Ip × m. And. By doing so, a channel current of Ip can be passed through each cell to be erased.

(3) Next, another memory array configuration will be described. FIG. 10 is a circuit diagram showing another non-volatile semiconductor memory array of the present embodiment.

For the memory array configuration shown in Fig. 5, multiple source lines are connected to form a common source line SL. In addition, a plurality of memory gate lines are connected to form a common memory gate line MGL.

By sharing the source line SL and the memory gate line MGL, the number of high-voltage drivers that drive each line can be reduced, and the chip area can be reduced. The wiring that constitutes the memory array may be standardized to either the source line SL or the memory gate line MGL.

11 and 12 show the voltage conditions applied to each wiring during writing, erasing, and reading in the memory array of FIG. 11 and 12 show the conditions for setting the channel current at the time of writing / erasing with the potential of the selected gate line SGL and the potential of the bit line BL, respectively.

The voltage applied to the bit line BL and the selected gate line SGL is exactly the same as in the case of the memory array shown in FIG. 5, and the common source line SL and the memory gate line MGL are applied to the selected cell BIT1 in the memory array of FIG. Apply the same voltage as the applied voltage.

That is, when writing, the source line SL and memory gate line MGL are 5V and 10V, respectively, when erasing, 7V and -5V, respectively, when reading, 0V and 1.5V, respectively, when reading in the reverse direction, and when reading in the same direction, respectively. Apply 1.5V and 1.5V.

(4) Next, another memory array configuration will be further described. FIG. 13 is a circuit diagram showing another non-volatile semiconductor memory array of the present embodiment.

Compared with the memory array configuration shown in FIG. 5, in the case of FIG. 13, the positions of the memory transistor and the selection transistor are exchanged, and the bit line BL is selected in the diffusion layer (drain area) on the memory transistor side. The source line SL is connected to the diffusion layer (source region) on the transistor side.

14 and 15 show the voltage conditions applied to each wiring during writing, erasing, and reading in the memory array of FIG. 14 and 15 show the conditions for setting the channel current at the time of writing / erasing with the potential of the selected gate line SGL and the potential of the bit line BL, respectively.

When the voltage applied to the source line SL in the memory array shown in FIG. 5 is applied to the bit line BL and the voltage applied to the bit line BL is applied to the source line SL, the same write / erase / read operations as those in the memory array of FIG. 5 are performed. To do.

That is, under the writing conditions shown in FIG. 14, the selection gate line boosts only SGL0 from 0V to around 0.7V, and the source line steps down only SL0 from 1.5V to 0V, and the bit line to which the selection cell is connected. 5V is applied to BL0, and 10V is applied to the memory gate line MGL0 at the time of writing. As a result, writing is performed in the memory cell BIT1 shown in FIG.

Under the erasing conditions shown in Fig. 14, when erasing the memory cell WORD1 connected to one word line, the bit line BL and the source line SL are all 0V, and the selected gate line SGL0 is changed from 0V to around 0.7V. Boost the voltage and apply 7V to the bit line BL0 to which the selected cell is connected and -5V to the memory gate line MGL0. As a result, in the memory cell WORD1 shown in FIG. 13, the potential of the selected gate line SGL becomes larger than the potential of the source line SL, the selected transistor is turned on, and the erasing condition shown in FIG. 2 is satisfied, and erasing is performed. Be struck. When erasing all cells in Fig. 13 connected to multiple word lines, the source line SL is all 0V and the selection gate line SGL to which the selection cells are connected is boosted from 0V to around 0.7V and selected. 7V and -5V should be applied to all the bit line BL and the memory gate line MGL to which the cell is connected, respectively.

Regarding the read conditions shown in FIGS. 14 and 15, in this memory array, the positions of the memory transistor and the selected transistor are exchanged with those of the memory array shown in FIG. 5, so that reverse read in the case of FIG. 5 is performed. The applied voltage conditions are opposite to those in the case of "reading in the same direction".

As described above, the voltage conditions for memory operation have been shown in FIGS. 2, 6, 7, 11, 15, 12, and 15, but these conditions are examples, and the numerical values shown here are used in the present invention. Is not limited. Further, also in the memory cell array shown in FIGS. 10 and 13, the circuit method shown in FIG. 9 may be applied to write / erase the constant channel current.

(5) Next, the specific configuration of the memory cell, which realizes the above-mentioned method of erasing and enables high-speed erasing / reading and improvement of rewriting / high-temperature data retention reliability, is described below using FIG. explain.

To perform the above erasure, a current must flow between the source and drain when a negative voltage is applied to the memory gate electrode MG.

For this purpose, it is necessary to shorten the channel length of the memory transistor or to make the channel region (ME) of the memory transistor n-type.

Both of these contribute to an increase in read current, so a memory cell that employs the erasing method of the present invention is suitable for high-speed read.

In addition, the erasing method of the present invention utilizes hole injection, and the threshold voltage after erasing can be lowered below the neutral threshold voltage to obtain a large read current. Therefore, in that respect as well, it is suitable for high-speed reading.

Moreover, the erasing speed is higher than that of tunneling erasing because hot carrier injection is used. Further, by shortening the channel length of the memory transistor or increasing the concentration of n-type impurities in the channel region (ME) of the memory transistor, the read current is increased and the speed is further increased.

For the channel region SE of one of the selected transistors, the impurity concentration is set so that the threshold voltage of the selected transistor becomes larger than the neutral state threshold voltage of the memory transistor. The neutral state threshold voltage of the memory transistor means the threshold value in the state where no charge is accumulated in the charge storage region.

If the threshold voltage of the selected transistor is too high, a large read current cannot be taken, and if it is too low, it will not be completely turned off even when the gate voltage is 0 V, and the leak current will hinder normal read operation. It ends up. Therefore, it is desirable that the threshold voltage of the selected transistor be low in the positive range.

Next, the impurity profiles of the drain region MD and the source region MS will be described.

First, regarding the drain area MD, the maximum voltage applied to this area during memory operation is about 1.8V, so adopt a MOS transistor source and drain structure that is premised on driving at 1.8V. Just do it. For example, the drain region MD may be configured in a high-concentration n-type impurity region similar to that of a MOS transistor operating at 1.8 V. Further, a low-concentration n-type impurity region MDM may be provided at the end of the drain region MD in the gate electrode direction to form an LDD structure.

The other source region MS is also a high-concentration n-type impurity region. Further, an n-type impurity region (low-concentration n-type impurity region) MSM may be provided at the end of the high-concentration n-type impurity region (source region) MS in the gate electrode direction. The impurity concentration of this n-type impurity region MSM needs to be a concentration suitable for causing BTBT. For example, the impurity concentration of the n-type impurity region MSM is 10.¹⁸~10²⁰/cm³More preferable if it is about 10¹⁸~10¹⁹/cm³The degree is more preferable. Further, the impurity concentration of the n-type impurity region MSM is preferably lower than the impurity concentration of the high-concentration n-type impurity region MS.

The film thickness of the silicon nitride film SIN under the memory gate electrode MG and the oxide films TOPOX and BOTOX above and below it are important factors for determining the memory characteristics.

In the memory cell adopting the erasing method of the present invention, since hot carrier injection is used for both writing and erasing, the oxide films above and below the silicon nitride film can be thickened. The film thickness is about 3 to 15 nm for the silicon nitride film SIN, and about 3 to 10 nm for the oxide films TOPOX and BOTOX above and below the silicon nitride film. By setting the film thickness of the oxide films TOPOX and BOTOX to 3 nm or more, it is possible to suppress the change in accumulated charge due to the tunneling phenomenon.

By thickening the oxide films above and below the silicon nitride film in this way, the retention characteristics at high temperatures are improved, and deterioration of the retention characteristics after rewriting is also suppressed.

(6) Subsequently, an example of a method for manufacturing the non-volatile semiconductor storage device (memory cell) shown in FIG. 16 will be described below with reference to FIGS. 17 to 24. 17 to 24 are cross-sectional views of a main part of a substrate showing a method of manufacturing the non-volatile semiconductor storage device of the present embodiment. Each figure shows a cross section of two memory cell areas that share a source area.

First, FIG. 17 will be described. The device separation oxide film region STI is formed on the p-type silicon substrate PSUB, and the p-type well region PWEL, which is the memory cell region, is formed.

A p-type impurity region (channel region) SE that adjusts the threshold value of the selection transistor is formed on the surface of the p-type well region PWEL. Next, after cleaning the surface of the silicon substrate, the gate insulating film SGOX of the selection transistor is formed by thermal oxidation, and the n-type polysilicon layer NSG (about 100 nm) serving as the selection gate electrode and the selection gate electrode are formed on the gate insulating film SGOX. Protective silicon oxide film CAPs are sequentially deposited.

Next, FIG. 18 will be described. Using photolithography technology and dry etching technology, the n-type polysilicon layer NSG formed on the silicon substrate in FIG. 17 is processed to form the selection gate electrodes SG1 and SG2 of the selection transistor. These gate electrodes extend in the depth direction of the drawing and have a linear pattern. This pattern corresponds to the selected gate line SGL of the memory array (see Fig. 5 etc.). When forming this pattern, dry etching is stopped when the surface of the thermal oxide film (SGOX) is exposed so that the surface of the silicon substrate is not damaged unnecessarily. Next, an n-type impurity region ME for adjusting the threshold is formed in the channel region of the memory transistor on the surface of the silicon substrate. For example, the impurity concentration of the n-type impurity region ME is 1 × 10.¹²/cm²Degree.

Next, FIG. 19 will be described. In FIG. 18, the thermal oxide film (SGOX) left for protection of the surface of the silicon substrate is removed with hydrofluoric acid, and an ONO (Oxide-Nitride-Oxide) film serving as a gate insulating film of the memory transistor is laminated. When removing the thermal oxide film (SGOX), the silicon oxide film CAP on the selective gate electrode SG may also be removed.

To form an ONO film, for example, the lower oxide film BOTOX (about 3 to 10 nm) is formed by thermal oxidation, the silicon nitride film SIN is deposited by the vapor phase growth method, and the upper oxide film TOPOX is vapor-deposited. Formed by method and thermal oxidation. Here, it is desirable that the film thicknesses of the lower oxide film BOTOX and the upper oxide film TOPOX are 3 nm or more in which the tunneling phenomenon is unlikely to occur.

Subsequently, an n-type polysilicon layer NMG (about 100 nm) to be a memory gate electrode MG is deposited on the ONO film.

Next, FIG. 20 will be described. The n-type polysilicon layer NMG deposited in FIG. 19 is removed by anisotropic etching technology until the upper oxide film TOPOX is exposed, and the side walls of the selective gate electrodes SG1 and SG2 are connected to the memory gate electrode MG1 via the ONO film. Form MG2. The spacer width of the memory gate electrodes MG1 and MG2 is preferably 40 to 90 nm. At this time, a polysilicon side wall spacer MGR is also formed on the side walls of the selective gate electrodes SG1 and SG2 on the opposite sides of the memory gate electrodes MG1 and MG2.

Next, in order to remove the side wall spacer MGR, the memory gate electrodes MG1 and MG2 are covered with a photoresist film RES1 using a photolithography technique. At this time, the photoresist film RES1 is formed so that the end portion thereof is on the selection gate electrodes SG1 and SG2.

Next, FIG. 21 will be described. The polysilicon side wall spacer MGR made in FIG. 20 is removed by dry etching technology, and the photoresist film RES1 is further removed. Subsequently, the exposed upper oxide film TOPOX and silicon nitride film SIN are removed with hydrofluoric acid and thermal phosphoric acid, respectively. After that, ion injection of low-concentration n-type impurities is performed to form a low-concentration n-type impurity region MDM in the drain portion. At the time of this ion implantation, a low-concentration n-type impurity region MSM is also formed in the source portion. The low-concentration n-type impurity region MDM and MSM in the drain portion and the source portion may be formed separately by using a photolithography technique and a resist film.

The polysilicon side wall spacer MGR is removed in FIG. 21 in order to form a low-concentration n-type impurity region MDM in the drain portion. For example, in FIG. 18, if the n-type impurity region ME is formed, then the upper part of the source portion is covered with a photoresist by using photolithography technology, and the low-concentration n-type impurity region MDM is formed in the drain portion, poly. It is not necessary to remove the silicon side wall spacer MGR.

Next, FIG. 22 will be described. After removing the exposed part of the lower oxide film BOTOX of the ONO film with hydrofluoric acid, the oxide film is deposited and etched using the anisotropic etching technique to form the side walls of the selective gate electrodes SG1 and SG2. A side wall spacer SW is formed on the side walls of the memory gate electrodes MG1 and MG2.

Next, FIG. 23 will be described. The drain region MD of the selected transistor and the source region MS of the memory transistor are formed by ion-implanting n-type impurities.

Next, FIG. 24 will be described. The wiring interlayer insulating film INS1 is deposited on the entire surface of the silicon substrate. Using photolithography technology and dry etching technology, a contact hole is opened on the drain region MD, and a metal layer (plug) CONT is deposited (formed) in the opening (contact hole). After that, the first layer wiring M1 is formed by using the photolithography technique and the etching technique.

As shown in the figure, the memory gate electrode MG and the selection gate electrode SG extend in a direction perpendicular to the paper surface, are connected to the drain region MD, and the first layer wiring M1 which becomes the bit line BL is the memory gate electrode MG. And the selection gate electrode Extends in the direction orthogonal to the electrode SG (see Fig. 5 etc.). In the case of the circuit diagram shown in FIG. 13, the positions of the memory gate electrode MG and the selection gate electrode SG are interchanged.

Next, the wiring interlayer insulating film INS2 is deposited. Hereinafter, although not shown, a contact hole is formed in the wiring interlayer insulating film INS2, and a conductive film is further deposited and patterned to form the wiring. By repeating the steps of forming the wiring interlayer insulating film and the wiring in this way, it is possible to form a multi-layered wiring.

(7) Subsequently, examples of other memory cell structures that realize the erasing method of the present invention will be shown with reference to FIGS. 25 to 27. 25 to 27 are cross-sectional views of a main part of another non-volatile semiconductor storage device (flash memory) of the present embodiment.

FIG. 25 is a memory cell in which the selection gate electrode SG is formed in the shape of a side wall spacer of the memory gate electrode MG.

In the case of such a memory cell, the ONO film (BOPOX, SIN and TOPOX) of the memory transistor and the memory gate electrode MG are first formed, and the side wall spacer GAPSW made of an insulating film is formed on the side wall thereof. Further, a selective gate electrode SG is formed on the side wall thereof by using an anisotropic etching technique in the same manner as the memory gate of the memory cell described with reference to FIG. 1 and the like.

By forming the side wall spacer GAPSW with an oxide film thicker than the gate insulating film SGOX of the selection transistor, the withstand voltage between the memory gate electrode MG and the selection gate electrode SG can be improved.

Further, the injection of impurities in the channel region (n-type impurity region ME) of the memory transistor and the channel region SE of the selection transistor is performed before and after the formation of the memory gate electrode MG, respectively.

FIG. 26 shows a memory cell having a configuration in which the memory gate electrode MG is mounted on the selective gate electrode SG.

In the case of such a memory cell, as in the case of the memory cell described with reference to FIG. 1 and the like, the selection gate electrode SG is formed first, and the ONO film and the memory gate electrode MG are formed by using photolithography technology. To form. The injection of impurities in the channel region (n-type impurity region ME) of the memory transistor and the channel region SE of the selection transistor is performed in the same manner as described with reference to FIG.

FIG. 27 shows a memory cell having a configuration in which the selection gate electrode SG is mounted on the memory gate electrode MG.

In the case of such a memory cell, it can be formed in the same manner as the memory cell shown in FIG. 25 except that the selective gate electrode SG is formed by the photolithography technique. That is, the ONO film and the memory gate electrode MG are formed first, and then the selection gate electrode SG is formed. Impurities in the channel region (n-type impurity region ME) of the memory transistor and the channel region SE of the selected transistor are injected before and after the formation of the memory gate electrode MG, respectively.

In this way, the memory cell structures shown in FIGS. 25 to 27 can be operated in the same manner as the memory cells shown in FIG. 1 under the memory array and voltage conditions shown in FIGS. 5 to 15. Is.

Further, as described with reference to FIG. 16, the specific configuration of the memory cell that enables high-speed erasing / reading and improvement of reliability of high-temperature data retention is similarly described for the memory cells shown in FIGS. 25 to 27. Applicable.

(8) In a microprocessor chip, it is conceivable to integrate a plurality of non-volatile memory modules not only for increasing the degree of memory integration but also for various purposes. FIG. 28 is an explanatory diagram (block diagram) schematically showing a semiconductor chip MPU formed by integrating a plurality of non-volatile memory modules MMJ1 to MMJ4 and the like. In the semiconductor chip MPU of FIG. 28, a plurality of non-volatile memory modules MMJ1 to MMJ4 (MMJ1, MMJ2, MMJ3, MMJ4), a memory control module CMJ for controlling the non-volatile memory modules MMJ1 to MMJ4, and a non-volatile memory module The power supply module PMJ for supplying a predetermined potential to MMJ1 to MMJ4 and the arithmetic circuit section OPC are integrated. In this way, when a plurality of non-volatile memory modules MMJ1 to MMJ4 are integrated in one semiconductor chip MPU, it is conceivable that the usage of the memory cells of each module (MMJ1 to MMJ4) is different. In the present embodiment, the operating characteristics of the non-volatile memory module can be changed without changing the structure of the memory cell. Therefore, among the plurality of non-volatile memory modules MMJ1 to MMJ4 integrated in one semiconductor chip MPU, The method of the above embodiment (write / erase method) can be applied only to the necessary non-volatile memory module, and the other non-volatile memory modules can be operated by the conventional method (write / erase method). That is, the method of the above embodiment can be applied only to the necessary non-volatile memory modules, and at the same time, the non-volatile memory modules that operate as before can be integrated on one chip.

As described above, in the present embodiment, the silicon nitride film (charge trapping insulating film) is used as the charge storage film of the memory cell, but instead of the silicon nitride film, a silicon nitride film, a tantalum oxide film, an aluminum oxide film, etc. The charge trapping insulating film of the above may be used.

Further, fine particles (dots) made of a conductive material such as polysilicon may be used as the charge storage layer. The dots are, for example, those in which a plurality of granular lumps of polysilicon are deposited on the lower oxide film. An upper oxide film is further formed on the dots, and the individual dots are insulated from each other. When such dots are used, the charges (electrons) accumulated in the dots are difficult to move between the dots. Therefore, the above effect can be achieved by matching the electron injection position and the hole injection position. Further, the dots can be applied to the memory cells shown in FIGS. 1, 25 to 27. When dots are used, the diameter is preferably 10 nm or less, and an insulating film is deposited between the dots to discretely accumulate charges.

When a single conductive floating gate electrode is used, electrons and holes can move in the floating gate electrode, so that the effect of matching the electron injection position and the hole injection position is small.

Although the invention made by the present inventor has been specifically described above based on the embodiment thereof, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say.

The present invention can be applied to a non-volatile semiconductor storage device.

<figref num="1">It is sectional drawing of the main part of the non-volatile semiconductor storage device (flash memory) of the embodiment of this invention.</figref><figref num="2">It is a figure which shows the application condition of the voltage to each part of the selected memory cell at the time of writing, erasing, and reading of the non-volatile semiconductor storage device of embodiment of this invention.</figref><figref num="3">It is a graph which shows the erasing characteristic.</figref><figref num="4">It is a graph which compared the charge holding characteristic of the writing side of the memory cell by the presence or absence of a hole neutralization operation in the memory cell which repeated writing and erasing using the BTBT hot hole erasing method which passed the current through a channel.</figref><figref num="5">It is a circuit diagram which shows the non-volatile semiconductor memory array of embodiment of this invention.</figref><figref num="6">It is a figure which shows the voltage condition applied to each wiring at the time of writing, erasing, and reading in the memory array of FIG.</figref><figref num="7">It is a figure which shows the voltage condition applied to each wiring at the time of writing, erasing, and reading in the memory array of FIG.</figref><figref num="8">It is explanatory drawing which shows the timing of applying a voltage to each wiring at the time of writing in the memory array of FIG.</figref><figref num="9">It is a circuit diagram which realizes writing / erasing with a constant channel current in the memory array of FIG.</figref><figref num="10">It is a circuit diagram which shows the other non-volatile semiconductor memory array of embodiment of this invention.</figref><figref num="11">It is a figure which shows the voltage condition applied to each wiring at the time of writing, erasing, and reading in the memory array of FIG.</figref><figref num="12">It is a figure which shows the voltage condition applied to each wiring at the time of writing, erasing, and reading in the memory array of FIG.</figref><figref num="13">It is a circuit diagram which shows the other non-volatile semiconductor memory array of embodiment of this invention.</figref><figref num="14">It is a figure which shows the voltage condition applied to each wiring at the time of writing, erasing, and reading in the memory array of FIG.</figref><figref num="15">It is a figure which shows the voltage condition applied to each wiring at the time of writing, erasing, and reading in the memory array of FIG.</figref><figref num="16">It is sectional drawing of the main part of the non-volatile semiconductor storage device (flash memory) of the embodiment of this invention.</figref><figref num="17">It is sectional drawing of the main part of the substrate which shows the manufacturing method of the non-volatile semiconductor storage device of embodiment of this invention.</figref><figref num="18">It is sectional drawing of the main part of the substrate which shows the manufacturing method of the non-volatile semiconductor storage device of embodiment of this invention.</figref><figref num="19">It is sectional drawing of the main part of the substrate which shows the manufacturing method of the non-volatile semiconductor storage device of embodiment of this invention.</figref><figref num="20">It is sectional drawing of the main part of the substrate which shows the manufacturing method of the non-volatile semiconductor storage device of embodiment of this invention.</figref><figref num="21">It is sectional drawing of the main part of the substrate which shows the manufacturing method of the non-volatile semiconductor storage device of embodiment of this invention.</figref><figref num="22">It is sectional drawing of the main part of the substrate which shows the manufacturing method of the non-volatile semiconductor storage device of embodiment of this invention.</figref><figref num="23">It is sectional drawing of the main part of the substrate which shows the manufacturing method of the non-volatile semiconductor storage device of embodiment of this invention.</figref><figref num="24">It is sectional drawing of the main part of the substrate which shows the manufacturing method of the non-volatile semiconductor storage device of embodiment of this invention.</figref><figref num="25">It is sectional drawing of the main part of another non-volatile semiconductor storage device (flash memory) of embodiment of this invention.</figref><figref num="26">It is sectional drawing of the main part of another non-volatile semiconductor storage device (flash memory) of embodiment of this invention.</figref><figref num="27">It is sectional drawing of the main part of another non-volatile semiconductor storage device (flash memory) of embodiment of this invention.</figref><figref num="28">It is explanatory drawing which shows typically the semiconductor chip formed by integrating a plurality of non-volatile memory modules and the like.</figref><figref num="29">It is sectional drawing of the main part of the substrate which shows the place where the hot electron is generated at the time of writing of the non-volatile semiconductor storage device for demonstrating the subject of this invention.</figref><figref num="30">It is sectional drawing of the main part of the substrate which shows the place where the hot hole occurs at the time of erasing of the non-volatile semiconductor storage device for demonstrating the subject of this invention.</figref><figref num="31">It is sectional drawing of the main part of the memory cell which schematically represented the state of electric charge when the erasing potential is applied to the non-volatile semiconductor storage device for demonstrating the effect of this invention.</figref>

Code description

BIT1 Memory Cell (Selected Cell) BIT2 Memory Cell BL, BL0, BL1 Bit Wire BOTOX Lower Oxide Film (Oxide Film) BS0, BS1 Bit Wire Selective Switching Transistor CAP Silicon Oxide Film CCS1, CCS2 Constant Current Source CMJ Memory Control Module GAPSW Side Wall Spacer INS1 Wiring interlayer insulation film INS2 Wiring interlayer insulating film M1 First layer wiring MD Drain area MDM Low concentration n type impurity area ME n type impurity area MG, MG1, MG2 Memory gate electrode MGL, MGL0 ~ MGL3 Memory gate wire MGR Side wall spacer MMJ1 , MMJ2, MMJ3, MMJ4 Non-volatile memory modules MN0, MN1 NMOS transistors that make up the mirror circuit MP0, MP1 MOSFETs that make up the mirror circuit MPU Semiconductor chip MS Source area MSM Low concentration n type impurity area NMG n type Polysilicon layer NSG n-type polysilicon layer ONO ONO film PMJ power supply module PSUB p-type silicon substrate PWEL p-type well region RES1 Photoresist film RES2 Photoresist film SE channel region (impurity region) SG, SG1, SG2 Selective gate electrode SGL, SGL0 ~ 3 Selective gate wire SGOX Gate insulating film SIN Silicon nitride film SL , SL0 ~ SL3 Source line STI Element separation oxide film region SW Side wall spacer TOPOX Upper oxide film (oxide film) Vd Voltage applied to drain region Vmg Voltage applied to memory gate electrode Vs Voltage applied to source region Vsg Select gate electrode Voltage applied Vwell Voltage applied to the well WORD1 Memory cell connected to the selected gate line