Shift register, its driving method, and driving apparatus for liquid crystal display panel

The present invention relates to a drive circuit of a liquid crystal display device, and more particularly to a shift register using an amorphous silicon thin film transistor and a drive method thereof. The present invention also relates to a drive device for a liquid crystal display panel using the shift register.

Liquid crystal display devices used in television and computer display devices display images by adjusting the light transmittance of the liquid crystal using an electric field. For this purpose, the liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, and a drive circuit for driving the liquid crystal panel.

The liquid crystal panel is arranged so that the gate line and the data line intersect, and the liquid crystal cell is located in the area prepared by the intersection of the gate line and the data line. The liquid crystal panel is provided with a pixel electrode and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via the source and drain terminals of the thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines.

The drive circuit includes a gate driver for driving the gate line and a data driver for driving the data line. The gate driver sequentially supplies scan signals to the gate line to sequentially drive the liquid crystal cells on the liquid crystal panel. The data driver supplies a video signal to each of the data lines each time a scan signal is fed to any one of the gate lines. As a result, the liquid crystal display device displays an image by adjusting the light transmittance by the electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

In such a drive circuit, the gate driver uses a shift register to generate a scan signal for sequentially driving the gate line. Further, the data driver uses a shift register to generate a sampling signal that enables the video signal input from the outside to be sequentially sampled in fixed units.

FIG. 1 is a block diagram illustrating a general two-image shift register, which the shift register illustrated in FIG. 1 comprises subordinately connected first to nth stages.

The first clock signal (C1) and the second clock signal (/ C1) are commonly supplied to the first to nth stages together with the high potential and high potential drive voltage (not shown), and the start pulse (Vst). Alternatively, the output signal of the front all-stage stage is supplied. The first stage outputs to the first output signal (Out1) in response to the start pulse (Vst), the first clock signal (C1), and the second clock signal (/ C1). Further, the second to nth stages generate the second to nth output signals (Out2 to Outn) in response to the output signal of the previous stage and the first clock signal (C1) and the second clock signal (/ C1). Output. Such first to nth stages have the same circuit configuration and sequentially shift the specific voltage of the start pulse (Vst). The first to nth output signals (Out 1 to Out n) are supplied to the scan signal for sequentially driving the gate line of the liquid crystal panel, or as a sampling signal for sequentially sampling the video signal from within the data driver. Be supplied.

FIG. 2 shows a specific circuit configuration of one stage illustrated in FIG. The stage shown in Fig. 2 has a fifth MIMO transistor (T5) that outputs the first clock signal (C1) to the output line under the control of the Q node, and a low potential drive voltage (VSS) that outputs the low potential drive voltage (VSS) to the output line under the control of the QB node. It includes an output buffer unit 20 composed of a sixth MIMO transistor (T6) for output, and a control unit 10 composed of first to fourth MIMO transistors (T1 to T4) for controlling a Q node and a QB node.

High potential and low potential voltages (VDD, VSS) are supplied to such a stage, and at the same time, a start pulse (Vst), a first clock signal (C1), and a second clock signal (/ C1) are supplied. Here, in the first clock signal (C1), the high state voltage and the low state voltage having a constant pulse width are alternately supplied as shown in FIG. 3, and the second clock signal (/ C1) (not shown) is generated. It is supplied so as to have a polarity opposite to that of the first clock signal (C1). The start pulse (Vst) is supplied from the outside or the output signal of the previous stage is supplied. Hereinafter, the operation process of the stage will be described with reference to the drive waveform shown in FIG.

In period A, the high voltage of the start pulse (Vst) is supplied in synchronization with the high voltage of the second clock signal (/ C1). As a result, the high voltage of the second clock signal (/ C1) turns on the first MIMO transistor (T1), and the high voltage of the start pulse (Vst) is supplied at the Q node, that is, pre-charged. To. The high voltage precharged at the Q node turns on the 5th MIMO transistor (T5) to supply the low voltage of the 1st clock signal (C1) to the output line. At this time, the second MIMO transistor (T2) is also turned on by the high voltage of the second clock signal (/ C1) to supply the high potential drive voltage (VDD) to the QB node, and the high potential supplied to the QB node. The drive voltage (VDD) also turns on the 6th NMOS transistor (T6) to supply the low potential drive voltage (VSS). As a result, the output line of the stage outputs a low output signal (OUT) in the A period.

In the B period, the low voltage of the 2nd clock signal (/ C1) turns off the 1st MIMO transistor (T1), causing the Q node to float in the high state, so the 5th MIMO transistor (T5) is in the turn-on state. To maintain. At this time, the floating Q node as the high voltage is supplied to the first clock signal (C1) is affected by the parasitic capacitor (CGS) formed on the superposition of the gate electrode and the source electrode of the fifth MIMO transistor (T5). Bootstrapping. As a result, the Q node voltage rises further and the 5th MIMO transistor (T5) is clearly turned on, so that the high voltage of the 1st clock signal (C1) is quickly supplied to the output line. Then, the 4th NOTES transistor (T4) is turned on by the Q node floating in the high state, and the 3rd NOTES transistor (T3) is turned on by the 1st clock signal (C1) in the high state. Since (VSS) is supplied, the 6th MIMO transistor (T6) is turned off. As a result, the output line of the stage outputs the output signal (OUT) in the high state in the B period.

In the C period, the high voltage of the 2nd clock signal (/ C1) turns on the 1st NMOS transistor (T1) and the low voltage of the start pulse (Vst) is supplied to the Q node, so the 5th NMOS transistor (T5) is Turn-off. At this time, the high voltage of the second clock signal (/ C1) turns on the second MIMO transistor (T2), and the high potential drive voltage (VDD) is supplied to the QB node, so that the sixth MIMO transistor (T6) is turned on. Turn-on to output low potential drive voltage (VSS) to the output line. At this time, the 3rd NMOS transistor (T3) is turned off by the low voltage of the 1st clock signal (C1), and the 4th NMOS transistor (T4) is turned off by the low voltage of the Q node and has a high potential at the QB node. The drive voltage (VDD) is maintained. As a result, the output line of the stage outputs a low output signal (OUT) in the C period.

In the D period, the low voltage of the 2nd clock signal (/ C1) turns off the 1st NMOS transistor (T1), so that the Q node floats in the low state. Furthermore, the low voltage of the 2nd clock signal (/ C1) turns off the 2nd NMOS transistor (T2), and the Q node floating in the low state turns off the 4th NMOS transistor (T4), so the QB node Is in a high state where the high voltage of the 1st clock signal (C1) makes the 3rd NMOS transistor (T3) turn-on but slightly lower than the high potential drive voltage (VDD) supplied in the previous period (C). Floating while maintaining. As a result, the 6th MIMO transistor (T6) maintains the turn-on state and outputs the low potential drive voltage (VSS) to the output line. As a result, the output line of the stage outputs a low output signal (OUT) in the D period.

Then, in other periods, the C period and the D period are alternately repeated, so that the output signal (OUT) of the stage remains in the low state all the time.

<p> Here, since each of the first to sixth MIMO transistors (T1 to T6) formed in the amorphous silicon thin film transistor process has a structure in which the gate electrode is superimposed on each of the source and drain electrodes, it is inevitable that the parasitic capacitor is used. Includes (CGD, CGS). Then, in order to compensate for the low mobility of the Amopass silicon thin film transistor, the size of the 5th and 6th MIMO transistors (T5, T6) constituting the output buffer unit 20 becomes very large, thereby causing the parasitic capacitors (CGD, CGS). ) Will also increase. Here, pull-up transistor (pull-up) The parasitic capacitor (CGS) formed in the superimposition of the gate electrode and the source electrode in the 5th MIMO transistor (T5), which is a transistor), is useful for bootstrapping the Q node. On the other hand, the parasitic capacitor (CGD) formed at the superposition of the gate electrode and the drain electrode of the 5th MIMO transistor (T5) has the first clock signal (C1) supplied to the drain electrode from low to high as shown in FIG. There is a problem that the output voltage (Vout) also fluctuates by fluctuating the voltage of the Q node, which is in a floating state, every time it shifts to. Referring to FIG. 3, the first clock signal (C1) transitioned from the D period to the high voltage changes the voltage of the Q node floating in the low state to a slightly higher state, and thereby the output voltage (OUT) is also low. It can be seen that the voltage rises a little. Since the output voltage (OUT) distorted in this way is used at the input of the next stage, the amount of distortion of the output voltage (OUT) increases as the number of stages passes, and at some point the circuit malfunctions. There is a problem that can come.</p>

<p> Therefore, an object of the present invention is to provide a shift register and a driving method thereof that can prevent the voltage of the node (Q) that controls the output buffer unit from being fluctuated by the parasitic capacitor of the thin film transistor.</p><p> Another object of the present invention is to provide a drive device for a liquid crystal display panel using the shift register.</p><p> In order to achieve the above object, each of the stages of the shift register according to the first embodiment of the present invention is a pull-up transistor that supplies a first clock signal controlled by the first node to the output line, and a second node. A first pull-down transistor that supplies the first drive voltage controlled by the above to the output line, a control unit that controls the first and second nodes so as to contradict each other, and the first node. The second clock signal is different from the first clock signal, and includes a compensating capacitor connected between the second clock signal and the input line of the second clock signal.</p><p> The capacitance of the compensating capacitor is larger than the capacitance of the parasitic capacitor of the pull-up transistor. Before the voltage of the first node changes according to the transition voltage of the first clock signal transmitted through the parasitic capacitor while the first node is floating, or at a time approximately the same as the voltage change of the first node. The voltage of the first node changes in the opposite direction according to the transition voltage of the second clock signal.</p><p> The control unit supplies the start pulse at the first node in response to the second clock signal, and supplies the second drive voltage at the second node in response to the second clock signal. The second transistor, the third transistor that supplies the first drive voltage to the second node in response to the first clock signal, and the first drive voltage in response to the voltage of the first node. It includes a fourth transistor supplied by the third transistor.</p><p> Each of the stages further comprises a second pull-down transistor connected in parallel with the first pull-down transistor between the output line controlled by the third node and the supply line of the first drive voltage.</p><p> The control unit is a first node control unit for supplying the start pulse to the first node in response to the second clock signal, and a fourth node in response to the first and second clock signals. The second node control unit that selectively supplies the voltage and the first drive voltage, and the voltage of the fourth node and the second drive voltage in response to the first and second clock signals are supplied in opposite forms. A fourth node control unit for selectively supplying the first and second drive voltages to the fourth node in response to the first and second clock signals and the voltage of the first node. It includes a node control unit.</p><p> The first node control unit includes a first transistor for supplying the start pulse to the first node in response to the second clock signal.</p><p> The fourth node control unit supplies the second drive voltage to the fourth node in response to the second clock signal, and the second transistor to the fourth node in response to the first clock signal. It includes a third transistor that supplies a drive voltage, and a fourth transistor that supplies the first drive voltage to the fourth node in response to the voltage of the first node.</p><p> The shift register driving method according to the first embodiment of the present invention is the step of floating the first node and the floating in the opposite direction according to the transition voltage of the second clock signal transmitted via the compensation capacitor. Includes the step of changing the voltage of the first node.</p><p> The step of changing the voltage of the floating first node is before the voltage of the first node changes according to the transition voltage of the first clock signal transmitted through the parasitic capacitor while the first node is floating. Alternatively, it is executed at approximately the same time as the voltage change of the first node.</p><p> In the drive device of the liquid crystal display panel according to the first embodiment of the present invention, each of the stages of the shift register is a pull-up transistor for supplying the first clock signal controlled by the first node to the output line, and the second node. A first pull-down transistor for supplying the first drive voltage controlled by the above to the output line, a control unit for controlling the first and second nodes so as to contradict each other, and the first node and the second clock signal. The second clock signal is different from the first clock signal because it includes a compensating capacitor connected between the input lines of the above.</p><p> Each of the stages of the shift register according to the second embodiment of the present invention has a pull-up transistor for supplying a first clock signal controlled by the first node on the output line and a first stage controlled by the second node. The compensation circuit includes a pull-down transistor for supplying a drive voltage on the output line, a control unit for controlling the first and second nodes, and a compensation circuit unit connected to the first node. The unit selectively supplies the first drive voltage to the first node.</p><p> The compensation circuit unit selectively prevents the first node from floating. The compensation circuit unit supplies the first drive voltage to the first node when the first node is floated.</p><p> The compensation circuit unit uses the first transistor that supplies the first clock signal controlled by the second drive voltage to the third node and the first drive voltage controlled by the voltage of the third node. It includes a second transistor that supplies the node, and a third transistor that supplies the first drive voltage controlled by the voltage of the third node to the third node.</p><p> The compensation circuit unit supplies the first transistor that supplies the second drive voltage controlled by the first clock signal to the third node and the first drive voltage controlled by the voltage of the third node. It includes a second transistor that supplies the node, and a third transistor that supplies the first drive voltage controlled by the voltage of the third node to the third node.</p><p> The compensation circuit unit uses the first transistor that supplies the first clock signal controlled by the first clock signal to the third node, and the first drive voltage that is controlled by the voltage of the third node. It includes a second transistor that supplies the first node and a third transistor that is controlled by the voltage of the third node and supplies the first drive voltage to the third node.</p><p> The shift register driving method according to the second embodiment of the present invention includes a step of selectively supplying the first driving voltage to the first node by using the compensation circuit unit. The first drive voltage is selectively supplied to the first node in order to prevent the first node from floating. The step of selectively supplying the first drive voltage to the first node is performed when the first node is floated.</p><p> In the drive device of the liquid crystal display panel according to the second embodiment of the present invention, each of the stages of the shift register is controlled by the first node to supply the first clock signal on the output line, and the pull-up transistor and the second. A pull-down transistor controlled by two nodes to supply the first drive voltage on the output line, a control unit for controlling the first and second nodes, and a compensation circuit unit connected to the first node. The compensation circuit unit selectively supplies the first drive voltage to the first node.</p><p> The shift register is formed on a glass substrate. Each output line of the stage is connected to the gate line of the liquid crystal display panel.</p>

<p> The shift register according to the present invention can reduce the distortion of the output voltage by preventing the control node (Q) of the pull-up transistor from changing according to the clock signal by utilizing the inverting clock signal and the compensation capacitor. .. This makes it possible to prevent circuit malfunction due to distortion of the output voltage.</p>

Hereinafter, desirable embodiments of the present invention will be described with reference to FIGS. 4 to 12.

FIG. 4 shows one of a large number of stages subordinately connected by the shift register according to the first embodiment of the present invention in the center of the output buffer unit 30, and FIG. 5 shows a drive waveform diagram. It is illustrated. The shift register stage shown in Fig. 4 outputs a 1-clock signal (C1) to the output line to control the Q node, and a low potential drive voltage (VSS) under the control of the QB node. An output buffer unit 20 composed of a sixth MIMO transistor (T6) that outputs to the output line, a control unit 10 that controls the Q node and the QB node, and a compensation capacitor (CC) for compensating for the fluctuation voltage of the Q node. Equipped. Such shift registers are formed directly on the glass substrate of the LCD.

The compensation capacitor (CC) is connected between the Q node and the supply line of the second clock signal (/ C1). As a result, the compensating capacitor (CC) applies a voltage contradictory to the parasitic capacitor (CGD) formed at the superposition of the gate electrode and drain electrode of the fifth NMOS transistor (T5), which is a pull-up transistor, to the Q node. By doing so, the fluctuation of the Q node can be prevented. Specifically, as shown in FIG. 5, before the first clock signal (C1) shifts from low to high at the edge of the C and D periods, Q is obtained by the second clock signal (/ C1) and the compensation capacitor (CC). The node will change in the opposite direction to the first clock signal (C1). This is because the capacitance of the compensating capacitor (CC) is set larger than that of the parasitic capacitor (CGD) so that the Q node responds to the transition of the second clock signal (/ C1) before the transition of the first clock signal (C1). Because. As a result, when the 1st clock signal (C1) shifts to a high voltage, the parasitic capacitor (CGD) of the 5th NMOS transistor (T5) allows the Q node to return to the low voltage in almost its original state. As a result, the distortion of the output voltage (OUT) can be reduced.

In FIG. 4, the control unit 10 is composed of the first to fourth MIMO transistors (T1 to T4) as shown in FIG. 2, or can have any configuration capable of controlling the Q node and the QB node. .. Here, for convenience of explanation, only the case where the control unit 40 has the same configuration as the control unit 10 shown in FIG. 2 will be taken as an example, and the drive waveform shown in FIG. 5 will be referred to. To do.

In period A, the high voltage of the start pulse (Vst) is supplied in synchronization with the high voltage of the second clock signal (/ C1). As a result, the high voltage of the second clock signal (/ C1) turns on the first MIMO transistor (T1), and the high voltage of the start pulse (Vst) is supplied at the Q node, that is, precharged. The high voltage precharged at the Q node turns on the 5th MIMO transistor (T5) to supply the low voltage of the 1st clock signal (C1) to the output line. At this time, the second MIMO transistor (T2) is also turned on by the high voltage of the second clock signal (/ C1) to supply the high potential voltage (VDD) to the QB node, and the high potential voltage supplied to the QB node. The 6th NMOS transistor (T6) is also turned on by (VDD) to supply a low potential voltage (VSS). As a result, the output line of the stage outputs a low output signal (OUT) in the A period.

In the B period, the low voltage of the 2nd clock signal (/ C1) turns off the 1st MIMO transistor (T1), causing the Q node to float in the high state, so the 5th MIMO transistor (T5) is in the turn-on state. To maintain. At this time, the floating Q node due to the high voltage supplied to the first clock signal (C1) is affected by the parasitic capacitor (CGS) formed on the superposition of the gate electrode and the source electrode of the fifth MIMO transistor (T5). Bootstrapping is done with. As a result, the Q node voltage rises further and the 5th MIMO transistor (T5) is clearly turned on, so that the high voltage of the 1st clock signal (C1) is quickly supplied to the output line. In addition, the Q node floating in the high state turns on the 4th MIMO transistor (T4), and the 1st clock signal (C1) in the high state turns on the 3rd NOTES transistor (T3), and the QB node has a low potential voltage ( Since VSS) is supplied, the 6th MIMO transistor (T6) is turned off. As a result, the output line of the stage outputs the output signal (OUT) in the high state in the B period.

In the C period, the high voltage of the 2nd clock signal (/ C1) turns on the 1st NMOS transistor (T1) and the low voltage of the start pulse (Vst) is supplied to the Q node, so the 5th NMOS transistor (T5) is Turn-off. At this time, the high voltage of the second clock signal (/ C11) turns on the second MIMO transistor (T2), and the high potential voltage (VDD) is supplied to the QB node to turn the sixth MIMO transistor (T6). -Turned on to output low potential voltage (VSS) to the output line. At this time, the 3rd NMOS transistor (T3) is turned off by the low voltage of the 1st clock signal (C1), and the 4th NMOS transistor (T4) is turned off by the low voltage of the Q node and has a high potential at the QB node. The voltage (VDD) is maintained. As a result, the output line of the stage outputs a low output signal (OUT) in the C period.

In the D period, the low voltage of the 2nd clock signal (/ C1) turns off the 1st NMOS transistor (T1), so that the Q node floats in the low state. Furthermore, the low voltage of the 2nd clock signal (/ C1) turns off the 2nd NMOS transistor (T2), and the Q node floating in the low state turns off the 4th NMOS transistor (T4), so the QB node Maintains a high state slightly lower than the high potential voltage (VDD) supplied in the previous period (C) even when the 3rd NMOS transistor (T3) is turned on by the high voltage of the 1st clock signal (C1). Floating while. As a result, the 6th MIMO transistor (T6) maintains the turn-on state and outputs the low potential voltage (VSS) to the output line. As a result, the output line of the stage outputs a low output signal (OUT) in the D period.

In particular, the second high-low transition before the low-to-high first clock signal (C1) is transmitted through the parasitic capacitor (CGD) of the fifth MIMO transistor (T5) at the beginning of the D period. The clock signal (/ C1) is transmitted to the Q node through the compensation capacitor (CC). As a result, the voltage of the Q node becomes lower according to the falling second clock signal (/ C1), and then returns to the original low voltage according to the rising first clock signal (C1). As a result, the distortion of the output voltage (OUT) can be reduced. Further, in other periods, the C period and the D period are alternately repeated, so that the output signal (OUT) of the stage maintains a low state with almost no distortion.

FIG. 6 shows a detailed circuit of any one of a large number of stages subordinately connected in the shift register according to the second embodiment of the present invention, and FIG. 7 shows a drive waveform diagram. It is illustrated.

Each stage of the shift register illustrated in FIG. 6 has a fifth MIMO transistor (T5) that outputs the first clock signal (C1) to the output line under the control of the Q node, and a low potential drive voltage under the control of the QB1 and QB2 nodes. An output buffer including 6th and 7th MIMO transistors (T6, T7) that output (VSS) to the output line, a Q node control unit including a 1st MIMO transistor (T1) that controls the Q node, and a QB node. QB node control unit including 2nd to 4th MIMO transistors (T2, T3, T4) to control, QB1 node control unit including 8th and 9th MIMO transistors (T8, T9) to control QB1 node, and QB2 It includes a QB2 node control unit including 10th and 11th MIMO transistors (T10, T11) for controlling the nodes, and a compensation capacitor (CC) for compensating for the fluctuation voltage of the Q node.

In the output buffer, the fifth MIMO transistor (T5), which is a pull-up transistor, is connected between the input line of the first clock signal (C1) and the output line of the stage and is controlled by the Q node. The 6th and 7th MIMO transistors (T6, T7), which are pull-down transistors, are connected in parallel between the output line of the stage and the input line of the low potential voltage (VSS) and controlled by the QB1 and QB2 nodes, respectively. ..

The first MIMO transistor (T1) of the Q node control unit is connected between the input line of the start pulse (Vst) and the Q node and is controlled by the second clock signal (/ C1).

The 2nd NMOS transistor (T2) of the QB node control unit is connected between the supply line of the high potential drive voltage (VDD) and the QB node and is controlled by the 2nd clock signal, and the 3rd NMOS transistor (T3) is the 2nd MIMO. It is connected in parallel with the transistor (T2) and controlled by the first clock signal (C1), and the fourth MIMO transistor (T4) is connected between the QB node and the low potential voltage (VSS) input line and controlled by the Q node. Will be done.

The 8th MIMO transistor (T8) of the QB1 node control unit is connected between the QB node and the QB1 node and controlled by the 1st clock signal (C1), and the 9th NMOS transistor (T9) is the input of low potential voltage (VSS). It is connected between the line and the QB1 node and controlled by the second clock signal (/ C1).

The 10th MIMO transistor (T10) of the QB2 node control unit is connected between the QB node and the QB2 node and controlled by the 2nd clock signal (C1), and the 11th MIMO transistor (T11) is the input of low potential voltage (VSS). It is connected between the line and the QB2 node and controlled by the second clock signal (/ C1).

The capacitor (CB) connected between the Q node and the low potential voltage (VSS) input line and the capacitor (CQB) connected between the QB node and the low potential voltage (VSS) input line are the Q node and Remove noise from the QB node.

The operation process of such a stage will be described with reference to the drive waveform shown in FIG.

During the A period, the high voltage of the start pulse (Vst) turns on the first MIMO transistor (T1), supplies a high potential drive voltage (VDD) to the Q node, and the Q node is precharged to the high state. The Q node precharged to the high state turns on the 5th MIMO transistor (T5) and supplies the low voltage of the 1st clock signal (C1) to the output line. At this time, a high potential voltage (VDD) is supplied to the QB node through the second MIMO transistor (T2) turned on by the second clock signal (/ C1). In addition, the second clock signal (/ C1) turns the 9th and 10th MIMO transistors (T9, T10) on, resulting in a low potential voltage (VSS) for the QB1 node and a QB node for the QB2 node. The supplied high potential voltage (VDD) is supplied. This turns the 7th MIMO transistor (T7) on and supplies a low potential voltage (VSS) at the output line. As a result, the output line of the stage outputs a low output signal (Out) in the A period.

In the B period, the low voltage of the 2nd clock signal (/ C1) turns off the 1st MIMO transistor (T1), causing the Q node to float in the high state, so the 5th MIMO transistor (T5) is in the turn-on state. To maintain. At this time, the Q node floated by the high voltage of the first clock signal (C1) is bootstrapped due to the influence of the capacitor (CGS) formed between the gate and drain of the fifth MIMO transistor (T5). Bootstrapping. As a result, the Q node voltage rises further and the 5th MIMO transistor (T5) is clearly turned on, so that the high voltage of the 1st clock signal (C1) is quickly supplied to the output line. At this time, the 3rd NMOS transistor (T3) is turned on by the 1st clock signal (C1), and the 4th PMOS transistor (T4) is turned on by the buttostreped Q node, so that the QB node is turned on. It goes low. Furthermore, the low potential voltage (VSS) supplied to the QB node is applied to the QB1 node by turning on the 8th and 11th MIMO transistors (T8, T11) by the 1st clock signal (C1), and the QB2 node. Is supplied with a low potential voltage (VSS). This turns off the 6th and 7th MIMO transistors (T6, T7). As a result, the output line of the stage outputs a high output signal (Out) in period B.

In the C period, the high voltage of the 2nd clock signal (/ C1) turns on the 1st NMOS transistor (T1), and the low voltage of the start pulse (Vst) is supplied to the Q node, so the 5th NMOS transistor (T5) Is turned off. At this time, the second MIMO transistor (T2) is turned on by the second clock signal (/ C1), and a high potential voltage (VDD) is supplied to the QB node. In addition, the second clock signal (/ C1) turns on the ninth and tenth NMOS transistors (T9, T10), resulting in a low potential drive voltage (VSS) for the QB1 node and a QB node for the QB2 node. The high potential drive voltage (VDD) supplied to is supplied to. This turns the 7th MIMO transistor (T7) on and supplies a low potential drive voltage (VSS) at the output line. As a result, the output line of the stage outputs a low output signal (Out) in the C period.

During the D period, the low voltage of the second clock signal (/ C1) turns off the first and second MIMO transistors (T1, T2). This causes the Q node to float to its previous low state, thus turning off the 5th MIMO transistor (T5). At this time, the high voltage of the first clock signal (C1) turns on the third MIMO transistor (T3), and a high potential drive voltage (VDD) is supplied to the QB node. Then, the 8th and 11th OSPF transistors (T9) are turned on by the 1st clock signal (C1), so that the high potential voltage (VDD) supplied to the QB node is sent to the QB1 node and the QB2 node is sent to the high potential voltage (VDD). Low potential voltage (VSS) is supplied. This turns the 6th MIMO transistor (T6) on and supplies a low potential drive voltage (VSS) at the output line. As a result, in the B period, the output line of the stage outputs a low output signal (Out).

Further, since the stage operates in the same manner as the C and D periods in other periods, the output signal (OUT) of the stage is maintained in the low state.

As described above, each stage of the shift register according to the second embodiment of the present invention shown in FIG. 6 is connected to the 6th MIMO transistor (T6) in parallel with the 7th MIMO transistor (T7) which operates in parallel, and the gate node thereof. The QB1 and QB2 nodes are AC-driven by the first clock signal (C1) and the second clock signal (/ C1). This prevents the DC bias from being applied to the gate nodes of the 6th and 7th MIMO transistors (T6, T7), causing the 6th and 77th MIMO transistors (T6, T7) to malfunction due to gate bias stress during high temperature drive. It can be prevented from doing so.

However, in the shift register shown in FIG. 6, the first pull-down transistor (T6, T7) is located in the region where one pull-down transistor (T6) must be formed in combination with the shift register shown in FIG. There is no choice but to reduce the size by being formed. As a result, the 6th and 7th MIMO transistors (T6, T7), which have become relatively small in size, can be alternately turned on to keep the output voltage (OUT) at a sufficiently low voltage. If this is not possible, that is, the output voltage (OUT) may be distorted. At this time, as described above, the voltage of the Q node as shown in the D period shown in FIG. 8a by the parasitic capacitor (CGD) and the first clock signal (C1) of the fifth MIMO transistor (T5) which is a pull-up transistor. When is changed and the output voltage (OUT) is distorted, the distortion of the output voltage (OUT) can only be increased.

To prevent this, each stage of the shift register illustrated in FIG. 6 further comprises a compensating capacitor (CC) connected between the Q node and the input line of the second clock signal (/ C1). The compensating capacitor (CC) is transmitted through the parasitic capacitor (CGD) of the 5th NMOS transistor (T5) before the low-transitioned 1st clock signal (C1) is transmitted, as in the D period illustrated in Figure 8b. The second clock signal (/ C1) that has transitioned from high to low is transmitted to the Q node. As a result, the voltage of the Q node becomes lower according to the falling second clock signal (/ C1), and then returns to the original low voltage according to the rising first clock signal (C1). As a result, the distortion of the output voltage (OUT) can be reduced.

FIG. 9 shows one stage of any one of a large number of stages sequentially connected by the shift register according to the third embodiment of the present invention in the center of the output buffer unit 330, and FIG. 10 shows the drive waveform of the stage. Is illustrated.

The shift register stage shown in Fig. 9 is a pull-up NMOS transistor (T38) that outputs the first clock signal (C1) to the output line under the control of the Q node, and a low potential drive voltage (VSS) under the control of the QB node. An output buffer unit 330 composed of a pull-down NMOS transistor (T39) that outputs the power to the output line, a control unit 340 that controls the Q node and the QB node, and a compensation circuit unit 350 that compensates for the fluctuation voltage of the Q node. Equipped. Such shift registers are formed directly on the glass substrate.

The compensation circuit unit 350 has a 5th MIMO transistor (T35) for supplying a low potential voltage (VSS) at the Q node under the control of the P node, and a 6th and 7th MIMO transistors (T36_1, T37) for controlling the P node. And. The 6th MIMO transistor (T36_1) always maintains a turn-on state by a high potential voltage (VDD) and supplies the 1st clock signal (C1) to the P node. The 7th MIMO transistor (T37) supplies a low potential voltage (VSS) to the P node under the control of the Q node. Such a compensation circuit unit 350 has a low potential voltage (VSS) at the Q node every period (D) when the first clock signal (C1) is in the high state after there is a high state output (OUT) in the current stage. ) Will be supplied to prevent the Q node from floating in the low state. In other words, the compensation circuit unit 350 prevents the Q node from floating in the low state and prevents the voltage fluctuation of the Q node due to the coupling of the second generation capacitor (CGS) of the pull-up transistor (T38). Will come to do. This makes it possible to prevent distortion of the output signal (OUT) due to voltage fluctuations of the Q node.

As shown in FIG. 2, the control unit 340 in FIG. 9 is composed of the first to fourth MIMO transistors (T1 to T4), or can be configured to control the Q node and the QB node. .. Here, for convenience of explanation, only the case where the control unit 340 has the same configuration as the control unit 10 shown in FIG. 2 will be taken as an example, and the drive waveform shown in FIG. 10 will be referred to for explanation. ..

During the A period, the low voltage of the first clock signal (C1), the high voltage of the second clock signal (/ C1), and the high voltage of the start pulse (Vst) are supplied. The high voltage of the 2nd clock signal (/ C1) turns on the 1st NMOS transistor (T1), and the high voltage of the start pulse (Vst) is supplied at the Q node, that is, precharged. The high voltage of the Q node turns on the pull-up NMOS transistor (T38) to supply the low voltage of the first clock signal (C1) to the stage output line. At this time, a low potential voltage is applied to the P node by the 6th MIMO transistor (T36_1) that maintains the turn-on state by the high potential voltage (VDD) and the 7th MIMO transistor (T37) that is turned on by the high voltage of the Q node. Since (VSS) is supplied, the 5th MIMO transistor (T35) is turned off. Furthermore, the high voltage of the second clock signal (/ C1) turns on the second NMOS transistor (T2), and the high potential voltage (VDD) is supplied to the QB node, so the pull-down NMOS transistor (T39) is turned on. The low potential voltage (VSS) is supplied to the output line of the stage. As a result, the output line of the stage outputs a low output signal (OUT) in the A period.

During the B period, the high voltage of the first clock signal (C1), the low voltage of the second clock signal (/ C1), and the low voltage of the start pulse (Vst) are supplied. The low voltage of the second clock signal (/ C1) turns off the first MIMO transistor (T1) and floats the Q node in a high state. The Q node floating in the high state is the high voltage of the first clock signal (C1) due to the coupling action of the first parasitic capacitor (CGD) formed by superimposing the gate electrode and the source electrode of the pull-up NMOS transistor (T38). Bootstrapping is performed according to the above. As a result, the Q node voltage rises further and the pull-up NMOS transistor (T38) is clearly turned on, so that the high voltage of the first clock signal (C1) is quickly supplied to the output line. Here, in order to enhance the bootstrapping effect of the Q node, a separate capacitor is formed in parallel with the first parasitic capacitor (CGD). In this case, the high Q node turns on the 7th MIMO transistor (T37) to supply a low potential voltage (VSS) to the P node, and at the same time, the 6th MIMO transistor (T37) maintains the turn-on state. The high voltage of the first clock signal (C1) is supplied by T36_1). Here, a low potential voltage (VSS) is supplied to the P node by forming the 7th MIMO transistor (T37) larger than the 6th MIMO transistor (T36_1). For example, the size of the 7th NMOS transistor (T37) and the 6th NMOS transistor (T36_1) are approximately 3: It is formed to have a ratio of 1st place. In addition, the Q node in the high state turns on the 4th NMOS transistor (T4), and the 1st clock signal (C1) in the high state turns on the 3rd NMOS transistor (T3), and the QB node has a low potential voltage (VSS). Since it is supplied, the pull-down NMOS transistor (T39) is turned off. As a result, the output line of the stage outputs the output signal (OUT) in the high state in the B period.

During the C period, the low voltage of the first clock signal (C1), the high voltage of the second clock signal (/ C1), and the low voltage of the start pulse (Vst) are supplied. The high voltage of the 2nd clock signal (/ C1) turns on the 1st NMOS transistor (T1) and the low voltage of the start pulse (Vst) is supplied to the Q node, so the pull-up NMOS transistor (T38) turns- It is turned off. In addition, the P node has a low potential voltage (T36_1) due to the 6th NMOS transistor (T36_1) that maintains the turn-on state by the high potential voltage (VDD) and the 7th NMOS transistor (T37) that is turned off by the low voltage of the Q node. Since VSS) is supplied, the 5th MIMO transistor (T35) is turned off. At this time, the second NMOS transistor (T2) is turned on by the high voltage of the second clock signal (/ C1), and the high potential voltage (VDD) is supplied to the QB node, so that the pull-down NMOS transistor (T39) is turned. -Turned on to supply low potential voltage (VSS) to the output line. The 3rd and 4th MIMO transistors (T3, T4) are turned off by the low voltage of the 1st clock signal (C1) and the low voltage of the Q node, respectively. As a result, the output line of the stage outputs a low output signal (OUT) in the C period.

During the D period, the high voltage of the first clock signal (C1), the low voltage of the second clock signal (/ C1), and the low voltage of the start pulse (Vst) are supplied. The low voltage of the 2nd clock signal (/ C1) turns off the 1st NMOS transistor (T1), so the Q node keeps its previous low state and the 7th NMOS transistor (T37) is turned off. At this time, the high voltage of the 1st clock signal (C1) is supplied to the P node by the 6th MIMO transistor (T36_1) which always maintains the turn-on state, so that the 5th MIMO transistor (T35) is turned on. This locks the Q node in a low state with the low potential voltage (VSS) supplied through the turn-on fifth MIMO transistor (T35). Therefore, since the Q node is not floated, it is possible to prevent the pull-up NMOS transistor (T38) from being fluctuated according to the high voltage of the first clock signal (C1) due to the coupling action of the second parasitic capacitor (CGS). become. As a result, it becomes possible to prevent distortion of the output signal (OUT) due to fluctuations in the Q node voltage during the D period. On the other hand, the low voltage of the 2nd clock signal (/ C1) turns off the 2nd NMOS transistor (T2), and the low Q node turns off the 4th NMOS transistor (T4), so the QB node is the 1st. Floating while maintaining a high state slightly lower than the high potential voltage (VDD) supplied in the previous period (C) even when the 3rd NMOS transistor (T3) is turned on by the high voltage of the clock signal (C1). Will be done. As a result, the pull-down NMOS transistor (T39) maintains a turn-on state and supplies a low potential voltage (VSS) on the output line. As a result, the output line of the stage outputs a low output signal (OUT) in the D period.

Then, in other periods, the C period and the D period are alternately repeated, so that the output signal (OUT) of the stage maintains a low state without distortion.

As described above, the shift register according to the present invention uses the compensation circuit unit 350 to prevent the Q node that controls the pull-up NMOS transistor (T38) from floating in the D period, thereby preventing the high voltage first clock. It becomes possible to prevent the voltage of the Q node from changing due to the signal (C1).

FIG. 11 shows only the compensation circuit unit 460 according to the fourth embodiment of the present invention. The compensation circuit unit 460 illustrated in FIG. 11 is shown in FIG. 9 except that the 6th MIMO transistor (T46_2) is controlled by the 1st clock signal (C1) to supply a high potential voltage (VSS) to the P node. It has the same components as the illustrated compensation circuit unit 250.

During the A period, the low voltage of the 1st clock signal (C1) turns the 6th MIMO transistor (T46_2) off, and the Q node precharged with the high voltage turns the 7th MIMO transistor (T47) on to the P node. Is supplied with a low potential voltage (VSS). This turns off the 5th MIMO transistor (T45).

In period B, the high voltage of the 1st clock signal (C1) turns on the 6th MIMO transistor (T46_2), and the Q node, whose high voltage rises further during bootstrapping, turns on the 7th MIMO transistor (T47). At this time, even if the 7th NMOS transistor (T47) is formed to have a size larger than that of the 6th NMOS transistor (T46_2) and is turned on at the same time, the P node has a high potential voltage (T46_2) via the 6th NMOS transistor (T46_2). Since the low potential voltage (VSS) is supplied via the 7th NMOS transistor (T47) rather than VDD), the 5th NMOS transistor (T45) is turned off. For this reason, the 7th and 6th MIMO transistors (T47, T46_2) are formed to have a magnitude ratio of at least 3: 1.

In the C period, the low voltage of the 1st clock signal (C1) turns off the 6th NMOS transistor (T46_2), and the Q node converted to low voltage turns off the 7th NMOS transistor (T47), so the P node is Floating in the previous low state. This turns off the 5th MIMO transistor (T45).

In the D period, the high voltage of the 1st clock signal (C1) turns the 6th MIMO transistor (T46_2) on, and the low voltage Q node turns the 7th MIMO transistor (T47) off, so it is high for the P node. Potential voltage (VDD) is supplied. This prevents the Q node from being altered by the high voltage first clock signal (C1) because the 5th MIMO transistor (T45) is turned on and supplies the low potential voltage (VSS) to the Q node. Will be.

FIG. 12 shows only the compensation circuit unit 570 according to the fifth embodiment of the present invention. The compensation circuit unit 570 illustrated in FIG. 12 is shown in FIG. 9 except that the 6th MIMO transistor (T56_3) is controlled by the 1st clock signal (C1) to supply the 1st clock signal (C1) to the P node. It has the same components as the compensation circuit unit 250 shown in.

During the A period, the low voltage of the 1st clock signal (C1) turns the 6th MIMO transistor (T56_2) off, and the Q node precharged with the high voltage turns the 7th MIMO transistor (T57) on to the P node. Is supplied with a low potential voltage (VSS). This turns off the 5th MIMO transistor (T55).

In period B, the high voltage of the 1st clock signal (C1) turns on the 6th MIMO transistor (T56_2), and the Q node, whose high voltage rises further during bootstrapping, turns on the 7th MIMO transistor (T57). .. At this time, even if the 7th NMOS transistor (T57) is formed to have a size larger than the 6th NMOS transistor (T56_2) and is turned on at the same time, the P node has the 1st clock signal via the 6th NMOS transistor (T56_2). Since the low potential voltage (VSS) is supplied via the 7th NMOS transistor (T57) rather than the high voltage of (C1), the 5th NMOS transistor (T55) is turned off. For this reason, the 7th and 6th MIMO transistors (T57, T56_2) are formed to have a magnitude ratio of at least 3: 1.

In the C period, the low voltage of the 1st clock signal (C1) turns off the 6th NMOS transistor (T56_2), and the Q node converted to low voltage turns off the 7th NMOS transistor (T57), so the P node is Floating in the previous low state. This turns off the 5th MIMO transistor (T55).

In the D period, the high voltage of the 1st clock signal (C1) turns on the 6th NMOS transistor (T56_2), and the low voltage Q node turns off the 7th NMOS transistor (T57). High voltage of 1 clock signal (C1) is supplied. This prevents the Q node from being altered by the high voltage first clock signal (C1) because the 5th MIMO transistor (T55) is turned on and supplies the low potential voltage (VSS) to the Q node. Will be.

The drive device of the liquid crystal display panel using such a shift register operates more stably than the conventional drive device.

Those skilled in the art can make various changes and modifications without departing from the technical idea of the present invention through the contents described above. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but must be determined by the scope of claims.

<figref num="1">A block diagram illustrating a conventional two-image shift register.</figref><figref num="2">Detailed circuit diagram of the first stage illustrated in FIG.</figref><figref num="3">The drive waveform diagram of the stage illustrated in FIG.</figref><figref num="4">The circuit diagram which illustrated one stage of the shift register which concerns on 1st Embodiment of this invention is shown in the center of an output part.</figref><figref num="5">The drive waveform diagram of the stage illustrated in FIG.</figref><figref num="6">A detailed circuit diagram for one stage of the shift register according to the second embodiment of the present invention.</figref><figref num="7">The drive waveform diagram of the stage illustrated in FIG.</figref><figref num="8A">The drawing which compared and illustrated the drive waveform in the case where there is no compensating capacitor (CC) in the stage illustrated in FIG.</figref><figref num="8B">The drawing which compared and illustrated the drive waveform in the case of having a compensating capacitor (CC) in the stage illustrated in FIG.</figref><figref num="9">The circuit diagram which illustrated one stage of the shift register which concerns on 3rd Embodiment of this invention is shown in the center of an output part.</figref><figref num="10">The drive waveform diagram of the stage illustrated in FIG.</figref><figref num="11">The detailed circuit diagram for the compensation circuit part of the shift register which concerns on 4th Embodiment of this invention.</figref><figref num="12">The detailed circuit diagram for the compensation circuit part of the shift register which concerns on 5th Embodiment of this invention.</figref>

Code description

10, 40, 340 Control unit 20, 30, 330 Output buffer unit 350, 460, 570 Compensation circuit unit