Optical disk recording/reproducing device and optical disk evaluation method

According to the present invention, an optical disc is irradiated with a laser beam, the laser beam changed by a pit or a mark recorded on the optical disk is received, and the amount of the received laser beam is converted into an electric signal to obtain a reproduced signal to obtain the optical disk. The present invention relates to an optical disc recording / reproducing device and an optical disc evaluation method for evaluating the above.

Conventionally, an evaluation device called a jitter meter has been used as an evaluation device for an optical disk (see, for example, Patent Document 1 shown below). Such an evaluation device quantitatively measures the degree of blurring of the reproduced signal of the optical disc, which is called jitter. However, the dedicated jitter meter is expensive, and it has not been possible to easily evaluate the jitter. Therefore, a method of evaluating jitter using an optical disc playback device has been devised.

FIG. 20 shows a CD recording / playback device 100 as an optical disc recording / playback device having an optical disc evaluation function. The playback operation of the optical disk 2 in the CD recording / playback device 100 will be described.

The pickup unit 1 receives the reflected light of the light radiated to the optical disk 2, and extracts the intensity of the light as a change in the voltage value. The pickup control unit 3 controls the reading position of the pickup unit 1 with respect to the optical disc 2 so that the pickup unit 1 can read the data corresponding to the pits or lands stored in the optical disc 2 in the correct order. The binarization circuit 4 reads the change in the voltage value output from the pickup unit 1 and generates an EFM (Eight to Fourteen Modulation) signal having 588 bits as one frame. This EFM signal is a repetition of "High" and "Low". There are nine types of periods corresponding to "High" or "Low" between 3T and 11T. T here means about 230 ns at 1-bit intervals.

The digital signal processing circuit 5 performs EFM demodulation on the EFM signal input from the binarization circuit 4. Furthermore, CIRC (Cross-Inter leave Reed-Solomon Code) decoding is performed on the demodulated signal to generate CD-ROM data consisting of 24 bytes per frame. The CD-ROM decoder 6 detects a read error in the demodulated CD-ROM data input from the digital signal processing circuit 5, corrects the error, and sends the processed CD-ROM data to the host computer. Output.

The buffer RAM 7 is connected to the CD-ROM decoder 6 and temporarily stores the CD-ROM data input from the digital signal processing circuit 5 to the CD-ROM decoder 6 in block units. Since error correction is performed on one block of data, at least one block of CD-ROM data is required for processing by the CD-ROM decoder 6. Since the CD-ROM data is read sequentially, the buffer RAM 7 stores one block of CD-ROM data required for each process. Since the buffer RAM 7 needs to store a large amount of data, DRAM is used. The control microcomputer 8 is composed of a so-called one-chip microcomputer having a built-in ROM and RAM, and controls the operation of the CD-ROM decoder 6 according to a control program stored in the ROM. At the same time, the control microcomputer 8 temporarily stores the command data input from the host computer or the subcode data input from the digital signal processing circuit 5 in the built-in RAM. As a result, the control microcomputer 8 controls the operation of each part in response to the instruction from the host computer, and causes the CD-ROM decoder 6 to output the desired CD-ROM data to the host computer.

Next, a method of evaluating the jitter of the optical disk 2 in the CD recording / playback device 100 will be described.

The pickup unit 1, the optical disc 2, the pickup control unit 3 and the binarization circuit 4 are operated by the control microcomputer 8 in the same manner as the reproduction operation of the optical disc 2. However, the control microcomputer 8 stops the operation of the digital signal processing circuit 5 and the CD-ROM decoder 6, and the buffer RAM 7 operates differently from the playback operation.

The counter 10 is connected to the binarization circuit 4 and takes in the EFM signal output from the binarization circuit 4. Then, the counter 10 counts each clock period from the change point of the polarity of the EFM signal to the next change point by a counter clock having a frequency higher than that of the input EFM signal, and sequentially writes each count value to the buffer RAM 7. Since 1T of the EFM signal is about 230 ns in 1x speed operation of CLV operation with constant linear velocity, the clock period 3T of the EFM signal is about 690 ns (about 230 ns) when counting using a counter clock of 1 cycle 2 ns, which is higher frequency than that. Since it is × 3), the count value is ideally 345. Similarly, ideally, the count value of the clock period 4T of the EFM signal is 460, the count value of the clock period 5T is 575, and so on, and the count value of the clock period 11T is 1265. After performing such an operation on the data in a certain area recorded on the optical disk 2, the control microcomputer 8 analyzes each count value recorded in the buffer RAM 7 to evaluate the jitter.

Here, the operation of writing the measurement data of the count value from the counter 10 to the buffer RAM 7 composed of the DRAM in units of one word (16 bits) is performed as shown in FIG. Counter 10 outputs five commands of ACT (active), NOP (no operation), WRIT (write: input DATA1), PRE (precharge), and NOP (no operation) to the basic clock of buffer RAM7. This makes it possible to write one count value as measurement data. That is, in order to write one count value to the buffer RAM 7 as measurement data, a period of 5 cycles of the basic clock is required.

The writing of the measurement data in the CD recording / playback device 100 will be described in more detail with reference to FIG. The EFM signal is continuously taken into the counter 10 from the binarization circuit 4. The counter 10 resets the count value each time the polarity of the EFM signal changes from High to Low (or from Low to High), and is a counter clock with a higher frequency than the EFM signal. Count each EFM clock period in. Then, when the polarity of the EFM signal changes from "Low" to "High" (or from "High" to "Low"), the count value up to that point is held in the register in the counter 10 and the count value is held. To reset. Then, the next EFM clock period is counted again, and the count value of the immediately preceding EFM clock period held in the register is written to the buffer RAM7. The memory management circuit built into the counter 10 exclusively writes to the buffer RAM 7, and outputs a command for writing to the buffer RAM 7. In this way, the counter 10 simultaneously performs an operation of counting the current EFM clock period and an operation of writing the count value of the immediately preceding EFM clock period to the buffer RAM 7. In order for the counter 10 to write the count value of the immediately preceding EFM clock period to the buffer RAM 7 as measurement data, a period T1 of 5 cycles of the basic clock is required.

When the polarity of the EFM signal changes for the first time, the counter 10 resets the count value. The first EFM clock period is counted by the counter clock, and when the polarity of the EFM signal changes next time, the count value N1 is held in the register and the count value is reset.

Then, the counter 10 counts the second EFM clock period again with the counter clock, and writes the count value N1 held in the register during that period to the buffer RAM 7 for the period T1. Next, when the polarity of the EFM signal changes, the count value N2 is held in the register and the count value is reset. Then, the counter 10 counts the third EFM clock period again with the counter clock, and writes the count value N2 held in the register to the buffer RAM 7 in the period T1 during that period. By repeating such an operation, the count value of each EFM clock period is sequentially written to the buffer RAM7.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 11-167720</text></patcit>

<p> However, in the above-mentioned prior art, since a predetermined period T1 is required to write the count value of the immediately preceding EFM clock period to the buffer RAM 7, if the polarity of the EFM signal changes during that period, the counter 10 is changed to the buffer RAM 7. The count value to be written may be missing in the measurement data. In the example of FIG. 22, the polarity of the EFM signal changes while the count value N3 of the third EFM clock period is written from the counter 10 to the buffer RAM 7. Therefore, there is a problem that the measurement data of the count value N4 is not written to the buffer RAM7 and the jitter evaluation cannot be evaluated accurately.</p><p> In view of the above problems of the prior art, the present invention provides an optical disc recording / playback device and an optical disc evaluation method capable of accurately evaluating jitter by eliminating the omission of measurement data of each count value in the EFM clock period. The purpose.</p>

<p> The present invention irradiates an optical disk with a laser beam, receives the laser beam changed by a pit or a mark recorded on the optical disk, and converts the light amount of the received laser beam into an electric signal to generate a reproduction signal. In an optical disk recording / playback device that evaluates the optical disk, a binarization circuit that converts the reproduced signal into a binary signal sequence and a high-frequency counter clock that sets each clock period of the reproduced signal into a binary signal sequence into a high-frequency counter clock. It has a counter that counts by the above, and a temporary storage circuit that temporarily stores the count value in the counter and collectively transfers the stored count values to the measurement data storage area of the buffer RAM. It is a feature.</p>

<p> According to the present invention, it is possible to accurately evaluate jitter by eliminating the omission of measurement data of each count value during the EFM clock period.</p>

=== 1st Embodiment === &lt;Structure&gt; The CD recording / playing device 200 as an optical disk recording / / or playing device (hereinafter referred to as an optical disk recording / playing device) according to the 1st embodiment of the present invention has the configuration shown in FIG. Is. In the present embodiment, the circuits having the same functions as those of the prior art of FIG. 20 are designated by the same reference numerals, and the description thereof will be omitted.

In the CD recording / playback device 200, the counter 11 is connected to the binarization circuit 4 and captures the EFM signal output from the binarization circuit 4. Then, the counter 11 counts each clock period of the EFM signal by a counter clock having a frequency higher than that of the input EFM signal, and transfers each count value to the FIFO 12, which is a temporary storage circuit that temporarily stores the count value. The FIFO 12 is composed of registers and the like, and unlike the buffer RAM 7 composed of DRAM, it takes almost no time to transfer the measurement data. The FIFO 12 is composed of two register groups, a first register group and a second register group, and each register group can temporarily store four count values. Therefore, the FIFO 12 temporarily stores the count values of the four EFM clock periods input from the counter 11 in one register group, and collectively stores the four count values stored in the other register group into the buffer RAM7. Write. After performing such an operation on the data recorded on the optical disk 2 for a certain period of time, the control microcomputer 8 analyzes each count value recorded in the buffer RAM 7 to evaluate the jitter.

&lt;Writing of measurement data&gt; &lt;&lt; Normal mode &gt;&gt; Writing of measurement data in the CD recording / playback device 200 will be described in more detail with reference to FIG. The EFM signal is continuously taken into the counter 11 from the binarization circuit 4. The counter 11 resets the count value each time the polarity of the EFM signal changes from High to Low (or from Low to High), and is a counter clock having a higher frequency than the EFM signal. Count each EFM clock period in. Then, when the polarity of the EFM signal changes from "Low" to "High" (or from "High" to "Low"), the count value up to that point is held in the register in the counter 11 and the count value is set. Reset. Then, the next EFM clock period is counted again, and the count value of the immediately preceding EFM clock period held in the register is transferred to the FIFO 12. In this way, the counter 11 sequentially transfers the count value to the FIFO 12.

The FIFO 12 sequentially stores the count values transferred from the counter 11 in the first register group, and when four count values are stored in the first register group, the four count values are collectively used as measurement data in the buffer RAM7. Write to. While the FIFO 12 collectively writes the four count values stored in the first register group to the buffer RAM 7, the count values transferred from the counter 11 are temporarily stored in the second register group. Then, when four count values are stored in the second register group, the four count values are collectively written to the buffer RAM 7 as measurement data, and during that time, the count values transferred from the counter 11 are the first register group. Temporarily store in.

The memory management circuit built into the FIFO 12 exclusively writes the measurement data to the buffer RAM7, and outputs a command for writing to the buffer RAM7. In this way, the counter 11 counts each EFM clock period with the counter clock, and sequentially transfers the count value to the FIFO 12. The FIFO 12 temporarily stores each transferred count value, and writes the four count values to the buffer RAM 7 at once each time the four count values are stored.

When the polarity of the EFM signal changes for the first time, the counter 11 resets the count value. The first EFM clock period is counted by the counter clock, and when the polarity of the EFM signal changes next time, the count value N1 is held in the register and the count value is reset. Then, the counter 11 counts the second EFM clock period again with the counter clock, and transfers the count value N1 held in the register during that period to the FIFO 12. When the FIFO 12 receives the count value N1, the memory management circuit in the FIFO 12 returns the measurement data reception signal to the counter 11.

Next, when the polarity of the EFM signal changes, the count value N2 is held in the register and the count value is reset. Then, the counter 11 counts the third EFM clock period again with the counter clock, and transfers the count value N2 held in the register to the FIFO 12 during that period. When the FIFO 12 receives the count value N2, the memory management circuit returns the measurement data reception signal to the counter 11. By repeating this operation, when the counter 11 counts the fifth EFM clock period again with the counter clock, the count value N4 held in the register during that period is transferred to the FIFO 12. Then, when the FIFO 12 receives the count value N4, the memory management circuit returns the reception signal of the measurement data to the counter 11, but since the FIFO 12 stores all four count values that can be stored, they are temporarily stored. Write the four count values to buffer RAM7 at once.

While the FIFO 12 is writing the count value to the buffer RAM7 in a batch, even if the EFM clock period counted by the counter 11 contains a short one, if the total of the four EFM clock periods to be counted is long, the count value is calculated. All measurement data can be written to the buffer RAM7. For example, in Figure 2, the 7th EFM clock period is shorter than the time required to write one measurement data to buffer RAM7, but the sum of the 5th to 8th EFM clock periods buffers RAM7 with count values N1 to N4. Since it is longer than the time required to write to, all the measurement data of the count value can be written to the buffer RAM7.

&lt;&lt; Burst mode &gt;&gt; Here, the measurement data can be written from the FIFO 12 to the buffer RAM 7 at a higher speed by using the burst mode as shown in FIG. The burst mode is a write operation mode in which a plurality of data are collectively written to a synchronous DRAM or the like. ACT (active), NOP (no operation), WRIT (write: input DATA1), NOP (no operation: input DATA2), NOP (no operation: input DATA3), NOP for the basic clock of buffer RAM7 (No operation: input DATA4), PRE (precharge), NOP (no operation) 8 commands are output by FIFO12 to write 4 count values as measurement data at once. That is, in order to write four count values, the period T2 of eight cycles of the basic clock is sufficient.

When the measurement data is written to the buffer RAM 7 using the burst mode of FIG. 3, the measurement data is written in the CD recording / playback device 200 as shown in FIG. At this time, since the period T2 is significantly shorter than the total time of the four periods T1, the FIFO 12 can write the count value to the buffer RAM 7 with a margin.

In addition to the burst mode illustrated in FIG. 3, another write mode may be used as long as it is a method for efficiently writing a plurality of measurement data to the buffer RAM 7 in a short time.

&lt;&lt; Specific example &gt;&gt; Next, the writing of the measurement data in the present embodiment will be specifically described. FIG. 5 is an example of measurement data. The counter 11 counts each EFM clock period as a count value. At the same time, the counter 11 determines whether it is at the High level or the Low level for each EFM clock period. Further, the counter 11 determines whether or not the measurement data is normally transferred to the FIFO 12, and outputs an error signal to the FIFO 12 if any abnormality is found. The measurement data transferred from the counter 11 to the FIFO 12 is a total of 16 bits, with 14 bits assigned to the count value, 1 bit assigned to the polarity data indicating the High / Low level, and 1 bit assigned to the error presence / absence information. .. The first measurement data has a count value of 803, so the data is 7T (the closest ideal value is a 7T count value of 805). The second measurement data has a count value of 916, so the data is 8T (the closest ideal value is an 8T count value of 920). When the level for each EFM clock period is "Low", the polarity data is set to "0", and when the level is "High", the polarity data is set to "1". Then, in the case of normal measurement data, the error signal is set to "0", and in the case of abnormal measurement data, the error signal is set to "1".

By the way, in FIG. 5, the measurement data of the 1st to 3rd EFM clock periods are normally transferred from the counter 11 to the FIFO 12. However, the 5th and 6th EFM clock periods are abnormally shorter than 1T (ideal value of 1T is 115) due to causes such as poor pit formation and noise during reproduction. Therefore, the 4th and 5th measurement data to be transferred while the counter 11 is counting the 5th and 6th EFM clock periods cannot be normally transferred to the FIFO 12. That is, the FIFO 12 cannot receive the fourth and fifth measurement data, and the FIFO 12 does not output the reply of the measurement data reception signal to the counter 11. At this time, since the counter 11 has not received the reply of the reception signal of the fourth measurement data from the FIFO 12, it tries to add an error signal to the next fifth measurement data and transfer it to the FIFO 12. Similarly, since the counter 11 has not received the reply of the reception signal of the fifth measurement data from the FIFO 12, the error signal is also added to the next sixth measurement data and transferred to the FIFO 12.

In this way, the measurement data in the 4th and 5th EFM clock periods are not normally transferred to FIFO12, the measurement data is lost, and the measurement data written in the buffer RAM is as shown in FIG. In FIG. 6, 16-bit information written to each address of the buffer RAM 7 is described separately for the count value, the polarity data indicating High / Low, and the error signal for the sake of clarity. That is, the measurement data of the 1st to 3rd and 6th and subsequent EFM clock periods are written to the buffer RAM 7, but an error signal is added to the 6th measurement data. Therefore, it is presumed that there is missing measurement data that was not written immediately before the measurement data to which the error signal was added. Therefore, when evaluating jitter, the missing measurement data and the measurement data to which the error signal is added are estimated. By excluding the measurement data before and after that, more reliable jitter evaluation can be performed. In the example of FIG. 6, by excluding the measurement data at addresses 3 to 5 of the buffer RAM 7 from the evaluation target, more reliable and accurate jitter evaluation can be performed.

In the above embodiment, the number of count values that can be stored in the FIFO 12 is four, but the number is not limited to four if there are a plurality of count values.

&lt;Jitter evaluation&gt; In this way, as shown in FIG. 7, the measurement data of the EFM clock period is written to the measurement data storage area 7a of the buffer RAM 7. A part of the buffer RAM 7 is allocated to the measurement data storage area 7a. When the writing of the measurement data to the buffer RAM 7 is completed, the control microcomputer 8 reads the measurement data from the buffer RAM 7 and performs various statistical calculations. Then, the intermediate result of the statistical calculation is temporarily stored in the statistical data storage area 7b, which is an area different from the measurement data storage area 7a of the buffer RAM 7, and the data stored in the statistical data storage area 7b each time the statistical calculation is advanced. Will be updated.

For example, the EFM signal can be divided into "High" and "Low", and the frequency of appearance for each count value can be obtained by statistical calculation. Each address of the statistical data storage area 7b is used as an area for storing the appearance frequency of each count value of the pit or land, and the control microcomputer 8 calculates which count value the measurement data of the measurement data storage area 7a is and uses that count value. The data of the address of the corresponding statistical data storage area 7b is added. When this is performed for all the measurement data in the measurement data storage area 7a, the data finally stored in each address in the statistical data storage area 7b shows the appearance frequency for each count value of the pit or land. .. When the host computer reads the statistical calculation result from the statistical data storage area 7b of the buffer RAM 7 through the control microcomputer 8 and graphs it, the result is as shown in FIG. From this figure, it is possible to quantitatively evaluate the degree of blurring of the reproduced signal of the optical disc, which is called jitter.

It is also possible to evaluate jitter under various conditions. For example, as shown in FIG. 9, for a pit having a count value within the range of 3T during statistical calculation, the first condition that the data of the immediately preceding land is 4T and the data of the immediately following land is 8T. In the case of, it is assumed that the frequency of appearance for each count value is 2.88T on average as in 3T (1). Then, for a pit having a count value within the range of 3T at the time of statistical calculation, in the case of the second condition that the data of the immediately preceding land is 8T and the data of the immediately following land is 4T, each count value is changed. It is assumed that the frequency of appearance of is 3.08T on average as shown in 3T (2) in Fig. 9. In this way, even with the same 3T pit jitter, there is a difference depending on the conditions of the front and rear lands.

Therefore, when forming a pit on the optical disk 2 and recording data, the timing of laser irradiation for forming the pit is delayed by 0.12T under the first condition even with the same 3T. On the contrary, when recording on the optical disc 2, the timing of laser irradiation for pit formation is advanced by 0.08T under the second condition even if the same 3T is used. As a result, the jitter of the entire 3T can be reduced quantitatively. Jitter can be reduced by adjusting such things under various conditions. In particular, when recording data on a recordable optical disc such as a CD-R / RW at high speed, jitter greatly affects the quality of the data recorded on the disc. Therefore, high-quality recording can be achieved by recording predetermined data on an optical disc at a high double speed in advance, evaluating the recording quality, and then adjusting the laser irradiation timing for each condition as described above.

In addition, by evaluating the jitter by changing the threshold condition in the binarization circuit or changing the focus condition of the optical pickup, it is possible to write data to the optical disc under the optimized conditions for these conditions as well. become able to.

Further, as another jitter evaluation, it is evaluated whether there is a problem in the optical disc itself by evaluating how the jitter is depending on the physical position such as the inner peripheral portion, the outer peripheral portion, or a specific part of the optical disc. You can also do it. Further, in the present invention, since the measurement data of the EFM signal can be written to the buffer RAM at high speed, the jitter evaluation due to the double speed of the reproduction operation can be evaluated by setting the reproduction operation at a high double speed instead of the 1x speed at the time of jitter evaluation. It is possible.

Further, the evaluation of jitter is not limited to the histogram, and other statistical operations such as calculation of mean value and calculation of variance value may be used.

Although the optical disc recording / playback device using the CD recording / playback device has been described in the present embodiment, the present invention is of course effective for other types of optical disc recording / playback devices such as DVDs.

Further, in the above description, the case of CLV operation in which the linear velocity is constant has been described, but even in the case of CAV operation in which the angular velocity is constant, the evaluation of the optical disk is correctly performed by applying a predetermined correction to the count value. It can be carried out. That is, since the linear velocity is expressed by the product of the angular velocity and the radial distance of the pickup, in the case of CAV operation, the count value written in the buffer RAM is multiplied by the radial distance of the pickup to correct the correction. How to do it.

Further, for example, there is also a method of generating a high-frequency counter clock from a PLL circuit that generates a clock synchronized with a bit of a digital signal read from an optical disk to obtain a high-frequency counter clock depending on the linear velocity. In the case of a DVD, a method of generating a high frequency counter clock from a PLL circuit that generates a clock synchronized with a wobble signal or an LPP (Land Pre Pit) signal may be used.

Although the first embodiment of the present invention has been described above, this first embodiment is for facilitating the understanding of the present invention, and is not for limiting the interpretation of the present invention. The present invention can be modified / improved without departing from the spirit thereof, and its equivalents are also included. In the following, as embodiments other than the first embodiment of the present invention, the second embodiment of the present invention and the third embodiment of the present invention will be described.

=== Second Embodiment === &lt;Preformatting DVD-R / RW Media&gt; A groove wobble and LPP, which are preformatting methods for DVD-R / RW media, will be described with reference to FIG.

For DVD-R / RW media, a groove track (recording groove), which is a spirally formed track for recording data, and a land track in which an LPP is formed in advance between adjacent groove tracks are set. ing. The groove track is undulated in advance at regular intervals. The frequency of this swell (wobbling frequency) is about 140.6 KHz at the standard speed of DVD-R / RW, and by multiplying this wobbling frequency by 186, a clock signal corresponding to the unit length of the mark can be obtained. That is, the period of one wobbling frequency component is "186T" when the standard speed "1 / 26.16MHz" of DVD-R / RW is expressed by "1T".

The data recorded in the groove track has a plurality of ECC (Error Correcting Code) blocks which are error correction units. One ECC block is composed of 16 sectors (sectors 0 to 15), and each sector is composed of 26 frames (frames 0 to 25).

Of the 26 frames contained in one sector, the even-numbered frames (frames 0, 2, ..., 24) are called EVEN frames, and the odd-numbered frames (frames 1, 3, ..., 25) are called EVEN frames. It is called an ODD frame. Of the 8 wobbles corresponding to the EVEN frame or ODD frame, the LPP code is placed at the apex position of the first 3 wobbles. Data is recorded on the DVD-R / RW media in synchronization with the first bit of the LPP code and the data sync code included in the frame.

In addition, one sector contains 13 LPP codes, and based on these 13 LPP codes, a 1-bit LPP sync code that serves as reference information for the data recording position and a 12-bit LPP sync code that serves as physical address information. LPP information and is decoded. Here, by using the decoding result of the 1-bit LPP sync code, various sink signals indicating that they are at the beginning of the ECC block, sector, or frame (block sync signal (described later), sector sync (Sector Sync)) are used. It is possible to generate signals (Frame Sync signals). Further, by using the decoding result of 12-bit LPP information, it is possible to acquire the block address, sector address, and frame address.

&lt;Preformatting DVD + R / RW (Registered Trademark) Media&gt; ADIP (ADdress In Pre groove), which is a preformatting method for DVD + R / RW media, will be described with reference to FIG. In the ADIP method, the reference information and physical address information of the data recording position do not use LPP in the case of DVD-R / RW media, but correspond to the phase modulation pattern of the wobbling frequency component of the groove track in advance. It is a method of being recorded.

In DVD + R / RW media, groove tracks are pre-wound at regular intervals. The period of one wobbling frequency component is "32T" when the standard speed "1 / 26.16MHz" of DVD + R / RW is represented by "1T".

Further, the DVD + R / RW media has a plurality of ECC blocks which are error correction units. One ECC block is composed of 16 sectors, and one sector is composed of 26 sink frames. Here, 93 wobbles are included in the 2 sync frames, and the sync code indicating the beginning of the 2 sync frames and the ADIP bit indicating the physical address information are included by the phase modulation pattern in the first 8 wobbles.

Here, the sync code will be described in detail. For example, as shown in FIG. 11, it is assumed that the phase of the wobbling frequency component between the 3rd cycle and the 4th cycle is switched by 180 ° in the first sink frame of the first sector in one ECC block. In this case, the sync code indicating the beginning of the sync frame is decoded by using the wobbling frequency components for a total of 4T from 0T to 3T. Then, by using the decoding result of such a sync code, various sync signals (block sync signal, sector sync signal, frame sync signal, which will be described later) indicating that the ECC block, sector, and the beginning of the frame are generated can be generated. Is possible.

In addition, 13 ADIP bits are included in one sector. Here, since one ECC block is composed of 16 sectors, 208 ADIP bits are included in one ECC block. In addition, 1 ADIP word is composed of 52 bits of ADIP bits contained in 4 sectors. Then, the block address, sector address, and frame address can be obtained from the decoding result of this 1ADIP word.

&lt;Configuration / Operation&gt; The configuration / operation of the DVD recording / playback device 300 as the optical disc recording / playback device according to the second embodiment of the present invention will be described with reference to FIG. 12 with reference to the timing chart of FIG. 13 as appropriate.

In the second embodiment of the present invention, the circuits having the same functions as those of the first embodiment of the present invention shown in FIG. 1 include a pickup 301, a pickup control circuit 303, a binarization circuit 304, and a digital signal processing circuit 306. The buffer RAM 307, the control microcomputer 308, and the FIFO 313. Since the optical disk 302 is a DVD medium (DVD ± R / RW, DVD-RAM, DVD-ROM, etc.), the CD-ROM decoder 6 shown in FIG. 1 is unnecessary.

The digital signal processing circuit 306 is equipped with a DVD decoder function that performs 8-16 demodulation processing, descramble processing, ECC block decoding processing, and the like based on the DVD standard. Therefore, the digital signal processing circuit 306 performs decoding processing for DVD on the EFMPlus signal (8-16 modulated signal) supplied from the binarization circuit 304 to bit the MPEG video, audio, subpicture, etc. Play stream data. The buffer RAM 307 is a buffer memory used for the DVD decoding function of the digital signal processing circuit 306.

Next, a characteristic configuration / operation of the second embodiment of the present invention will be described.

The pickup 301 reads out the preformat information from the optical disc 302, which is a DVD medium, in parallel with reading out the data corresponding to the pits or marks recorded on the groove track. For example, in the case of DVD-R / RW, the pre-groove wobble signal including LPP information is read, and in the case of DVD + R / RW, the pre-groove wobble signal including ADIP information is read.

The LPP / ADIP decoder 305 is supplied with a wobble signal including LPP information or ADIP information as preformat information from the pickup 301. Then, the sync detection unit 311 detects the sync code included in the wobble signal, and also blocks the block sync signal indicating the beginning of each ECC block corresponding to the detected sync code and the frame sync indicating the beginning of each frame. A signal is generated and supplied to the counter control circuit 314. Note that FIGS. 13A and 13B are examples of block / frame signals supplied from the LPP / ADIP decoder 305 to the counter control circuit 314.

Further, the LPP / ADIP decoder 305 decodes the sector / frame address indicating the physical address on the optical disk 302 by the LPP / ADIP decoding process for the wobble signal supplied from the pickup 310, and the sector / frame address storage register 310. In addition to being stored in, it is supplied to the counter control circuit 314 in synchronization with the block / frame sync signal described above. Note that FIGS. 13 (c) and 13 (d) are examples of sector / frame addresses supplied from the LPP / ADIP decoder 305 to the counter control circuit 314, and the counters are synchronized with the falling edge of the block / frame sync signal. It is assumed that the control circuit 314 is sequentially supplied. Further, the sector / frame address stored in the sector / frame address storage register 310 may be acquired by the control microcomputer 308 by an interrupt or polling process.

The counter control circuit 314 is binarized based on the block / frame sync signal and sector / frame address supplied from the LPP / ADIP decoder 305 and the count start address and count end address supplied from the control microcomputer 308. Controls the start / end of the counting operation for the EFM Plus signal supplied from the circuit 304. That is, the counter control circuit 314 counters each clock period of the EFM Plus signal corresponding to the desired partition region on the optical disk 302 specified by the sector / frame address (and block address) decoded by the LPP / ADIP decoder 305. It is a control circuit for counting in 312. Further, the counter control circuit 314 identifies the clock period of the EFMPlus signal to be counted based on the sector / frame address based on the block / frame sync signal supplied from the LPP / ADIP decoder 305, and counts at the counter 312. It synchronizes the operation with.

Specifically, the sector / frame address (counting start address) at which the counting operation at the counter 312 starts and the sector / frame address at which the counting operation at the counter 312 ends (counting start address) from the control microcomputer 308 to the counter control circuit 314 The count end address) and are supplied in advance. The count start address is stored in the start address storage register 315, and the count end address is stored in the end address storage register 316.

The control microcomputer 308 suspends the counter control circuit 314 by supplying a sampling trigger (Sampling Trigger) signal to the counter control circuit 314 before the block sync signal of the target ECC block to be counted is generated. Switch from state to operating state. Note that FIG. 13 (e) is an example of a sampling trigger signal. That is, since the counter control circuit 314 is in a hibernate state until the sampling trigger signal is supplied from the control microcomputer 308, it can contribute to the reduction of power consumption by that amount.

When the counter control circuit 314 is in the operating state by the sampling trigger signal, the counter control circuit 314 first switches the switch 317 to the start address storage register 315 side. Then, the block sync signal relating to the target ECC block and the frame sync signal relating to the first frame of the first sector of the ECC block are supplied from the LPP / ADIP decoder 305, and the block sync signal is sequentially supplied from the LPP / ADIP decoder 305 in the comparator 318. The sector / frame address to be created is compared with the count start address stored in the start address storage register 315.

If the results of the comparison in the comparator 318 match, the counter control circuit 314 asserts the Sampling Enable signal. The sampling enable signal is a control signal for starting the counting operation of the counter 312, and is, for example, a signal for switching between valid / invalid of the counter clock in the counter 312. That is, the counter clock of the counter 312 is invalid (stopped) until the sampling enable signal is asserted by the counter control circuit 314, so that the counting operation is stopped, which can contribute to the reduction of power consumption.

Note that FIG. 13 (f) is an example of a sampling enable signal, and when the target sector / frame is sector 0 / frame 1, the falling edge of the frame sync signal indicating the beginning of the sector 0 / frame 1 is shown. Causes the sampling enable signal to be asserted (from L level to H level). Then, when the sampling enable signal is asserted, as shown in FIG. 13 (g), the counter clock in the counter 312 becomes valid, and each clock period of the EFM Plus signal is counted. The temporary storage of the count value in the FIFO 313 and the writing of the plurality of count values to the buffer RAM 307 collectively are the same as in the case of the first embodiment described above.

Further, the counter control circuit 314 switches the switch 317 to the end address storage register 316 side after asserting the sampling enable signal. Then, in the comparator 318, the sector / frame address sequentially supplied from the LPP / ADIP decoder 305 is compared with the count end address stored in the end address storage register 315. When the results of the comparison in the comparator 318 match, the counter control circuit 314 negates the sampling enable signal. As a result, at the counter 312, the counter clock is invalidated again and the counting operation is stopped.

&lt;Other Examples&gt; &lt;&lt; Control of Writing to Buffer RAM &gt;&gt; In the second embodiment described above, the counter operation of the counter 312 is started / stopped by the sampling enable signal, but as another method, The counter clock is always in the operating state to continue the counting operation, the assertion of the sampling enable signal starts the writing of the count value to the buffer RAM307, and the negate of the sampling enable signal ends the writing of the count value to the buffer RAM307. You may adopt a method such as letting.

In this case, the counter 312 is substantially the same as the counting operation being controlled by the sampling enable signal supplied from the counter control circuit 314 as in the case of the second embodiment described above. Therefore, the control of the counting operation of the counter 312 by the counter control circuit 314 according to the present invention includes the embodiment of starting / ending the writing of the count value to the buffer RAM 307 as described above.

&lt;&lt; Counter control by block sync signal &gt;&gt; When the optical disc recording / playback device receives a playback operation command of the optical disc 302 from the host computer, it is on the optical disc 302 corresponding to the 1 ECC block immediately before the 1 ECC block to be played back. Since the area of 1 ECC block is wider than the sector area and frame area, moving the optical pickup 301 to the ECC block area of the control microcomputer 308 can be easily performed by the existing firmware incorporated in the control microcomputer 308. Is.

Therefore, in the second embodiment described above, when the optical disc recording / playback device performs jitter evaluation in units of 1 ECC blocks, it detects the block sync signal of the first 1 ECC block to be evaluated for jitter, and uses the block sync signal. The counting operation of the counter 312 may be started. In this case, since the optical disc recording / playback device does not need to acquire the block address, it is not necessary to provide the sector / frame address register 310 shown in FIG. Further, the LPP / ADIP decoder 305 shown in FIG. 12 is configured to receive the signal decoded by the digital signal processing circuit 306, not from the pickup 301.

&lt;&lt; CD recording / playback device &gt;&gt; In the second embodiment described above, the DVD recording / playback device has been described, but of course, it can also be implemented as a CD recording / playback device. In this case, the configuration of the DVD recording / playback device 300 shown in FIG. 12 may be replaced with that of the CD recording / playback device as shown in FIG. For example, the LPP / ADIP decoder 305 will be replaced with an ATIP (Absolute Time In Pre groove) decoder (not shown), which is a preformatting method for CD media.

Here, the ATIP is an address as absolute time information preformatted in the groove track of the CD media. A 1ATIP frame corresponding to 1/75 second is composed of the following 42 bits as shown in FIG. The first 4 bits are a sync code that indicates the start of a 1ATIP frame. That is, when the optical disc recording / reproducing device reproduces 1ATIP, the start of the 1ATIP frame is recognized by this sink code. The 24 bits from the 5th to the 28th bits are ATIP addresses corresponding to the 1ATIP frame, and are composed of Minute (minutes), Second (seconds), and Frame (frames). The 14 bits from the 29th bit to the 42nd bit are the CRC (Cyclic Redundancy Code) code as the error detection code.

Therefore, in the CD recording / playback device as the second embodiment, the ATIP decoder detects the sink code of each ATIP frame included in the wobble signal based on the wobble signal including the ATIP information supplied from the pickup. A sync signal indicating that the sync code has been detected is generated, and the ATIP address is decoded. Further, in this case, the counter control circuit controls the counter to count each clock period of the EFM signal corresponding to the desired partition area on the optical disk specified by the ATIP address decoded by the ATIP decoder. ..

&lt;&lt; Sync code recorded as pit / mark data &gt;&gt; In the second embodiment described above, the position information on the optical disk 302 is the physically predetermined preformat information (LPP information, ADIP information) of the optical disk 302. , Wobble information), a method of obtaining from pit data or mark data recorded on the optical disc 302 may be adopted.

For example, in a DVD standard such as a DVD-ROM, as described above, one ECC block has 16 sectors, and header information indicating an address is added to each sector. Further, as shown in FIG. 15, there are 26 frames in one sector, and at the beginning of each frame, any of the sync codes SY0 to SY7 is recorded as a pit or a mark according to the order of the frames. .. Therefore, the optical disc recording / playback device detects the sector address and the frame address by detecting the appearance order of the sink codes SY0 to SY7, regardless of the physically predetermined preformat information of the optical disc 302. May be.

&lt;Example of Effect&gt; As described above, according to the second embodiment of the present invention, the EFM / EFM Plus signal corresponding to the desired partition region on the optical disc is based on the address information obtained from the preformat information of the optical disc. Since each clock period can be specified for jitter evaluation, it is possible to improve the reliability of jitter evaluation. Further, according to the second embodiment of the present invention, the specification of the clock period for jitter evaluation and the counting operation in the counter 312 are synchronized based on the address information and the sync code obtained from the preformat information of the optical disk. be able to. This synchronization process is performed independently of the control microcomputer 308 that performs asynchronous control (interrupt / polling) for the LPP / ADIP decoder 305, the counter control circuit 314, and the like. That is, according to the second embodiment of the present invention, the specification of the clock period to be evaluated for jitter and the counting operation at the counter can be synchronized with high accuracy without depending on the control microcomputer. As a result, the jitter evaluation is performed. The reliability of the can be further improved.

=== Third Embodiment === &lt;Preformatting DVD-RAM / ROM Media&gt; As shown in Fig. 16, in the DVD-RAM / ROM media, a ReWritable area in which user information can be rewritten and physical on the media. Emboss areas in which header information such as addresses are recorded as Embossed-Pit are arranged alternately. The ReWritable region, which is a land track or a groove track, is wobbled at regular intervals. By measuring this wobbling cycle, the start position of the next Embossed region can be grasped.

Embossed-Pit is recorded for each sector by a method called CAPA (Complimentary Allocated Pit Addressing). The CAPA method is a method of recording Embossed-Pit by shifting the embossed-Pit by 1/2 track with respect to the land track or groove track which is the recording track. The address for groove tracking can be obtained from the Embossed-Pit information (headers-1, 2) on one side, and the address for land tracking can be obtained from the Embossed-Pit information (headers-3, 4) on the other side. it can.

&lt;Structure / Operation&gt; The configuration / operation of the DVD recording / playback device 500 as the optical disc recording / playback device according to the third embodiment of the present invention will be described with reference to FIG. 17 with reference to the timing chart of FIG. 18 as appropriate.

In the third embodiment of the present invention, the circuits having the same functions as those of the first embodiment of the present invention shown in FIG. 1 and the second embodiment of the present invention shown in FIG. 12 are the pickup 501 and the pickup control circuit 503. , Binarization circuit 504, digital signal processing circuit 506, buffer RAM 507, control microcomputer 508, counter 512. Since the optical disk 502 is a DVD-RAM / ROM medium, the CD-ROM decoder 6 shown in FIG. 1 is unnecessary.

Further, similarly to the second embodiment of the present invention described above, the digital signal processing circuit 506 performs decoding processing for DVD on the EFMPlus signal (8-16 modulated signal) supplied from the binarization circuit 504. This plays back bitstream data such as MPEG video, audio, and subpictures. In this case, the buffer RAM 507 is a buffer memory used for the DVD decoding function of the digital signal processing circuit 506.

Next, a characteristic configuration / operation of the third embodiment of the present invention will be described. The pickup 501 reads data corresponding to the pits or marks recorded on the groove track from the optical disc 502, which is a DVD-RAM medium. At this time, since the CAPA method Embossed-Pit is pre-recorded in the Emboss area on the optical disk 502, the data read from the optical disk 502 includes the Embossed-Pit information.

Here, in the Embossed area, the Embossed-Pit is recorded with the position shifted by 1/2 track from the groove / land track in the ReWritable area. Therefore, in order to improve the reliability of the jitter evaluation, it is necessary to divide the jitter evaluation into an Emboss region and a ReWritable region. Therefore, in the third embodiment of the present invention, the following CAPA decoder 505 is newly provided.

In the CAPA decoder 505, the data read from the optical disk 502 by the optical pickup 501, and thus the EFMPlus signal supplied from the binarization circuit 504 to the counter 512 and to be counted, is the Embossed-Pit information in the Emboss area or the ReWritable area. It is for determining whether the signal corresponds to any of the user information of. Further, when the CAPA decoder 505 determines that the EFMPlus signal corresponds to the Embossed-Pit information, the header signal (header signal) for indicating that the count value counted by the counter 512 is the count value corresponding to the Embossed area. Header Signal) is generated and supplied to FIFO513.

FIG. 18 shows an example of a header signal. Note that the header signal shown in FIG. 18 may be out of synchronization with the data determined to be either Embossed-Pit information or user information by the CAPA decoder 505 and the data to be counted by the counter 512. Therefore, it is treated as Embossed-Pit information of Emboss area including user information of ReWritable area near the boundary with Emboss area.

Similar to the case of the first or second embodiment of the present invention, the FIFO 513 temporarily stores the count values sequentially transferred from the counter 512, and collectively stores the count values temporarily stored for a predetermined number of minutes in the buffer RAM507. It is written to the measurement data storage area 7a of. Note that the FIFO 513 identifies that, when the header signal is supplied from the CAPA decoder 505, the count value sequentially transferred from the counter 512 and temporarily stored is the count value corresponding to the Emboss area. At this time, the FIFO 513 associates the count value temporarily stored for a predetermined number of minutes with a code (CAPA ERROR described later) indicating that the count value corresponds to the Emboss area, and measures the measurement data of the buffer RAM 507. It is assumed that the data is written to the storage area 7a all at once.

FIG. 19 is an example of data written in the buffer RAM 507 according to the third embodiment of the present invention. Similar to the example shown in FIG. 5, the count value is a value obtained by counting each EFM Plus clock period in the counter 512, and High / Low is the polarity data of the EFM Plus clock period. Further, the "count ERROR" is an error code for identifying whether or not the control microcomputer 508 has normally transferred the measurement data from the counter 512 to the FIFO 513. For example, if it is normal, "0". ", In case of abnormality, set to" 1 ".

Further, the "CAPA ERROR" is an error code for the control microcomputer 508 to identify whether or not the EFMPlus clock period counted by the counter 512 is a period corresponding to the Emboss area. For example, if the EFMPlus clock period counted by the counter 512 is the period corresponding to the header signal generated by the CAPA decoder 505, including the period corresponding to the Emboss region, it is set to "1", otherwise it is set to "1". In the case of, set to "0".

&lt;Other Examples&gt; In the third embodiment described above, the area to be separated from the area where user information is recorded on the optical disk (for example, the ReWritable area) is limited to the Emboss area of the DVD-RAM media described above. It may be a specific area where special data according to various optical disc standards is recorded, such as Embossed-Pit, which records by shifting the position by 1/2 track with respect to the groove / land track. ..

Further, in the third embodiment described above, when the jitter evaluation of the Emboss region is not performed, the counter clock supplied to the counter 512 is invalidated and the counter 512 is set when the CAPA decoder 505 determines that the information is Embossed-Pit information. You may stop it.

&lt;Example of effect&gt; After the writing of various data to the buffer RAM 507 as described above is completed, the control microcomputer 508 analyzes each count value written to the buffer RAM 507 and evaluates the jitter. In addition, "CAPA ERROR" is written in the buffer RAM 507 in association with each count value. Therefore, the control microcomputer 508 can perform the jitter evaluation of the Emboss area and the ReWritable area separately based on the "CAPA ERROR" written in the buffer RAM 507. That is, according to the third embodiment of the present invention, the reliability of jitter evaluation can be further improved.

<figref num="1">It is a block diagram which shows 1st Embodiment of the optical disk recording / reproduction apparatus by this invention.</figref><figref num="2">It is explanatory drawing of the measurement data writing in 1st Embodiment of this invention.</figref><figref num="3">It is explanatory drawing of the writing operation of the buffer RAM in 1st Embodiment of this invention.</figref><figref num="4">It is explanatory drawing of the measurement data writing in 1st Embodiment of this invention.</figref><figref num="5">This is an example of measurement data according to the first embodiment of the present invention.</figref><figref num="6">It is explanatory drawing of the measurement data written in the buffer RAM in 1st Embodiment of this invention.</figref><figref num="7">It is explanatory drawing of the data storage area in the buffer RAM in 1st Embodiment of this invention.</figref><figref num="8">This is an example of statistical calculation of measurement data according to the first embodiment of the present invention.</figref><figref num="9">This is another example of statistical calculation of measurement data according to the first embodiment of the present invention.</figref><figref num="10">It is explanatory drawing of the preformat of the optical disk which adopted the LPP method.</figref><figref num="11">It is explanatory drawing of the preformat of the optical disk which adopted the ADIP method.</figref><figref num="12">It is a block diagram which shows the 2nd Embodiment of the optical disk recording / reproduction apparatus by this invention.</figref><figref num="13">It is explanatory drawing of the setting operation of the measurement data sampling section in 2nd Embodiment of this invention.</figref><figref num="14">It is explanatory drawing of the preformat of the optical disk which adopted the ATIP method.</figref><figref num="15">It is a figure explaining the data format of one sector of a DVD standard.</figref><figref num="16">It is explanatory drawing of the preformat of the optical disk which adopted the CAPA method.</figref><figref num="17">It is a block diagram which shows the 3rd Embodiment of the optical disk recording / reproduction apparatus by this invention.</figref><figref num="18">It is explanatory drawing of the setting operation of the measurement data sampling section in 3rd Embodiment of this invention.</figref><figref num="19">This is an example of measurement data in the third embodiment of the present invention.</figref><figref num="20">It is a block diagram of the conventional optical disk recording / reproduction apparatus.</figref><figref num="21">It is explanatory drawing of the writing operation to the buffer RAM of the conventional optical disk recording / reproduction apparatus.</figref><figref num="22">It is explanatory drawing of the measurement data writing of the conventional optical disk recording / reproduction apparatus.</figref>

Code description

1,301,501 Pickup 2,302,502 Optical disk 3,303,503 Pickup control circuit, 4,304,504 Binarization circuit 5,306,506 Digital signal processing circuit, 6 CD-ROM decoder 7,307,507 Buffer RAM 8,308,508 Control microcomputer 10,11,312,512 counter, 12,313,513 FIFO 100,200 CD recording / playback device 300,500 DVD recording / playback device 305 LPP / ADIP decoder 310 Sector / frame address storage register 311 Sink detector, 314 Counter control circuit 315 Start address storage register, 316 End address storage register 317 Switch, 318 Comparer