Semiconductor memory device

The present invention relates to a semiconductor storage device having a soft error correction function.

Dynamic random access memory (hereinafter referred to as DRAM) is widely used as a low-cost, large-capacity main memory mainly in computers and the like. The basic structure of the DRAM memory cell currently used is composed of one transistor and one capacitor.

When a cosmic ray having an electric charge such as an α ray reaches the ground and collides with the capacitor, the amount of electric charge stored in the capacitor changes. On the other hand, when uncharged cosmic rays such as neutrons collide with a semiconductor substrate having DRAM, the amount of charge stored in the capacitor changes due to the influence of the ions generated at that time, and the stored data is lost. May be done.

The malfunction of the memory circuit caused by such a phenomenon is temporary or accidental, and is called a soft error, which is distinguished from a hard error that causes fatal damage to the memory circuit. Soft errors that occur at normal frequencies can be sufficiently dealt with by providing an error correction function in the DRAM alone or in the system.

As a conventional error correction method, an error collection code (hereinafter referred to as ECC) circuit is mainly used. For example, 64-bit data to be stored is set as one unit, and it is stored together with 8-bit redundant data obtained by logical calculation from this data, and out of the total 72-bit data, data errors of up to 2 bits are logical. This is a method that enables correction by calculation.

Further, even when an error correction circuit such as ECC is used, a device such as a test circuit and a test method for recognizing an error has been proposed. (See, for example, Patent Document 1.).

FIG. 10 is an image diagram when the conventional error correction method by ECC is performed. For example, an additional cell block 70 for parity is added for eight columns. In the conventional ECC method, due to restrictions, 72 (64 + 8) block configurations must be used as a unit. Therefore, the area increase rate is 72/64 + 5.882%. That is, it becomes 9/8 times and the chip area increases. Therefore, the cost of the product increases.

In the DRAM market, where price competition is fierce, it is necessary to reduce the chip area as much as possible, increase the number of chips per semiconductor substrate, and reduce costs. Therefore, it is required to suppress an increase in the chip area in DRAM, enable correction of soft errors, and improve the reliability of DRAM.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2003-157696 (Page 10, Fig. 1)</text></patcit>

<p> The present invention suppresses an increase in the chip area in a semiconductor storage device, enables correction of soft errors, and enhances reliability in the operation of the semiconductor storage device.</p>

<p> In order to solve the above problems, the first aspect of the present invention is a memory cell array in which memory cells are arranged in the row direction and the column direction, a row decoder circuit, a column decoder circuit, and a memory in the column direction as a semiconductor storage device. A sense amplifier corresponding to the cell, a read / write circuit corresponding to the memory cell in the column direction, a calculation means for calculating the parity value of each row and the parity value of each column in the memory cell array, and the parity value are used. A storage means for storing, a checking means for checking the occurrence of a parity error with respect to the parity value, and an identification means for identifying a memory cell in which an error has occurred based on the information of the row and column in which the parity error has occurred. It is characterized by having a correction means for correcting the memory cell in which an error has occurred.</p><p> A second aspect of the present invention is a memory cell array (m, n) having a block configuration in which memory cell blocks having m rows and n columns of memory cells are arranged over M rows and N columns as a semiconductor storage device. , M, N are positive integers), row decoder circuit, column decoder circuit, sense amplifier corresponding to the memory cell in the column direction of the memory cell block, and read / write arranged for each block column of the block configuration. An operation for calculating the parity value of m rows and n columns of memory cells common in each memory cell block and the parity value of the memory cell arranged in the memory cell block of the block column. Means, storage means for storing the parity value, checking means for checking the occurrence of a parity error with respect to the parity value, row and column information of the memory cell block in which the parity error has occurred, and the inside of the memory cell block. It is characterized by having an identification means for identifying a memory cell in which an error has occurred and a correction means for correcting the memory cell in which an error has occurred based on the information in the row and column of.</p>

<p> According to the present invention, by using a local parity cell and a global parity cell, it is possible to provide a semiconductor storage device capable of suppressing an increase in the area of the entire chip and performing error correction as compared with the conventional ECC method.</p>

Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a basic principle in the first embodiment of the semiconductor storage device according to the present invention.

The semiconductor storage device of this embodiment is a DRAM, and has 1 kilobit, that is, a data memory cell 11 of 32 rows × 32 columns in a memory cell array 10. It also has one local parity cell 12 in each row. The local parity cell 12 stores the parity value in each row. In addition, the local parity value is stored as even parity by calculating the data for all cells in the row by exclusive OR.

Further, a low decoder 13 is arranged for a word line, a first sense amplifier and a precharge circuit 14 for a bit line, a read / write circuit and an error correction circuit 15, a parity calculation circuit 16 and a column decoder 17 are arranged respectively. There is.

Each of the read / write circuit and the error correction circuit 15 has a register (not shown) which is a global parity cell that stores 1 bit as global parity. In addition, the global parity value is stored as even parity by calculating all cell data in each column by exclusive OR.

Next, the principle of error detection will be described. When one of the data memory cells, for example, error cell 18 is bit-inverted due to a soft error, the parity value of the local parity cell 18a in the row corresponding to the error cell 18 and the global parity cell in the corresponding read / write circuit and error correction circuit 18b. The parity value of is inverted from the previously calculated value. That is, the error cell 18 can be known by tracing the row of the local parity and the column of the global parity in which the previously calculated value and the calculated value of this time are inverted.

Error correction can be performed by further inverting the error cell.

FIG. 2 is a block diagram showing a memory cell array and main peripheral circuits in the second embodiment of the present invention.

The semiconductor storage device in this embodiment is a DRAM, and data memory cell blocks 21 of 512 rows × 64 columns are arranged as memory cell array 20 over 32 rows and 32 columns, and the local parity cell block 22 is in the center of the columns. It is placed in the part. Therefore, a total of 33 memory cell blocks are arranged in the column direction.

Further, a low decoder 23 is arranged for a word line, a first sense amplifier and a precharge circuit 24 for a bit line, a read / write circuit and an error correction circuit 25, a parity calculation circuit 26, and a column decoder 27 are arranged respectively. There is.

The principle of error detection will be described below. When one of the data memory cells is bit-inverted due to, for example, a soft error, first, the parity value in the local parity cell of the column corresponding to the data memory cell block 28 including the error cell and the corresponding read / write circuit of the local parity cell block 28a. And the parity value in the global parity cell in the error correction circuit 28b is inverted from the previously calculated value. That is, the memory cell block 28 including the error cell can be known by tracing the row of the local parity block and the column of the global parity block in which the previously calculated value and the calculated value of this time are inverted. Further, in the memory cell block 28 including the error cell, the cell that actually caused the error is the same as the error part of the local parity cell block in which the error is detected.

Further, as in the first embodiment, the error can be corrected by inverting the error cell.

FIG. 3 is a circuit diagram showing the arrangement of the data memory cells 31 in the data memory cell block 30. The data memory cell 31 is arranged for 512 rows × 64 columns, and the first sense amplifier and the precharge circuit 35 are arranged for 64 columns at the right end.

Next, the operation in the data memory cell block 30 will be described. First, during standby for memory operation, the precharge circuit in the first sense amplifier and precharge circuit 35 resets all bit lines 34 from BL0 to / BL63 to the same potential, that is, an intermediate potential between high level and low level. Will be done.

Next, as the row selection line 33 corresponding to the row address given from the outside (not shown), only one row selection line 33 is selected from WL0 to WL511, and the level becomes high.

As a result, the electric charge of the data stored in the capacitor 32a connected to the transistor 32 is transferred to the bit line via the transistor 32 connected to the selection line, and BLn or / BLn (an integer of n: 0 to 63). Increase or decrease the potential of either of these by several hundred mV.

Subsequently, the first sense amplifier and the first sense amplifier in the precharge circuit 35 are operated, and the potential difference between BLn or / BLn on the side where the potential has increased or decreased and the other side where the potential has not increased or decreased is logically high-level potential. Alternatively, it is amplified to a low level potential. Due to this amplification, the capacitor that released the charge when WL was selected is charged again. This is the refresh operation.

Next, one line is selected from the 64 column selection lines 37 for the column address given from the outside (not shown), and is connected to the data bus 36 in the block. Further, it is connected to the data bus 39 by controlling the block selection line 38. The data bus 39 is connected to a read / write circuit (not shown). The data from the data bus 39 is output to the read / write circuit as Dn and / Dn (integers of n: 0 to 31).

When the above-mentioned data memory cell block is applied to the entire block diagram shown in FIG. 2, one data memory cell can be read and written at the same time from each of the 32 data memory cell block columns arranged in the column direction.

FIG. 4 shows the local parity block 30a in detail, and has the same structure as that of FIG. 3 described above. However, the data from the data bus 39 is output to the read / write circuit as Dp and / Dp.

A detailed circuit diagram of the read / write circuit and the error correction circuit 25 in the block diagram of this embodiment shown in FIG. 2 is shown in FIG. The read / write circuit 50 is basically the same as the circuit used for ordinary DRAM.

First, the read operation (read) will be described. As shown in FIG. 5, the data Dn and / Dn output through the data bus 51 are amplified by the second sense amplifier 52 and output as read data DataN and / DataN (integers of N: 0 to 31). .. A timing signal RDE is given when amplifying with the second sense amplifier 52. Here, Dn and DataN and / Dn and / DataN are independent as nodes. The amplified signal DataN is sent to the output circuit in the case of normal operation, and the read operation (read) ends.

Next, the writing operation (write) in FIG. 5 will be described. In normal writing, Wn, which is data writing data from an input buffer circuit (not shown), is input, while WTE is given as a writing timing signal. The combination of the inverter, NAND circuit and NOR circuit gives WRT0n or WRT1n that activates the write gate 53, drops either the Dn or / Dn signal to a low level, and the first sense amplifier of the memory cell described above. Written to memory cell via 35.

In this embodiment, in addition to the normal read and write operations, the read and write operations associated with the memory cell error check and error correction are required. Error checking and error correction will be described below.

First, when performing an error correction operation, data is output to the local parity calculation circuit 60 and the error correction circuit 50a, which will be described later, in order to check the occurrence of error cells.

Figure 6 shows a local parity arithmetic circuit that detects local parity. The arithmetic circuit unit 61 of the local parity arithmetic circuit 60 is composed of an exclusive OR circuit. The signals of Data0 to Data31 obtained by amplifying the data D0 to D31 generated from each data memory cell block are read, and the final calculation result is set as the local parity calculation data 62 and the local parity value DataP is output. Since the exclusive OR circuit is used, if one data is inverted due to an error, the final data, DataP, is also inverted.

Next, the error correction function and its operation will be described. FIG. 7 shows a read / write circuit 50b and an error correction circuit 50a corresponding to the local parity cell block.

First, for local parity writing, the DataP shown in FIG. 6 is synchronized with the write timing signal WTE shown in FIG. 7 and input as a data write signal DataP. The combination of the inverter, NAND circuit and NOR circuit gives the signal PWRT0 or PWRT1 that activates the write gate 53, drops either the DP or / DP signal to a low level, and is the first sense amplifier in the memory cell. Written to memory cell via 35.

On the other hand, reading the local parity value is the same as in FIG. 5, and detailed description thereof will be omitted. As a result, the value stored in the cell is amplified and output as LP and / LP which are local parity signals.

The error check of local parity is performed by the error check circuit 57. This reads the parity value written in the local parity cell last time, compares that value with the DataP that is the result of the parity calculation this time, and if they do not match, generates the local parity generation signal LPERR.

Next, error correction will be described. The data DataN sent from the read / write circuit 50 in FIG. 5 is input to the error correction circuit 50a. Further, the exclusive OR circuit performs an operation with the data stored in the global parity operation register 54, and sends the data to the global parity operation register 54 through the first shift register 56a. Here, when the data to be sent sequentially is processed and the processing of one row in the data memory cell block is completed, the calculation result is sent to the global parity storage register 54a, which is a global parity cell, via the second shift register 56b. Store data. This data is the global parity value.

Further, after the series of processing is completed, the reset signal GPRST is sent to the global parity operation register 54, and the operation processing of the next column is performed.

To detect the global parity error, the global parity value stored in the global parity storage register 54a and the data sent to the global arithmetic register 54 are calculated by using the exclusive OR circuit. That is, if they do not match, an error occurs.

The result is stored in the global parity error status circuit 55. When a global parity error occurs, the error is corrected by writing the data in which Dn or Dn is inverted from DataN and / DataN in synchronization with the timing signal CWTE together with the signal indicating the local parity error LPERR. The occurrence of the global parity error is controlled by the timing signal GPCHECK.

In this embodiment, the refresh cycle is used to perform calculation and storage of local parity and global parity, and when the calculation result and the stored result do not match, error correction is performed internally.

FIG. 8 is a conceptual diagram illustrating the operation of error correction in this embodiment. The horizontal axis is time (time), and the vertical axis is the refresh address or error occurrence address. To make the explanation easier to understand, the addresses are only 0 to 3, and the refresh interval is 1 on the time axis, which is the horizontal axis. White circles and black circles in the figure indicate the time of refresh operation and its address.

As the refresh operation step S1, address 0 is refreshed at time 0, address 1 is refreshed at time 1, and then refreshing is repeated in the order of addresses. The mark at time 3 indicates the time when the soft error occurred and its address.

When a soft error occurs, the occurrence of a local parity error is detected during refreshing at time 5 in refresh operation step S2 starting at time 4. Subsequently, the occurrence of a global parity error is detected at the end of the refresh operation step S2 at time 7.

Further, this global parity error is retained, the recurrence of the local parity error is detected at the time of refreshing at time 9 in the refresh operation step S3, and at this point, the error is corrected by combining the local parity error and the global parity error. Then, at the end of refresh operation step S3, the global parity error is reset. At this stage, it returns to the normal state without errors.

After that, if a soft error occurs again at the Δ mark at time 12, the error can be corrected by the procedure after the refresh operation step S4, as in the case of the soft error at time 3.

If this is compared to the actual time axis in the embodiment of FIG. 2, every time a refresh command is received, 32-bit cell data is read, a local parity cell calculation and a global parity calculation are performed, and the refresh regulation is performed. If is set to 8,192 times / 64 milliseconds, 8.192 seconds are required to refresh the 32-bit cell array once. Therefore, it is possible to correct an error with a frequency of 1 bit every 16.384 seconds, which is twice that.

For example, when screening cells that are vulnerable to soft errors with a low frequency of several hours / bit or less, it is necessary to use the test device for several hours to several days or more, resulting in an increase in test cost. The present invention can reduce the number of defective products, reduce the test cost, and improve the reliability by automatically relieving those error cells inside the DRAM.

FIG. 9 shows the number of memory cell blocks in the column direction of FIG. 2 changed from 33 (32 + 1) to 65 (64 + 1). Even in this case, the only block added for error correction is the local parity cell block 22, and the area increase rate is small. For example, if the area of the memory cell without the soft error correction function is 100%, the area increase rate by the soft error correction method in Fig. 2 is 33/32 = + 3.1250%, and the area increase by the soft error correction method in Fig. 9 is 33/32 = + 3.1250%. The rate is 65/64 = + 1.5625%.

As described above, in the case of the present invention, as the number of memory cell blocks in the column direction increases, the area increase required for incorporating the error correction function decreases.

<figref num="1">The block diagram which shows the basic principle in 1st Example of the semiconductor storage device by this invention.</figref><figref num="2">The block diagram which shows the memory cell array and the main peripheral circuit in the 2nd Example of the semiconductor storage device by this invention as a whole.</figref><figref num="3">The circuit diagram of the data cell array part in the 2nd Example of the semiconductor storage device according to this invention.</figref><figref num="4">The circuit diagram of the parity cell array part in the 2nd Example of the semiconductor storage device according to this invention.</figref><figref num="5">The circuit diagram which shows the read / write circuit and the error correction circuit connected to the data cell array part in the 2nd Example of the semiconductor storage device by this invention.</figref><figref num="6">The circuit diagram which shows the parity operation circuit in the 2nd Example of the semiconductor storage device by this invention.</figref><figref num="7">The circuit diagram which shows the read / write circuit and the error correction circuit connected to the parity cell array part in the 2nd Example of the semiconductor storage device by this invention.</figref><figref num="8">The conceptual diagram which shows the refresh operation and the timing of error correction in the 2nd Example of the semiconductor storage device by this invention.</figref><figref num="9">FIG. 2 is a block diagram showing a memory cell array and main peripheral circuits when the number of blocks in the column direction is increased with respect to the invention according to FIG. 2 according to the present invention.</figref><figref num="10">The block diagram which shows the memory cell array and the main peripheral circuit which uses the conventional correction method.</figref>

Code description

10, 20 Memory cell array 11, 31 Data memory cell 12 Local parity cell 13, 23 Row decoder 14, 24 First sense amplifier 15, 25 Read / write circuit and error correction circuit 16, 26 Parity arithmetic circuit 17, 27 Column decoder 18 Error cell 18a Local parity cell where error was detected 18b, 28b Read / write circuit and error correction circuit where error was detected 21, 30 Data memory cell block 22 Local parity cell block 28 Data memory cell block 28a including error cell Detected local parity cell block 32 transistor 32a capacitor 33 row selection line 34 bit line 35 first sense amplifier and precharge circuit 36 intra-block data bus 37 column selection line 38 block selection line 39 data bus 30a local parity memory cell block 31a Local parity cell 50, 50b Read / write circuit 50a Error correction circuit 51 Data bus 52 Second sense amplifier circuit 53 Write gate 54 Global parity calculation register 54a Global parity storage register 55 Global parity error status circuit 56a First shift register 56b Second shift register 60 Parity calculation circuit 61 Calculation circuit unit 62 Local parity calculation data 70 Additional cell block for parity