Nonvolatile semiconductor storage device

The present invention relates to a non-volatile semiconductor storage device, and more specifically, the present invention relates to a non-volatile semiconductor storage device having a memory cell array in which a plurality of memory cells are arranged in a matrix and divided into a plurality of sectors. Is.

Conventional non-volatile semiconductor storage devices, such as flash EEPROM, utilize various high voltages to realize write / erase and read operations. When generating these various high voltages, a booster circuit that boosts the power supply voltage and outputs a high voltage is generally used, and therefore a non-volatile semiconductor storage device having a built-in booster circuit is widely used. (See, for example, Patent Document 1).

Hereinafter, FIG. 16 which is a conventional non-volatile semiconductor storage device will be described.

FIG. 16 is a block diagram showing a conventional EEPROM configuration. The memory array 1 is divided into N (natural number) sectors S1 to SN, and each sector S1 to SN is a floating gate type as shown in FIG. 17 as an electrically rewritable non-volatile memory cell. Memory cells MC are array-connected in NOR type. The drain of the memory cell MC is connected to the bit line BL, the source is connected to the common source line SL, and the control gate is connected to the word line WL. The word line WL of each sector S1 to SN is selected by the row decoder 2 divided into N (natural number) decoder blocks XDEC1 to XDECN, and the bit line BL is selected by the column gate 4 driven by the column decoder 3. Will be done. The address AD is input to the address / data buffer 5, and the row address and the column address are decoded by the row decoder 2 and the column decoder 3, respectively.

At the time of data reading, the bit line data selected by the column gate 4 is detected and amplified by the sense amplifier 6 and taken out to the I / O terminal via the address / data buffer 5. When writing data, the data DB input from the I / O terminal is latched by the sense amplifier 6 via the address / data buffer 5, and the latched data DB is the bit selected by the column gate 4. Transferred to line BL.

The high voltage generation booster circuit 7 and the low voltage generation booster circuit 8 are provided to generate a booster voltage higher than the power supply voltage required when writing / erasing / reading data. The low boost output voltage VPPL of the low voltage generation booster circuit 8 is supplied to the regulator circuit 9, and after voltage stabilization, the regulator circuit 9 outputs the output voltage VRO. Further, the high boost output voltage VPPH of the high voltage generation booster circuit 7 is supplied to the voltage selector switch circuit 10 together with the output voltage VRO of the regulator circuit 9. The voltage selector switch circuit 10 selects either the high boost output voltage VPPH or the output voltage VRO of the regulator circuit 9 according to the switch control signal supplied from the control circuit 11, and sends a word line to the low decoder 2. Supply voltage Vwl1 ~ VwlN. The control circuit 11 performs a predetermined operation for each data write / erase / read mode according to the mode signal MD, the chip enable signal CEB, the write enable signal WEB, and the output enable signal OEB. , High voltage generation booster circuit 7, low voltage generation booster circuit 8, regulator circuit 9 and voltage selector switch circuit 10 are provided.

FIG. 18 shows an example of the booster circuit 7 for generating a high voltage. Here, diode-connected MIMO transistors Mn1 to Mn6 and Mn10 are connected in series in 7 stages, the input terminal of the 1st stage MIMO transistor Mn1 is fixed to the power supply potential VCC (= 2.5V), and the high boost output voltage VPPH. A smoothing capacitance Co and a Zener diode Dzh are inserted between the output terminal that supplies the voltage and the ground potential VSS, and a switch circuit 12 that controls conduction / non-conduction by a stop mode signal is inserted between the output terminal and the power supply potential VCC. In addition, a two-phase clock type booster circuit driven by a booster clock is shown.

FIG. 19 shows an example of the booster circuit 8 for generating a low voltage. In FIG. 19, the parts corresponding to those in FIG. 18 are designated by the same reference numerals. Here, the diode-connected NMOS transistors Mn1 to Mn4 and Mn10 have five stages, and a Zener diode Dzl is inserted between the output terminal that supplies the low boost output voltage VPPL and the ground potential VSS.

As shown in FIG. 20, the regulator circuit 9 is a comparator CMP that uses a low boost output voltage VPPL as a power source, and a MOSFET transistor that is on / off controlled by the output of the comparator CMP and is connected in series between the VPPL node and the VSS terminal. Equipped with Mp1. At this time, the drain terminal of the MOSFET transistor Mp1 becomes an output terminal, and the regulator output voltage VRO is supplied. The VRO output terminal is provided with a resistance voltage divider circuit in which resistors R1 to R3 are connected in series, and the feedback voltage VFB of the resistor R3 is fed back to the non-inverting input terminal of the comparator CMP. The reference voltage VREF is input to the inverting input terminal of the comparator CMP. Therefore, on / off control of the MOSFET transistor Mp1 is performed so that the feedback voltage VFB becomes equal to the reference voltage VREF. Further, a short-circuit MOSFET Mp2 controlled by the mode control signal RDB is connected between the node NR between the resistors R1 and R2 and the VRO output terminal. For example, in the read operation, the mode control signal RDB is inactive and the MOSFET transistor Mp2 is turned on, and in the write verify operation, the potential control is performed so that the MOSFET transistor Mp2 is turned off. As a result, for example, VRO = 4.5V can be output in the read operation, and VRO = 5.5V can be output in the write verify operation. Further, a switch circuit 13 controlled by a stop mode signal is inserted between the VRO output terminal and the VCC power supply terminal, and a switch circuit 14 controlled by a stop mode bar signal is provided between the node N1 of the resistor R3 and the VSS ground terminal. ing.

FIG. 21 shows an example of a unit decoder constituting the row decoder 2. The unit decoder is composed of a NAND gate G1 that takes a logical product of a plurality of row address ADRs, a level shift circuit 15, and a driver circuit 16. For the selected unit decoder, node N2 is at an inactive level. The level shift circuit 15 is composed of MOSFET transistors Mp3 and Mp4, NMOS transistors Mn11 and Mn12, and an inverter gate G2. The signal of node N2 is input to the gate of the NMOS transistor Mn11, and the inverting signal of node N2 is input to the gate of the other NMOS transistor Mn12. The driver circuit 16 is an inverter circuit composed of an NMOS transistor Mn13 and a MOSFET transistor Mp5, which uses the output of the level shift circuit 15 as an input and uses a word line supply voltage Vwl1 as a power source, and its output voltage is a memory cell. It is applied to the control gate of MC. Further, here, all the N-well nodes NW of the MIMO transistors Mp3 to Mp5 are connected to the word line supply voltage Vwl1.

The operation of the non-volatile semiconductor storage device configured as described above will be described below.

In the data writing operation, a high boost output voltage VPPH (= 10V) is applied as the word line WL voltage to the control gate of the memory cell MC selected according to the write address AD and the data DB input, and the non-selected word line. 0V is applied to the WL. At this time, 5V or 0V is applied to the bit line BL depending on the data DB to be written. In addition, 0V is applied to the common source line SL. As a result, the memory cell MC connected to the selected word line WL and 5V is applied to the drain terminal through the bit line BL is written, electrons are injected into the floating gate, and the threshold value of the memory cell MC is positive. Ascend in the direction. As a specific operation of the power supply circuit and the decoder 2, a booster clock is input from the control circuit 11 to the booster circuit 7 for high voltage generation shown in FIG. 18, and a boost voltage higher than the power supply voltage is applied by a known charge transfer operation. It is generated and clamped to 10V by the Zener diode Dzh provided at the output terminal, and a high boost output voltage VPPH (= 10V) is supplied to the voltage selector switch circuit 10. At this time, the stop mode signal input from the control circuit 11 is in an inactive state, and the switch circuit 12 is non-conducting. Similarly, a boost clock is input to the low voltage generation booster circuit 8 shown in FIG. 19, a booster voltage higher than the power supply voltage is generated, and the Zener diode Dzl provided at the output terminal clamps the booster voltage to 7V, resulting in a low voltage. The boost output voltage VPPL (= 7V) is supplied to the regulator circuit 9. At this time, since the regulator circuit 9 shown in FIG. 20 is stopped during the writing operation, the stop mode signal is activated and the stop mode bar signal is deactivated. Therefore, the switch circuit 13 and the switch circuit 14 are respectively. It becomes conductive and non-conducting, and the regulator output voltage VRO (= VCC) is supplied to the voltage selector switch circuit 10. Subsequently, in the voltage selector switch circuit 10, a high boost output voltage VPPH (= 10V) is selected by the switch control signal supplied from the control circuit 11, and all the decoder blocks XD of the low decoder 2 are selected. It is supplied to EC1 to XDECN as a word line supply voltage Vwl1 to VwlN. At this time, as shown in FIG. 21, the word line supply voltages Vwl1 to VwlN are charged to a very large load capacity such as the N well node NW common to all decoder blocks XDEC1 to XDECN, and charging is completed. Later, the specified word line WL (1) is selected, only the node N2 of the unit decoder that drives the selected word line WL becomes inactive level, the high boost output voltage VPPH (= 10V) is output, and the selected memory cell. It is applied to the control gate of MC. The other non-selected word line WL voltage remains 0V.

Next, in the write verification operation, the regulator output voltage VRO (= 5.5V) is applied to the control gate of the cell to be written, and at the same time, 1V is applied to the selection bit line BL. Further, 0V is applied to the common source line. At this time, the bit line potential is detected and amplified by the sense amplifier 6, and if it is determined to be a write cell, the next write operation is canceled, and if it is determined to be an erase cell, the next write operation is continued. As a specific circuit operation of the power supply circuit and the decoder 2, the boost clock supplied to the high voltage generation boost circuit 7 shown in FIG. 18 is stopped, the stop mode signal is activated at the same time, and the switch circuit 12 is in a conductive state. Therefore, the power supply potential VCC is supplied to the voltage selector switch circuit 10. In the low voltage generation booster circuit 8 shown in FIG. 19, a booster clock is input, a booster voltage higher than the power supply voltage is generated, and the booster circuit 8 for low voltage generation is clamped to 7V by a Zener diode Dzl provided at the output terminal. The low boost output voltage VPPL (= 7V) is supplied to the regulator circuit 9. At this time, in the regulator circuit 9 shown in FIG. 20, the mode control signal RDB is activated, the MOSFET transistor Mp2 is turned off, and the resistor R1 becomes effective. At the same time, the stop mode signal is deactivated and the stop mode bar signal is activated, so that the switch circuit 13 and the switch circuit 14 are in a non-conducting and conductive state, respectively, and the regulator output voltage VRO (= 5.5V) is increased. It is supplied to the voltage selector switch circuit 10. Subsequently, in the voltage selector switch circuit 10, the regulator output voltage VRO (= 5. 5V) is selected and supplied to all decoder blocks XDEC1 to XDECN of the row decoder 2 as word line supply voltages Vwl1 to VwlN. At this time, as shown in FIG. 21, the word line supply voltages Vwl1 to VwlN are charged to the N well node NW or the like common to all decoder blocks XDEC1 to XDECN, and the predetermined word line WL is charged after the charging is completed. (1) is selected, the regulator output voltage VRO (= 5.5V) is output, and it is applied to the control gate of the selected memory cell MC. The other non-selected word line WL voltage remains 0V.

Regarding the above write / write verification operation, Fig. 22 shows the timing chart focusing on the voltage system supplied to the word line WL. First, in the stop state (STOP), the high voltage generation booster circuit 7, the low voltage generation booster circuit 8 and the regulator circuit 9 are all stopped. Therefore, the word line supply voltages Vwl1 to VwlN are set to the power supply potential VCC. Become. Next, when transitioning to the write (Program) state, the high voltage generation booster circuit 7 and the low voltage generation booster circuit 8 enter the operating state, and from the power supply potential VCC, the high voltage boost output voltage VPPH (= 10V) and low voltage boost, respectively. The load capacity is charged up to the output voltage VPPL (= 7V). At this time, the high-voltage output voltage VPPH (= 10V) is passed through the low decoder 2 by the voltage selector switch circuit 10, so the high-voltage generation booster is used. The load capacitance seen from circuit 7 becomes very large and requires a very long setup time τl1. Subsequently, when transitioning from the write state to the write verify (PV) state, the high voltage generation booster circuit 7 is stopped, and the high voltage boost output voltage VPPH (= 10V) is discharged to the power supply potential VCC. Further, the regulator circuit 9 is put into operation, and the regulator output voltage VRO (= 5.5V) obtained by stepping down the low boost output voltage VPPL (= 7V) is supplied to the low decoder 2 via the voltage selector switch circuit 10. .. If it is not determined that the writing is completed in this PV operation, the process proceeds to the next Program operation and PV operation. However, the setup time τ1 of the high boost output voltage VPPH (= 10V) in the second and subsequent write modes is the regulator output voltage VRO (= 5. Since it is charged from 5V), it is slightly shorter than the first setup time τl1. Hereinafter, the above write / write verify operation is repeated until all the desired memory cell MCs are in the write state. In this way, in the method of repeating the write / write verify operation multiple times in many cases, the high boost output voltage VPPH (= 10V) is applied to the N-well node NW of the low decoder 2 each time the write mode is entered. A large load capacity must be charged, requiring a very long setup time τl for the number of loops. Therefore, the time required for the write / write verify operation becomes very long, and at the same time, the high boost charge is charged and discharged to a very large load capacitance, so that the power consumption of the high voltage generation boost circuit 7 that supplies the high boost charge is high. There was a drawback that it would increase. Further, if the current supply capacity of the high voltage generation booster circuit 7 that generates VPPH is increased in order to shorten τ1, the problem of increased power consumption will be caused.<patcit num="1"><text>Japanese Patent Application Laid-Open No. 5-290587 (pages 4-5, Fig. 1)</text></patcit>

<p> As described above, in the above-mentioned conventional configuration, it is difficult to shorten the time required for the write / write verify operation and reduce the power consumption, and there is a problem that the power consumption increases in order to reduce the required time. It was.</p><p> The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a high-performance non-volatile semiconductor storage device capable of shortening the time required for write / write verify operation while reducing power consumption. There is.</p>

<p> In the non-volatile semiconductor storage device according to the present invention, in the memory cell array, a plurality of memory cells are arranged in a matrix and divided into a plurality of sectors, and the plurality of row decoding circuits correspond to each sector of the memory cell array. A memory cell included in a corresponding sector is selected based on an address signal provided and input from the outside, and a plurality of switches are supplied with a plurality of types of voltages and correspond to a plurality of low decoding circuits. Any one of the plurality of types of voltages can be independently switched and output to the corresponding low decoding circuit. Each row decoding circuit selects a memory cell using the voltage output from the corresponding switch.</p><p> Further, the booster circuit generates a plurality of types of voltages by boosting the power supply voltage.</p><p> Further, the regulator circuit stabilizes the voltage value by stepping down at least one of the plurality of types of voltages generated by the booster circuit, and outputs the voltage to each switch.</p><p> Further, the control circuit generates a switch control signal for switching each switch based on the address signal, and each switch switches the voltage output to the corresponding low decoding circuit based on the switch control signal.</p><p> Further, the plurality of types of voltages include at least a first voltage and a second voltage lower than the first voltage, and the control circuit selects the memory cell when writing data to the memory cell. A switch control signal for outputting the first voltage to the low decoding circuit of the above and outputting the second voltage to the low decoding circuit other than the low decoding circuit is generated based on the address signal.</p><p> Further, each low decoding circuit includes a plurality of MOSFETs configured in the N well. The N-well input terminal is a terminal for applying one of a plurality of types of voltages generated by the booster circuit to the N-well, and the booster control circuit inputs the N-well before writing data to the memory cell. The booster circuit is controlled so that a voltage is applied to the terminals.</p><p> Further, a third voltage, which is the largest of the plurality of types of voltages, is applied to the N-well input terminal before writing data.</p><p> Further, the N-well voltage changeover switch switches the voltage output to the N-well input terminal, and the switch control circuit switches between the third voltage and the fourth voltage smaller than the third voltage to obtain the N-well voltage. Output to the changeover switch.</p><p> Further, the switch control circuit controls the N-well voltage changeover switch so as to apply a third voltage to the N-well input terminal before writing the data, and when reading the data, the fourth voltage is applied. The N-well voltage changeover switch is controlled so as to be applied to the N-well input terminal.</p><p> Further, the voltage drop circuit lowers the voltage of the N-well input terminal when the switch control circuit switches the N-well voltage changeover switch so as to apply the fourth voltage, and the comparison circuit lowers the voltage drop circuit. The voltage of the N-well input terminal was compared with the fourth voltage, and the switch control circuit determined that the voltage of the N-well input terminal dropped by the voltage drop circuit and the fourth voltage became equal. In this case, the N-well voltage selector switch is switched so that the fourth voltage is applied to the N-well input terminal.</p><p> Further, the low decoder includes a plurality of MOSFETs formed in the N wells and a plurality of NMOS transistors formed in the P wells formed in the N wells.</p><p> The negative voltage input terminal is for applying any one of at least one negative voltage or ground voltage contained in the plurality of voltages generated by the booster circuit to the control gate of the memory cell via the low decoding circuit. It is a terminal, and the boost control circuit controls the boost circuit so as to apply a negative voltage to the negative voltage input terminal when extracting electrons from a floating gate provided in the memory cell.</p>

<p> According to the first invention, when the mode is changed to the write mode, the high voltage can be charged only for the load capacitance such as N well in the predetermined decoder block by providing the switch. As a result, the load capacitance is significantly reduced, the high voltage charge / discharge charge to the load capacitance is reduced, the power consumption is reduced, and the high voltage setup time is also shortened, so that the write / write verify operation is required. You can save time.</p><p> According to the second invention, by providing the booster circuit, the non-volatile semiconductor storage device can operate with a single power source without supplying a plurality of power sources from the outside. Therefore, the versatility of the non-volatile semiconductor storage device is improved. Furthermore, when a booster circuit is used, the voltage setup time is significantly longer than when an external high-voltage power supply is used, and the charge / discharge current of the high-voltage voltage has a large effect on power consumption. In consideration of the above, the power consumption reduction effect becomes larger and the setup time of the high boost voltage is further shortened, so that the time required for the write / write verify operation can be shortened more effectively.</p><p> According to the third invention, the voltage output from the switch is stabilized by providing the regulator circuit. As a result, the memory cell gate voltage can be controlled with high accuracy, and the write and read disturb characteristics are improved.</p><p> According to the fourth invention, the switch is controlled by the control circuit.</p><p> According to the fifth invention, when the mode is changed to the write mode, the high voltage can be charged only for the load capacitance such as N well in the predetermined decoder block by providing the switch. As a result, the load capacitance is significantly reduced, the high voltage charge / discharge charge to the load capacitance is reduced, the power consumption is reduced, and the high voltage setup time is also shortened, so that the write / write verify operation is required. You can save time.</p><p> According to the sixth invention, during the write / write verify operation, the maximum voltage used inside the non-volatile semiconductor storage device is always applied to the N-well voltage input terminal to set up the voltage for supplying the memory cell gate. Since the time can be further shortened and the charge / discharge current of the load capacity such as the useless N-well capacity can be further reduced, a high-performance, low-power consumption non-volatile semiconductor storage device can be realized.</p><p> According to the seventh invention, by using the existing booster circuit that generates the maximum voltage, the external high voltage application terminal and the external application voltage control circuit are not required, so that the area can be reduced.</p><p> According to the eighth invention and the ninth invention, a fourth voltage lower than the third voltage is applied to the N well of the MOSFET transistor during the read operation. With such simple control using the existing booster circuit, it is possible to suppress the increase in the threshold voltage due to the back bias effect of the MOSFETs constituting the low decoder section in the normal read operation, so that the current drive capability is improved. However, high-speed reading is possible. In addition, the booster circuit that supplies the maximum voltage can be stopped during the read operation, and the power consumption during read can be significantly reduced.</p><p> According to the tenth invention, by providing the voltage drop circuit and the comparison circuit that operate as the discharge circuit, the extraction speed of the high boosted charge is increased, so that the read-out setup time can be shortened.</p><p> According to the eleventh and twelfth inventions, the transistor in the low decoder has a so-called triple-well structure, so that a negative voltage can be applied to the WL line at the time of erasing, and the memory cell's disturb, endurance characteristics, etc. Reliability can be improved.</p>

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing a configuration of a non-volatile semiconductor storage device according to the first embodiment of the present invention. The same parts as those in FIG. 16 are designated by the same reference numerals, and detailed description thereof will be omitted. Will be described only.

The feature of this first embodiment is that two types of voltages, a high boost output voltage VPPH (= 10V) and a regulator output voltage VRO (= 5.5V), are input, and these two types of voltages are used according to the switch control signal. It is equipped with a voltage selector switch circuit 17 composed of N (natural number) unit switches that select and output one from. In this voltage selector switch circuit 17, in the case of the stop state (STOP) and the write verification operation (PV), all the unit switches select the regulator output voltage VRO by the switch control signal, and in the case of the write operation (Program). Select the high boost output voltage VPPH for only one desired unit switch, and select the regulator output voltage VRO for the other unit switches. At this time, each of the word line supply voltages Vwl1 to VwlN, which are the output voltages of the voltage selector switch circuit 17, is supplied to the corresponding decoder blocks XDEC1 to XDECN.

The operation of the non-volatile semiconductor storage device of this embodiment configured as described above will be described below.

Figure 2 shows a timing chart focusing on the voltage system supplied to the word line WL regarding the write / write verify operation. First, in the stop state (STOP), the high voltage generation booster circuit 7, the low voltage generation booster circuit 8 and the regulator circuit 9 are all stopped, and all of the voltage selector switch circuits 17 are stopped by the switch control signal. Since the unit switch selects the regulator output voltage VRO, the word line supply voltages Vwl1 to VwlN become the power supply potential VCC. Next, when transitioning to the write (Program) state, the high voltage generation booster circuit 7 and the low voltage generation booster circuit 8 enter the operating state, and from the power supply potential VCC, the high voltage boost output voltage VPPH (= 10V) and low voltage boost, respectively. The load capacity is charged to the output voltage VPPL (= 7V). At this time, in the voltage selector switch circuit 17, only one desired unit switch selects the high boost output voltage VPPH, so that the high voltage generation boost circuit 7 is used. The visible load capacity becomes very small (about 1 / N compared to the conventional one), and the setup time τs1 (&lt;τl1) for charging the load capacity of the decoder block XDEC1 is significantly shortened. Subsequently, when transitioning from the write state to the write verify (PV) state, the high voltage generation booster circuit 7 is stopped, and the high voltage boost output voltage VPPH (= 10V) is discharged to the power supply potential VCC. In addition, the regulator circuit 9 is in the operating state, and the regulator output voltage VRO (= 5.5V), which is the step-down of the low boost output voltage VPPL (= 7V), is set by the switch control signal, and all the unit switches of the voltage selector switch circuit 17 are switched. To select the regulator output voltage VRO, it is supplied to all decoder blocks XDEC1 to XDECN. If it is not determined that the writing is completed in this PV operation, the process proceeds to the next Program operation and PV operation. However, the setup time τs (&lt;τl) of the high boost output voltage VPPH (= 10V) in the second and subsequent write modes is the regulator output voltage VRO (= 5. Since it is charged from 5V), it is slightly shorter than the first setup time τs1 (τs &lt;τs1). Hereinafter, the above write / write verify operation is repeated until all the desired memory cell MCs are in the write state.

As described above, according to the first embodiment, by providing the voltage changeover switch circuit 17, it is possible to charge a high voltage only with respect to a load capacity such as N well in a predetermined decoder block. As a result, the load capacity is significantly reduced, and as a result, the charge / discharge charge of the high voltage with respect to the load capacity is reduced, the power consumption is reduced, and the setup time of the high voltage is also shortened, so that the write / write verification is performed. The time required for operation can be shortened, and a high-performance non-volatile semiconductor storage device can be realized. In addition, by providing a booster circuit, it is possible to operate with a single power supply, improving versatility, and by providing a regulator circuit, it is possible to control the memory cell gate voltage with high accuracy. The read-disturbing characteristics are improved, and the memory cell can be made highly reliable.

The N wells constituting each decoder block XDEC1 to XDECN of this embodiment are independent of each other, and the N wells in each decoder block XDEC1 to XDECN may be divided into one or a plurality of N wells. , The smaller the number of N-well divisions in each decoder block XDEC1 to XDECN, the smaller the decoder block area can be.

In this embodiment, the number of sectors S1 to SN (N) and the number of decoder blocks XDEC1 to XDECN (N) constituting the memory array 1 are the same, but they do not necessarily have to be the same. The number of unit switches (N) and the number of decoder blocks XDEC1 to XDECN (N) also match, but they do not necessarily have to match.

FIG. 3 is a configuration diagram showing the configuration of the non-volatile semiconductor storage device according to the second embodiment of the present invention, and the same parts as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals and detailed description thereof will be given. Is omitted, and only the different parts will be described here.

The feature of this second embodiment is that one N-well potential input terminal can be controlled independently of the gate voltage applied to the memory cell so that the voltage of the N-well constituting the MOSFET in the row decoder 2 can be controlled independently. It is provided and further connected to the output terminal of the high voltage generation booster circuit 7.

As shown in FIG. 3, the low decoder 2 is provided with an N-well potential input terminal, the N-well potential input terminal is connected to the output of the high voltage generation booster circuit 7, and the low decoder 2 is shown in FIG. Each decoder block XDEC1 to XDECN is composed of N (natural number) decoder blocks XDEC1 to XDECN, and each decoder block XDEC1 to XDECN is composed of M (natural number) unit decoders U1X to UMX (X = 1, 2, ..., N). , Each unit decoder U1X to UMX (X = 1, 2, ..., N) is input with a high boost output voltage VPPH via the N-well potential input terminal. Each unit decoder U1X to UMX (X = 1, 2, ..., N) can control the voltage Vnwell of the N-well node NW independently of the word line supply voltage Vwl1 as shown in FIG. It is composed of a level shift circuit 117 and a driver circuit 18.

The operation of the non-volatile semiconductor storage device of this embodiment configured as described above will be described below.

Fig. 6 shows a timing chart focusing on the voltage system supplied to the word line WL regarding the write / write verify operation. First, in the stop state (STOP), the high voltage generation booster circuit 7, the low voltage generation booster circuit 8 and the regulator circuit 9 are all stopped, and all of the voltage selector switch circuits 17 are stopped by the switch control signal. Since the unit switch selects the regulator output voltage VRO, the word line supply voltages Vwl1 to VwlN become the power supply potential VCC. Next, when transitioning to the write (Program) state, the high voltage generation booster circuit 7 and the low voltage generation booster circuit 8 enter the operating state, and from the power supply potential VCC, the high boost output voltage VPPH (= 10V) and low boost, respectively. The load capacitance is charged to the output voltage VPPL (= 7V). At this time, the high boost output voltage VPPH is charged to the very large N-well load capacitance of the low decoder 2 via the N-well potential input terminal, and at the same time. The load capacitance of the desired decoder block XDEC1 selected in the voltage selector switch circuit 17 is charged. At this time, the setup time for charging the load capacity of the N-well and the decoder block XDEC1 is τm1 (τs1 &lt;τm1 &lt;τl1). Subsequently, when the state transitions from the write state to the write verify (PV) state, the regulator circuit 9 goes into the operating state, and the regulator output voltage VRO (= 5.5V), which is the step-down of the low boost output voltage VPPL (= 7V), is switched. By the signal, all the unit switches of the voltage changeover switch circuit 17 select the regulator output voltage VRO, so that they are supplied to all the decoder blocks XDEC1 to XDECN. If it is not determined that the writing is completed in this PV operation, the process proceeds to the next Program operation and PV operation. However, the setup time of the high boost output voltage VPPH (= 10V) in the second and subsequent write modes τss (&lt;τs &lt; For τl), since the N-well load capacitance of the low decoder 2 is already charged to VPPH (= 10V), it is sufficient to charge only the load capacitance of the desired decoder block XDEC1, which is dramatically shortened. Hereinafter, the above write / write verify operation is repeated until all the desired memory cell MCs are in the write state.

As described above, according to the second embodiment, the N-well potential input terminal is provided so that the voltage of the N-well constituting the MIMO transistor in the row decoder 2 can be controlled independently of the gate voltage applied to the memory cell. By providing the N-well potential input terminal and connecting the output terminal of the booster circuit 7 for high voltage generation, the maximum voltage used inside the non-volatile semiconductor storage device is always during the write / write verify operation. Can be applied to the N-well potential input terminal, eliminating the need to charge and discharge the N-well load capacitance of the low decoder 2 during a series of write / write verification cycles, resulting in additional voltage setup time for memory cell gate supply. Since the charge / discharge current of the load capacity such as shortening and useless N-well capacity can be reduced, a high-performance, low-power consumption non-volatile semiconductor storage device can be realized. Further, by using the existing booster circuit that generates the maximum voltage, the external high voltage application terminal and the external application voltage control circuit are not required, so that the circuit area can be reduced.

If one very large N-well is provided in the low decoder 2 and a MOSFET transistor is configured in the N-well, it is not necessary to separate the N-well, so that the circuit area can be reduced.

FIG. 7 is a configuration diagram showing the configuration of the non-volatile semiconductor storage device according to the third embodiment of the present invention, and the same parts as those of the second embodiment shown in FIG. Is omitted, and only the different parts will be described here.

The feature of this third embodiment is that two types of voltages, a high boost output voltage VPPH and a regulator output voltage VRO, are input, and one of these two types of voltages is selected according to the N-well control signal. It is equipped with an N-well voltage selector switch 19 that supplies the well potential input terminal. This N-well voltage selector switch 19 selects the regulator output voltage VRO according to the N-well control signal in the case of stop state (STOP) and read (Read) operation, and writes (Program) / write verify (PV). ) For operation, select high boost output voltage VPPH.

The operation of the non-volatile semiconductor storage device of this embodiment configured as described above will be described below.

In the case of write / write verify operation, a high boost output voltage VPPH is supplied to the N-well potential input terminal in response to the N-well control signal. , The description thereof will be omitted, and the reading operation will be described. In the read operation, the regulator output voltage VRO (= 4.5V) is applied to the control gate of the cell to be read, and at the same time, 1V is applied to the selection bit line BL. Further, 0V is applied to the common source line SL. At this time, the bit line potential is detected and amplified by the sense amplifier 6, and the read data DB is output via the address / data buffer 5. Here, FIG. 8 shows a timing chart focusing on the voltage system supplied to the word line WL regarding the read operation. First, in the stop state (STOP), the high voltage generation booster circuit 7, the low voltage generation booster circuit 8 and the regulator circuit 9 are all stopped, and the N well voltage is generated by the N well control signal and the switch control signal. Since all the unit switches of the changeover switch 19 and the voltage changeover switch circuit 17 select the regulator output voltage VRO, the voltage Vnwell of the N-well node and the voltage Vwl1 to VwlN for supplying the word line become the power supply potential VCC. Next, when transitioning to the read state, the high voltage generation booster circuit 7 remains in the stopped state, but the low voltage generation booster circuit 8 is in the operating state, and from the power supply potential VCC, the low voltage booster output voltage VPPL (=) Charge the load capacity up to 7V). At this time, the regulator circuit 9 shown in FIG. 20 is also in the operating state, the mode control signal RDB is deactivated, the MOSFET transistor Mp2 is turned on, the resistor R1 is invalidated, and at the same time, the stop mode signal is deactivated. Since the stop mode bar signal is activated, the switch circuit 13 and the switch circuit 14 are in a non-conducting and conducting state, respectively, and the regulator output voltage VRO (= 4. 5V) is supplied to the N-well voltage selector switch 19 and the voltage selector switch circuit 17. Subsequently, the N-well voltage selector switch 19 selects the regulator output voltage VRO by the N-well control signal, and the voltage selector switch circuit 17 also selects the regulator output voltage VRO by the switch control signal. The voltage Vnwell and the word line supply voltages Vwl1 to VwlN are all charged to the regulator output voltage VRO (= 4.5V). Therefore, since the source potential and the N-well potential of the MIMO transistors Mp3, Mp4, and Mp5 constituting the unit decoder shown in FIG. 5 are the same potential, the threshold voltage does not increase due to the substrate bias effect.

As described above, according to the third embodiment, one of two types of voltages, a high boost output voltage VPPH and a regulator output voltage VRO, is selected and supplied to the N-well potential input terminal according to the N-well control signal. By providing the N-well voltage selector switch 19, the voltage setup time for supplying the memory cell gate in a series of write / write verification cycles can be shortened, and the wasteful N-well capacity can be achieved, which is the same effect as that of the second embodiment. By simple control using the existing regulator circuit 9, it is possible to suppress the threshold voltage rise due to the back bias effect of the MIMO transistors that make up the unit decoder in the read operation while reducing the load capacitance charge / discharge current. Therefore, the current drive capability is improved and high-speed reading becomes possible. In addition, the booster circuit that supplies the maximum voltage can be stopped during the read operation, and the power consumption during read can be significantly reduced.

FIG. 9 is a configuration diagram showing the configuration of the non-volatile semiconductor storage device according to the fourth embodiment of the present invention, and the same parts as those of the third embodiment shown in FIG. 7 are designated by the same reference numerals to explain the details thereof. Is omitted, and only the different parts will be described here.

The feature of this fourth embodiment is that the voltage Vnwell of the N-well node changes from the high boost output voltage VPPH to the regulator output while comparing the regulator output voltage VRO and the voltage Vnwell of the N-well node according to the discharge control signal DEN. When the voltage VRO is discharged, the discharge operation is stopped, and the discharge circuit 20 for outputting the discharge determination signal RDY to the control circuit 11 is provided.

As shown in FIG. 9, the N-well voltage selector switch 19 selects the high boost output voltage VPPH, selects the regulator output voltage VRO, and selects the regulator output voltage VRO according to the N-well control signal NW [1: 0] output from the control circuit 11. , It is switched to the non-selected state (HiZ) in which none is selected and the three states. Specifically, the N-well voltage selector switch 19 selects the high boost output voltage VPPH when the N-well control signal NW [1: 0] is 0h, and is in the non-selected state (HiZ) when the N-well control signal NW [1: 0] is 1h. At 2h, select the regulator output voltage VRO.

As a specific configuration of the discharge circuit 20, as shown in FIG. 10, the main part is composed of a current mirror unit 21, a voltage detection comparison unit 22, a detection result amplification unit 23, and a discharge unit 24. The current mirror unit 21 is composed of an NMOS transistor Mn14, a MOSFET transistor Mp6, and a resistor R4. Output, the drain terminal is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the drain terminal of the MOSFET transistor Mp6, the source terminal and the board terminal are fixed to the power supply potential VCC, and the gate terminal is The inversion signal of the discharge control signal DEN is input. In this way, when the discharge control signal DEN is activated, the current mirror unit 21 operates as a current mirror circuit in which the MIMO transistor Mp6 conducts and a current of 10 uA flows, and the gate potential Vgm is set to the voltage detection comparison unit 22 and the discharge. When the discharge control signal DEN is in the inactive state by outputting to the unit 24, the MIMO transistor Mp6 becomes non-conducting and cuts off the DC current path. The voltage detection comparison unit 22 is composed of MIMO transistors Mn15, Mn16 and MIMO transistors Mp7, Mp8 having the same ratio as the NMOS transistors Mn14. Is fixed to the ground potential VSS, the drain terminal of the NMOS transistor Mn15 is connected to the drain terminal of the MOSFET transistor Mp7 to which the gate terminal and drain terminal are connected, and the regulator output voltage is connected to the source terminal and board terminal of the MOSFET transistor Mp7. VRO is input, its gate terminal is connected to the gate terminal of the MOSFET transistor Mp8, the voltage Vnwell of the N-well node is input to the source terminal and board terminal of the MOSFET transistor Mp8, and the drain terminal is the detection voltage VO. Is output and connected to the drain terminal of the NMOS transistor Mn16. In this way, the voltage detection comparison unit 22 compares the voltage Vnwell of the N-well node with the regulator output voltage VRO when the discharge control signal DEN is active, and if the voltage Vnwell of the N-well node is higher than the regulator output voltage VRO. If it is high, it outputs a high level as the detection voltage VO, and if the voltage Vnwell of the N-well node is lower than the regulator output voltage VRO, it outputs a low level. At this time, the currents flowing through the current mirrored NMOS transistors Mn15 and Mn16 are both 10uA. The detection result amplification unit 23 includes a 2-input NAND circuit composed of NMOS transistors Mn17 and Mn18 and MOSFET transistors Mp9 and Mp10, and an inverter composed of NMOS transistors Mn19 and MOSFET transistors Mp11. In the NAND circuit, the voltage Vnwell of the NW node is input as the power supply, and the detection voltage VO and the inverted signal of the discharge control signal DEN are level-shifted from the power supply voltage amplitude to the voltage Vnwell amplitude of the NW node by the level shift circuit 25. The discharged discharge control bar signal DENB is input, and the NAND output voltage VO1 is output. The inverter circuit powered by the voltage Vnwell of the NW node inverts the NAND output voltage VO1 and outputs the detection result amplified output voltage VO2. In this way, in the detection result amplification unit 23, when the discharge control signal DEN is activated, the discharge control bar signal DENB becomes low level, the MOSFET transistor Mp10 becomes conductive, and the NMOS transistor Mn18 becomes non-conductive, so that the inverter It operates as a two-stage amplifier circuit, amplifies the detection voltage VO, and outputs the detection result amplification output voltage VO2. On the other hand, when the discharge control signal DEN is deactivated, the discharge control bar signal DENB becomes high level, and as a result, the MOSFET transistor Mp10 becomes non-conducting and the NMOS transistor Mn18 becomes conductive. Therefore, the DC current path is cut off. The discharge unit 24 is composed of NMOS transistors Mn20 and Mn21 connected in series. Mirror gate potential Vgm and ground potential VSS are input to the gate terminal and source terminal of the NMOS transistor Mn20, respectively, and the gate terminal of the NMOS transistor Mn21. The detection result amplification output voltage VO2 and the voltage Vnwell of the NW node are input to the and drain terminals, respectively. In this way, in the discharge unit 24, when the discharge control signal DEN is activated and the detection result amplification output voltage VO2 is at a high level, the MIMO transistors Mn20 and Mn21 are in a conductive state, and the MIMO transistors Mn20 are replaced by the MIMO transistors Mn14. Assuming that it has a ratio of 50 times that of, the voltage Vnwell of the NW node is discharged by the current mirrored DC current of 500uA, and when the detection result amplification output voltage VO2 is low level, the MIMO transistor Mn21 is in a non-conducting state. Therefore, the discharge operation of the voltage Vnwell of the NW node is stopped. The NMOS transistor Mn22 is a discharge control signal DEN. Is provided to cut off the DC current path of the current mirror unit 21, the voltage detection comparison unit 22, and the discharge unit 24 when the current mirror unit 21, the voltage detection comparison unit 22, and the discharge unit 24 are stopped when is inactive. An inverting signal is input, the source terminal is fixed to the ground potential VSS, and the drain terminal is connected to the gate terminals of the NMOS transistors Mn14 to Mn16 and Mn20. Therefore, when the discharge control signal DEN is in the active state, the NMOS transistor Mn22 is in the non-conducting state, and when the discharge control signal DEN is in the inactive state, the NMOS transistor Mn22 is in the conductive state, and the mirror gate potential Vgm is It is fixed to the ground potential VSS and cuts off the DC current path of the current mirror unit 21, the voltage detection comparison unit 22, and the discharge unit 24. Further, the discharge circuit 20 outputs the inverting and amplified discharge determination signal RDY of the detection result amplification output voltage VO2. FIG. 11 shows a specific circuit configuration of the level shift circuit 25 of FIG. 10, which is composed of NMOS transistors Mn23, Mn24, MOSFET transistors Mp12, Mp13, and an inverter gate G3, and a high level is input to the input terminal IN. Then, the voltage level input to the voltage supply terminal SUPPLY is output to the output terminal OUT, and when the low level is input to the input terminal IN, the ground potential VSS level is output to the output terminal OUT. As described above, the discharge circuit 20 is in the stopped state when the discharge control signal DEN is inactive, the discharge determination signal RDY is in the low level, and the discharge control signal DEN is in the active state, and N. When the well node voltage Vnwell is higher than the regulator output voltage VRO, the N well node voltage Vnwell is discharged with a current of about 510uA, and the N well node voltage Vnwell becomes lower than the regulator output voltage VRO. At that time, the discharge operation is stopped and the discharge judgment signal RDY becomes high level.

The operation of the non-volatile semiconductor storage device of this embodiment configured as described above will be described below.

FIG. 12 shows a timing chart for explaining the discharge operation of the voltage Vnwell of the N-well node in the transition from the write verify (PV) operation to the read (Read) operation. First, in the write verify state (PV), the high voltage generation booster circuit 7, the low voltage generation booster circuit 8 and the regulator circuit 9 are all in the operating state, and the control circuit 11 is in the N-well control signal NW [1: 0]. ] To output 0h, the N-well voltage selector switch 19 selects the high boost output voltage VPPH (= 10V), so the voltage Vnwell of the N-well node becomes 10V. At this time, the mode control signal RDB becomes a high level, so the regulator circuit 9 outputs VRO = 5.5V. On the other hand, since the discharge control signal DEN remains at the low level, the discharge operation of the voltage Vnwell of the N-well node is not performed, and the discharge determination signal RDY also remains at the low level. Therefore, since the write verification (PV) operation performs the same operation as that of the third embodiment of the present invention, the description thereof will be omitted here. Next, when all write verify passes and the state transitions from the write verify (PV) state to the read ready (Read_Ready) state, the high voltage generation booster circuit 7 is first stopped, and the high voltage boost output voltage VPPH (10V). Is discharged to the power supply potential VCC, and the control circuit 11 outputs 1h as the N-well control signal NW [1: 0], so that the N-well voltage selector switch 19 is in the non-selected state (HiZ). At this time, since the mode control signal RDB becomes low level, the regulator circuit 9 outputs VRO = 4.5V. On the other hand, the discharge control signal DEN becomes a high level, and the voltage Vnwell (= 10V) of the N-well node is higher than the regulator output voltage VRO (= 5.5V), so the voltage Vnwell of the N-well node is the regulator output voltage VRO (=). Four. It is discharged to 5V), and after the discharge is completed, the discharge judgment signal RDY becomes high level, and the control circuit 11 that receives this discharge judgment signal RDY lowers the discharge control signal DEN, so that the discharge circuit 20 is stopped. Then, the discharge judgment signal RDY becomes low level. Triggered by the falling edge of this discharge determination signal RDY, the control circuit 11 outputs 2h as an N-well control signal NW [1: 0]. Therefore, the N-well voltage selector switch 19 sets the regulator output voltage VRO (= 4.5V). ) Is selected, a stable voltage (4.5V) is supplied as the voltage Vnwell of the N-well node, and the read (Read_Ready) state transitions to the read (Read) operation. Here, since the Read operation is the same as that of the third embodiment of the present invention, the description thereof will be omitted here.

As described above, according to the fourth embodiment, the same effect as that of the third embodiment is realized, and further, the regulator output voltage VRO and the N-well node voltage Vnwell are compared according to the discharge control signal DEN. At the same time, by providing a discharge circuit 20 that discharges the voltage Vnwell of the N-well node from the high boost output voltage VPPH to the regulator output voltage VRO, the extraction speed of the high boost charge becomes faster, so the read setup time can be shortened. Become.

FIG. 13 is a configuration diagram showing the configuration of the non-volatile semiconductor storage device according to the fifth embodiment of the present invention. The same parts as those in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted. Will be described only.

The feature of this fifth embodiment is that each decoder block XDEC1 to XDECN constituting the row decoder 2 has a plurality of MOSFETs in the N wells and a plurality of NMOS transistors in the P wells provided in the N wells. It is composed of and. That is, the low decoder 2 having a triple well structure is adopted.

As shown in FIG. 13, there are two types of voltages: negative voltage VNG (= -8V) input to the negative voltage input terminal from the negative voltage generation booster circuit or negative voltage external application terminal, etc., and ground potential VSS. A negative voltage selector switch circuit 26 composed of N (natural number) unit switches that select and output one of these two types of voltages according to the negative voltage control signal is provided. In the case of the erase operation, the changeover switch circuit 26 selects the negative voltage VNG for only one desired unit switch by the negative voltage control signal, selects the ground potential VSS for the other unit switches, and performs other operations. In the state, all unit switches select the ground potential VSS by the negative voltage control signal. At this time, each of the non-selected word line voltages VNG1 to VNGN, which is the output voltage of the negative voltage selector switch circuit 26, is supplied to the corresponding decoder blocks XDEC1 to XDECN. The row decoder 2 is composed of each unit decoder U1X to UMX (X = 1, 2, ..., N) shown in FIG. 14, and each unit decoder U1X to UMX (X = 1, 2, ..., N). The non-selected word line voltage VNGX (X = 1, 2, ..., N) is input to). As shown in FIG. 15, each unit decoder U1X to UMX (X = 1, 2, ..., N) has a triple-well structure, and the N-wells are common to the NMOS transistors Mn25 to Mn27, the MOSFET transistors Mp3 to Mp5, and It is composed of an inverter gate G2, the level shift circuit 27 has a triple-well structure of the level shift circuit 117 of FIG. 5, and the driver circuit 28 has a triple-well structure of the driver circuit 18 of FIG. The ground potential VSS is changed to the non-selection word line voltage VNG1. Therefore, during the erasing operation in which a negative voltage is applied to the word line WL, the negative voltage selector switch circuit 26 supplies the negative voltage VNG (= -8V) only to the desired non-selected word line voltage VNG1 by the negative voltage control signal. Since the ground potential VSS is supplied to the other non-selected word line voltages VNG2 to VNGN, the whole unit decoder U1X to UM

The operation of the non-volatile semiconductor storage device of this embodiment configured as described above will be described below.

In the data erasing operation, the non-selected word line voltage VNG1 (= -8V) is applied as the word line WL voltage to the control gate of the memory cell MC of the sector S1 selected according to the address AD input of the erasing sector S1. Then, 0V is applied to the word line WL of the other sectors S2 to SN. At this time, 5V is applied to all bit lines BL, and the common source line SL has high impedance. As a result, all memory cell MCs in sector S1 connected to the word line WL to which a negative voltage is applied and 5V is applied to the drain terminal through the bit line BL are erased, and electrons are drawn from the floating gate. The threshold value of the memory cell MC decreases in the negative direction. As a specific operation of the power supply circuit and the decoder 2, the high voltage generation booster circuit 7, the low voltage generation booster circuit 8, and the regulator circuit 9 shown in FIG. 13 are all stopped, and the high boost output voltage VPPH and the high voltage boost output voltage VPPH Both the regulator output voltage VRO becomes the power supply potential VCC and is supplied to the voltage changeover switch circuit 17 and the N-well voltage changeover switch 19. Subsequently, in the voltage selector switch circuit 17, the regulator output voltage VRO (= VCC) is selected by the switch control signal supplied from the control circuit 11, and the word line is supplied to all the decoder blocks XDEC1 to XDECN of the row decoder 2. It is supplied as voltages Vwl1 to VwlN. At the same time, in the N-well voltage selector switch 19, the regulator output voltage VRO (= VCC) is selected by the N-well control signal supplied from the control circuit 11, and the regulator output voltage is connected to the N-well potential input terminal of the low decoder 2. VRO (= VCC) is applied. At this time, the negative voltage changeover switch circuit 26 supplies the negative voltage VNG (= -8V) only to the desired non-selected word line voltage VNG1 by the negative voltage control signal, and the other non-selected word line voltages VNG2 to VNGN. Since the ground potential VSS is supplied to, all unit decoders U1X to UMX (X = 1, 2, ..., N) are deselected, and the non-selected word line voltage VNG1 (= -8V) Non-selected working

As described above, according to the fifth embodiment, the same effect as that of the third embodiment is realized, and each decoder block XDEC1 to XDECN constituting the low decoder 2 is a plurality of MOSFET transistors in the N well. And, by being composed of a plurality of NMOS transistors in the P well provided in the N well (triple well structure), it is possible to apply a negative voltage to the word line WL at the time of erasing, and only a positive voltage. It is possible to improve the reliability of the memory cell MC's disturb, endurance characteristics, etc., as compared with the case of erasing using.

In this embodiment, the number of sectors S1 to SN (N) constituting the memory array 1 and the number of non-selected word line voltages VNG1 to VNGN (N) are the same, but they are not necessarily the same. There is no need.

The present invention can be modified in various ways without departing from the gist thereof.

The non-volatile semiconductor storage device according to the present invention has an effect that the time required for write / write verification operation can be shortened while reducing power consumption. A plurality of memory cells are arranged in a matrix, and a plurality of memory cells are arranged in a matrix. It is useful as a non-volatile semiconductor storage device or the like having a memory cell array divided into sectors.

<figref num="1">A block diagram showing a configuration of a non-volatile semiconductor storage device according to the first embodiment of the present invention.</figref><figref num="2">Timing diagram showing write and write verify operations according to the first embodiment of the present invention.</figref><figref num="3">A block diagram showing a configuration of a non-volatile semiconductor storage device according to a second embodiment of the present invention.</figref><figref num="4">A block diagram showing an example of a configuration of a low decoder according to the second, third, and fourth embodiments of the present invention.</figref><figref num="5">A circuit diagram showing a configuration of a unit decoder according to the second, third, and fourth embodiments of the present invention.</figref><figref num="6">Timing diagram showing write and write verify operations in the second embodiment of the present invention.</figref><figref num="7">A block diagram showing a configuration of a non-volatile semiconductor storage device according to a third embodiment of the present invention.</figref><figref num="8">Timing diagram showing the reading operation according to the third embodiment of the present invention.</figref><figref num="9">A block diagram showing a configuration of a non-volatile semiconductor storage device according to a fourth embodiment of the present invention.</figref><figref num="10">A circuit diagram showing an example of the configuration of the discharge circuit according to the fourth embodiment of the present invention.</figref><figref num="11">Level shift circuit according to the fourth embodiment of the present invention</figref><figref num="12">Timing diagram showing write verification and read operation according to the fourth embodiment of the present invention.</figref><figref num="13">A block diagram showing a configuration of a non-volatile semiconductor storage device according to a fifth embodiment of the present invention.</figref><figref num="14">A block diagram showing an example of a configuration of a low decoder according to a fifth embodiment of the present invention.</figref><figref num="15">A circuit diagram showing a configuration of a unit decoder according to a fifth embodiment of the present invention.</figref><figref num="16">Block diagram showing the configuration of a conventional non-volatile semiconductor storage device</figref><figref num="17">Equivalent circuit diagram showing a floating gate type memory cell array</figref><figref num="18">Circuit diagram showing the configuration of the booster circuit for high voltage generation</figref><figref num="19">Circuit diagram showing the configuration of the booster circuit for low voltage generation</figref><figref num="20">Circuit diagram showing the configuration of the regulator circuit</figref><figref num="21">A circuit diagram showing a configuration of a unit decoder according to a conventional method and a first embodiment of the present invention.</figref><figref num="22">Timing diagram showing write and write verify operations in a conventional non-volatile semiconductor storage device</figref>

Code description

1 Memory cell array 2 Low decoder 3 Column decoder 4 Column gate 5 Address / data buffer 6 Sense amplifier 7 High voltage generation booster circuit 8 Low voltage generation booster circuit 9 Regulator circuit 10, 17 Voltage selector switch circuit 11 Control circuit 12 ~ 14 Switch circuit 15, 117, 25, 27 Level shift circuit 16, 18, 28 Driver circuit 19 N-well voltage selector switch 20 Discharge circuit 21 Current mirror unit 22 Voltage detection comparison unit 23 Detection result amplification unit 24 Discharge unit 26 Negative voltage selector switch Circuit S1 ~ SN Sector MC Memory cell BL Bit line SL Common source line WL Word line XDEC1 ~ XDECN Decoder block AD Address DB Data VPPL Low boost output voltage VPPH High boost output voltage VRO Regulator output voltage Vwl1 ~ VwlN Ward line supply voltage MD Mode signal CEB Chip enable signal WEB write enable signal OEB output enable signal Mn1 to Mn6, Mn10 to Mn27 NMOS transistor VCC Power supply potential VSS Ground potential Co Smoothing capacitance Dzh, Dzl Zener diode CMP comparator Mp1 ~ Mp13 photoresist transistor R1 ~ R4 resistance VFB feedback voltage VREF reference voltage NR, N1, N2 node RDB mode control signal ADR row address G1 NAND gate G2, G3 inverter Gate NW N Well node τl1, τl, τs1, τs, τm1, τss Setup time U1X ~ UMX (X = 1, 2, ..., N) Unit decoder Vnwell N Well node voltage DEN Discharge control signal RDY Discharge judgment signal NW [1: 0] N well control signal Vgm mirror gate potential VO detection voltage DENB discharge control bar signal VO1 NAND output voltage VO2 detection result amplification output voltage IN input terminal SUPPLY voltage supply terminal OUT output terminal VNG negative voltage VNG1 ~ VNGN not selected Word line voltage