Semiconductor device, radio chip, ic card, ic tag, transponder, note, securities, passport, electronic equipment, bag, and clothing

The present invention relates to a semiconductor device used as an IC chip (hereinafter, also referred to as ID chip) capable of storing or reading information required in a memory circuit by non-contact means such as wireless communication. In particular, the present invention relates to a semiconductor device used as an ID chip formed on an insulating substrate such as glass or plastic.

With the development of computer technology and the improvement of image recognition technology, information recognition using media such as barcodes has become widespread and is used for recognition of product data. It is expected that a larger amount of information will be recognized in the future. On the other hand, reading information using a barcode has the disadvantages that the barcode reader requires contact with the barcode and that the amount of information recorded on the barcode cannot be increased so much that non-contact information recognition and non-contact information recognition and It is desired to increase the storage capacity of the medium.

In response to these demands, ID chips using ICs have been developed in recent years. An ID chip stores information required for a memory circuit in an IC chip, and reads internal information using non-contact means, generally wireless means. It is expected that the practical application of such ID chips will enable simplification of product distribution, cost reduction, and ensuring high security.

The outline of the individual authentication system using the ID chip will be described with reference to FIG. FIG. 4 is a diagram showing an outline of an individual authentication system for the purpose of obtaining individual information of a bag in a non-contact manner. The ID chip 401 that stores specific individual information is attached to or embedded in the bag 404. Electromagnetic waves are emitted from the antenna unit 402 of the interrogator (also called a lead writer) 403 to the ID chip 401. Upon receiving the electromagnetic wave, the ID chip 401 sends back the individual information contained in the ID chip to the antenna unit 402. The antenna unit 402 sends the sent back individual information to the interrogator 403, and the interrogator 403 discriminates the individual information. In this way, the interrogator 403 can obtain the information of the bag 404. In addition, by using this system, it becomes possible to manage physical distribution, tabulate, and remove counterfeit products.

Examples of such ID chip technology include those shown in FIG. The semiconductor device 200 used for the ID chip is an antenna circuit 201, a rectifier circuit 202, a regulated power supply circuit 203, a modulation circuit 204, an amplifier 205, a logic circuit 206, a demodulation circuit 207, an amplifier 208, a logic circuit 209, a memory control circuit 210, and a memory. It is composed of circuit 211. Further, the antenna circuit 201 is composed of an antenna coil 301 and a tuning capacitance 302 (FIG. 3 (A)). The rectifier circuit 202 is composed of diodes 303 and 304 and a smoothing capacity 305 (FIG. 3 (B)).

The operation of such an ID chip will be described below. The AC signal received by the antenna circuit 201 is half-wave rectified by the diodes 303 and 304 and smoothed by the smoothing capacitance 305. Since this smoothed voltage contains a large number of ripples, it is stabilized by the regulated power supply circuit 203, and the voltage after stabilization is modulated by the modulation circuit 204, the amplifier 205, the logic circuit 206, the demodulation circuit 207, and the amplifier 208. , Logic circuit 209, memory control circuit 210, memory circuit 211. On the other hand, the signal received by the antenna circuit 201 is input to the logic circuit 209 as a clock signal via the amplifier 208. Further, the signal input from the antenna circuit 201 is demodulated by the demodulation circuit 207 and input to the logic circuit 209 as data.

In the logic circuit 209, the input data is decoded. Since the interrogator encodes the data with a modified mirror code, NRZ-L code, etc. and transmits it, the logic circuit 209 decodes it. The decoded data is sent to the memory control circuit 210, and the stored data stored in the memory circuit 211 is read out accordingly. The memory circuit 211 needs to be a non-volatile memory circuit that can be retained even when the power is turned off, and a mask ROM or the like is used. The stored content is, for example, 16 bytes of data (see Fig. 12 (A)), and there are two types: family code 4 bytes indicating the ID chip sequence, application code 4 bytes, and user code 4 bytes set by the user. It has become.

The signals to be transmitted and received include 125kHz, 13.56MHz, 915MHz, 2.45GHz, etc., and ISO standards are set for each. In addition, the modulation / demodulation method for transmission / reception is also standardized (see, for example, Patent Document 1).<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2001-250393</text></patcit>

<p> The conventional semiconductor device for ID chips described above has the following problems. When a mask ROM is used for the memory circuit, data cannot be written except when the chip is manufactured. Therefore, there is a demand for an ID chip capable of writing data other than when the chip is manufactured. In addition, when EEPROM is used for the memory circuit, the user can freely rewrite the contents, but on the other hand, a person other than the original user can rewrite the information that should not be rewritten for authentication, and it is also possible to forge. Is. Therefore, in order to prevent such forgery, there is a demand for an ID chip that can be written only once.</p><p> Therefore, it is an object of the present invention to provide a semiconductor device used as an ID chip that can be rewritten only once in the semiconductor device used for the ID chip. Another object of the present invention is to provide a semiconductor device used as an ID chip capable of writing data other than when the chip is manufactured.</p>

<p> The gist of the present invention is that the memory circuit is composed of a non-volatile memory using a ferroelectric substance, and the memory circuit is provided with a control circuit capable of writing only once. By using a non-volatile memory using a ferroelectric substance, it is possible to enable high-speed reading and writing and improve reliability as compared with a so-called flash memory.</p><p> The present invention has a modulation circuit, a demodulation circuit, a logic circuit, and a memory circuit on an insulating substrate, an antenna circuit is electrically connected to the modulation circuit and the demodulator circuit, and the logic circuit is connected to the demodulator circuit. Is connected, the memory circuit stores the output signal of the logic circuit, the memory circuit is a FeRAM circuit having a dielectric capacitive element, and the memory circuit is characterized by having a control circuit that can be written only once. And.</p><p> Further, the present invention has a modulation circuit, a demodulation circuit, a logic circuit, and a memory circuit on an insulating substrate, an antenna circuit is electrically connected to the modulation circuit and the demodulator circuit, and a logic circuit is connected to the demodulator circuit. The circuit is connected, the memory circuit stores the output signal of the logic circuit, the memory circuit is a FeRAM circuit having a dielectric capacitive element, and the logic circuit determines whether or not the memory circuit can be written by the data stored in the memory circuit. It is characterized by controlling.</p><p> Further, in the semiconductor device, the memory cell constituting the memory circuit is characterized by having two transistors and two ferroelectric capacitive elements.</p><p> Further, in the semiconductor device, the memory cell constituting the memory circuit is characterized by having one transistor and one ferroelectric capacitive element.</p><p> Further, in the semiconductor device, at least one of the modulation circuit, the demodulation circuit, the logic circuit, and the memory circuit is composed of a thin film transistor (hereinafter, also referred to as "TFT (Thin Film Transistor)"). It is characterized by being.</p><p> Further, in the semiconductor device, the antenna circuit, the modulation circuit, the demodulator circuit, the logic circuit, and the memory circuit are integrally formed on the same insulating substrate, or the modulation circuit, the demodulator circuit, and the logic The circuit and the memory circuit are integrally formed on the same insulating substrate, and the antenna circuit is formed on another insulating substrate.</p><p> Further, in the semiconductor device, the antenna circuit is characterized in that it is formed above at least one of a pre-modulation circuit, a demodulation circuit, a logic circuit, and a memory circuit.</p><p> In the present invention, the ID chip is a semiconductor chip used for individual recognition, and is used for a wireless tag, a wireless chip such as RFID, an IC tag, an IC card, a transponder, and the like.</p>

<p> As described above, by using the present invention, it is possible to write information to the memory circuit in the ID chip only once. In this way, data forgery of the ID chip can be prevented, and a semiconductor device used as an ID chip that ensures security can be configured. Further, it is possible to provide a semiconductor device used as an ID chip capable of writing data other than when the chip is manufactured.</p>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, those skilled in the art can easily understand that the present invention can be carried out in many different modes, and that the forms and details thereof can be variously changed without departing from the spirit and scope of the present invention. Will be done. Therefore, the interpretation is not limited to the description of the present embodiment. In the drawings shown below, the same parts or parts having similar functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

The semiconductor device of the present invention will be described. In the following description, RAM using a ferroelectric substance is referred to as FeRAM (Ferroelectric RAM). In FIG. 1, the semiconductor device 100 used for the ID chip is an antenna circuit 101, a rectifier circuit 102, a stabilized power supply circuit 103, a modulation circuit 104, an amplifier 105, a logic circuit 106, a demodulator circuit 107, an amplifier 108, a logic circuit 109, and a FeRAM control. It is composed of a circuit 110 and a FeRAM circuit 111. Further, the antenna circuit 101 is the same as that shown in FIG. 3 (A) in the conventional example. The rectifier circuit 102 is the same as that shown in FIG. 3 (B) in the conventional example. In the present embodiment, the antenna circuit is configured on the semiconductor device 100, but the present invention is not limited to this, and the antenna circuit may be connected to the outside of the semiconductor device 100. The chip of the present invention on which an antenna is mounted is also referred to as a wireless chip.

The operation of such an ID chip will be described below. The AC signal received by the antenna circuit 101 is rectified and smoothed by the rectifier circuit 102. Since this smoothed voltage contains a large number of ripples, it is stabilized by the regulated power supply circuit 103, and the stabilized voltage is supplied to the amplifier 105, the demodulation circuit 107, the amplifier 108, and the logic circuit 109.

The signal input from the antenna circuit 101 is logically operated by the logic circuit 109 and then input to the FeRAM circuit 111. Further, the logic circuit 109 specifies the presence / absence of writing, the address, and the like to the FeRAM control circuit 110. Data is written to the FeRAM circuit 111 according to the instruction of the FeRAM control circuit 110.

When the interrogator calls the data stored in the FeRAM circuit 111, it operates as follows. The AC signal received by the antenna circuit 101 is rectified and smoothed by the rectifier circuit 102. Since this smoothed voltage contains a large number of ripples, it is stabilized by the regulated power supply circuit 103, and the voltage after stabilization is modulated by the modulation circuit 104, the amplifier 105, the logic circuit 106, the demodulation circuit 107, and the amplifier 108. , The logic circuit 109, the FeRAM control circuit 110, and the FeRAM circuit 111. On the other hand, the AC signal received by the antenna circuit is input to the logic circuit 109 through the amplifier 108, and a logical operation is performed. Then, the FeRAM control circuit 110 is controlled by using the signal from the logic circuit 109, and the data stored in the FeRAM circuit 111 is called. Next, the data called from the FeRAM circuit 111 is processed by the logic circuit 106, amplified by the amplifier 105, and then the modulation circuit 104 is operated. Data is processed according to the method specified in the standards such as ISO14443, ISO15693, and ISO18000, but it may be other than the above standards as long as the consistency with the interrogator is ensured.

When the modulation circuit 104 operates, the impedance of the antenna circuit 101 changes. This causes a change in the interrogator signal reflected by the antenna circuit 101. By reading this change by the interrogator, it becomes possible to know the data stored in the FeRAM circuit 111 of the semiconductor device 100. Such a modulation method is called a load modulation method.

Hereinafter, the operation of the FeRAM circuit will be described with reference to FIG. Figure 5 shows an example in which the FeRAM circuit uses the 2T2C method (a method in which one memory cell consists of two transistors and two ferroelectric capacitances). The FeRAM circuit in FIG. 5 is a 4-bit memory circuit for the sake of brevity, but it is not limited to 4 bits. The FeRAM circuit shown in FIG. 5 includes a bit line decoder 501, a word line decoder 502, a plate line decoder 503, a precharge circuit 504, an n-type memory transistor 505 to 512 (hereinafter abbreviated as transistors 505 to 512), and a ferroelectric capacitive element. 513 ~ 520, bit line 521 ~ 524, word line 525, 526, plate line 527, 528, sense amplifier 529, 530, sense amplifier selection switch 531, 532, precharge switch 533 ~ 536, bit line selection switch 537 ~ 540 , Input terminals 541, 542, and output terminals 543.

The ferroelectric capacitive element contained in the memory cell has a three-layer structure as shown in FIG. That is, Pt / IrO₂Lower electrode layer consisting of PZT (PbZrTiO)₃) Etc., Ir / IrO₂It is an upper electrode layer composed of such as. In order to form a good PZT film, it is desirable that the lattice constant of the undercoat film is close to that of PZT. Pt / IrO₂Is chosen for this reason.

The ferroelectric capacitance has a hysteresis characteristic with respect to a voltage. This is shown in Fig. 8. FeRAM uses this hysteresis to form a non-volatile memory. Hereinafter, the memory cell 500 composed of the transistors 505 and 506 will be described as a representative.

Here, a case where the memory cell outputs one of the binary digital signals will be illustrated. In the following description, the high potential signal is referred to as 1 and the low potential signal is referred to as 0. First, consider the case where the memory cell 500 writes so as to output "1". First, a high potential (for example, VDD) is given to the input terminal 541 and a low potential (for example, GND) is given to the input terminal 542. Next, the bit line decoder 501 is operated, and the bit line selection switches 537 and 538 are turned on. As a result, a high potential is supplied to the bit wire 521 and a low potential is supplied to the bit wire 522. At this time, the potential of the plate wire 527 is set to an intermediate potential (for example, VDD / 2). The word wire decoder 502 is then activated to activate the word wire 525, which turns on the transistors 505 and 506, shorts the bit wire 521 and the ferroelectric capacitive element 513, and activates the bit wire 522 and the ferroelectric capacitance. The element 514 is also short-circuited. Therefore, the voltage of VDD / 2 and -VDD / 2 are applied to the ferroelectric capacitive elements 513 and 514, respectively.

This state is shown to be points B and D in FIG. Next, the same potential as the plate wire 527 (here, VDD / 2) is applied to the input terminals 541 and 542. Since the transistors 505 and 506 remain on, the voltage applied between the terminals of the ferroelectric capacitive elements 513 and 514 becomes zero. As a result, the states of the ferroelectric capacitive elements 513 and 514 become points C and E in FIG. Then, the word line decoder 502 is operated to turn off the transistors 505 and 506. In this way, the data is stored in the memory cell 500.

When reading the data in the memory cell 500, the bit line selection switches 537 and 538 are turned off, and the input terminals 541 and 542 and the bit lines 521 and 522 are separated. Next, the precharge switches 533 and 534 are turned on, and the bit wires 521 and 522 are precharged to the same potential by the precharge circuit 504. This potential may be, for example, VDD / 2. After the precharge is completed, the precharge switches 533 and 534 are turned off. Next, the word line decoder 502 is operated to turn on the transistors 505 and 506. Then, the plate wire decoder 503 is operated to set the potential of the plate wire 527 to a high potential (VDD).

Since the potential of the terminal connected to the plate wire 527 of the ferroelectric capacitive elements 513 and 514 rises, the potential of the bit wires 521 and 522 also rises via the transistors 505 and 506. However, since the amount of polarization stored in the ferroelectric capacitive element is different, the rising potentials of the bit wires 521 and 522 are different. The difference voltage can be amplified by the sense amplifier 529 and output to the output terminal 543 via the sense amplifier selection switch 531.

At the time of writing, if the voltage applied to the input terminals 541 and 542 is reversed, the potential of "0" can be written. The reading is the same as above. FeRAM operates in this way.

Next, an embodiment in which writing is performed only once will be described. In this embodiment, as shown in FIG. 12 (B), a bit indicating the write state is added after the memory area (16 bytes in FIG. 12 (B)) originally required by the memory circuit. Data indicating whether or not writing has been performed is stored in this part.

Next, the operation will be described with reference to FIG. FIG. 13 shows the internal block of the logic circuit 109. The logic circuit 109 is composed of a decoding circuit 1301, a delay circuit 1302, a switch 1303, and a volatile memory circuit 1304. At the initial stage, the write / storage bit shown in FIG. 12B shows a state in which writing is not performed. Here, it is assumed that "0" is stored. (For explanation, "0" memory is used, but "1" memory may be used). When a signal is input from the antenna circuit and the regulated power supply is turned on, the FeRAM circuit 111 outputs this value to the volatile memory circuit 1304 inside the logic circuit 109. And the volatile memory circuit stores this value. This volatile memory circuit 1304 does not care about the circuit configuration as long as it can store DRAM, SRAM, registers, etc.

On the other hand, the signal input from the demodulation circuit 107 is decoded by the decoding circuit 1301 and input to the switch 1303 via the delay circuit 1302. The switch 1303 is controlled by the volatile memory circuit 1304, and if the data of the volatile memory circuit 1304 is "0" as shown above, it operates to turn on the switch 1303. When the switch 1303 is on, the signal is output to the FeRAM circuit 111 and written to the FeRAM circuit 111. When the writing is completed, "1" is stored in the write storage bit shown in FIG. 12 (B) (when the initial value is "1", "0" is stored). The delay circuit 1302 is for preventing data from passing through the switch 1303 and being output to the FeRAM circuit before the stabilized power supply is turned on and the state of the switch 1303 is confirmed. Therefore, malfunction may be prevented before the switch is confirmed.

When "1" is stored in the write / storage bit shown in FIG. 12B, the volatile memory circuit 1304 operates so as to turn off the switch 1303. In this way, since the data after the first time cannot pass through the switch 1303, the writing to the FeRAM circuit is limited to one time.

Next, an embodiment of one-time writing different from that of FIG. 13 will be described with reference to FIG. FIG. 9 shows the internal block of the logic circuit 109. The logic circuit 109 is composed of a decoding circuit 901, a delay circuit 902, a switch 903, and a 1-bit FeRAM circuit 904. The write storage bit shown in FIG. 12 (B) is stored in the 1-bit FeRAM904, and in the initial state, it shows a state in which writing is not performed. Here, it is assumed that "0" is stored. (For explanation, "0" memory is used, but "1" memory may be used).

When a signal is input from the antenna circuit and the regulated power supply is turned on, the signal input from the demodulation circuit 107 via the antenna circuit is decoded by the decoding circuit 901, and is input to the switch 903 via the delay circuit 902. The switch 903 is controlled by the 1-bit FeRAM circuit 904, and if the data of the 1-bit FeRAM circuit 904 is "0" as shown above, it operates to turn on the switch 903. When the switch 903 is on, the signal is output to the FeRAM circuit 111 and written to the FeRAM circuit 111. When the writing is completed, the FeRAM control circuit stores "1" in the write storage bit (inside the 1-bit FeRAM circuit 904) shown in FIG. 12 (B) ("0" when the initial value is "1". Remember). The delay circuit 902 is for preventing data from passing through the switch 903 and being output to the FeRAM circuit before the stabilized power supply is turned on and the state of the switch 903 is determined, and a means other than the delay circuit is used. Therefore, malfunction may be prevented before the switch is confirmed.

When "1" is stored in the write / storage bit shown in FIG. 12B, the 1-bit FeRAM circuit 904 operates so as to turn off the switch 903. In this way, since the data after the first time cannot pass through the switch 903, the writing to the FeRAM circuit 111 is limited to one time.

As described above, by using FeRAM, high-speed reading and writing can be enabled and reliability can be improved. Further, by providing a control circuit that enables writing to the memory circuit only once, information can be written to the memory circuit in the ID chip only once. In this way, it is possible to prevent data forgery of the ID chip and provide an ID chip that ensures security.

Hereinafter, the operation of the FeRAM circuit different from the embodiment will be described with reference to FIG. 7. Figure 7 shows an example in which the FeRAM circuit is a 1T1C system (a system in which one memory cell is composed of one transistor and one ferroelectric capacitance). The FeRAM circuit in FIG. 7 is a 4-bit memory circuit for simplification of explanation, but is not limited to 4-bit. The FeRAM circuit shown in FIG. 7 includes a bit line decoder 701, a word line decoder 702, a plate line decoder 703, a precharge circuit 704, an n-type memory transistor 705 to 708 (hereinafter, may be abbreviated as transistor 705 to 708), and a ferroelectric substance. Body capacitance elements 709 to 712, bit wire 713, 714, word wire 715, 716, plate wire 717, 718, sense amplifier 719, 720, sense amplifier selection switch 721, 722, precharge switch 723, 724, bit line selection switch It is composed of 725, 726, input terminal 727, and output terminal 728.

Hereinafter, the memory cell 700 composed of the transistor 705 will be described as a representative. First, consider the case where the memory cell 700 writes to output "1". First, a high potential (for example, VDD) is applied to the input terminal 727. Next, the bit line decoder 701 is operated and the bit line selection switch 725 is turned on. As a result, a high potential is supplied to the bit wire 713. At this time, the potential of the plate wire 717 is set to an intermediate potential (for example, VDD / 2). The word line decoder 702 is then activated to activate the word line 715, which turns on the transistors 705 and 706 and short-circuits the bit line 713 and the ferroelectric capacitive element 709. Therefore, a voltage of VDD / 2 is applied to the ferroelectric capacitive element 709.

This state is shown to be the point B in FIG. Next, the same potential as the plate wire 717 (here, VDD / 2) is applied to the input terminal 727. Since the transistors 705 and 706 remain on, the voltage applied between the terminals of the ferroelectric capacitive element 709 becomes zero. As a result, the state of the ferroelectric capacitive element 709 becomes the point C in FIG. Then, the word line decoder 702 is operated to turn off the transistors 705 and 706. In this way, the data is stored in the memory cell 700.

When reading the data in the memory cell 700, the bit line selection switch 725 is turned off, and the input terminal 727 and the bit line 713 are separated. Next, the precharge switch 723 is turned on, and the bit line 713 is precharged to VDD / 2 by the precharge circuit 704. After the precharge is completed, the precharge switch 723 is turned off. Next, the word line decoder 702 is operated to turn on the transistors 705 and 706. Then, the plate wire decoder 703 is operated to set the potential of the plate wire 717 to a high potential (VDD).

Since the potential of the terminal connected to the plate wire 717 of the ferroelectric capacitive element 709 rises, the potential of the bit wire 713 also rises via the transistor 705. However, the rising voltage differs depending on the amount of polarization stored in the ferroelectric capacitive element. The difference between the reference voltage and the bit line voltage can be amplified by the sense amplifier 719 and output to the output terminal 728 via the sense amplifier selection switch 721.

At the time of writing, if the voltage applied to the input terminal 727 is reversed, the potential of "0" can be written. The reading is the same as above. In this way, the FeRAM of this embodiment operates.

An example of a regulated power supply circuit will be described with reference to FIG. The regulated power supply circuit consists of a reference voltage circuit and a buffer amplifier. The reference voltage circuit is composed of a resistor 2201 and diode-connected transistors 2202 and 2203, and generates a reference voltage equivalent to two VGSs of the transistors. The buffer amplifier is composed of a differential circuit composed of transistors 2205 and 2206, a current mirror circuit composed of transistors 2207 and 2208, a current supply resistor 2204, a transistor 2209, and a source grounded amplifier composed of a resistor 2210.

When the current flowing from the output terminal is larger, the current flowing through the transistor 2209 is smaller, and when the current flowing from the output terminal is smaller, the current flowing through the transistor 2209 is larger, and the current flowing through the resistor 2210 is almost constant. Operate. The potential of the output terminal is almost the same as that of the reference voltage circuit. Here, a regulated power supply circuit including a reference voltage circuit and a buffer amplifier is shown, but the regulated power supply circuit used in the present invention is not limited to the above, and may be a circuit of another type.

A method of simultaneously producing the memory element shown in the embodiment and the TFT used for the logic circuit portion such as the decoder on the insulating substrate will be described with reference to FIGS. 14 to 17. In this embodiment, a capacitance using a ferroelectric material and an n-channel type TFT and a p-channel type TFT as semiconductor elements are shown as examples, but in the present invention, the semiconductor element included in the memory unit and the logic circuit unit. Is not limited to this. Further, this manufacturing method is an example, and does not limit the manufacturing method on the insulating substrate.

First, in FIG. 14A, as the substrate 4000, for example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a stainless steel substrate, or the like can be used. Further, a substrate made of a flexible synthetic resin such as plastic generally tends to have a lower heat resistant temperature than the above substrate, but can be used as long as it can withstand the processing temperature in the manufacturing process. Is.

Base films 4001 and 4002 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxide film are formed on the substrate 4000. For example, as the base film 4001, SiH by plasma CVD method₄, NH₃, N₂A silicon oxynitride film made from O is formed at 10 to 200 nm (preferably 50 to 100 nm), and SiH is used as the base film 4002.₄, N₂A silicon oxide hydrogenated silicon film made from O is laminated and formed to a thickness of 50 to 200 nm (preferably 100 to 150 nm). In this embodiment, the base film is shown as a two-layer structure, but it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are laminated. Further, if the diffusion of impurities such as a quartz substrate does not pose a problem, it is not always necessary to provide the mixture.

The island-shaped semiconductor layers 4003 to 4005 are formed of a crystalline semiconductor film having an amorphous structure formed by a laser crystallization method or a known thermal crystallization method (FIG. 14 (B)). The island-shaped semiconductor layers 4003 to 4005 are formed to have a thickness of 25 to 100 nm (preferably 30 to 60 nm). The island-shaped semiconductor layers 4003 to 4005 may be amorphous semiconductors or polycrystalline semiconductors. Further, as the semiconductor, not only silicon but also silicon germanium can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%.

To produce a crystalline semiconductor film by the laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO₄Use a laser. When these lasers are used, it is preferable to use a method in which the laser light emitted from the laser oscillator is linearly focused by an optical system and irradiated to the semiconductor film. The crystallization conditions are appropriately selected by the practitioner, but when using an excimer laser, the pulse oscillation frequency is set to 30 Hz and the laser energy density is 100 to 400 mJ / cm.²(Typically 200 ~ 300mJ / cm²). When using a YAG laser, use its second harmonic and set the pulse oscillation frequency to 1 to 10 kHz, and set the laser energy density to 300 to 600 mJ / cm.²(Typically 350 ~ 500mJ / cm²). Then, the laser beam focused linearly with a width of 100 to 1000 μm, for example, 400 μm is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is set to 80 to 98%.

Next, a gate insulating film 4006 covering the island-shaped semiconductor layers 4003 to 4005 is formed (FIG. 14 (C)). The gate insulating film 4006 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this example, it is formed of a silicon oxide film having a thickness of 120 nm. Of course, the gate insulating film 4006 is not limited to such a silicon oxide nitride film, and an insulating film containing other silicon may be used as a single layer or a laminated structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Ortho Silicate) and O2 are mixed by the plasma CVD method, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C, the high frequency (13.56 MHz), and the power density is 0.5. ~ 0.8W / cm²It can be formed by discharging with. The silicon oxide film thus produced can subsequently obtain good properties as an insulating film by thermal annealing at 400 to 500 ° C.

Next, as shown in FIG. 15A, gate electrodes 4100 to 4102 are formed on the gate insulating film 4006. The gate electrodes 4100 to 4102 may be formed of tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), an alloy containing the above elements as a main component, polycrystalline silicon, or the like. First, a conductive layer is formed on the surface of the gate insulating film 4006, and the conductive layer is etched with a resist mask (not shown) to form gate electrodes 4100 to 4102.

Then, the impurity element that imparts N-type is doped. In this way, low-concentration n-type impurity regions 4103 to 4108 are formed in the semiconductor active layer.

Next, a resist mask (not shown) is formed so as to cover the gate electrode 4102, n-type impurity elements are added in a self-aligned manner using the gate electrode 4101 and the resist mask as a mask, and the gate electrode 4101 is used as a mask. Add p-type impurity elements in a self-aligned manner.

In this way, the high-concentration n-type impurity regions 4111, 4112, 4113, 4114 functioning as the source region or drain region of the n-channel TFT and the high-concentration p-type impurity regions 4109, 4110 functioning as the source region or drain region of the p-channel TFT. To form. Phosphorus (P) or arsenic (As) is used as the impurity element that imparts n-type, and boron (B) is used as the impurity element that imparts p-type.

Then, the n-type and p-type impurity elements are activated. As the activating means, furnace anneal, laser anneal, lamp anneal, or a combination of these may be used. The thermal annealing method is carried out at a heating temperature of 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.

Then, as shown in FIG. 15C, a first interlayer insulating film 4115 made of a silicon nitride film or a silicon oxynitride film is formed on the gate electrodes 4100 to 4102.

As described above, the switching TFT that constitutes the pixel portion and the TFT that constitutes the drive circuit and other logic circuits are formed on the same substrate. Next, a capacitance is formed on the first interlayer insulating film 4115 using a ferroelectric material.

First, the lower electrode layer 4201 is formed (Fig. 16 (A)). The forming method may be selected from a CVD method, a sputtering method, an ion beam sputtering method, a laser ablation method and the like. Pt / IrO for the material of the lower electrode layer 4201₂, Pt / Ta / SiO₂Etc. can be used. Since the electrical properties of the ferroelectric thin film strongly depend on the crystal orientation, it is particularly preferable to use Pt on the surface of the lower electrode, which is easy to control the orientation. After forming the metal film, the unnecessary portion is treated by plasma etching or the like to form the lower electrode layer 4201.

Next, the ferroelectric layer 4202 is formed on the lower electrode layer 4201 (FIG. 16 (B)). Ferroelectrics are PZT and PbTiO₃Lead-containing perovskite, Bi₄Ti₃O₁₂Bismuth layered compounds such as LiNbO₃, LiTaO₃Ilmenite compounds such as these can be used. Of these, a ferroelectric substance using lead-containing perovskite, particularly PZT, is preferable because it exhibits properties of the ferroelectric substance in a wide composition range.

The method for forming the ferroelectric layer 4202 may be selected from a CVD method, a sputtering method, an ion beam sputtering method, a laser ablation method, and the like. In particular, the CVD method is preferable because it has high controllability of film composition and crystallinity, and is excellent in large area and mass production. When formed by the CVD method, the material conditions are that it has a large vapor pressure at a relatively low temperature and is stable for a long period of time, that the deposition rate is determined by the amount of raw material supplied within the deposition temperature range, and that it is in the vapor phase. PZT is also excellent in these respects, such as the fact that the nucleation reaction does not occur.

The process of forming the ferroelectric layer by the CVD method may follow a known procedure. For example, a ferroelectric layer can be formed by PZT at a pressure of 660 Pa and a substrate temperature of 500 to 650 degrees.

Next, the upper electrode layer 4203 is formed on the ferroelectric layer 4202 (Fig. 16 (C)). As with the lower electrode layer 4201, the forming method can be selected from a CVD method, a sputtering method, an ion beam sputtering method, a laser ablation method, and the like. The material of the upper electrode layer 4203 includes the material used in the lower electrode layer 4201 and Ir / IrO.₂Etc. can be used.

Next, as shown in FIG. 17 (A), after forming a second interlayer insulating film 4307 made of a silicon nitride film or a silicon oxynitride film as a material, a contact hole is formed, and the contact hole is formed through the contact hole. Form wirings 4300-4306. The form of electrical connection between the wirings 4300 to 4306 and the TFT is not limited to this embodiment.

Finally, as shown in FIG. 17 (B), the protective layer 4308 is formed on the second interlayer insulating film 4307. As the material of the protective layer 4308, a photocurable or thermosetting organic resin material such as polyimide or acrylic resin can be used.

Through such a procedure, a capacitance using a TFT that constitutes a pixel portion, a TFT that constitutes a drive circuit or another logic circuit, and a ferroelectric material that constitutes a non-volatile latch circuit is simultaneously produced on the same substrate. can do.

In this embodiment, a case is shown in which a structure having an LDD region that does not overlap with the gate electrode is manufactured as the switching TFT constituting the pixel, and a single drain structure is manufactured as the TFT constituting the drive circuit and the logic circuit. However, this embodiment is not limited to this structure. If necessary, a TFT structure suitable for applications such as a GOLD structure and other LDD structures may be produced according to a known method.

An example of constructing a flexible ID tag by using the peeling process will be described with reference to FIG. The ID tag is composed of flexible protective layers 2301 and 2303 (hereinafter sometimes abbreviated as protective layers 2301 and 2303), and an ID chip 2302 formed by a peeling process. In this embodiment, the antenna 2304 is formed on the protective layer 2303, not on the ID chip 2302, and is electrically connected to the ID chip 2302. Although it is formed only on the protective layer 2303 in FIG. 21 (A), the antenna 2304 may also be formed on the protective layer 2301. The antenna is preferably silver, copper, or a metal plated with them. The ID chip 2302 and the antenna 2304 are connected by using an anisotropic conductive film and UV treatment, but the connection method is not limited to this.

FIG. 21 (B) shows a cross section of FIG. 21 (A). The thickness of the ID chip 2302 is 5 μm or less, preferably 0.1 μm to 3 μm. The thickness of the protective layers 2301 and 2303 is preferably (d / 2) ± 30 μm, where d is the thickness when the protective layers 2301 and 2303 are stacked, especially (d / 2). ± 10 μm is the best. The thickness of the protective layers 2301 and 2303 is preferably 10 μm to 200 μm. The area of the ID chip 2302 is 5 mm square or less, and preferably has an area of 0.3 mm square to 4 mm square.

The protective layers 2301 and 2303 are made of an organic resin material and have a structure resistant to bending. Since the ID chip 2302 itself using the peeling process is more resistant to bending than the single crystal semiconductor, it can be brought into close contact with the protective layers 2301 and 2303. An ID chip surrounded by such protective layers 2301 and 2303 may be placed on the surface or inside of yet another individual. It may also be embedded in paper.

A case where the ID chip is placed on a curved surface, that is, an example in which the TFT is arranged perpendicular to the direction in which the ID chip draws an arc will be described with reference to FIG. The TFT included in the ID chip of FIG. 19 has a linear arrangement in which the current flows, that is, the positions of the drain electrode, the gate electrode, and the source electrode are linear, and the influence of stress is reduced. By performing such an arrangement, fluctuations in the TFT characteristics can be suppressed. In addition, the crystals that make up the TFT are aligned in the direction of current flow, and by forming these with CWLC or the like, the S value is 0.35 V / dec or less (preferably 0.09 to 0.25 V / dec), and the mobility is increased. It can be 100 cm2 / Vs or more. When a 19-stage ring oscillator is configured using such a TFT, the oscillation frequency has a characteristic of 1 MH or more, preferably 100 MHz or more at a power supply voltage of 3 to 5 V. At a power supply voltage of 3 to 5 V, the delay time per stage of the inverter is 26 ns, preferably 0.26 ns or less.

In addition, in order not to destroy active elements such as TFTs against stress, the area of the active area (silicon island portion) of active elements such as TFTs occupies 5% to 50% of the total area. Is desirable. Underlayer insulating materials, interlayer insulating materials, and wiring materials are mainly provided in regions where active elements such as TFTs do not exist. The area other than the active area of the TFT is preferably 60% or more of the total area. The thickness of the active region of the active device is preferably 20 nm to 200 nm, typically 40 to 170 nm. When the active region is wide, the thickness of the active region is preferably 45 to 55 nm, and when the active region is narrow, the thickness of the active region is preferably 145 to 155 nm.

In this embodiment, an example in which an external antenna is attached to the circuit using the present invention will be described with reference to FIGS. 10 and 11.

Figure 10 (A) shows the circuit covered with a one-sided antenna. The antenna 1001 is configured on the substrate 1000, and the circuit 1002 using the present invention is connected. In the drawing, the circuit 1002 is covered with the antenna 1001, but the entire substrate may be covered with the antenna 1001 and the circuit 1002 having the electrodes may be attached on the antenna 1001.

Figure 10 (B) shows a thin antenna arranged around the circuit. The antenna 1004 is configured on the substrate 1003, and the circuit 1005 using the present invention is connected. The arrangement of the antenna wiring is an example and is not limited to this.

Figure 10 (C) shows a form of antenna shape for receiving high-frequency electromagnetic waves. The antenna 1007 is configured on the substrate 1006, and the circuit 1008 using the present invention is connected.

Figure 10 (D) shows a 180-degree omnidirectional antenna (which can be received from any direction). The antenna 1010 is configured on the substrate 1009, and the circuit 1011 using the present invention is connected.

Figure 10 (E) shows an antenna that is elongated in a rod shape. The antenna 1013 is configured on the substrate 1012, and the circuit 1014 using the present invention is connected.

The circuit using the present invention and the connection to these antennas can be performed by a known method. For example, the antenna and the circuit may be connected by wire bonding connection or bump connection, or one side of the chipped circuit may be used as an electrode and attached to the antenna. In this method, the circuit can be attached to the antenna using ACF (anisotropic conductive film).

The appropriate length of the antenna depends on the frequency used for reception. Generally, it is recommended to set the length to an integral fraction of the wavelength. For example, when the frequency is 2.45 GHz, it may be about 60 mm (1/2 wavelength) and about 30 mm (1/4 wavelength).

Further, a substrate may be mounted on the circuit of the present invention, and an antenna may be configured on the substrate. 11 (A) to 11 (C) show a top view and a cross-sectional view of a circuit board 1100 mounted on a circuit and a spiral antenna 1101 arranged as an example.

The example shown in this embodiment is only one example, and does not limit the shape of the antenna. The present invention can be implemented for antennas of any shape. This embodiment can be realized by using a configuration consisting of any combination of the embodiment and the above-described Examples 1 to 5.

In this embodiment, a specific method for manufacturing a thin film integrated circuit device including a TFT will be described with reference to FIGS. 22 to 24. Here, for the sake of simplicity, the manufacturing method will be described by showing the cross-sectional structure of the CPU and the memory unit using the n-type TFT and the p-type TFT.

First, the release layer 61 is formed on the substrate 60 (FIG. 22 (A)). Here, an a-Si film (amorphous silicon film) having a film thickness of 50 nm (500 Å) was formed on a glass substrate (for example, a 1737 substrate manufactured by Corning Inc.) by a reduced pressure CVD method. As the substrate 60, in addition to the glass substrate, a quartz substrate, a substrate formed of an insulating material such as alumina, a silicon wafer substrate, a plastic substrate having heat resistance that can withstand the processing temperature in the subsequent process, and the like can be used. it can.

The release layer 61 contains silicon as a main component, such as polycrystalline silicon, single crystal silicon, and SAS (semi-amorphous silicon (also referred to as microcrystalline silicon or microcrystal silicon)), in addition to amorphous silicon. It is desirable, but not limited to, to use a membrane. The release layer 61 may be formed by a plasma CVD method, a sputtering method, or the like, in addition to the reduced pressure CVD method. Further, a membrane doped with impurities such as phosphorus may be used. The film thickness of the release layer 61 is preferably 50 to 60 nm. For SAS, it may be 30 to 50 nm.

Next, a protective film 55 (sometimes called a base film or a base insulating film) is formed on the release layer 61 (FIG. 22 (A)). Here, the protective film 55 is sequentially applied from the release layer 61 side to a SiON (silicon oxide containing nitrogen) film having a film thickness of 100 nm, a SiNO (silicon nitride containing oxygen) film having a film thickness of 50 nm, and a SiON film having a film thickness of 100 nm. Although it has a layered structure, the material, film thickness, and number of layers are not limited to this. For example, instead of the lower SiON film, a heat-resistant resin such as siloxane having a film thickness of 0.5 to 3 μm may be formed by a spin coating method, a slit coater method, a droplet ejection method, or the like. Further, a silicon oxide film may be used instead of the SiON film in the upper layer. In addition, silicon nitride film (SiN, Si)₃N₄Etc.) may be used. Further, each film thickness is preferably 0.05 to 3 μm, and can be freely selected from the range.

Here, the silicon oxide film is SiH.₄/ O₂, TEOS (Tetraethoxysilane) / O₂It can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECR CVD, etc. using a mixed gas such as The silicon nitride film is typically SiH.₄/ NH₃It can be formed by plasma CVD using a mixed gas of. The SiON film or SiNO film is typically SiH.₄/ N₂It can be formed by plasma CVD using a mixed gas of O.

When a silicon-based material such as a-Si is used as the release layer 61 and the island-shaped semiconductor film 57, SiOxNy is used as the protective film 55 in contact with them from the viewpoint of ensuring adhesion. You may.

Next, a thin film transistor (TFT) constituting the CPU and memory unit of the thin film integrated circuit device is formed on the protective film 55. In addition to TFTs, thin film active elements such as organic TFTs and thin film diodes can also be formed.

As a method for producing the TFT, first, an island-shaped semiconductor film 57 is formed on the protective film 55 (FIG. 22 (B)). The island-shaped semiconductor film 57 is formed of an amorphous semiconductor, a crystalline semiconductor, or a semi-amorphous semiconductor. In either case, a semiconductor film containing silicon, silicon germanium (SiGe) or the like as a main component can be used.

Here, amorphous silicon having a film thickness of 70 nm was formed, and the surface thereof was further treated with a nickel-containing solution. Further, a crystalline silicon semiconductor film was obtained by a thermal crystallization step at 500 to 750 ° C., and laser crystallization was performed to improve the crystallinity. Further, as the film forming method, a plasma CVD method, a sputtering method, an LPCVD method or the like may be used. Crystallization methods include laser crystallization, thermal crystallization, thermal crystallization using other catalysts (Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, etc.), or alternating them. You may go to.

Further, as the crystallization treatment of the semiconductor film having an amorphous structure, a continuously oscillating laser may be used, and in order to obtain crystals having a large particle size during crystallization, a solid-state laser capable of continuous oscillation is used. , It is preferable to apply the 2nd to 4th harmonics of the fundamental wave (crystallization in this case is called CWLC). Typically, Nd: YVO₄The second harmonic (532 nm) or third harmonic (355 nm) of the laser (primary wave 1064 nm) may be applied. When using a continuously oscillating laser, a continuously oscillating YVO with an output of 10W₄The laser light emitted from the laser is converted into harmonics by a nonlinear optical element. Also, YVO in the resonator₄Crystal or GdVO₄There is also a method of inserting a crystal and a non-linear optical element to emit harmonics. Then, preferably, the laser beam having a rectangular or elliptical shape is formed on the irradiation surface by an optical system, and the object to be processed is irradiated. The energy density at this time is 0.01 to 100 MW / cm²Degree (preferably 0.1-10 MW / cm²)is required. Then, the semiconductor film may be moved and irradiated relative to the laser beam at a speed of about 10 to 2000 cm / s.

When a pulse-oscillating laser is used, a frequency band of several tens of Hz to several hundreds of Hz is usually used, but a pulse-oscillating laser having an oscillation frequency of 10 MHz or more, which is significantly higher than that, may be used (in this case). Crystallization is called MHzLC). It is said that the time from irradiating the semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is said to be several tens of nsec to several hundred nsec. Therefore, by using the above high frequency band, the semiconductor film can be made. The laser light of the next pulse can be irradiated from the time of melting by the laser light to the time of solidification. Therefore, unlike the case of using a conventional pulse oscillation laser, the solid-liquid interface can be continuously moved in the semiconductor film, so that a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Will be done. Specifically, it is possible to form an aggregate of crystal grains having a width of 10 to 30 μm in the scanning direction of the contained crystal grains and a width of about 1 to 5 μm in the direction perpendicular to the scanning direction. By forming single crystal grains extending long along the scanning direction, it is possible to form a semiconductor film having almost no grain boundaries at least in the TFT channel direction.

When siloxane, which is a heat-resistant organic resin, is used as a part of the protective film 55, it is possible to prevent heat from leaking from the semiconductor film during the above crystallization, and crystallization can be performed efficiently. It can be carried out.

A crystalline silicon semiconductor film is obtained by the above method. It is desirable that the crystals are aligned in the source, channel, and drain directions. The thickness of the crystal layer is preferably 20 to 200 nm (typically 40 to 170 nm, more preferably 50 to 150 nm). Then, an amorphous silicon film for gettingtering the metal catalyst was formed on the semiconductor film via an oxide film, and the gettering treatment was performed by heat treatment at 500 to 750 ° C. Furthermore, in order to control the threshold value as a TFT element, 10 is applied to the crystalline silicon semiconductor film.¹³/cm²A custom dose amount of boron ions was injected. Then, the island-shaped semiconductor film 57 was formed by etching using the resist as a mask.

In forming a crystalline semiconductor film, disilane (Si)₂H₆) And germanium fluoride (GeF)₄), A crystalline semiconductor film can also be obtained by directly forming a polycrystalline semiconductor film by the LPCVD (vacuum CVD) method. Gas flow ratio is Si₂H₆/ GeF₄= 20 / 0.9, the film formation temperature was 400 to 500 ° C, and He or Ar was used as the carrier gas, but the present invention is not limited to this.

In the TFT, especially in the channel area, 1x10¹⁹~1×10²²cm^-3, Preferably 1x10¹⁹~5×10²⁰cm^-3Hydrogen or halogen should be added. For SAS, 1x10¹⁹~2×10²¹cm^-3Is desirable. In any case, it is desirable that the content is higher than the content of hydrogen or halogen contained in the single crystal used for the IC chip. As a result, even if a local crack occurs in the TFT portion, it can be terminated by hydrogen or halogen.

Next, the gate insulating film 58 is formed on the island-shaped semiconductor film 57 (FIG. 22 (B)). The gate insulating film 58 is preferably formed by using a thin film forming method such as a plasma CVD method or a sputtering method, and forming a film containing silicon nitride, silicon oxide, silicon oxide or silicon oxide in a single layer or in a laminated manner. .. In the case of laminating, for example, it is preferable to have a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film from the substrate side.

Next, the gate electrode 56 is formed (FIG. 22 (C)). Here, the gate electrode 56 was formed by laminating and forming Si and W (tungsten) by a sputtering method and then etching using the resist 62 as a mask. Of course, the material, structure, and manufacturing method of the gate electrode 56 are not limited to this, and can be appropriately selected. For example, it may be a laminated structure of Si and NiSi (nickel silicide) doped with n-type impurities, or a laminated structure of TaN (tantalum nitride) and W (tungsten). Further, it may be formed in a single layer by using various conductive materials.

Further, a mask such as SiOx may be used instead of the resist mask. In this case, a pattern forming step of a mask (called a hard mask) of SiOx, SiON, etc. is added, but since the film loss of the mask at the time of etching is less than that of the resist, it is possible to form a gate electrode layer having a desired width. it can. Further, the gate electrode 56 may be selectively formed by using the droplet ejection method without using the resist 62.

As the conductive material, various materials can be selected depending on the function of the conductive film. Further, when the gate electrode and the antenna are formed at the same time, the material may be selected in consideration of their functions.

The etching gas used for etching and forming the gate electrode is CF.₄, Cl₂, O₂Mixed gas and Cl₂Gas was used, but it is not limited to this.

Next, the portion to be the p-type TFT 70, 72 is covered with the resist 63, and the impurity element 64 (typically P) that imparts the n-type into the island-shaped semiconductor film of the n-type TFT 69, 71 using the gate electrode as a mask. (Phosphorus) or As (arsenic)) is doped to a low concentration (first doping step (light doping of n-type impurity element), FIG. 22 (D)). The condition of the first doping step is the dose amount: 1 × 10¹³~6×10¹³/cm², Acceleration voltage: 50 ~ 70keV, but not limited to this. By this first doping step, through doping is performed through the gate insulating film 58 to form a pair of low-concentration impurity regions 65. The first doping step may be performed on the entire surface of the p-type TFT region without covering it with a resist.

Next, after removing the resist 63 by ashing or the like, a resist 66 covering the n-type TFT region is newly formed, and the p-type is imparted to the island-shaped semiconductor films of the p-type TFT 70 and 72 using the gate electrode as a mask. Impurity element 67 (typically B (boron)) is doped at a high concentration (second doping step (light doping of p-type impurity element), FIG. 22 (E)). The condition of the second doping step is the dose amount: 1 × 10¹⁶~3×10¹⁶/cm², Acceleration voltage: 20 ~ 40keV. By this second doping step, through doping is performed through the gate insulating film 58, and a pair of p-type high-concentration impurity regions 68 are formed.

Next, after removing the resist 66 by ashing or the like, an insulating film 75 was formed on the substrate surface (FIG. 23 (A)). Here, SiO with a film thickness of 100 nm₂The film was formed by the plasma CVD method. Then, the insulating film 75 and the gate insulating film 58 were removed by etching by the etch back method, and the sidewall (side wall) 76 was formed in a self-aligned manner (FIG. 23 (B)). CHF as the etching gas₃And He mixed gas was used. The process of forming the sidewall is not limited to these.

The method of forming the sidewall 76 is not limited to the above. For example, the method shown in FIG. 24 can be used. FIG. 24 (A) shows an example in which the insulating film 75 has a two-layer or more laminated structure. The insulating film 75 has, for example, a two-layer structure consisting of a SiON (silicon oxynitride) film having a film thickness of 100 nm and an LTO film (Low Temperature Oxide) having a film thickness of 200 nm. Here, the SiON film is formed by the plasma CVD method, and the LTO film is SiO.₂The membrane was formed by the reduced pressure CVD method. After that, by performing etch back, a sidewall 76 composed of an L-shape and an arc-shape is formed.

Further, FIG. 24 (B) shows an example in which etching is performed so as to leave the gate insulating film 58 at the time of etching back. The insulating film 75 in this case may have a single-layer structure or a laminated structure.

The sidewall functions as a mask when a high-concentration n-type impurity is later doped to form a low-concentration impurity region or a non-doped offset region under the sidewall 76. In any of the forming methods, the etching back conditions may be appropriately changed depending on the width of the low-concentration impurity region or the offset region to be formed.

Next, a resist 77 that covers the p-type TFT region is newly formed, and the gate electrode 56 and the sidewall 76 are used as masks, and the impurity element 78 (typically P or As) that imparts the n-type is doped at a high concentration. (Third doping step (heavy doping of n-type impurity element), FIG. 23 (C)). The condition of the third doping step is the dose amount: 1 × 10¹³~5×10¹⁵/cm², Acceleration voltage: 60 ~ 100keV. This third doping step forms a pair of n-type high-concentration impurity regions 79.

After removing the resist 77 by ashing or the like, the impurity region may be thermally activated. For example, after forming a 50 nm SiON film, heat treatment may be performed at 550 ° C. for 4 hours in a nitrogen atmosphere. Further, by forming a SiNx film containing hydrogen to a film thickness of 100 nm and then performing a heat treatment at 410 ° C. for 1 hour in a nitrogen atmosphere, defects in the crystalline semiconductor film can be improved. This terminates the dangling bond existing in the crystalline silicon, for example, and is called a hydrogenation treatment step or the like. Further, after that, a SiON film having a film thickness of 600 nm is formed as a cap insulating film that protects the TFT. The hydrogenation treatment step may be performed after the SiON film is formed. In this case, the SiNx and SiON films can be continuously formed. As described above, an insulating film formed by sequentially laminating SiON, SiNx, and SiON is formed on the TFT, but the structure and material thereof are not limited to these. In addition, since these insulating films also have a function of protecting the TFT, it is desirable to form them as much as possible.

Next, the interlayer film 53 is formed on the TFT (FIG. 23 (D)). As the interlayer film 53, a heat-resistant organic resin such as polyimide, acrylic, polyamide, or siloxane can be used. As the forming method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. are adopted depending on the material. be able to. Further, an inorganic material may be used, in which case silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), BPSG (phosphorus glass), alumina film and the like can be used. The interlayer film 53 may be formed by laminating these insulating films.

Further, the protective film 54 may be formed on the interlayer film 53. As the protective film 54, a film having carbon such as DLC (diamond-like carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride film, or the like can be used. As a forming method, a plasma CVD method, an atmospheric pressure plasma, or the like can be used. Alternatively, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, resist or benzocyclobutene, or a heat-resistant organic resin such as siloxane may be used.

In addition, in order to prevent peeling and cracking of these films due to stress generated by the difference in the coefficient of thermal expansion between the interlayer film 53 or the protective film 54 and the conductive material or the like constituting the wiring to be formed later, the interlayer film 53 or the protective film 54 is formed between layers. The filler may be mixed in the film 53 or the protective film 54.

Next, after forming the resist, a contact hole is formed by etching to form a wiring 51 for connecting the TFTs and a connection wiring 21 for connecting the external antenna (FIG. 23 (D)). The gas used for etching during contact hole formation is CHF.₃A mixed gas of and He was used, but the present invention is not limited to this. Further, the wiring 51 and the connection wiring 21 may be formed at the same time using the same material, or may be formed separately. Here, the wiring 51 connected to the TFT has a structure in which Ti, TiN, Al-Si, Ti, and TiN are sequentially laminated, formed by a sputtering method, and then patterned.

By mixing Si in the Al layer, it is possible to prevent the occurrence of hillock in the resist bake during wiring patterning. Further, instead of Si, about 0.5% Cu may be mixed. Further, by sandwiching the Al-Si layer with Ti or TiN, the hillock resistance is further improved. At the time of patterning, it is desirable to use the above hard mask made of SiON or the like. The wiring material and the forming method are not limited to these, and the material used for the gate electrode described above may be adopted.

In this embodiment, the case where only the TFT area constituting the CPU 73, the memory 74, etc. and the terminal portion 80 connected to the antenna are integrally formed is shown, but also when the TFT area and the antenna are integrally formed. The examples can be applied. In this case, it is preferable to form an antenna on the interlayer film 53 or the protective film 54 and further cover it with another protective film. As the conductive material of the antenna, Ag, Au, Al, Cu, Zn, Sn, Ni, Cr, Fe, Co or Ti, or an alloy containing them can be used, but is not limited thereto. Further, the material may be different for the wiring and the antenna. It is desirable that the wiring and the antenna are formed so as to have a metal material having high malleability and ductility, and more preferably, the film thickness is increased so as to withstand the stress due to deformation.

Further, as a forming method, after forming the entire surface by a sputtering method, patterning may be performed using a resist mask, or selectively forming using a nozzle by a droplet ejection method may be performed. The droplet ejection method referred to here includes not only an inkjet method but also an offset printing method, screen printing and the like. The wiring and the antenna may be formed at the same time, or one may be formed first and then the other may be formed so as to ride on.

Through the above steps, a thin film integrated circuit device made of TFT is completed. In this embodiment, the top gate structure is used, but a bottom gate structure (reverse stagger structure) may be used. The underlying insulating film material, the interlayer insulating film material, and the wiring material are mainly provided in the region where the thin film active element portion (active element) does not exist such as the TFT, but the region is the entire thin film integrated circuit device. It is desirable that it accounts for 50% or more, preferably 70 to 95% of the total. This makes the ID chip easier to bend and makes it easier to handle finished products such as ID labels. In this case, the island-shaped semiconductor region (island) of the active element including the TFT portion preferably occupies 1 to 30%, preferably 5 to 15% of the entire thin film integrated circuit device.

Further, as shown in FIG. 23 (D), the distance (t) from the semiconductor layer of the TFT to the protective film below in the thin film integrated circuit device._under) And the distance (t) from the semiconductor layer to the upper interlayer film (or the protective film if it is formed)._overIt is desirable to adjust the thickness of the upper and lower protective films or interlayer films so that) is equal or substantially equal. By arranging the semiconductor layer in the center of the thin film integrated circuit device in this way, the stress on the semiconductor layer can be relaxed and the occurrence of cracks can be prevented.

In this embodiment, the semiconductor device of the present invention can be used for wireless chips, IC cards, IC tags, ID chips, transponders, banknotes, securities, passports, electronic devices, bags and clothing. Here, an example of an IC card, an ID tag, an ID chip, and the like will be described with reference to FIG.

Figure 18 (A) shows an IC card, which is a credit card or electronic money that can be used to settle payments without using cash by using the fact that the built-in memory circuit is rewritable in addition to personal identification. You can also use it like this. The circuit unit 2001 using the present invention is incorporated in the IC card 2000.

FIG. 18B shows an ID tag, which can be used not only for personal identification but also for admission management at a specific place because it can be miniaturized. The circuit unit 2011 using the present invention is incorporated in the ID tag 2010.

Figure 18 (C) shows an example in which the ID chip 2022 for managing products when handling products at retail stores such as supermarkets is attached to product 2020. The present invention applies to circuits within the ID chip 2022. By using the ID chip in this way, it is possible not only to facilitate inventory management but also to prevent damage such as shoplifting. In the drawing, a protective film 2021 that also serves as an adhesive is used to prevent the ID chip 2022 from peeling off, but a structure may be adopted in which the ID chip 2022 is directly attached with an adhesive. Further, due to the structure to be attached to the product, it is preferable to manufacture using the flexible substrate described in Example 4.

FIG. 18 (D) shows an example in which an ID chip for identification is incorporated at the time of manufacturing a product. In the drawing, the ID chip 2031 is incorporated in the display housing 2030 as an example. The present invention applies to circuits within the ID chip 2031. By adopting such a structure, it is possible to easily identify the manufacturer and manage the distribution of products. Although the display housing is taken as an example in the drawings, the present invention is not limited to this, and can be applied to various electronic devices and articles.

FIG. 18 (E) is a tag for transporting goods. In the drawing, the ID chip 2041 is incorporated in the tag 2040. The present invention applies to circuits within the ID chip 2041. By adopting such a structure, it is possible to easily select the transport destination and manage the distribution of products. In the drawing, the structure is such that it is attached to a string-like object that binds the article, but the present invention is not limited to this, and it should be directly attached to the article using something like a sealing material. Structure may be taken.

Figure 18 (F) shows the ID chip 2052 incorporated in the book 2050. The present invention applies to circuits within the ID chip 2052. By adopting such a structure, distribution management in bookstores and lending processing in libraries and the like can be easily performed. In the drawing, a protective film 2051 that also serves as an adhesive is used to prevent the ID chip 2052 from peeling off, but the structure is such that the ID chip 2052 is directly attached with an adhesive, or it is embedded in the cover of the book 2050. It may have a structure.

FIG. 18 (G) shows the ID chip 2061 incorporated in the banknote 2060. The present invention applies to circuits within the ID chip 2061. By adopting such a structure, it is possible to easily prevent the circulation of counterfeit bills. Due to the nature of the banknote, it is more preferable to adopt a structure in which the ID2061 chip is embedded in the banknote 2060 in order to prevent the chip from peeling off. The present invention is applicable not only to banknotes but also to securities, passports and the like made of paper.

Figure 18 (H) shows the ID chip 2072 incorporated in the shoe 2070. The present invention applies to circuits within RFID chips 2072. By adopting such a structure, it is possible to easily identify the manufacturer and manage the distribution of products. In the drawing, a protective film 2071 that also serves as an adhesive is used to prevent the ID chip 2072 from peeling off, but a structure that directly attaches the ID chip 2072 with an adhesive or a structure that is embedded in shoes 2070 is used. You may take it. The present invention is not limited to shoes, but can be applied to things to be worn such as bags and clothing.

A case where the ID chip is mounted on various articles for the purpose of ensuring security will be described. Ensuring security can be understood from the perspective of anti-theft or anti-counterfeiting.

As an example of theft prevention, a case where an ID chip is mounted on a bag will be described. As shown in FIG. 25, the ID chip 2502 is mounted on the bag 2501. For example, the ID chip 2502 can be mounted on the bottom or a part of the side surface of the bag 2501. Since the ID chip 2502 is very thin and small, it can be mounted without deteriorating the design of the bag 2501. In addition, the ID 2502 chip is translucent, making it difficult for a thief to determine if the ID 2502 chip is mounted. Therefore, there is no risk that the ID chip 2502 will be removed by a thief.

If such an ID chip mounting bag is stolen, information on the current position of the bag can be obtained using, for example, GPS (Global Positioning System). Note that GPS is a system that captures signals sent from GPS satellites, obtains the time difference, and performs positioning based on this.

In addition to stolen items, forgotten items and lost items can be obtained using GPS to obtain information on the current location.

In addition to bags, ID chips can be mounted on vehicles such as automobiles and bicycles, watches and accessories.

Next, as an example of anti-counterfeiting, a case where an ID chip is mounted on a passport, a driver's license, or the like will be described.

Figure 26 (A) shows the passport 2601 with the ID chip mounted. In FIG. 26 (A), the ID chip 2602 is mounted on the cover of the passport 2601, but it may be mounted on other pages, and the ID chip 2602 may be mounted on the surface because it is translucent. It is also possible to mount the ID chip 2602 inside the cover by sandwiching it with a material such as the cover.

Figure 26 (B) shows the driver's license 2603 with the ID chip mounted. In FIG. 26 (B), the ID chip 2604 is mounted inside the license 2603. Further, since the ID chip 2604 is translucent, it may be provided on the printed surface of the license 2603. For example. The ID chip 2604 can be mounted on the printed surface of the license 2603 and covered with a laminate. It is also possible to mount the ID chip 2604 inside by sandwiching it with the material of the license 2603.

Forgery can be prevented by mounting the ID chip on the above-mentioned articles. It is also possible to mount an ID chip on the bag described above to prevent counterfeiting. In addition, because it uses a very thin and small ID chip, it does not impair the design of passports and driver's licenses. Furthermore, since the ID chip is translucent, it may be mounted on the surface.

In addition, the ID chip makes it easy to manage passports, driver's licenses, and the like. Furthermore, privacy can be protected because the information can be saved in the ID chip without directly entering the information in the passport or driver's license.

A case where the ID chip is mounted on a product such as food for safety management will be described with reference to FIG. 27. A label 2702 with the ID chip 2703 mounted and a meat pack 2701 with the label 2702 attached are shown. The ID chip 2703 may be mounted on the surface of the label 2702 or may be mounted inside the label 2702. In the case of fresh food such as vegetables, the ID chip may be mounted on the wrap covering the fresh food.

The ID chip 2703 can record basic items related to the product such as the place of production, producer, processing date, expiration date, and application items such as cooking examples using the product. Since such basic items do not need to be rewritten, it is preferable to record them using a non-rewritable memory such as MROM. Further, such application items may be recorded by using a rewritable or erasable memory such as EEPROM.

In addition, in order to manage food safety, it is important to know the condition of animals and plants before processing. Therefore, it is advisable to embed an ID chip in the flora and fauna and acquire information on the flora and fauna with a reader device. Information on animals and plants includes the breeding ground, feed, breeder, and the presence or absence of infectious disease infection.

Further, if the price of the product is recorded on the ID chip, it is possible to settle the product more easily and in a shorter time than the conventional method using a barcode. That is, it is possible to settle a plurality of products on which an ID chip is mounted at once. However, when reading a plurality of ID chips in this way, it is necessary to equip the reader device with an anti-collision function.

Further, depending on the communication distance of the ID chip, it is possible to settle the product even if the distance between the register and the product is long. The ID chip also helps prevent shoplifting.

Furthermore, the ID chip can also be used in combination with other information media such as barcodes and magnetic tapes. For example, it is advisable to record basic items that do not need to be rewritten on the ID chip, and record information to be updated, such as discount prices and special price information, on the barcode. This is because, unlike an ID chip, a barcode can easily correct information.

By mounting the ID chip in this way, the information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

A case where an ID chip is mounted on a product such as a beer bottle for physical distribution management will be described. As shown in FIG. 28 (A), the ID chip 2802 is mounted on the beer bottle. For example, the ID chip 2802 can be mounted using the label 2801.

The ID chip 2802 records basic items such as the date of manufacture, the place of manufacture, and the materials used. Since such basic items do not need to be rewritten, it is preferable to record them using a non-rewritable memory such as MROM. In addition, the ID chip records individual items such as the delivery destination of each beer bottle and the delivery date and time. For example, as shown in FIG. 28 (B), when each beer bottle 2803 flows by the belt conveyor 2806 and passes through the writer device 2805, each delivery destination and delivery date and time are recorded on the ID chip 2807 built in the label 2804. be able to. Such individual items may be recorded using a rewritable or erasable memory such as EEPROM.

When the product information purchased from the delivery destination is transmitted to the distribution management center via the network, the writer device or the personal computer that controls the writer device calculates the delivery destination and the delivery date and time based on this product information, and the ID It is advisable to build a system that records on a chip.

Further, since delivery is performed for each case, an ID chip can be mounted for each case or for each of a plurality of cases, and individual items can be recorded.

For beverages in which a plurality of delivery destinations can be recorded, by mounting an ID chip, it is possible to reduce the time required for manual input and reduce input errors caused by the input. In addition, the most costly labor costs in the field of logistics management can be reduced. Therefore, by mounting the ID chip, it is possible to perform low-cost physical distribution management with few mistakes.

Further, at the delivery destination, application items such as foodstuffs suitable for beer and cooking methods using beer may be recorded. As a result, it is possible to serve as a promotion for foodstuffs and the like, and it is possible to increase consumers' purchasing motivation. Such applications may be recorded using a rewritable or erasable memory such as EEROM. By mounting the ID chip in this way, the information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

In order to perform manufacturing control, a manufactured product on which an ID chip is mounted and a manufacturing device (manufacturing robot) controlled based on the information of the ID chip will be described.

Currently, there are many situations where original products are produced, and in such cases, the production line produces the products based on the original information of the products. For example, in an automobile production line in which the paint color of a door can be freely selected, an ID chip is mounted on a part of the automobile, and the coating device is controlled based on the information from the ID chip. And you can produce an original car. As a result of mounting the ID chip, it is not necessary to adjust the order and the number of vehicles having the same color to be put on the production line in advance. You don't have to set up a program to control the order and number of cars and the painting equipment to match them. That is, the manufacturing apparatus can operate individually based on the information of the ID chip mounted on the automobile.

In this way, the ID chip can be used in various places. Then, the information recorded on the ID chip can be used to obtain unique information about manufacturing, and the manufacturing apparatus can be controlled based on the information.

Next, a mode in which the IC card using the ID chip of the present invention is used as electronic money will be described. Figure 29 shows how the IC card 2901 is used for payment. The IC card 2901 has the ID chip 2902 of the present invention. When using the IC card 2901, use the register 2903 and the reader / writer 2904. The ID chip 2902 holds information on the amount of money deposited in the IC card 2901, and the reader / writer 2904 can read the information on the amount of money in a non-contact manner and send it to the register 2903. Register 2903 confirms that the amount deposited on the IC card 2901 is equal to or greater than the amount to be settled, and then setstles. Then, the information on the balance after payment is sent to the reader / writer 2904. The reader / writer 2904 can write the remaining amount information to the ID chip 2902 of the IC card 2901.

A key 2905 that allows input of a password or the like may be added to the reader / writer 2904 so that it is possible to restrict unauthorized payment by a third party using the IC card 2901. It should be noted that the examples shown in this example are only examples and are not limited to these uses.

As described above, the scope of application of the present invention is extremely wide, and it can be applied as a chip for individual recognition of any article. Further, the present embodiment can be realized by using any combination of the embodiments and the first to eighth embodiments.

<figref num="1">The block diagram which shows the structure of the semiconductor device of this invention.</figref><figref num="2">The block diagram which shows the structure of the conventional semiconductor device.</figref><figref num="3">The block diagram which shows the structure of the conventional semiconductor device.</figref><figref num="4">The figure which shows the outline of the RF tag system.</figref><figref num="5">The figure which shows the circuit structure of FeRAM of 2T2C system.</figref><figref num="6">The figure which shows the structure of FeRAM.</figref><figref num="7">The figure which shows the circuit structure of 1T1C system FeRAM.</figref><figref num="8">The figure which shows the hysteresis of a ferroelectric material.</figref><figref num="9">The block diagram of the logic circuit of this invention.</figref><figref num="10">The figure which shows the Example of the antenna of this invention.</figref><figref num="11">The figure which shows the Example of the antenna of this invention.</figref><figref num="12">The figure which shows the example of the data stored in a memory circuit.</figref><figref num="13">The block diagram of the logic circuit of this invention.</figref><figref num="14">The cross-sectional view which shows the manufacturing process of this invention.</figref><figref num="15">The cross-sectional view which shows the manufacturing process of this invention.</figref><figref num="16">The cross-sectional view which shows the manufacturing process of this invention.</figref><figref num="17">The cross-sectional view which shows the manufacturing process of this invention.</figref><figref num="18">The figure which shows the application example of this invention.</figref><figref num="19">The figure which shows the arrangement of the TFT in this invention.</figref><figref num="20">The figure which shows the example of the stabilized power supply circuit of this invention.</figref><figref num="21">The figure which combined the semiconductor device of this invention and a protective layer.</figref><figref num="22">The cross-sectional view which shows the manufacturing process of this invention.</figref><figref num="23">The cross-sectional view which shows the manufacturing process of this invention.</figref><figref num="24">The cross-sectional view which shows the manufacturing process of this invention.</figref><figref num="25">The figure which shows the bag using this invention.</figref><figref num="26">The figure which shows the certificate using this invention.</figref><figref num="27">The figure explaining the food food management using this invention.</figref><figref num="28">The figure explaining the physical distribution management using this invention.</figref><figref num="29">The figure explaining the IC card payment using this invention.</figref>

Code description

21 Connection wiring, 51 wiring, 53 thin film transistor, 54 protective film, 55 protective film, 56 gate electrode, 57 island-shaped semiconductor film, 58 gate insulating film, 60 substrate, 61 peeling layer, 62 resist, 63 resist, 64 impurity elements , 65 low-concentration impurity region, 66 resist, 67 impurity element, 68 high-concentration impurity region, 69 n-type TFT, 70 p-type TFT, 71 n-type TFT, 72 p-type TFT, 73 CPU, 74 memory, 75 insulating film, 76 sidewalls, 77 resists, 78 impurity elements, 79 high-concentration impurity regions, 80 terminals. 100 semiconductor devices, 101 antenna circuits, 102 rectifier circuits, 103 regulated power supply circuits, 104 modulation circuits, 105 amplifiers, 106 logic circuits, 107 demodulation circuits, 108 amplifiers, 109 logic circuits, 110 FeRAM control circuits, 111 FeRAM circuits. 200 semiconductor devices, 201 antenna circuits, 202 rectifier circuits, 203 regulated power supply circuits, 204 modulation circuits, 205 amplifiers, 206 logic circuits, 207 Demodulation circuit, 208 amplifier, 209 logic circuit, 210 memory control circuit, 211 memory circuit. 301 antenna, 302 tuning capacitance, 303, 304 diode, 305 smoothing capacitance. 401 ID chip, 402 antenna unit, 403 interrogator, 404 bag. 500 memory cells, 501 bit line decoder, 502 word line decoder, 503 plate line decoder, 504 precharge circuit, 505 to 512 n type memory transistor (transistor), 513 to 520 strong dielectric capacitive element, 521 to 524 bit line, 525, 526 word line, 527, 528 plate line, 529, 530 sense amplifier, 531 and 532 sense amplifier selection switch, 533 to 536 precharge switch, 537 to 540 bit line selection switch, 541, 542 input terminal, 543 output terminal .. 700 memory cells, 701 bit line decoder, 702 word line decoder, 703 plate line decoder, 704 precharge circuit, 705 ~ 708 n-type memory transistor (transistor), 709 to 712 ferroelectric capacitive element, 713, 714 bit wire, 715, 716 word wire, 717, 718 plate wire, 719, 720 sense amplifier, 721, 722 sense amplifier selection switch, 723 , 724 precharge switch, 725, 726 bit line selection switch, 727 input terminal, 728 output terminal. 901 decode circuit, 902 delay circuit, 903 switch, 904 1-bit FeRAM circuit. 1000 board, 1001 antenna, 1002 circuit, 1003 board, 1004 antenna, 1005 circuit, 1006 board, 1007 antenna, 1008 circuit, 1009 board, 1010 antenna, 1011 circuit, 1012 board, 1013 antenna, 1014 circuit, 1100 top board, 1101 Antenna wiring. 1301 decode circuit, 1302 delay circuit, 1303 switch, 1304 volatile memory circuit. 2000 IC card, 2001 circuit section, 2010 ID tag, 2011 circuit section, 2020 Commodity, 2021 Protective Film, 2022 ID Chip, 2030 Housing, 2031 ID Chip, 2040 Tag, 2041 ID Chip, 2050 Books, 2051 Protective Film, 2052 ID Chip, 2060 Bills, 2061 ID Chip, 2070 Shoes, 2071 Protective Film, 2072 ID chip. 2201 resistor, 2202 transistor, 2203 transistor, 2204 current supply resistor, 2205-2209 transistor, 2210 resistor. 2301 Flexible protective layer (protective layer), 2302 ID chip, 2303 Flexible protective layer (protective layer), 2304 antenna, 2501 bag, 2502 ID chip. 2601 passport, 2602 ID chip, 2603 driver's license, 2604 ID chip. 2701 pack, 2702 label, 2703 ID chip. 2801 label, 2802 ID chip, 2803 beer bottle, 2804 label, 2805 writer device, 2806 belt conveyor, 2807 ID chip. 2901 IC card, 2902 ID chip, 2903 Register, 2904 reader / writer, 2905 key.