Information processor and semiconductor integrated circuit

The present invention relates to an information processing apparatus having a normal mode and a power saving mode as operation modes, and a semiconductor integrated circuit used for manufacturing such an information processing apparatus.

As is well known, most of the information processing devices (computers, printers, copiers, etc.) on the market generally operate in a normal operation mode (hereinafter, normal) when nothing is done for a predetermined time or longer. It is a device that stops the operation in the mode) and starts the operation in the operation mode with less power consumption (hereinafter referred to as the power saving mode).

Many information processing devices having a power saving mode employ a method in which the clock frequency is lowered in the power saving mode (hereinafter referred to as a clock frequency changing method). A method that employs a method in which power is not supplied to such a portion (hereinafter referred to as a power supply cutoff method) is also known (see, for example, Patent Document 1).

Depending on the device configuration, this power supply cutoff method can suppress the power consumption in the power saving mode to a lower level than when the clock frequency changing method is adopted. However, if the power supply cutoff method is selected only from the viewpoint of whether or not it is necessary to operate the part (circuit / unit / device group) that does not supply power in the power saving mode, when the operation mode is changed. It is also possible to obtain an information processing device that may malfunction (mainly when shifting from the power saving mode to the normal mode).

Specifically, an information processing device schematically shown in FIG. 7 (A) by adopting a power supply cutoff method, that is, a constantly operating unit in which power is always supplied, and power is supplied in the power saving mode. When an information processing device equipped with a power saving unit that does not operate only passively is manufactured, it is possible to obtain an information processing device that functions without any problem. However, information processing is provided with an information processing device that employs a power supply cutoff method and is schematically shown in FIG. 7 (B), that is, a power saving unit that may interrupt the constantly operating unit. When the device is manufactured, noise may appear in the interrupt signal output by the power saving unit when the second power supply is turned on / off. Therefore, the operating unit always malfunctions when the operation mode is changed. A certain information processing device will be obtained.

Therefore, when manufacturing an information processing device by adopting the power supply cutoff method, it is possible to reduce the power consumption in the power saving mode by adopting the configuration shown in FIG. 7 (B). There was no choice but to adopt the configuration of A).<patcit num="1"><text>JP 2000-326590</text></patcit>

<p> Therefore, an object of the present invention is to provide a configuration that does not cause a malfunction even if the power saving unit interrupts the constantly operating unit in order to reduce the power consumption in the power saving mode. It is to provide the information processing apparatus which has.</p><p> Another object of the present invention is to provide a semiconductor integrated circuit that can be used in the manufacture of the above-mentioned information processing apparatus.</p>

<p> In order to solve the above problems, in the present invention, an information processing device having a normal mode and a power saving mode as operation modes is supplied with power from a power supply unit capable of ON / OFF control and a power supply unit. The power saving unit and the constantly operating unit that supplies power regardless of the operating mode, and when it detects the occurrence of an event that should shift to the power saving mode while operating in the normal mode, it saves power. After performing processing to fix the levels of some signals supplied to itself in order to indicate the execution timing of processing, the power supply unit is turned off, and then the power saving mode When the occurrence of an event that should shift to the normal mode is detected while operating in the power saving mode, some signal lines are processed after the power supply unit is turned on. It is configured as a device including a constantly operating unit that starts operation in the normal mode after performing a process of releasing the fixing of the level of.</p><p> The information processing device of the present invention having such a configuration functions as an information processing device that does not malfunction even if the power saving unit may interrupt the constantly operating unit. .. If there are no restrictions on the configuration of the power saving unit (if the circuits / units / devices that are the components of the power saving unit can be selected only from the viewpoint of whether or not it is necessary to operate in the power saving mode), the power saving is saved. Since the power consumption in the power mode can be easily reduced, according to the present invention, it is possible to realize an information processing device having a lower power consumption in the power saving mode than the existing information processing device.</p><p> When the information processing apparatus of the present invention is realized as having a power supply unit whose output is not stable after being turned on, the constantly operating unit is supplied with power in order to start operation in the normal mode. After performing the process of turning on the unit, it is possible to wait for the elapse of a predetermined time, and then perform the process of releasing the fixing of the levels of some signal lines.</p><p> The information processing apparatus of the present invention may be realized in such a form that a part of the power saving unit and a part of the constantly operating unit are formed on one chip.</p><p> The semiconductor integrated circuit of the present invention is a power saving unit in which power is supplied from a power supply unit capable of ON / OFF control, and a constant operation unit in which power is supplied regardless of the operation mode, and is a normal mode. When it detects the occurrence of an event that should shift to the power saving mode while operating in the power saving mode, some signals supplied from the power saving unit to itself in order to start the operation in the power saving mode. When the power supply unit is turned off after the process for fixing the level of is detected and the occurrence of an event that should shift to the normal mode is detected while operating in the power saving mode, it is normal. In order to start the operation in the mode, it is provided with a constantly operating unit that performs a process of turning on the power supply unit and then a process of releasing the fixing of the levels of some signal lines. Therefore, if this semiconductor integrated circuit is used, an information processing device equivalent to the information processing device of the present invention (the information processing device according to claim 3) can be easily manufactured.</p><p> Further, the information processing apparatus of another aspect of the present invention is a constantly operating unit in which power is supplied regardless of the operating mode, and a power saving unit including a CPU, and the electric power is generated when the operating mode is the normal mode. A power saving unit to be supplied and a power supply unit capable of ON / OFF control for supplying power to the power saving unit are provided, and the CPU of the power saving unit starts operation in the power saving mode. It is programmed to issue a sleep request with a predetermined content to the constantly operating unit when it detects the occurrence of a power event, and when a sleep request is issued as the constantly operating unit, the power saving unit It is a unit that turns off the power supply unit after performing processing to fix the levels of some signals supplied to itself in order to indicate the execution timing of the processing, and also the power supply unit. After turning it off, it monitors the occurrence of an event that should start operation in normal mode, and when it detects the occurrence of that event, it turns on the power supply unit and then turns on some signal line levels. It has a configuration in which a unit that performs a process of releasing the fixing of the electric power is used.</p><p> The information processing device of the present invention having this configuration also functions as a device that does not malfunction even if the power saving unit may interrupt the constantly operating unit. Further, since this information processing device is a device in which power is not supplied to the CPU in the power saving mode, the information processing device of this aspect of the present invention is more than a type of information processing device in which power is supplied to the CPU. It can be said that the device consumes less power in the power saving mode.</p><p> In order to realize the information processing device of this aspect, the power saving unit is set as a unit including the non-volatile memory, and the CPU of the power saving unit is generated as an event that should start the operation in the power saving mode. When it is detected, the sleep state information indicating that the sleep request has been issued is stored in the non-volatile memory before the sleep request is issued, and the sleep state information is stored in the non-volatile memory at the start of the operation. If the sleep state information is not stored in the non-volatile memory, the original operation is started after the type 1 initialization process is performed, and the non-volatile memory is in the sleep state. When the information is stored, the process of erasing the sleep state information from the non-volatile memory and the type 2 initialization process (for example, related to the power saving unit) which is simpler than the type 1 initialization process. It can be programmed to start the original operation after performing (processing that only initializes).</p>

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

&lt;&lt; First Embodiment &gt;&gt; First, the configuration of the information processing apparatus 10 according to the first embodiment of the present invention will be described with reference to FIG.

As shown in the figure, the information processing device 10 according to the first embodiment of the present invention is a device (so-called printer) that operates by receiving a print request (print data in the image data format in the present embodiment) from a host. Is. Further, the information processing apparatus 10 includes a printer engine 11, a printer control ASIC 12, ROM 13, RAM 14, an operation panel 15, a host I / F unit 16, RAM 17, a first power supply 18, and a second power supply 19 as main components. It is a device.

The printer engine 11 included in the information processing device 10 is a unit that actually prints on paper. The operation panel 15 is a unit including an LCD, an LED, a push button switch, etc., which is provided in the housing of the information processing device 10 as an interface means with the user. The host I / F unit 16 is a unit (so-called communication interface boat) that receives a print request from the host.

The ROM 13 is a read-only memory in which a program (firmware) that defines the operating procedure of the printer control ASIC 12 (CPU 21 in the printer) is recorded. RAM14 is a memory in which the program recorded in ROM13 is loaded. This RAM 14 is also used as a work area for the printer control ASIC 12.

RAM17 is a memory used for temporary storage of print requests sent from the host. The first power supply 18 supplies power to a part of the printer control ASIC 12 (the part of the printer control ASIC 12 excluding the DMA control unit 31 and the image processing unit 32), the ROM 13, the RAM 14, the operation panel 15, and the host I / F unit 16. It is a power source for supplying. The second power supply 19 is a power supply for supplying power to the other parts (DMA control unit 31 and image processing unit 32) of the printer control ASIC 12 and the RAM 17. In this embodiment, the portion to which power is supplied by the second power supply 19 (or the portion of the printer control ASIC 12 included in the portion) corresponds to the power saving unit, and the first power supply 18 described above corresponds to the power saving unit. The part to which power is supplied (or the part of the printer control ASIC 12 included in the part) corresponds to the constantly operating part.

The printer control ASIC12 (corresponding to the semiconductor integrated circuit of the present invention) includes a CPU 21, a panel control unit 22, an I / F control unit 23, an engine control unit 24, a power supply control unit 25, an interrupt signal gate 26, and a data request signal. It is an ASIC (Application Specific Integrated Circuit) consisting of a gate 27, a DMA control unit 31, an image processing unit 32, and the like. As is clear from the above description of the first power supply 18 and the second power supply 19, the printer control ASIC 12 is an ASIC provided with two so-called power supply terminals.

The CPU 21 included in the printer control ASIC 12 is a unit (circuit module) that integrally controls each part in the information processing apparatus 10. An interrupt signal (details will be described later) is supplied to this CPU 21 from the interrupt signal gate 26, and the process of causing the CPU 21 to execute the program recorded in the ROM 13 described above is supplied to the CPU 21. It includes processing that is executed when the level of the interrupt signal changes.

The panel control unit 22 is a unit capable of controlling the content instructed by the CPU 21 to the operation panel 15 and notifying the CPU 21 of the operation content performed on the operation panel 15. The engine control unit 24 is a unit capable of starting / stopping the printer engine 11 and grasping the operating state of the printer engine 11.

The I / F control unit 23 is a unit that supplies the print request received by the host I / F unit 16 to the DMA control unit 31. The I / F control unit 23 includes a buffer for storing data (a part of a print request) received by the host I / F unit 16, and a predetermined amount (predetermined size) of data in the buffer. Is a unit that outputs data to the DMA control unit 31 when the level of the data request signal (details will be described later) input from the data request signal gate 27 changes.

The image processing unit 32 performs image processing on the image data (print request for one page temporarily stored in RAM 17) supplied from the DMA control unit 31, and prints the image data after the image processing. It is a unit that supplies the engine 11.

The DMA control unit 31 receives the print request transmitted by the host via the host I / F unit 16 and the I / F control unit 23 and stores it in the RAM 17, and the print request stored in the RAM 17 is stored on one page. It is a unit that performs processing to supply to the image processing unit 32 minute by minute. The DMA control unit 31 is a signal (hereinafter, referred to as an original interrupt signal) supplied to the interrupt signal gate 26 when the storage of one page's print request on the RAM 17 is completed. It is a unit that changes the level. Further, when the DMA control unit 31 is ready to receive a predetermined amount of print request (data of a predetermined size constituting the print request), the DMA control unit 31 supplies a signal (hereinafter, original) to the data request signal gate 27. It is also a unit that changes the level of the data request signal).

The interrupt signal gate 26 has a constant level regardless of the normal state in which the original interrupt signal from the DMA control unit 31 is supplied to the CPU 21 as it is and the level of the original interrupt signal from the DMA control unit 31. It is a unit that can operate in a power-saving state that supplies an interrupt signal (CPU21 recognizes that no interrupt has been made; GND level in this embodiment) to the CPU21. The data request signal gate 27 is in a normal state in which the original data request signal from the DMA control unit 31 is supplied to the I / F control unit 23 as a data request signal as it is, and at a constant level (the I / F control unit 23 is of data). A level that recognizes that no output is required; in this embodiment, it is a unit that can operate in a power saving state that supplies a data request signal (GND level) to the I / F control unit 23.

The power supply control unit 25 is a unit capable of operating the interrupt signal gate 26 and the data request signal gate 27 in an arbitrary state (either a normal state or a power saving state). The power supply control unit 25 is also a unit capable of performing ON / OFF control of the second power supply 19.

Next, the operation of the information processing device 10 according to the present embodiment will be described.

When the power of the information processing apparatus 10 is turned on, the printer control ASIC 12 performs a process of loading the program on the ROM 13 onto the RAM 14, and then performs the process of the procedure shown in FIG. 2 according to the program loaded on the RAM 14. Start.

That is, the printer control ASIC 12 first performs an initialization process (step S101) for operating the information processing device 10 and its own ASIC in the normal mode. Specifically, in this step S101, the printer control ASIC 12 waits for the elapse of the specified time given as the time required for the second power supply 19 to stabilize after the second power supply 19 is turned on. Then, when the specified time elapses, the printer control ASIC 12 performs a process for operating both the interrupt signal gate 26 and the data request signal gate 27 in the own ASIC in a normal state.

After completing the initialization process as described above, the printer control ASIC 12 starts the operation in the normal mode (execution of the processing loop in steps S102 and S103), and "print request starts to be received by the host I / F unit 16." , "The operation panel 15 is operated", and "A predetermined time elapses without receiving a print request by the host I / F unit 16" (step S102). It becomes a state.

Then, the printer control ASIC 12 generates an event different from the event that "a predetermined time elapses without receiving the print request by the host I / F unit 16" (hereinafter, referred to as a power saving mode transition required event). When is detected (step S102; other), in step S103, after executing the process according to the content of the event that has occurred, the occurrence of various events is being monitored again. The process performed by the printer control ASIC 12 in step S103 is for controlling the operation panel 15 and for causing the printer engine 11 to print a printed matter having contents corresponding to the print request received by the host I / F unit 16. It is a process.

On the other hand, when the occurrence of the power saving mode transition required event is detected (step S102; power saving mode transition required event), the printer control ASIC 12 has both the interrupt signal gate 26 and the data request signal gate 27 in the own ASIC. Is operated in a power-saving state (step S104). Then, the printer control ASIC 12 performs the process for turning off the second power supply 19 (step S105), and then starts the operation in the power saving mode (execution of the process loop of steps S106 and S107).

The printer control ASIC 12 that has started operation in the power saving mode monitors the occurrence of two types of events such as "print request starts to be received by host I / F unit 16" and "operation panel 15 is operated" (step). S106) It will be in the state of being.

Then, when the operation panel 15 is operated (step S106; other), the printer control ASIC 12 executes a process according to the content of the event that occurred (operation content for the operation panel 15) in step S107. , Again, it returns to the state of monitoring the occurrence of the above two types of events.

On the other hand, when the occurrence of a normal mode transition required event (an event such as a print request being received by the host I / F unit 16 or the operation panel 15 being operated) is detected (step S106; normal mode transition required event), the printer The control ASIC 12 waits for the specified time (the time given as the time until the second power supply 19 stabilizes) elapses after performing the process for turning on the second power supply 19 (step S108). (Step S109). Then, the printer control ASIC 12 performs a process of operating both the interrupt signal gate 26 and the data request signal gate 27 in the normal state (step S110), and then operates in the normal mode (processes of steps S102 and S103). (Running the loop) is started.

As described above, in the information processing apparatus 10 of the first embodiment, when the mode shifts from the normal mode to the power saving mode, the CPU 21, I / F control unit 23 receives a predetermined level interrupt signal and data request signal. Is configured as a device in which the second power supply 19 is turned off after the power is supplied. Further, in the information processing device 10, when the power saving mode is changed to the normal mode, the second power supply 19 is turned on, and after the output is stabilized, the CPU 21 and the I / F control unit 23 are connected to the DMA control unit, respectively. It is also a device in which the interrupt signal (original interrupt signal) and data request signal (original data request signal) from 31 are supplied.

Therefore, in this information processing device 10, as a result of ON / OFF control of the second power supply 19, an interrupt signal (original interrupt signal) and a data request signal (original data request signal) output by the DMA control unit 31 are performed. ), The CPU 21 and the I / F control unit 23 will not operate abnormally. Further, when the configuration of the information processing device 10 is adopted, is it necessary to operate the circuit / unit / device group which is a component of the part to which the power is supplied by the second power supply 19 in the power saving mode? It will be possible to select only from the viewpoint of whether or not. Therefore, if the configuration of the information processing device 10 is adopted, it is possible to manufacture an information processing device having lower power consumption in the power saving mode than the existing information processing device because such selection is possible.

&lt;&lt; Second Embodiment &gt;&gt; As shown in FIG. 3, the information processing apparatus 50 according to the second embodiment of the present invention includes a first power supply 51, a constantly operating unit 52, a second power supply 61, a power saving unit 62, and a printer. It is a device (so-called printer) equipped with an engine.

The first power source 51 constituting the information processing device 50 is a power source that is always functioning when the power switch of the information processing device 50 is turned on. The constant operation unit 52 is a unit that operates by receiving power supplied from the first power supply 51. The constant operation unit 52 includes a power supply control unit 53, a panel control unit 54, an I / F control unit 55, a data request signal gate 56, an OR gate 57, an operation panel, a host I / F unit, and the like.

The second power supply 61 is a power supply whose ON / OFF control is performed by the second power supply control signal from the power supply control unit 53. The power saving unit 62 is a unit that operates by receiving power supplied from the second power source 61. The power saving unit 62 includes a CPU 63, an EEPROM 64, a DMA control unit 65, ROM, RAM, an image processing unit, and the like.

Each component of the information processing device 50 (constant operation unit 52, power saving unit 62) basically has the same function as the component of the same name in the information processing device 10. Therefore, in the following, only the main components of the information processing apparatus 10 will be described.

The DMA control unit 65, which constitutes the power saving unit 62, is ready to receive a predetermined amount of print requests (data of a predetermined size that constitutes the print request), similarly to the DMA control unit 31 (see FIG. 1). In this case, it is a unit that changes the level of the original data request signal supplied to the data request signal gate 56. The EEPROM 64 is a rewritable non-volatile memory provided in the information processing device 50 in order to store various information (information about operating conditions of the information processing device 50, etc.). A storage area for a sleep flag (details will be described later) is secured in this EEPROM 64.

The CPU 63 is a unit (IC) that integrally controls each part in the information processing device 50. When the CPU 63 recognizes that the operation mode of the information processing device 50 should be the power saving mode, the level of the sleep request signal supplied to the power supply control unit 53 is temporarily set to a high level. , Programmed (details below).

The data request signal gate 56 constituting the constantly operating unit 52 is in a state of supplying the original data request signal from the DMA control unit 65 as a data request signal to the I / F control unit 55 as it is, and at a constant level (I /). It is a unit that can operate in a state where the F control unit 55 recognizes that data output is not required; in this embodiment, the data request signal (GND level in this embodiment) is supplied to the I / F control unit 55. .. The data request signal gate 56 operates in the former state when a high-level gate control signal is supplied from the power supply control unit 53, and a low-level gate control signal is supplied from the power supply control unit 53. Under these circumstances, it is configured to operate in the latter state.

The I / F control unit 55 and the panel control unit 54 are units having basically the same functions as the I / F control unit 23 and the panel control unit 22, respectively. However, the I / F control unit 55 has a function to temporarily raise the level of the signal supplied to the OR gate 57 when it detects that a print request has been received by the host I / F unit. Has been granted. Further, the panel control unit 54 is provided with a function of temporarily setting the level of the signal supplied to the OR gate 57 to a high level when it is detected that an operation on the operation panel has been performed.

The power supply control unit 53 receives the reset signal (not shown), the return request signal which is the output of the OR gate 57, and the sleep request signal from the CPU 63, and receives the second power supply control signal and the gate control signal. It is a unit to output. The reset signal is a signal that becomes a high level when the power is turned on to the information processing apparatus 50 and temporarily becomes a low level when a reset is instructed by the user.

As shown in FIG. 4, the power supply control unit 53 includes an OR gate 71, an RS latch 72, a first delay circuit 73 (shift register in the present embodiment), a second delay circuit 74, (in the present embodiment , the shift register) . It is a unit that combines shift register), OR gate 75, and gate 76, and RS latch 77.

That is, as shown in FIG. 5, the power supply control unit 53 changes the level of the gate control signal to a low level when the sleep request signal changes to a high level, and then changes the Ts time (first delay circuit). It is a unit that changes the level of the second power supply control signal to a low level when the delay time (73) elapses. Further, when the return request signal changes to a high level, the power supply control unit 53 changes the level of the second power supply control signal to a high level, and then the Tw time (delay time by the second delay circuit 73) is increased. It is also a unit that changes the level of the gate control signal to a high level when it elapses.

Then, the CPU 63 in the power saving unit 62 is programmed to process the procedure shown in FIG. 6 when the power starts to be supplied to itself (when the second power supply is turned on).

That is, the CPU 63 from which the power supply has been started first performs a process (step S101) of reading the sleep flag on the EEPROM 64. Then, the CPU 63 determines whether the read at sleep flag is ON (actually 1) or OFF (actually 0) (step S102), and if the sleep flag is not ON. In (step S102; NO), a normal initialization process (step S105) is performed. Here, the normal initialization process is a process of initializing all the parts in the information processing apparatus 50.

On the other hand, when the sleep flag is ON (step S102; YES), the CPU 63 has a process of rewriting the sleep flag on the EEPROM 64 to OFF (step S103) and a process of initializing only the power saving unit (step S104). I do.

The CPU 63 that has completed the processing of steps S104 or S105 has an event that "a predetermined time elapses without receiving a print request or operating the operation panel" (hereinafter, a power saving mode transition required event). While monitoring the occurrence of various events including (notation), the state is such that the contents are processed according to the generated event (the processing loop of steps S106 and S107 is being executed).

Then, when the CPU 63 detects the occurrence of the power saving mode transition required event (step S106; power saving transition required event), the CPU 63 issues a sleep request after rewriting the sleep flag on the EEPROM 64 to ON (sleep request). The process (step S108) of temporarily setting the signal level to a high level is performed. As described above, when the sleep request signal changes to a high level, the power supply control unit 53 (see FIGS. 3 and 4) changes the level of the gate control signal to a low level, and then Ts time later. , It is a unit that changes the level of the second power supply control signal to a low level. Therefore, when the process of step S108 is performed, the data request signal gate 56 to which the gate control signal is supplied recognizes that a constant level (I / F control unit 55 is not required to output data). The second power supply 61 is turned off after Ts time after starting the operation in the state of supplying the data request signal of (level) to the I / F control unit 55.

As described above, the information processing apparatus 50 of the second embodiment is in a state where a predetermined level data request signal is supplied to the I / F control unit 55 at the time of transition from the normal mode to the power saving mode. After that, the second power supply 61 is turned off. Further, in the information processing device 50, when the power saving mode is changed to the normal mode, the second power supply 61 is turned on, and after the output is stabilized, the data from the DMA control unit 65 is sent to the I / F control unit 55. It is also a device in which a request signal (original data request signal) is supplied.

Therefore, in this information processing apparatus 50, even when noise appears in the data request signal (original data request signal) output by the DMA control unit 65 as a result of ON / OFF control of the second power supply 61, The I / F control unit 55 will not operate abnormally. Further, since the information processing device 50 is a device in which the CPU 63 is included in the power saving unit 62, the power consumption in the power saving mode is higher than that of the information processing device 10 in which the CPU 21 is included in the normal operation unit. It will operate as a small number of devices.

<figref num="1">The block diagram of the information processing apparatus which concerns on 1st Embodiment of this invention.</figref><figref num="2">The flow chart which showed the operation procedure of the information processing apparatus which concerns on 1st Embodiment.</figref><figref num="3">The block diagram of the information processing apparatus which concerns on 2nd Embodiment of this invention.</figref><figref num="4">The block diagram of the power supply control part provided in the information processing apparatus which concerns on 2nd Embodiment.</figref><figref num="5">The explanatory view of the operation of the power supply control part provided in the information processing apparatus which concerns on 2nd Embodiment.</figref><figref num="6">The flow chart which showed the operation procedure of the CPU in the information processing apparatus which concerns on 2nd Embodiment.</figref><figref num="7">Explanatory drawing of the problem of the information processing apparatus which adopted the conventional power supply cutoff system.</figref>

Code description

10,50 Information processing device 11 Printer engine, 12 Printer control ASIC 13 ROM, 14,17 RAM, 15 Operation panel, 16 Host I / F section 18,51 1st power supply, 19, 61 2nd power supply, 21, 63 CPU 22,54 Panel control unit 23,55 I / F control unit, 24 Engine control unit, 25,53 Power supply control unit 26,56 Interrupt signal gate, 27 Data request signal gate 31,65 DMA control unit, 32 Image Processing unit, 57 OR gate