Memory controller, flash memory system, and control method for flash memory

The present invention relates to a memory controller, a flash memory system including the memory controller, and a method for controlling the flash memory.

In recent years, flash memory has been widely adopted as a semiconductor memory used in a memory system such as a memory card or a silicon disk. Flash memory is a type of non-volatile memory. The data stored in the flash memory is required to be retained even when power is not supplied.

NAND flash memory is a type of flash memory that is particularly often used in the above memory systems. Each of the plurality of memory cells included in the NAND flash memory sets the logical value "0" from the erased state in which the data indicating the logical value "1" is stored independently of the other memory cells. It is possible to change to the writing state in which the indicated data is stored. In contrast, each memory cell cannot change independently of the other memory cells when changing from the write state to the erase state. At this time, a predetermined number of memory cells called blocks are all erased at the same time.

This batch erase operation is generally referred to as "block erase". The write process or read process for the NAND flash memory is performed in units of a predetermined number of memory cells called pages. A block, which is a unit of erasing processing, is composed of a plurality of pages.

NAND flash memory applies a high voltage to memory cells to inject and eject electrons when changing each memory cell from the erased state to the write state or from the write state to the erased state. I'm doing it. If the injection or ejection of electrons is not performed normally, or if the memory cells deteriorate, each memory cell may not change normally from the erased state to the written state, or from the written state to the erased state. is there. In order to detect and correct such a defect, an error collection code is written on each page in addition to the user data supplied from the host system side. Here, additional data (error collection code, etc.) other than user data is written to the memory cells allocated to the redundant area in the page.

For example, in Patent Document 1 below, an area of 512 bytes from the beginning of each page is allocated to a user area for writing user data and the like, and a subsequent area is allocated to a redundant area for writing additional data such as an error collection code. There is.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2001-297038</text></patcit>

<p> As described above, conventionally, a certain area from the top of the page is allocated to the user area for writing user data and the like, and the subsequent area is allocated to the redundant area for writing additional data such as an error collection code. The user data written in the flash memory is usually held in a buffer provided outside the flash memory and then transferred to the flash memory. The capacity of this buffer is usually set to the same capacity as the user area in each page.</p><p> However, in order to make the capacity of the buffer provided outside the flash memory the same as the user area in each page, the capacity of the buffer must be changed according to the capacity of the page of the flash memory. On the other hand, if the capacity of the buffer provided outside the flash memory is not the same as the capacity of the pages of the flash memory, the transfer from the buffer to the flash memory is divided into multiple times when writing the data for one page. In some cases, it must be done. When the user data for one page is transferred in multiple times, the additional data (error collection code, etc.) to be written in the redundant area is also transferred in multiple times. Since the transfer of user data and the transfer of additional data (error collection code, etc.) are performed alternately, the settings such as the address must be changed frequently, and the processing efficiency is not good.</p><p> Therefore, the present invention is a memory controller and a flash memory system with improved processing efficiency when the transfer of user data and the transfer of additional data must be performed in a plurality of times when writing data for one page. , Also, it is an object of the present invention to provide a control method of a flash memory.</p>

<p> In order to achieve the above object, the memory controller according to the first aspect of the present invention has a first data holding function for holding user data supplied from the host system side and additional data corresponding to the user data. A second data holding function to be held, a data transfer function to transfer the user data held in the first data holding function and the additional data held in the second data holding function to the flash memory, and a data transfer function. The user data and the additional data corresponding to the user data are written in a plurality of sets on the page in the flash memory, and the user data and the additional data corresponding to the user data are continuously positioned. It is characterized by being configured to write in.</p><p> The capacity of the page may be an integral multiple of the capacity of the first data holding function and the capacity of the second data holding function combined.</p><p> Further, the capacity of the page may be 2112 bytes, the capacity of the first data holding function may be 512 bytes, and the capacity of the second data holding function may be 16 bytes.</p><p> In order to achieve the above object, the flash memory system according to the second aspect of the present invention is characterized by including any of the above-mentioned memory controllers according to the first aspect of the present invention and a flash memory.</p><p> In order to achieve the above object, the flash memory control method according to the third aspect of the present invention transfers the user data supplied from the host system side held in the first data holding function to the flash memory. By alternately repeating the process and the process of transferring the additional data corresponding to the user data held in the second data holding function to the flash memory a plurality of times, the user data and the user data are displayed on the page in the flash memory. It is characterized in that a plurality of sets of the additional data corresponding to the user data are written, and the user data and the additional data corresponding to the user data are continuously written.</p><p> The capacity of the page may be an integral multiple of the capacity of the first data holding function and the capacity of the second data holding function combined.</p><p> Further, the capacity of the page may be 2112 bytes, the capacity of the first data holding function may be 512 bytes, and the capacity of the second data holding function may be 16 bytes.</p>

<p> According to the present invention, when the user data and the additional data are transferred in a plurality of times, when the transfer data changes from the user data to the additional data, or when the additional data changes to the user data, the writing destination Processing can continue without changing the address. Therefore, the processing efficiency of the writing process can be improved.</p>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of Flash Memory System 1]

FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention.

As shown in FIG. 1, the flash memory system 1 is composed of a flash memory 2 and a memory controller (hereinafter, simply referred to as a controller) 3 that controls the flash memory 2. The flash memory system 1 is usually attached to and detachably attached to the host system 4 and used, and is used as a kind of external storage device for the host system 4. Examples of the host system 4 include various information processing devices such as a personal computer and a digital still camera that process various information such as character, voice, and image information.

The flash memory 2 is a device that reads or writes in page units and erases in block units. For example, one block consists of 32 pages, and one page consists of a 512-byte user area and a 16-byte redundant area.

Controller 3 includes host interface control block 5, microprocessor 6, host interface block 7, work area 8, buffer 9, flash memory interface block 10, ECC (error collection code) block 11, and It is composed of a flash memory sequencer block 12.

The controller 3 composed of these functional blocks is integrated on one semiconductor chip. The function of each block will be described below. The microprocessor 6 is a functional block that controls the operation of each functional block that constitutes the controller 3.

The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13, and in such a state, the host system 4 connects to the flash memory system 1. The supplied data and the like are taken into the controller 3 with the host interface block 7 as an inlet. The data and the like supplied from the flash memory system 1 to the host system 4 are supplied to the host system 4 with the host interface block 7 as an exit.

Further, the host interface block 7 has a task file register (not shown) that temporarily stores the host address and external commands supplied by the host system 4, and an error register (not shown) that is set when an error occurs. ) Etc.

The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block composed of a plurality of SRAM (Static Random Access Memory) cells.

The buffer 9 is a functional block that temporarily holds the data read from the flash memory 2 and the data written to the flash memory 2. That is, the data read from the flash memory 2 is held in the buffer 9 until the host system 4 is ready to receive the data. The data to be written to the flash memory 2 is held in the buffer 9 until the flash memory 2 is ready to be written.

The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on an internal command. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When the information required for executing the internal command is set in the plurality of registers, the flash memory sequencer block 12 executes the process based on the information. Here, the "internal command" is a command given from the controller 3 to the flash memory 2, and is distinguished from the "external command" of the command given from the host system 4 to the flash memory system 1.

The flash memory interface block 10 is a functional block that exchanges data, address information, status information, internal command information, device ID information, and the like with the flash memory 2 via the internal bus 14.

The ECC block 11 generates an error collection code added to the data written to the flash memory 2, and detects and corrects an error contained in the read data based on the error collection code added to the read data. It is a functional block to be used.

[Explanation of flash memory 2]

The flash memory 2 in FIG. 1 is a NAND type memory. NAND flash memory is a non-volatile memory developed for use in storage devices (as an alternative to hard disks). This NAND flash memory cannot perform random access, and writes and reads are performed in page units, and erasure is performed in block units. Since the data cannot be overwritten, when writing the data, the data is written to the erased area.

Since the flash memory 2 has such a feature, normally, when rewriting data, new data (data after rewriting) is written to the erased block that has been erased, and old data (data after rewriting) is written. The process of erasing the block in which the data before rewriting) was written is performed. When such data is rewritten, the data after rewriting is written in a block different from that before rewriting, so the logical block address based on the address given from the host system 4 side and the flash memory 2 The correspondence with the physical block address, which is the block address of, changes dynamically every time the data is rewritten. The correspondence between the logical block address and the physical block address is usually managed by an address translation table showing the correspondence, and the address translation table is created based on the corresponding logical block address described later.

Here, the relationship between the block and the page will be described. FIGS. 2 (a) and 2 (b) are explanatory diagrams showing the relationship between blocks and pages. The structure of blocks and pages differs depending on the specifications of the flash memory 2, but in a general flash memory, one block is composed of 32 pages (P0 to P31) as shown in FIG. 2 (a). Each page consists of a 512-byte user area and a 16-byte redundant area. As the storage capacity increases, as shown in Fig. 2 (b), one block consists of 64 pages (P0 to P63), and each page consists of a user area of 2048 bytes and a redundant area of 64 bytes. What has been done is also provided.

The user area is mainly an area where data supplied from the host system 4 is stored, and the redundant area is an area where additional data such as an error collection code, a corresponding logical block address, and a block status are stored. is there.

The error collection code is additional data for detecting and correcting an error contained in the data stored in the user area, and is generated by an external ECC block. The corresponding logical block address indicates which logical block address the block corresponds to when data is stored in the block.

If no data is stored in that block, the corresponding logical block address is also not stored, so whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. You can also judge. That is, if the corresponding logical block address is not stored, it is determined that the block has been erased.

The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be written normally), and if it is determined that the block is a bad block, it is bad. A flag indicating that it is a block is set.

Next, the circuit configuration of the flash memory 2 will be described. Similar to a general NAND flash memory, the flash memory 2 is composed of a register for holding memory write data or read data and a memory cell array for storing the data. The memory cell array includes a plurality of memory cell groups in which a plurality of memory cells are connected in series, and a specific memory cell of the memory cell group is selected by a word line. Data is copied (register-to-memory cell copy or memory cell-to-register copy) between the memory cell and the register selected by this word line.

The memory cells that make up the memory cell array are made up of MOS transistors that have two gates. Here, the upper gate is called a control gate, and the lower gate is called a floating gate, and data is written by injecting an electric charge (electron) into the floating gate or discharging an electric charge (electron) from the floating gate. Or the data is being erased. Since this floating gate is surrounded by an insulator, the injected electrons are retained for a long period of time.

When injecting electrons into the floating gate, a high voltage is applied to the control gate on the high potential side to inject electrons, and when discharging electrons from the floating gate, the control gate is on the low potential side. A voltage is applied to emit electrons. Here, the state in which electrons are injected into the floating gate (writing state) corresponds to the data of the logical value "0", and the state in which electrons are discharged from the floating gate (erasing state) is the logical value. Corresponds to the data of "1".

[Description of operation]

Next, the process in which the user data supplied from the host system is written to the flash memory 2 will be described with reference to FIG. FIG. 3 is an explanatory diagram of the operation of the flash memory system.

The buffer 21 and the additional data register 22 of FIG. 3 are configured in the controller 3 of FIG. 1, the buffer 21 holds the user data supplied from the host system 4, and the additional data register 22 has an error. Additional data such as collection code is set.

On the other hand, the register 24 and the memory cell array 25 are configured in the flash memory 2, the register 24 holds the data supplied from the controller 3 or the data output from the memory cell array 25, and the memory cell array 25 is from the controller 3. Store the supplied data. Here, the capacity of the register 24 is the same as the capacity of the page of the flash memory 2.

When writing the user data supplied from the host system 4 to the flash memory 2, the user data supplied from the host system 4 is held in the buffer 21, and an error created for the user data held in the buffer 21 is created. The collection code and other additional data are set in the additional data register 22. The user data held in the buffer 21 and the additional data set in the additional data register 22 are transferred to the flash memory 2 and held in the register 24 in the flash memory 2. The user data and additional data held in the register 24 are copied (stored) to the page specified by the controller 3.

In the conventional flash memory, as shown in FIG. 4, a user area is allocated to the area at the top of the page, and a redundant area is allocated to the area at the end of the page. FIGS. 4 (a) and 4 (b) are schematic views showing a conventional writing situation. In the example shown in FIG. 4A, 512 bytes at the beginning are allocated to the user area, and 16 bytes at the end are allocated to the redundant area. In the example shown in Fig. 4 (b), the first 2048 bytes are allocated to the user area and the last 64 bytes are allocated to the redundant area. In this way, the user area was allocated to the top side of the page, and the redundant area was allocated to the end side of the page.

In the writing process to the flash memory 2, the data held in the register in the flash memory 2 is copied to the page in the flash memory 2, so that the user data and the additional data are stored in the register in the flash memory 2. When transferring data, the data must be transferred according to the allocation of the user area and the redundant area in the page. That is, if the user area is allocated to the first area in the page and the redundant area is allocated to the last area in the page, the user data (written to the user area) is assigned to the first area in the register. Data must be transferred so that additional data (data written in the redundant area) is retained in the trailing area.

Next, refer to the drawing for the processing when writing data to a page with a user area of 2048 bytes (Fig. 4 (b)) using a 512-byte buffer and a 16-byte additional data register in the controller. I will explain. FIG. 5 is a diagram showing data held in a register in the flash memory 2 in the conventional writing process. FIG. 6 shows the data held in the register in the flash memory 2 in the writing process according to the present invention.

In the writing process, the data held in the register in the flash memory is copied to the write destination page as described above, so that the array of user data and additional data held in the register and the writing are performed. The array of user data and additional data of the data copied on the previous page is the same. Therefore, in the register in the flash memory, the area where the user data is held corresponds to the user area in the page, and the area where the additional data is held corresponds to the redundant area in the page. Therefore, in the following description, the array of user data and additional data held in the register in the flash memory will be mainly described.

In the conventional writing process shown in FIG. 5, user data and additional data are transferred to the flash memory in the following order. User data is transferred in step 0, additional data is transferred in step 1, user data is transferred in step 2, additional data is transferred in step 3, user data is transferred in step 4, and additional data is transferred in step 5. Is transferred, user data is transferred in step 6, and additional data is transferred in step 7.

Here, the additional data transferred in step 1 corresponds to the user data transferred in step 0, the additional data transferred in step 3 corresponds to the user data transferred in step 2, and is transferred in step 5. The additional data corresponds to the user data transferred in step 4, and the additional data transferred in step 7 corresponds to the user data transferred in step 6. Further, the user data transferred in step 0, step 2, step 4 and step 6 is held in this order from the area on the head side of the register, and is transferred in steps 1, step 3, step 5 and step 7. The data is held in this order after the user data.

In the writing process according to the present invention shown in FIG. 6A, user data and additional data are transferred to the flash memory in the following order, and are held in registers in the flash memory in the transferred order. Will be done. User data is transferred in step A0, additional data is transferred in step A1, user data is transferred in step A2, additional data is transferred in step A3, user data is transferred in step A4, and additional data is transferred in step A5. Is transferred, user data is transferred in step A6, and additional data is transferred in step A7. Here, the additional data transferred in step A1 corresponds to the user data transferred in step A0, the additional data transferred in step A3 corresponds to the user data transferred in step A2, and is transferred in step A5. The additional data corresponds to the user data transferred in step A4, and the additional data transferred in step A7 corresponds to the user data transferred in step A6.

That is, in the writing process according to the present invention, 512 bytes of user data and 16 bytes of additional data corresponding thereto are held in a continuous area in the register. Further, the user data and the additional data are alternately arranged in the area in the register. Correspondingly, the area in the page where the data held in the register is copied is also allocated alternately with the 512-byte user area and the 16-byte redundant area.

In the example shown in Fig. 6 (a), write processing was performed using a 512-byte buffer and a 16-byte additional data register, but in the example shown in Fig. 6 (b), a 1024-byte buffer was used. Writing processing is performed using a 32-byte additional data register. Even when the write process is performed using the 1024-byte buffer and the 32-byte additional data register, the user data and the corresponding additional data are held in a continuous area in the register. Further, the user data and the additional data are alternately arranged in the area in the register. However, since the write process is performed using the 1024-byte buffer and the 32-byte additional data register, the 1024-byte user area and the 32-byte redundant area are alternately allocated to the area on the page.

Next, refer to the drawings for the signal supplied to the flash memory by the conventional writing process shown in FIG. 5 and the signal supplied to the flash memory by the writing process according to the present invention shown in FIG. 6 (a). I will explain. FIG. 7 is a waveform diagram of a signal supplied to the flash memory 2 in the conventional write process, and FIG. 8 is a waveform diagram of the signal supplied to the flash memory 2 in the write process according to the present invention shown in FIG. 6 (a). It is a waveform diagram of the signal. In the waveform diagram shown in FIG. 7, S11 is a data signal output to a data bus that supplies commands, addresses, data (user data, additional data, etc.) and the like. S12 is a command latch enable signal that becomes a high level when the signal output to the data bus is a signal indicating a command. S13 is an address latch enable signal that becomes a high level when the signal output to the data bus is a signal indicating an address. S14 is a write enable signal that changes from a low level to a high level when commands, addresses, and data are output to the data bus. Control signals other than the command latch enable signal, the address latch enable signal, and the write enable signal are not shown. Further, in the following description, a signal indicating a command output to the data bus is referred to as a command signal, a signal indicating an address is referred to as an address signal, a signal indicating user data is referred to as a user data signal, and a signal indicating additional data. Is called an additional data signal.

In the waveform diagram in the conventional writing process shown in FIG. 7, first, the command signal C corresponding to the writing command is output to the data bus, and then the address signal A0 corresponding to step 0 and the user data signal D0 ~ The command C "corresponding to D511 and the address change command is sequentially output, and then the address signal A1 and the additional data signals D0'to D15' corresponding to step 1 are sequentially output. Similarly, step 2 and step 4 are similarly output. And the address signal corresponding to step 6, the user data signal, and the command C "corresponding to the address change command are sequentially output, and then the address signal and additional data signals corresponding to steps 3, 5, and 7 are sequentially output. To. In the above processing, the data held in the register in the flash memory is copied from the register to the write destination page by the command signal C'corresponding to the data copy. The signal output to the data bus is captured in the flash memory at the rising edge of the write enable signal (S14), and the signal captured when the command latch enable signal (S12) is at a high level is determined to be a command signal. The signal captured when the address latch enable signal (S13) is at a high level is determined to be an address signal.

In the waveform diagram in the conventional writing process shown in FIG. 7, the command C corresponding to the address change command and the address signal are output at the beginning of each step. This means that the addresses are discontinuous at the transition of each step. Therefore, the write destination address is specified. Since the specified address is counted up at the rising edge of the write enable signal, the write destination address is not specified in the address signal. In this case, the data corresponding to the user data signal or the additional data signal is sequentially fetched to consecutive addresses.

In the waveform diagram shown in FIG. 8, S21 is a data signal output to a data bus that supplies commands, addresses, data (user data, additional data, etc.) and the like. S22 is a command latch enable signal that becomes a high level when the signal output to the data bus is a signal indicating a command. , S23 are address latch enable signals that become high level when the signal output to the data bus is a signal indicating an address. The S24 is a write enable signal that changes from a low level to a high level when commands, addresses, and data are output to the data bus.

In the waveform diagram of the writing process according to the present invention shown in FIG. 8, first, the command signal C corresponding to the writing command is output to the data bus, and then the address signal A0 and the user data signal corresponding to step A0 are output. D0 to D511 are sequentially output, and further, additional data signals D0'to D15' corresponding to step A1 are sequentially output. Similarly, the user data signals corresponding to steps A2, A4 and A6 and the additional data signals corresponding to steps A3, A5 and A7 are in the order of step A2, step A3, ..., Step A7. Is output. In the above processing, the data held in the register in the flash memory is copied from the register to the write destination page by the command signal C'corresponding to the data copy.

The signal output to the data bus is captured in the flash memory at the rising edge of the write enable signal (S24), and the signal captured when the command latch enable signal (S22) is at a high level is determined to be a command signal. The signal captured when the address latch enable signal (S23) is at a high level is determined to be an address signal.

In the waveform diagram of the writing process according to the present invention shown in FIG. 8, the address signal is output at the beginning of step 0, and the command signal and the address signal corresponding to the address change command are output in steps 1 to 7 after that. Not done. This is because the data corresponding to the user data signal or the additional data signal output in steps 0 to 7 is sequentially fetched to the continuous addresses.

As described above, in the flash memory system 1 of the present embodiment, when the user data and the additional data are transferred, the transfer data is written when the transfer data changes from the user data to the additional data or when the additional data changes to the user data. There is no need to change the destination address. Therefore, the processing efficiency of the writing process can be improved.

<figref num="1">It is a block diagram which shows schematicly about the flash memory system 1 which concerns on this invention.</figref><figref num="2">An explanatory diagram showing the relationship between blocks and pages.</figref><figref num="3">It is explanatory drawing of the operation of a flash memory system.</figref><figref num="4">It is a schematic diagram which shows the conventional writing situation.</figref><figref num="5">It is a figure which shows the data held in the register in the flash memory by the conventional writing process.</figref><figref num="6">It shows the data held in the register in the flash memory by the writing process which concerns on this invention.</figref><figref num="7">It is a waveform diagram of the signal supplied to the flash memory by the conventional writing process.</figref><figref num="8">It is a waveform diagram of the signal supplied to the flash memory by the writing process shown in FIG. 6A.</figref>

Code description

1 Flash memory system 2 Flash memory 3 Memory controller 4 Host system