Manufacturing method of transistor for semiconductor element

The present invention relates to a method for manufacturing a transistor for a semiconductor device, more specifically, a trench type gate can be formed, the source / drain resistance and the gate resistance can be lowered without an additional step, and the single channel effect can be efficiently adjusted. The present invention relates to a method for manufacturing a transistor for a semiconductor element.

With the development of miniaturization technology accompanying the high integration of semiconductor elements, the line width of transistors is currently being miniaturized year by year . As a result, a hot carrier phenomenon occurs in the transistor. In this phenomenon, when the channel length is shorter than the external applied voltage, the horizontal electric field is largely concentrated on the drain region side, deteriorating the electrical characteristics of the drain region, and each hole generated at this time is directed toward the substrate. It is a phenomenon that comes out. The electrons are trapped in the lower part of the gate oxide film and the lower part of the spacer, and affect the threshold voltage.

That is, such a hot carrier phenomenon often occurs when a high electric field is applied to a channel of a semiconductor substrate, although the channel region is shortened due to miniaturization of the device, but the supply power supply voltage is unchanged and constant. In particular, the shorter the length of the channel, which is the movement passage of the carrier between the source region and the drain region, the more prominently it occurs. In order to overcome such hot carrier effect, most transistor manufacturing processes employ an LDD (Lightly Doped Drain) structure. This is a two-layered junction in which the gate electrode is placed in between and the ion implantation concentration in the source / drain region in the substrate is low near the edge of the gate electrode and high in the center. This is to reduce abrupt changes in the electric field by forming the above.

However, with the progress of high integration of semiconductor elements, the length of the channel is continuously shortened, so that the transistor having the LDD structure described above also causes the short channel phenomenon. Then, the dopant in the LDD region spreads to the channel, a high electric field is applied between the drains at the channel edge, and a hot-carrier phenomenon occurs, which deteriorates the performance of the transistor. In addition, when the transistor operates, impurities in the source and drain spread to the side surface, and it is easy to induce a punch-through effect, and it is troublesome to increase the number of ion implantation steps to prevent this. In addition, if the channel length and its concentration are not accurately adjusted, there is a difficult problem in adjusting the threshold voltage.

In order to solve such a problem, the lower surface of the transistor gate electrode is embedded inside the substrate between the spacers on the upper part of the substrate, and the side surface and the lower surface of the gate electrode have a gate oxide film formed into a concave platform. Patent documents describe a transistor having a trench-type gate electrode structure capable of increasing the length of an effective channel and improving the electrical characteristics of a highly integrated semiconductor device due to the structure. However, such a technique also has a structure in which the gate is partially filled and the gate is pierced higher than that of a silicon substrate, so that there is a problem in miniaturizing the element.

Patent Document 2 and Patent Document 3 describe a technique for forming a uniform oxide film on the surface of a trench by rounding a trench corner portion at the time of forming a trench in order to form a trench gate. However, this technique requires a separate masking process when forming the source / drain, which causes a problem that the manufacturing process becomes complicated.

Metal oxide semiconductor field effect transistor using a trench gate (MOSFET: The Metal Oxide Semiconductor Field Effect Transistor) has a low turn-on resistance. In such trench MOSFET elements, the channels are arranged vertically rather than horizontally, as in most planar configurations. FIG. 1 shows a partial cross-sectional view of a conventional trench gate MOSFET element (2). The MOSFET element includes a trench (4) filled with a conductive material (6) separated from the silicon region (8) by a thin layer of insulating material (10). Body area (body) The region) (12) extends from the epitaxial layer (18), and the source region (14) extends in order from the body region (12). The conductive material (6) and the insulating material (10) in the trench (4) form a gate and a gate oxide layer of the trench DMOS, respectively. In addition, the depth (L) measured from the source (14) to the epitaxial layer (18) constitutes the channel length (L) of the trench DMOS device. The epitaxial layer (18) is part of the drain (20) of the trench DMOS device. When a potential difference is applied between the body (12) and both ends of the gate, it is guided from within the body region (12) adjacent to the gate oxide layer (10) towards the capacitance, which leads to the channel (21) of the trench DMOS device. Will form.

Transistors with this structure are called double-diffusing metal oxide semiconductor field-effect transistors, or "trench DMOSs," due to two diffusion steps that spread over the body region and the epitaxial layer. Such trench DMOS transistors are described in Patent Documents 4 to 7. However, these techniques have a problem that the source and drain regions are separated, there is a limit to the miniaturization of the device, and the manufacturing process is complicated.<patcit num="1"><text>Republic of Korea Published Patent No. 2001-64434</text></patcit><patcit num="2"><text>U.S. Pat. No. 6,511,886</text></patcit><patcit num="3"><text>Republic of Korea Published Patent No. 10-0218260 Gazette</text></patcit><patcit num="4"><text>U.S. Pat. No. 5,907,776</text></patcit><patcit num="5"><text>U.S. Pat. No. 5,072,266</text></patcit><patcit num="6"><text>U.S. Pat. No. 5,541,425</text></patcit><patcit num="7"><text>U.S. Pat. No. 5,866,931</text></patcit>

<p> The present invention has been made to solve the above-mentioned problems of the prior art, and can reduce the source / drain resistance and the gate resistance without an additional step by forming a trench type gate, and has a short channel. It is an object of the present invention to provide a method for manufacturing a transistor of a semiconductor element capable of efficiently adjusting the effect.</p>

<p> In order to achieve the above object, the method for manufacturing a transistor for a semiconductor device according to the present invention includes a step of forming an LDD ion implantation region by ion implantation after depositing a first insulating film on a semiconductor substrate, and the first step. 1 After patterning the insulating film, the substrate is carved to form a trench, and the substrate on which the trench is formed is implanted with the second insulating film and a conductor and then flattened to form a trench gate. And the step of forming a source / drain region by implanting a photoresist on the substrate on which the trench gate is formed and patterning, and then ion-implanting the photoresist as a mask, and removing the photoresist. However, it is characterized by including a step of removing the first insulating film.</p><p> The object of the present invention is a step of injecting ions into a substrate to form an LDD region, a step of forming a first insulating film on the substrate, a step of patterning the first insulating film, and then carving the substrate. The stage of forming a trench, the stage of forming a trench gate by flattening the second insulating film and the conductor after depositing the entire surface on the substrate on which the trench is formed, and the stage of carving the first insulating film and spacers. It is also achieved by a method for manufacturing a transistor of a semiconductor device, which includes a step of forming a source / drain region and a step of forming a source / drain region by injecting ions into the substrate using the spacer and the gate as an ion injection mask.</p><p> The object of the present invention is a step of forming an LDD region by an ion injection step after depositing a first insulating film on a silicon substrate, and after patterning the first insulating film, the substrate is carved to form a trench. A step of forming a trench gate by depositing a second insulating film and a first conductor on the substrate on which the trench is formed and then flattening the substrate to form a trench gate, and a step of forming the trench gate on the substrate on which the trench gate is formed. Includes a step of depositing a second conductor and patterning the second conductor and the first insulating film, and a step of injecting ions using the second conductor as a mask to form a source / drain region. It is also achieved by a method for manufacturing a conductor of a semiconductor element, which is characterized by the above.</p>

<p> In the transistor manufacturing method of a semiconductor device of the present invention, a trench type gate can be formed to reduce the source / drain resistance and the gate resistance without an additional step, and the short channel effect can be efficiently adjusted.</p>

[Example 1]

First, an embodiment of the present invention will be described through the method for manufacturing the transistor shown in FIGS. 2a to 2g. First, FIG. 2a is a drawing in which the LDD ion implantation region (111) is formed by ion implantation (103) after the first insulating film (102) is vapor-deposited on the silicon substrate (101). It is desirable that the first insulating film (102) acts as a buffer film at the time of ion implantation and is formed by utilizing a nitride, a thallium-based oxide, a titanium-based oxide, or a hafnium-based oxide. The ion implantation energy for forming the LDD ion implantation region (111) is preferably 30 to 80 keV. The first insulating film (102) is preferably formed to a thickness of 500 to 1500 Å.

Next, as shown in FIG. 2b, the first photoresist (104) is vapor-deposited on the upper part of the first insulating film (102) and patterned. A first photoresist (104) is formed on top of the first insulating film (102) to pattern the area where the gate is formed during the phenomenon and exposure process. Next, as shown in FIG. 2c, the substrate is etched to form a trench (105). Using the patterned first photoresist (104) as a mask, the first insulating film (102) and the silicon substrate are etched to form a trench (105) in which a gate is formed, and then the first photoresist (104) is formed. ) Is removed. Dry etching is used for etching, and inclined etching with an angle of 5 to 30 ° is used for dry etching. In addition, as shown in Fig. 2d, a layer that uses Chemical Dry Etch (CDE) as the etching method to form a round lower corner of the trench (205) and will be vapor-deposited in the future. Uniformity can be increased. Trench (105, 205) should be etched to a depth of 100-1000 Å.

Next, as shown in FIG. 2e, the second insulating film (106) and the conductor (107) are vapor-deposited and then flattened to form a trench gate. An oxide film is formed as a second insulating film on the trench-formed substrate, and then a gate conductor is formed. Next, the conductor and the second insulating film are flattened using CMP (Chemical Mechanical Polishing) to form a trench gate. During the CMP process, the first insulating film is used as an etching-prepared stratum, and if the first insulating film appears, the CMP process is stopped. It is desirable to use a tungsten-based, titanium-based, or thallium-based metal compound as the conductor. The second insulating film can form a silicon discrete cargo layer by using a conventional thermal oxidation method or a conventional chemical vapor deposition method, and a multilayer oxide material can also be used. Further, the same gate insulating film as that of silicon nitride can also be used. The second insulating film is preferably deposited to a thickness of 15 to 80 Å.

Next, as shown in FIG. 2f, after forming and patterning the second photoresist (108), ion implantation (109) was performed using the second photoresist (108) as a mask, and the source / drain region (112) was used. To form. A second photoresist is deposited and patterned on the upper part of the substrate on which the trench gate is formed. Subsequently, the ion implantation process is carried out using the patterned second photoresist as a mask to form a source / drain region. The energy of ion implantation to form the source / drain region is 5 to 60 keV, and the first insulating film (102) is used as a buffer film to protect the substrate during ion implantation.

Next, as shown in FIG. 2g, the second photoresist (108) is removed and the first insulating film (102) is removed. After forming the source / drain region using the second photoresist as a mask, the second photoresist is removed. Subsequently, the first insulating film is removed by using wet etching. For wet etching, it is desirable to use a phosphoric acid solution for etching. The LDD region (111) and source / drain region (112) are formed above the gate, but at the same time the LDD region (111) and source / drain region (112) are stabilized by the subsequent heat treatment step. The length of the channel can be adjusted by diffusing the LDD region (111) and the source / drain region (112).

[Example 2]

Other embodiments of the present invention will be described through the method for manufacturing the transistors shown in FIGS. 3a to 3g. First, FIG. 3a is a diagram in which an LDD ion implantation region (311) is formed on a silicon substrate (301) by ion implantation (302). In the existing transistor in which the gate is formed on the upper part of the silicon substrate, after the gate is formed, the low-concentration impurity ion implantation step proceeds with this gate as a mask to form the LDD ion implantation region. The low-concentration impurity ion implantation step is carried out to form an LDD ion implantation region. The ion implantation energy for forming the LDD ion implantation region is preferably 10 to 80 keV.

Next, as shown in FIG. 3b, a first insulating film (303) is formed on the upper portion of the silicon substrate, and a photoresist (304) is vapor-deposited on the upper portion of the first insulating film (303) for patterning. A first insulating film is vapor-deposited on the upper part of the substrate on which the LDD ion implantation region is formed, a photoresist is formed on the upper part of the first insulating film, and the region where the gate is formed is patterned by the development and exposure steps. The first insulating film (303) is preferably a nitride film or an oxide film.

Next, as shown in FIG. 3c, the first insulating film and the substrate are etched to form a trench (305). The photoresist on which the patterning is formed is used as a mask, and the first insulating film and the silicon substrate are etched to form a trench in which a gate is formed, and then the photoresist is removed. This etching uses dry etching to form a trench, and as shown in Fig. 3d, after proceeding with dry etching using inclined etching, the photoresist pattern is removed and CF₄/0₂, Or CHF₃/0₂Chemical Dry Etch (CDE) can be used to form the lower corners of the trench in a round shape (405) to improve the uniformity of layers to be deposited in the future.

Next, as shown in FIG. 3e, the second insulating film (306) and the conductor (307) are vapor-deposited and then flattened to form a trench gate. A second insulating film is formed with a gate insulating film on the substrate on which the trench is formed, and a gate conductor is formed on the upper part of the second insulating film. Subsequently, the conductor and the second insulating film are flattened using CMP (Chemical Mechanical Polishing). During this CMP process, if the first insulating film is used as an etching surface layer and the first insulating film appears, the CMP process is stopped. It is desirable to use polysilicon or a tungsten-based, titanium-based, or thallium-based metal compound as the conductor (307). The second insulating film (306) is preferably a thallium-based oxide, a titanium-based oxide, or a hafnium-based oxide.

Next, as shown in FIG. 3f, the first insulating film is etched to form a spacer (308), and ion implantation (309) is performed using the gate and spacer (308) as masks to form a source / drain region (312). Form. After the gate is formed, the gate insulating film, that is, the first insulating film existing on both sides of the second insulating film is etched by anisotropic etching, leaving so that it exists only on the side wall of the second insulating film, and the rest is removed. To form a spacer.

Subsequently, the high-concentration impurity ion implantation step is carried out using the gate and the spacer as masks to form the source / drain region (312). The energy of ion implantation to form this source / drain region is preferably 10 to 100 keV. When the gate is severely damaged due to etching during spacer formation, the first insulating film can be completely etched and removed, and a spacer-forming insulating film can be formed and etched to form a spacer. The spacer-forming insulating film is preferably an oxide film or a nitride film.

Next, as shown in FIG. 3g, a heat treatment step is carried out to stabilize the LDD region (311) and the source / drain region (312). Although the LDD region (311) is formed above the gate, the LDD region (311) and the source / drain region (312) are stabilized by the subsequent heat treatment step, and at the same time, the LDD region (311) and the source / drain region (311) and the source / drain region are stabilized. The region (312) can be diffused to adjust the length of the channel.

[Example 3]

Yet another embodiment of the present invention will be described through the method for manufacturing the transistor shown in FIGS. 4a to 4g. First, FIG. 4a is a diagram in which the LDD region (511) is formed by ion implantation (503) after the first insulating film (502) is vapor-deposited on the silicon substrate (501). The first insulating film (502) acts as a buffer film during ion implantation, and it is desirable to deposit a nitride film with a thickness of 500 to 1500 Å. The ion implantation energy for forming the LDD region is preferably 5 to 60 keV.

Next, as shown in FIG. 4b, the first photoresist (504) is vapor-deposited on the upper part of the first insulating film and patterned. A first photoresist is formed on the upper part of the first insulating film, and a region where a gate is formed by a developing and exposure process is patterned. Next, as shown in FIG. 4c, the substrate is etched to form a trench (505). The first photoresist on which the pattern is formed is used as a mask, and the first insulating film and the silicon substrate are etched to form a trench in which a gate is formed, and then the first photoresist is removed. The trench should be formed at a depth of 100-1000 Å. In addition, dry etching is used for etching, and as shown in Fig. 4d, after inclined etching with an angle of 5 to 30 °, chemical dry etching (CDE) is used to remove the lower corner of the trench. It can be formed into a round shape (605) to improve the uniformity of layers to be deposited in the future.

Next, as shown in FIG. 4e, the second insulating film (506) and the first conductor (507) are vapor-deposited and then flattened. An oxide film is formed with a second insulating film on the substrate on which the trench is formed, and a conductor for a gate is formed. Subsequently, the first conductor and the second insulating film are flattened using CMP (Chemical Mechanical Polishing). During this CMP process, the first insulating film is used as an etching surface layer, and when the first insulating film appears, the CMP process is stopped. It is desirable to use polysilicon as the first conductor. The second insulating film can form a silicon discrete cargo layer by using a conventional thermal oxidation method or a conventional chemical vapor deposition method, and a multilayer oxide material can also be used. The second insulating film is preferably formed with a thickness of 15 to 80 Å.

Next, as shown in FIG. 4f, the second conductor (508) and the second photoresist (509) are sequentially formed to pattern the second photoresist (509). A second conductor is vapor-deposited on the substrate after the flattening step, and a second photoresist is formed on the upper part of the second conductor. The second conductor is preferably a tungsten-based, titanium-based, or thallium-based metal compound. The second photoresist is then patterned in a photo-etching step.

Next, as shown in FIG. 4g, the second conductor and the first insulating film are etched using the patterned second photoresist as a mask. Subsequently, the second photoresist is removed and ion-implanted (510) to form a source / drain region (512). More specifically, a second photoresist patterned on the upper part of the second conductor is formed as an etching mask, and the second conductor and the first insulating film are etched to remove the second photoresist. Subsequently, the ion implantation step is carried out to form a source / drain region. The energy of ion implantation to form the source / drain region is preferably 30-80 keV. Further, it is also possible to form an oxide film on the substrate to protect the substrate during ion implantation, protect the substrate as a buffer film during ion implantation, and then remove the oxide film after the ion implantation step. The etched first insulating film plays the same role as a spacer, and forms a metallic substance as a second conductor on the top of polysilicon, which is the first conductor, and reduces the resistance to the contacts formed in a later process. be able to.

After that, the heat treatment step is advanced to stabilize the LDD region (511) and the source / drain region (512). Subsequent heat treatment steps can stabilize the LDD region and source / drain region while at the same time diffusing the LDD region and source / drain region to adjust the channel length. As described above, in the transistor element formed by the trench, the length of the effective channel is longer than that of the transistor formed on the substrate, so that the short channel effect can be reduced.

From the above description, it is clear that changes and modifications, including features of the present invention, are clearly facilitated by ordinary people skilled in the art. The scope of such modifications of the invention is within the scope of those skilled in the art, including the features of the invention, and such modifications are within the scope of the claims of the invention. It is considered to be.

<figref num="1">Figure 1 is a partial cross-sectional view of a trench gate MOSFET element using conventional technology.</figref><figref num="2">2a to 2g are cross-sectional views by process showing a method for manufacturing a transistor according to an embodiment of the present invention.</figref><figref num="3">3a to 3g are cross-sectional views by process showing a method for manufacturing a transistor according to another embodiment of the present invention.</figref>

Code description

101 Silicon substrate 102 1st insulating film 103 Ion implantation 104 1st photoresist 105 Trench 106 2nd insulating film 107 Conductor 108 2nd photoresist 111 LDD region 112 Source / drain region