Threshold control device and its operation method

【0001】

[Technical field to which the invention belongs]

The present invention relates to a threshold control device and an operation method thereof in an insulated gate field effect transistor (MISFET) constituting a semiconductor integrated circuit.

【0002】

[Conventional technology]

As shown in FIG. 11, the conventional MISFET threshold control device is formed in, for example, N well 702 formed on the P conductive type semiconductor substrate 701, P well 703 formed in the N well 702, and P well 703 formed in the N well 702. It is composed of N-channel (ch) type MOS transistors formed in the P-type diffusion layer 704 for P-well and P-well 703. Here, the Nch type MOS transistor is composed of a source N type diffusion layer 705, a drain N type diffusion layer 706, a gate insulating film 707 sandwiched between them, and a gate electrode 708 formed in the P well 703. Has been done. Then, a P-well voltage Vsubn is applied to the P-type diffusion layer 704 for P-wells to control the threshold value of the Nch-type MOS transistor. Similarly, the N-well voltage Vsubp is applied to the N-well diffusion layer 709 formed in the N-well 702 to control the threshold value of the Pch-type MOS transistor formed in the N-well 702. Here, the Pch type MOS transistor is composed of a source P type diffusion layer 710, a drain P diffusion layer 711, a gate insulating film 712 sandwiched between them, and a gate electrode 713 formed in the N well 702. ing. The source voltage Vsn (Vsp) is applied to the source N-type diffusion layer 705 (source P-type diffusion layer 710), and the drain voltage Vdn (Vdp) is applied to the drain N-type diffusion layer 706 (drain P-type diffusion layer 711). , And a gate voltage Vgn (Vgp) is applied to the gate electrode 708 (713), respectively.

【0003】

In the case of an Nch type MOS transistor, the operation of this threshold control device is that when the gate voltage Vgn of the gate electrode 708 is active, the P well voltage Vsubn is increased to increase the source N type diffusion layer. Lower the threshold between the 705 and the P-well 703 to speed up the switching operation. Then, in the non-conducting state, that is, when the gate voltage Vgn of the gate electrode 708 is inactive, the threshold value between the source N-type diffusion layer 705 and the P-well 703 is set by lowering the P-well voltage Vsubn. Raise it to suppress the leakage current during standby of the semiconductor integrated circuit.

【0004】

On the other hand, in the case of a Pch type MOS transistor, when the gate electrode 713 is in the active state, that is, when the gate voltage Vgp of the gate electrode 713 is in the active state, the N well voltage Vsubp is lowered to form the source P type diffusion layer 710 and the N well 702. By lowering the threshold between, speeding up the switching operation, and increasing the N-well voltage Vsubp in the non-conducting state, that is, when the gate voltage Vgp of the gate electrode 713 is inactive, the P-type diffusion layer 710 for the source Raise the threshold between N-well 702 and suppress leakage during standby.

【0005】

Although we investigated this technology, we could only confirm the existence of documents such as a method of increasing the withstand voltage of the oxide film in order to prevent deterioration due to electric field concentration (see, for example, Patent Document 1).

【0006】

[Patent Document 1]

Japanese Unexamined Patent Publication No. 2-14529 [0007]

[Problems to be Solved by the Invention]

However, in the conventional MISFET threshold control device, in the case of the Nch type MOS transistor, first, the P well voltage Vsubn applied to the P type diffusion layer 704 for the P well is lowered to reduce the P well voltage Vsubn between the gate electrode 708 and the P well 703. The potential difference between the two is widened, and the withstand voltage of the gate insulating film 707 is likely to deteriorate. Secondly, since the P-well voltage Vsubn and the source voltage Vsn are supplied from different power sources, if a surge invades only one of them, the potential difference between the P-well 703 and the source N-type diffusion layer 705 will increase. The parasitic NPN bipolar transistor having the N-well 702 as the collector region, the P-well 703 as the base region, and the source N-type diffusion layer 705 as the emitter region becomes easier to operate, and the so-called latch-up withstand voltage decreases. Thirdly, the electrode connected to the P-type diffusion layer 704 for the P-well and the electrode connected to the N-type diffusion layer 705 for the source cannot be shared, and independent electrode wiring is required for each, which increases the area of the semiconductor chip. There was a problem.

【0008】

Similarly, in the case of a Pch type MOS transistor, first, by increasing the N well voltage Vsubp applied to the N type diffusion layer 709 for N well, the potential difference between the gate electrode 713 and the N well 702 is widened, and the gate insulating film 712. Insulation withstand voltage is likely to deteriorate. Secondly, since the N-well voltage Vsubp and the source voltage Vsp are supplied from different power sources, if a surge invades only one of them, the potential difference between the N-well 702 and the P-type diffusion layer 710 for the source increases. The parasitic PNP bipolar transistor having the P-well 703 as the collector region, the N-well 702 as the base region, and the source P-type diffusion layer 710 as the emitter region becomes easier to operate, and the so-called latch-up withstand voltage decreases. Thirdly, the electrode connected to the N-type diffusion layer 702 for N-well and the electrode connected to the P-type diffusion layer 710 for source cannot be shared, and independent electrode wiring is required for each, which increases the area of the semiconductor chip. There was a problem.

【0009】

The present invention has been made in view of the above circumstances, and prevents deterioration of the insulation withstand voltage of the gate insulating film in speeding up and reducing leakage by threshold control of the MISFET used in a semiconductor integrated circuit, and from a surge during operation. It is an object of the present invention to provide a threshold control device capable of preventing a decrease in latch-up resistance that occurs and further enabling a high density of semiconductor integrated circuits.

【0010】

[Means for solving problems]

The threshold control device of the present invention is a threshold control device that adjusts the threshold value of a MISFET on a semiconductor substrate, wherein the source electrode of the MISFET and the semiconductor substrate on which the MISFET is formed have the same potential, and the semiconductor substrate is formed. It has a configuration provided with carrier injection / suction means that reduces the threshold value of the MISFET to the conductive state by injection of carriers into the semiconductor substrate or suction of the carrier from the semiconductor substrate and increases the threshold value to the non-conducting state of the MISFET. .. Here, the MISFET may be provided in the well layer formed on the semiconductor substrate.

【0011】

With this configuration, the source voltage of the MISFET and the voltage of the semiconductor substrate or the source voltage and the well voltage are made the same for operation. Therefore, unlike the conventional threshold control device described above, the potential difference between the gate electrode and the semiconductor substrate or the well layer is large. However, deterioration of the insulation withstand voltage of the gate insulating film is prevented. In addition, the parasitic bipolar operation as described in the conventional technique does not occur, and the latch-up withstand voltage is greatly improved. In addition, it enables high-speed switching characteristics of MISFET and reduction of leakage current when the MISFET is in a non-conducting state. Further, the semiconductor substrate or the well layer and the source diffusion layer of the MISFET can be connected and connected to the common wiring. Therefore, the common wiring makes it easy to increase the density of the semiconductor integrated circuit.

【0012】

Then, the carrier injection / suction means includes a structure of a carrier conductive layer / carrier insulating layer laminated on the surface of the semiconductor substrate or the surface of the well layer, or the carrier injection / suction means is the well layer. It comprises a laminated structure of a carrier conductive layer / carrier insulating layer provided at least a part of the bottom portion or at least a part of a side portion of the carrier. Here, the structure is such that the semiconductor substrate, the insulating separation layer, the carrier conductive layer, the carrier insulating layer, and the well layer are laminated in this order.

【0013】

In this threshold control device, the carrier conductive layer functions as a carrier supply source to the semiconductor substrate or the well layer, and the carrier insulating layer functions as a carrier barrier between the well layer and the carrier conductive layer. In such a configuration, it is not necessary to specially apply the voltage Vsubn (p) to the semiconductor substrate or the well layer as in the conventional technique, and as described above, the source voltage of the MISFET and the voltage of the semiconductor substrate or the source voltage The well voltage can be the same.

【0014】

Then, in the threshold control device of the present invention, the impurity concentration of the semiconductor substrate becomes high in the interface region with the carrier insulating layer, or the impurity concentration of the well layer becomes high in the interface region with the carrier insulating layer. There is.

【0015】

With this configuration, when a voltage for carrier injection / suction is applied to the carrier conductive layer, the formation of a depletion layer in the interface region with the semiconductor substrate or the well layer is suppressed, and a high electric field is generated in the carrier insulating layer. Therefore, carrier injection / suction can be performed efficiently.

【0016】

Further, in the threshold control device of the present invention, the MISFET is an N-channel type MISFET, and the carrier conductive layer is P.⁺The carrier insulating layer comprises silicon nitride or silicon oxynitride. Alternatively, the MISFET is a P-channel type MISFET, and the carrier conductive layer is N.⁺It comprises type polycrystalline silicon, and the carrier insulating layer comprises silicon oxide.

【0017】

Such a structure of the carrier conductive layer makes carrier injection / suction more efficient. Further, with the above-mentioned configuration of the carrier insulating layer, fatigue / deterioration of the carrier insulating layer, which tends to occur at the time of injection / suction of the carrier, can be suppressed to a small extent.

【0018】

In the operation method of the threshold control device of the present invention, when the N-channel type MISFET is in a conductive state, a voltage higher than that of the semiconductor substrate or the well layer is applied to the carrier conductive layer, and the carrier conductivity is passed through the carrier insulating layer. Holes are injected from the layer into the semiconductor substrate or the well layer, and when the N-channel type MISFET is in a non-conducting state, a voltage lower than that of the semiconductor substrate or the well layer is applied to the carrier conductive layer to insulate the carrier. Through the layer, holes are attracted from the semiconductor substrate or the well layer to the carrier conductive layer.

【0019】

Further, in the operation method of the threshold control device of the present invention, when the P-channel type MISFET is in a conductive state, a voltage lower than that of the semiconductor substrate or the well layer is applied to the carrier conductive layer, and the carrier insulating layer is passed through the carrier insulating layer. Electrons are injected from the carrier conductive layer into the semiconductor substrate or the well layer, and when the P-channel type MISFET is in a non-conducting state, a voltage higher than that of the semiconductor substrate or the well layer is applied to the carrier conductive layer to apply the carrier. Electrons are attracted from the semiconductor substrate or the well layer to the carrier conductive layer through the insulating layer.

【0020】

This operation method enables high-speed switching characteristics of MISFET, reduction of leakage current during standby of semiconductor integrated circuits, improvement of insulation resistance by preventing deterioration of insulation withstand voltage of gate insulating film, and surge latch of CMOS circuit. It facilitates improvement of up resistance and higher density of semiconductor integrated circuits.

【0021】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the threshold control device according to the embodiment of the present invention and its operation method will be described with reference to the drawings. A cross-sectional view of the threshold control device according to the first embodiment of the present invention is shown in FIG. This is a threshold control device in the case of an Nch type MOS transistor. In FIG. 1, the threshold control device is formed between the carrier adjusting conductive layer 103, which is a carrier conductive layer provided between the semiconductor substrate 101 and the P well 102, the carrier adjusting conductive layer 103, and the P well 102. The carrier adjusting insulating layer 104, which is a carrier insulating layer, provided between the P well 102 and the carrier adjusting conductive layer 103, which adjusts the injection or suction of the holes, and the carrier adjusting conductive layer 103. The configuration has an insulating separation layer 105 provided between the semiconductor substrate 101 and the semiconductor substrate 101. That is, the carrier adjusting insulating layer 104 is formed so as to surround the periphery of the MISFET, and the carrier adjusting conductive layer 103 and the insulating separation layer 105 are sequentially formed on the outer side thereof. Here, when the semiconductor substrate 101 is a silicon substrate, the carrier adjusting conductive layer 103 is P.⁺It is composed of a type polycrystalline silicon film, and the carrier adjusting insulating layer 104 is composed of a silicon nitride film having a thickness of 2 nm to 5 nm or a silicon oxynitride film. Here, it is preferable to form a 0.2 nm-thick silicon oxide film between the P well 102 and the carrier adjusting insulating layer 104. The insulating separation layer 105 is composed of a silicon oxide film having a film thickness of about 50 nm. In the basic structure of such a threshold control device, two types of voltages are applied to the carrier adjustment voltage Vqn to the carrier adjustment conductive layer 103, which is a carrier conductive layer, and the P well 102 is a P-type diffusion layer for P well, which will be described later. It is fixed at the source voltage Vsn through 106.

【0022】

Then, a threshold-controlled Nch type MOS transistor is formed in the P well 102. That is, the P-type diffusion layer 106 for the P-well is formed in the P-well 102, and the gate insulating film 109 and the gate electrode 110 are formed in the region between the N-type diffusion layer 107 for the source and the N-type diffusion layer 108 for the drain. .. The gate insulating film 109 is made of a silicon oxide film, a metal oxide film, a metal silicate dielectric film, or the like, and the gate electrode 110 is made of a refractory metal polyside film, a polymetal film, or the like. Then, the P-type diffusion layer 106 for the P-well and the N-type diffusion layer 107 for the source are commonly connected, and the source voltage Vsn is connected to the P-well 102 and the N-type diffusion layer 107 for the source, and the drain is drained to the N-type diffusion layer 108 for the drain. A voltage Vdn and a gate voltage Vgn are applied to the gate electrode 110, respectively.

【0023】

The operation of the threshold control device configured as described above will be described with reference to FIGS. 2 and 3. FIG. 2 is a timing chart of the applied voltage during the operation of the present invention, and FIG. 3 is a band diagram during hole injection / suction.

【0024】

As shown in FIG. 2, the P-well voltage of the P-well 102 is fixed at the source voltage Vsn = 0V. When the gate voltage is Vgn = 0V and the Nch type MOS transistor is in a non-conducting state, the carrier adjustment voltage Vqn = -5 to -10V applied to the above-mentioned carrier adjustment conductive layer 103 is set to a negative voltage, and the above P well is used. By making the voltage lower than the P-well voltage of 102, the holes existing in the P-well 102 are attracted to the carrier adjusting conductive layer 103 side, and the hole concentration in the P-well 102 is lowered. Explaining this situation with reference to FIG. 3A, the electron energy of the carrier adjusting conductive layer 103 is higher than that of the P well 102, and the carrier adjusting insulating layer 104 is 1 to 5 × 10⁷A high electric field of about V / cm is generated. By this high electric field, the holes in the P well 102 are attracted to the carrier adjusting conductive layer 103 side. As a result, the potential barrier at the junction surface between the source N-type diffusion layer 107 and the P-well 102 becomes high, the threshold value of the Nch-type MOS transistor rises, and the diffusion current of electrons in the sub-threshold region of its operation decreases. Then, the leakage current between the drain N-type diffusion layer 108 and the source N-type diffusion layer 107 is reduced.

【0025】

On the other hand, as shown in FIG. 2, when the operating voltage of the Nch type MOS transistor, for example, the gate voltage is Vgn = 2 to 3V and the Nch type MOS transistor is in a conductive state, the carrier adjustment voltage Vqn = 5 to 10V described above. By doing so, holes are injected into the P well 102 from the carrier adjusting conductive layer 103 to increase the carrier concentration. Explaining this situation with reference to FIG. 3 (b), this time, the electron energy of the P well 102 is higher than that of the carrier adjusting conductive layer 103, and the 4 × 10 is applied to the carrier adjusting insulating layer 104.⁷Holes are injected into the P well 102 by a high electric field of about V / cm. As a result, the potential barrier at the junction surface between the source N-type diffusion layer 107 and the P-well 102 is lowered, the threshold value of the Nch-type MOS transistor is lowered, and the switching speed is increased.

【0026】

According to the threshold control device of the first embodiment of the present invention, the carrier adjusting insulating layer which is the carrier insulating layer and the carrier adjusting which is the carrier conductive layer are in the region in contact with the P well forming the Nch type MOS transistor. A conductive layer is provided, and the threshold value of the Nch type MOS transistor can be freely adjusted and controlled through the injection / suction of holes in the P well, and the leakage current is reduced when the Nch type MOS transistor is in a non-conducting state. This makes it possible to reduce power consumption and speed up operation when in a conductive state. Then, according to the above threshold control device, since the P well 102 and the source N-type diffusion layer 107 are commonly connected and fixed at the source voltage Vsn = 0V, if the potential difference between the gate electrode 110 and the P well 102 is too large. However, deterioration of the withstand voltage of the gate insulating film is prevented. Further, since the P well 102 is surrounded by the carrier adjusting insulating layer 104, the parasitic bipolar operation as described in the conventional technique does not occur at all, and the latch-up withstand voltage is greatly improved. Further, since the electrode connected to the P-type diffusion layer 106 for the P-well and the electrode connected to the N-type diffusion layer 107 for the source can be shared into one wiring, the density of the semiconductor integrated circuit can be easily increased. In the threshold control device of the present invention, the carrier conductive layer functions as a carrier supply source, and the carrier insulating layer functions as a carrier barrier between the well layer and the carrier conductive layer. Such a function is the same in all the following embodiments without particular mention.

【0027】

In the above embodiment, the carrier adjusting conductive layer 103 and the carrier adjusting insulating layer 104 for injecting / sucking holes are formed on the entire bottom surface and the entire side surface of the P well. The present invention is not limited to this, and the carrier adjusting conductive layer and the carrier adjusting insulating layer to be laminated may be formed on a part of the bottom surface or a part of the side surface of the P well. Further, in the above embodiment, it is desirable that the P-well layer in contact with the carrier adjusting insulating layer is set to a high concentration region. In this way, hole injection becomes efficient. This is because, as explained in FIG. 3 (b), when a positive voltage is applied to the carrier adjustment voltage Vqn, the band bending at the interface region between the P well 102 and the carrier adjustment insulating layer 104 becomes smaller, which is for carrier adjustment. This is because a high electric field can be easily formed in the insulating layer 104. In the above embodiment, the injection / suction of holes is described, but conversely, even if the injection of holes is performed by attracting electrons and the suction of holes is performed by injecting electrons, the same applies. I will mention that it becomes.

【0028】

Next, FIG. 4 shows a cross-sectional view of the threshold control device according to the second embodiment of the present invention. This is a threshold control device in the case of a Pch type MOS transistor. In FIG. 4, the threshold control device is a carrier adjusting conductive layer 203 provided between the semiconductor substrate 201 and the N well 202, and electron injection or electron injection performed between the carrier adjusting conductive layer 203 and the N well 202. An insulating layer 204 for carrier adjustment provided between the N well 202 and the conductive layer 203 for carrier adjustment for adjusting suction, and an insulating separation layer provided between the conductive layer 203 for carrier adjustment and the semiconductor substrate 201. It is a configuration having 205. Here, the impurity concentration of the N well 202 in the region in contact with the carrier adjusting insulating layer 204 is increased to form the N well high concentration region 202a. When the semiconductor substrate 201 is a silicon substrate, the carrier adjusting conductive layer 203 is N.⁺It is composed of a type polycrystalline silicon film, and the carrier adjusting insulating layer 204 is composed of a silicon oxide film having a film thickness of 3 nm to 6 nm. The insulating separation layer 205 is made of a silicon oxide film having a film thickness of about 50 nm. This is the basic structure of the threshold control device applied to the Pch type MOS transistor. In this case as well, two types of voltages are applied to the carrier adjusting conductive layer 203 to the adjusting voltage Vqp, and the N well 202 is fixed to the source voltage Vsp through the N-well N-type diffusion layer 206 described later.

【0029】

Then, a threshold-controlled Pch type MOS transistor is formed in the N well 202. That is, the N-well N-type diffusion layer 206 is formed in the N-well 202, and the gate insulating film 209 and the gate electrode 210 are formed in the region between the source P-type diffusion layer 207 and the drain P-diffusion layer 208. Here, the N-type diffusion layer 206 for the N-well and the P-type diffusion layer 207 for the source are commonly connected, and the source voltage Vsp is applied to the N-well 202 and the P-type diffusion layer 207 for the source to the P-type diffusion layer 208 for the drain. A drain voltage Vdp and a gate voltage Vgp are applied to the gate electrode 210, respectively.

【0030】

The operation of the threshold control device configured as described above will be described with reference to FIGS. 5 and 6. FIG. 5 is a timing chart of the applied voltage in the case of this embodiment, and FIG. 6 is a band diagram at the time of electron injection / suction.

【0031】

As shown in FIG. 5, the N-well voltage of the N-well 202 is fixed together with the source P-type diffusion layer 207 to the operating voltage of the Pch-type MOS transistor, for example, the positive voltage of the source voltage Vsp = 2 to 3V. Then, when the gate voltage Vgp = 2 to 3 V and the Pch type MOS transistor is in a non-conducting state, the carrier adjustment voltage Vqp = 5 to 10 V applied to the above-mentioned carrier adjustment conductive layer 203 is set to the above N well. By setting the voltage higher than the N-well voltage of 202, the electrons of the N-well 202 are attracted and the electron concentration of the N-well 202 is lowered. Explaining this situation with reference to FIG. 6A, the electron energy of the carrier adjusting conductive layer 203 is lower than that of the N well 202, and the carrier adjusting insulating layer 204 has 2 × 10⁷A high electric field of about V / cm is generated. Due to this high electric field, the electrons in the N well 202 are attracted to the carrier adjusting conductive layer 203 side. As a result, the potential barrier at the junction surface between the source P-type diffusion layer 207 and the N-well 202 is raised to raise the threshold value of the Pch-type MOS transistor and increase the diffusion current of holes in the sub-threshold region of its operation. Reduce. Then, the leakage current between the drain P-type diffusion layer 208 and the source P-type diffusion layer 207 is reduced.

【0032】

On the other hand, as shown in FIG. 5, when the gate voltage Vgp = 0V and the Pch type MOS transistor is in a conductive state, the carrier adjustment voltage Vqp = -5V is set as a negative voltage, and the N well voltage of the N well 202 is set. That is, by setting the voltage lower than Vsp = 2 to 3 V, electrons are injected into the N well 202 from the carrier adjusting conductive layer 203 to increase the electron concentration of the N well 202. Explaining this situation with reference to FIG. 6 (b), this time, the electron energy of the N well 202 is lower than that of the carrier adjusting conductive layer 203, and the 2 × 10 applied to the carrier adjusting insulating layer 204.⁷Electrons are injected into the N well 202 by a high electric field of about V / cm. As a result, the potential barrier at the junction surface between the source P-type diffusion layer 207 and the N-well 202 is lowered, the threshold value of the Pch-type MOS transistor is lowered, and the switching speed is increased.

【0033】

According to the threshold control device of the second embodiment of the present invention, the carrier adjusting insulating layer 204 and the carrier adjusting conductive layer 203 are provided in the region in contact with the N well 202 forming the Pch type MOS transistor. The threshold value of the Pch type MOS transistor can be freely adjusted and controlled through injection / suction of N-well electrons, and when the Pch type MOS transistor is in the non-conducting state, the leakage current is reduced to reduce power consumption and the conducting state. At the time of, the operation speed can be increased. Then, according to the above-mentioned threshold control device, since the N-well 202 and the source N-type diffusion layer 207 are commonly connected and fixed at the source voltage Vsn = 0V, if the potential difference between the gate electrode 210 and the N-well 202 is too large. However, deterioration of the withstand voltage of the gate insulating film is prevented. Further, since the N-well 202 is surrounded by the carrier adjusting insulating layer 204, the parasitic bipolar operation as described in the conventional technique does not occur at all, and the latch-up withstand voltage is significantly improved. Further, since the electrode connected to the N-type diffusion layer 206 for N-well and the electrode connected to the N-type diffusion layer 207 for source can be shared into one wiring, the density of the semiconductor integrated circuit can be easily increased.

【0034】

In the above embodiment, the carrier adjusting conductive layer 203 and the carrier adjusting insulating layer 204 for injecting / attracting electrons are formed on the entire bottom surface and the entire side surface of the N well 202. The present invention is not limited to this, and the carrier adjusting conductive layer and the carrier adjusting insulating layer to be laminated may be formed on a part of the bottom surface or a part of the side surface of the N well 202. Although the injection / suction of electrons is described in the above embodiment, it should be noted that the same can be achieved by suction / injection of holes which are the opposite of each other.

【0035】

Next, FIG. 7 shows a cross-sectional view of the threshold control device according to the third embodiment of the present invention. This is a threshold control device in the case of an Nch type MOS transistor. Unlike the first and second embodiments, the feature in this case is that in FIG. 7, the carrier adjusting insulating layer 303 which is a carrier insulating layer and the carrier adjusting electrode 304 which is a carrier conductive layer are formed on the upper surface of the P well 302. It has a structure in. As shown in the figure, the P-well 302 is formed on the N-conductive semiconductor substrate 301, and the P-well 302 is used for carrier adjustment via the carrier adjusting insulating layer 303 on the surface of the P-well 302 on which the Nch type MOS transistor is not formed. An electrode 304 is provided to allow hole injection or suction between the carrier adjusting electrode 304 and the P-well 302. Here, a P-well high concentration region 302a is provided directly below the carrier adjusting insulating layer 303. A first interlayer insulating film 305 is provided between the carrier adjusting electrode 304 and the semiconductor substrate 301 to separate the insulation. Then, as in the first embodiment, when the semiconductor substrate 301 is a silicon substrate, the carrier adjusting electrode 304 is P.⁺Molded polycrystalline silicon film, or P⁺The insulating layer 304 for carrier adjustment is composed of a silicon nitride film or a silicon oxynitride film having a film thickness of 2 nm to 5 nm. Alternatively, a silicon oxide film of about 0.2 nm is formed between the P-well high concentration region 302a and the carrier adjusting insulating layer 304. In the basic structure of such a threshold control device, the P well 302 is fixed to the source voltage Vsn described later through the P-type diffusion layer for the P well described later.

【0036】

Then, a threshold-controlled Nch type MOS transistor is formed in the P well 302. That is, the P-type diffusion layer 306 for the P-well is formed in the P-well 302, and is connected to the source / well shared wiring 308 through the contact plug 307. Similarly, the source N-type diffusion layer 309 is also connected to the source / well shared wiring 308 through the contact plug 307, and the drain N-type diffusion layer 310 is connected to the drain wiring 311 through the contact plug. Then, a gate insulating film 312 and a gate electrode 313 are formed in a region between the source N-type diffusion layer 308 and the drain N-type diffusion layer 310, and the gate electrode 313 is connected to the gate wiring 314 through a contact plug. Further, a second interlayer insulating film 315 that covers the entire surface is formed. Here, the source voltage Vsn is applied to the source / well shared wiring 308, the drain voltage Vdn is applied to the drain wiring 311 and the gate voltage Vgn is applied to the gate wiring 314.

【0037】

The operation of the threshold control device configured as described above is the same as the operation described with reference to FIGS. 2 and 3 in the first embodiment. The manufacturing method of the threshold control device of this embodiment is simpler than that of the first and second embodiments, and the threshold control device can be formed in exactly the same manner as the conventional method of manufacturing a semiconductor integrated circuit. Further, in order to form the P-type diffusion layer 306 for the P-well and the N-type diffusion layer 309 for the source by partially overlapping each other to standardize the electrodes and form one wiring, the carrier adjustment insulating layer 303 and the carrier adjustment electrode are used. Even in this embodiment in which 304 is provided on the upper surface of the P well 302, the high density of the semiconductor integrated circuit is not impaired. Then, exactly the same effect as described in the first and second embodiments will be produced.

【0038】

Next, FIG. 8 shows a cross-sectional view of the threshold control device according to the fourth embodiment of the present invention. This is a threshold control device in the case of a Pch type MOS transistor. In this case as well, as in the third embodiment, the feature is that the carrier adjusting insulating layer and the carrier adjusting electrode described above are provided on the upper surface of the N well. In FIG. 8, the carrier adjusting electrode 404 is formed on the surface of the N well 402 in which the N well 402 is formed on the P conductive type semiconductor substrate 401 and the Pch type MOS transistor is not formed, via the carrier adjusting insulating layer 403. Is provided so that electrons can be injected or aspirated between the carrier adjusting electrode 404 and the P well 402. Here, an N-well high concentration region 402a is provided directly below the carrier adjusting insulating layer 403. A first interlayer insulating film 405 is provided between the carrier adjusting electrode 404 and the semiconductor substrate 401 for insulation separation. Then, as in the second embodiment, when the semiconductor substrate 401 is a silicon substrate, the carrier adjustment electrode 404 is N.⁺Molded polycrystalline silicon film, or N⁺The insulating layer 404 for carrier adjustment is composed of a silicon oxide film having a thickness of 4 nm to 6 nm. In the basic structure of such a threshold control device, the N-well 402 is fixed to the source voltage Vsp described later through the N-type diffusion layer for N-well described later.

【0039】

Then, a threshold-controlled Pch-type MOS transistor is formed in the N-well 402. That is, an N-type diffusion layer 406 for N-well is formed on the N-well 402, and is connected to the source / well shared wiring 408 through the contact plug 407. Similarly, the source P-type diffusion layer 409 is connected to the source / well shared wiring 408 through the contact plug 407, and the drain P-diffusion layer 410 is connected to the drain wiring 411 through the contact plug. Then, a gate insulating film 412 and a gate electrode 413 are formed in a region between the source P-type diffusion layer 409 and the drain P-diffusion layer 410, and the gate electrode 413 is connected to the gate wiring 414 through a contact plug. Further, a second interlayer insulating film 415 that covers the entire surface is formed. Here, the source voltage Vsp is applied to the source / well shared wiring 408, the drain voltage Vdp is applied to the drain wiring 411, and the gate voltage Vgp is applied to the gate wiring 414.

【0040】

The operation of the threshold control device configured as described above is the same as the operation described with reference to FIGS. 5 and 6 in the second embodiment. The threshold control device of this embodiment can also be formed in exactly the same manner as the conventional method for manufacturing a semiconductor integrated circuit as described in the third embodiment. Further, in order to form the N-well N-type diffusion layer 406 and the source P-type diffusion layer 409 by partially overlapping each other to standardize the electrodes and form one wiring, the carrier adjustment insulating layer 403 and the carrier adjustment electrode 404 Even in this embodiment in which and is provided on the upper surface of the N-well 402, the high density of the semiconductor integrated circuit is not impaired. Then, in this case as well, exactly the same effect as described in the first and second embodiments will be produced.

【0041】

Next, FIG. 9 shows a cross-sectional view of the threshold control device according to the fifth embodiment of the present invention. This is a threshold control device in the case of a CMOS transistor, and has a structure in which the first and second embodiments are combined. Hereinafter, a brief description will be given. In FIG. 9, a carrier adjusting conductive layer 503 is provided between the semiconductor substrate 501 and the P well 502, and carrier adjustment is performed so that holes are injected or attracted between the carrier adjusting conductive layer 503 and the P well 502. An insulating layer 504 is provided between the carrier adjusting conductive layer 503 and the P well 502. Here, the impurity concentration of the P well 502 in the region in contact with the carrier adjusting insulating layer 504 is increased to form the P well high concentration region 502a. An insulation separation layer 505 is provided between the carrier adjusting conductive layer 503 and the semiconductor substrate 501.

【0042】

Then, a threshold-controlled Nch type MOS transistor is formed in the P well 502. That is, the P-type diffusion layer 506 for the P-well is formed in the P-well 502, and the gate insulating film 509 and the gate electrode 510 are formed in the region between the N-type diffusion layer 507 for the source and the N-type diffusion layer 508 for the drain. .. Here, the source voltage Vsn is applied to the P-type diffusion layer 506 for the P-well and the N-type diffusion layer 507 for the source, the drain voltage Vdn is applied to the drain N-type diffusion layer 508, and the gate voltage Vgn is applied to the gate electrode 510. To.

【0043】

Similarly, a carrier adjusting conductive layer 512 is provided between the semiconductor substrate 501 and the N well 511, and carrier adjusting insulation is provided between the carrier adjusting conductive layer 512 and the N well 511 to inject or attract electrons. A layer 513 is provided between the carrier adjusting conductive layer 512 and the N well 511. Here, the impurity concentration of the N well 511 in the region in contact with the carrier adjusting insulating layer 513 is increased, and the N well high concentration region 511a is formed. An insulation separation layer 505 is provided between the carrier adjusting conductive layer 512 and the semiconductor substrate 501.

【0044】

Then, a threshold-controlled Pch-type MOS transistor is formed in the N-well 511. That is, the N-type diffusion layer 514 for the N-well is formed in the N-well 511, the gate insulating film 517 and the gate electrode 518 are formed in the region between the source P-type diffusion layer 515 and the drain P-diffusion layer 516, and the N-well is formed. The source voltage Vsp is applied to the N-type diffusion layer 514 and the P-type diffusion layer 515 for the source, the drain voltage Vdp is applied to the drain P-type diffusion layer 516, and the gate voltage Vgp is applied to the gate electrode 518.

【0045】

If the CMOS circuit is formed based on the fifth embodiment, high-speed operation during switching and low power consumption during standby of the semiconductor integrated circuit become possible, and the gate described in the first and second embodiments. It becomes easy to prevent deterioration of the insulation withstand voltage of the insulating film, increase the density of semiconductor integrated circuits, and reduce the area of semiconductor chips. Further, because of the carrier adjusting insulating layers 504,513 or the insulating separating layer 505, there is no surge latch-up peculiar to the CMOS circuit.

【0046】

Next, a cross-sectional view of the threshold control device according to the sixth embodiment of the present invention is shown in FIG. This is also a threshold control device in the case of a CMOS transistor, and has a structure in which the third and fourth embodiments are combined. Hereinafter, a brief description will be given. P^-A P-well 602 is formed on the conductive semiconductor substrate 601, and a carrier-adjusting electrode 604 is provided via a carrier-adjusting insulating layer 603 on a surface on which the Nch-type MOS transistor of the P-well 602 is not formed. Holes are injected or aspirated between the adjusting electrode 604 and the P well 602. Here, the impurity concentration of the P well 602 in the region in contact with the carrier adjusting insulating layer 603 may be increased. A first interlayer insulating film 605 is provided between the carrier adjusting electrode 604 and the semiconductor substrate 601 to separate the insulation.

【0047】

Then, a threshold-controlled Nch type MOS transistor is formed in the P well 602. That is, a P-type diffusion layer 606 for P-well is formed in P-well 602, and is connected to the source / well shared wiring 608 through the contact plug 607. Similarly, the source N-type diffusion layer 609 is connected to the source / well shared wiring 608 through the contact plug 607, and the drain N-type diffusion layer 610 is connected to the drain wiring 611 through the contact plug. A gate insulating film 612 and a gate electrode 613 are formed in the region between the source N-type diffusion layer 608 and the drain N-type diffusion layer 610, and the gate electrode 613 is connected to the gate wiring 614 through a contact plug. Here, the source voltage Vsn is applied to the source / well shared wiring 608, the drain voltage Vdn is applied to the drain wiring 611, and the gate voltage Vgn is applied to the gate wiring 614.

【0048】

Similarly, P^-An N-well 615 is formed on the conductive semiconductor substrate 601, and a carrier-adjusting electrode 617 is provided via a carrier-adjusting insulating layer 616 on a surface on which the Pch-type MOS transistor of the N-well 615 is not formed. Electron injection or suction should be performed between the adjusting electrode 617 and the N-well 615. Here, the impurity concentration of the N well 615 in the region in contact with the carrier adjusting insulating layer 616 may be increased.

【0049】

Then, a threshold-controlled Pch type MOS transistor is formed in the N well 615. That is, an N-type diffusion layer 618 for N-wells is formed on the N-wells 615, and is connected to the source / well shared wiring 620 through the contact plug 619. Similarly, the source P-type diffusion layer 621 is connected to the source / well shared wiring 620 through the contact plug 619, and the drain P-diffusion layer 622 is connected to the drain wiring 623 through the contact plug. A gate insulating film 624 and a gate electrode 625 are formed in the region between the source P-type diffusion layer 621 and the drain P-diffusion layer 622, and the gate electrode 625 is connected to the gate wiring 626 through a contact plug. Further, a second interlayer insulating film 627 that covers the entire surface is formed. Here, the source voltage Vsp is applied to the source / well shared wiring 620, the drain voltage Vdp is applied to the drain wiring 623, and the gate voltage Vgp is applied to the gate wiring 626.

【0050】

If the CMOS circuit is formed based on the sixth embodiment, high-speed operation during switching of the semiconductor integrated circuit and low power consumption during standby are possible, and the increase in device area due to the installation of the source / well shared electrode is reduced. This makes it possible to increase the density of semiconductor integrated circuits and reduce the area of semiconductor chips. Then, it is possible to prevent deterioration of the withstand voltage of the gate insulating film based on the third and fourth embodiments, and the surge latch-up peculiar to the CMOS circuit is also significantly reduced.

【0051】

As described above, in the threshold control device of the present invention, the carrier conductive layer functions as a carrier supply source, and the carrier insulating layer functions as a carrier barrier between the well and the carrier conductive layer. In the above embodiment, the case where the carrier adjusting conductive layer 103,203,503,512, which is the carrier conductive layer, or the carrier adjusting electrode 304,404,604,617 is made of polycrystalline silicon has been described. Can be implemented in the same way. Similarly, a metal oxide film such as a tantalum oxide film or a hafnium oxide film can be used as the carrier insulating layer 104,204,303,403,504,513,603,616 as the carrier insulating layer.

【0052】

Further, the present invention is not limited to the above-described embodiment, and the embodiment can be appropriately modified within the scope of the technical idea of the present invention. For example, an SOI (Silicon on Insulator) substrate may be used as the semiconductor substrate. In the case of such a substrate, it is not always necessary to form P wells and N wells in the above embodiment. Further, a compound semiconductor substrate may be used as the semiconductor substrate. In such a case, a semiconductor film having a bandwidth wider than that of the substrate may be used instead of the carrier insulating layer, or a Schottky junction layer with a metal may be used. This is because these also function as a carrier barrier in the same manner as the carrier insulating layer.

【0053】

[Effect of the invention]

As described above, the present invention reduces the threshold value of the MISFET on the semiconductor substrate to the conductive state and increases the threshold value to the non-conducting state of the MISFET by injecting carriers into the semiconductor substrate or attracting carriers from the semiconductor substrate. By providing carrier injection / suction means, it is possible to speed up the switching characteristics of the MISFET, reduce the leakage current in the non-conducting state, improve the insulation resistance of the gate insulating film of the MISFET, and surge latch the CMOS circuit. It is possible to provide a threshold control device having an effect of improving up resistance and further increasing the density of semiconductor integrated circuits.

[Simple explanation of drawings]

FIG. 1 is a cross-sectional view of the threshold control device according to the first embodiment of the present invention. FIG. 2 is a timing chart diagram of an operation description of the threshold control device according to the first embodiment of the present invention. FIG. Band diagram in hole suction operation in the first embodiment of the present invention (b) Band diagram in hole injection operation in the first embodiment of the present invention [Fig. 4] Threshold in the second embodiment of the present invention. Cross-sectional view of the control device [FIG. 5] Timing chart diagram of an operation description of the threshold control device according to the second embodiment of the present invention [Fig. 6] (a) Band in the electron suction operation according to the second embodiment of the present invention. Diagram (b) Band diagram in electron injection operation according to the second embodiment of the present invention [Fig. 7] Cross-sectional view of the threshold control device according to the third embodiment of the present invention [Fig. 8] Fourth embodiment of the present invention. Cross-sectional view of the threshold control device according to the embodiment [FIG. 9] Cross-sectional view of the threshold control device according to the fifth embodiment of the present invention [FIG. 10] Cross-sectional view of the threshold control device according to the sixth embodiment of the present invention [FIG. 11] Cross-sectional view of a conventional threshold control device [Explanation of reference numerals]

101,201,301,401,501,601 Semiconductor substrate 102,302,502,602 P-well 103,203,503,512 Carrier adjustment conductive layer 104,204,303,403 Carrier adjustment insulating layer 105,205,505 Insulation separation layer 106,306,506,606 P-well P-type diffusion layer 107,309,507,609 P-well N-type diffusion layer 107,309,507,609 Source N-type diffusion layer 108,310,508,610 N-type diffusion layer 108,310,508,610 Electrodes 202,402,511,615 N-well high concentration region 206,406,514,618 N-well N-type diffusion layer 207,409,515,621 Source P-type diffusion layer 208,410,516,622 Drain P-type diffusion layer 302a,502a P-well high-concentration region 304,404,604,617 Carrier adjustment electrode 307,407,607 Contact plug 308,408,608,620 Source / well shared wiring 311,411,611,623 Drain wiring 314,414,614,626 Gate wiring 504,513,603,616 Carrier adjustment insulating layer 509,517,612,624 Gate insulating film 510,518,613,625 Gate electrode Vqn, Vqp Carrier adjustment voltage Vsn, Vsp Source voltage Vgn, Vgp Gate voltage Vdn, Vdp Drain voltage