Method and program for designing layout of semiconductor integrated circuit

【0001】

[Technical field to which the invention belongs]

The present invention relates to a method for designing a layout of a semiconductor integrated circuit, and more particularly to a method for designing a layout of a semiconductor integrated circuit in which automatic placement and wiring are performed using a fill cell dedicated to filling a gap on a substrate.

【0002】

[Conventional technology]

A semiconductor integrated circuit is basically manufactured as a product through a design process such as a logic design process and a layout design process, a manufacturing process, and an evaluation test process. Further, in the layout design process of the standard cell type semiconductor integrated circuit, although the literature cannot be specified, as a known technique, a logic basic cell which is a circuit pattern corresponding to a logic component such as a 2-input NAND, an inverter, and a flip-flop, and a logic basic cell. There is a technique for registering and using a fill cell, which is a pattern dedicated to filling gaps on a substrate, which does not correspond to a logical component, in a cell library.

【0003】

This fill cell is a cell to be embedded and arranged in advance in the arrangement prohibited area on the semiconductor substrate where the logical basic cell should not be arranged, and also to embed a gap in which the logical basic cell is not arranged after the arrangement of the logical basic cell. The cell to place. In addition, as the placement prohibition area, generally, an area where a short circuit occurs in the metal wiring when the logical basic cell is automatically placed and wired, such as an area of the vertically wired vertical power supply wiring, and a logical where the logical basic cell is automatically placed and wired. Areas where the wiring between the basic cells may become congested and the wiring may not be completed are set.

【0004】

FIG. 5 is a plan view showing an example of a fill cell pattern configuration in this conventional layout design method for a semiconductor integrated circuit, and the fractions (A) and (B) are a narrow fill cell 25 and a wide fill cell 26. And are shown respectively. These conventional fill cells 25 and 26 are provided with N wells 17 and P wells 18 connected to the power supply wirings 14 and 15 in the cell outer frame 16, and also have a power supply so as not to interfere with the metal wiring wired on the upper part. It is configured so that it does not have data for metal wiring layers other than wirings 14 and 15. Generally, as shown in FIG. 5, a plurality of types of fill cells having different cell widths are prepared. When filling an empty area in the layout design process, first, thick fill cells are arranged side by side, and then thin fill cells are arranged. Fill the free space by arranging them side by side. By doing so, it is possible to efficiently fill the free area and reduce the amount of layout data of the semiconductor integrated circuit.

【0005】

Further, it is known that a phenomenon called an optical proximity effect occurs in the manufacturing process of a semiconductor integrated circuit. This optical proximity effect occurs at the stage of exposing the layout pattern on the semiconductor substrate, and affects the wiring width and the like constituting the semiconductor integrated circuit. The greater the distance to the adjacent wiring in the same layer, the greater the influence of the optical proximity effect and the narrower the wiring width. Generally, when the logical basic cells are arranged by the automatic arrangement and wiring process, the intervals between the adjacent logical basic cells are random. A logical basic cell having a large distance from a adjacent logical basic cell is affected by the above-mentioned optical proximity effect, and for example, the gate dimensions of the transistors included in the logical basic cell vary.

【0006】

Even if this variation in gate dimensions occurs due to the effect of the optical proximity effect, it did not significantly affect the performance in the manufacturing process with a wiring width of about 0.5 μm, but in the current manufacturing process, it is 0.2 μm or less. The wiring width manufacturing process has come to be used, and further reduction of the wiring width is expected in the future. When the wiring width becomes narrower, the variation in the wiring width due to the optical proximity effect becomes larger relative to the wiring width, and the characteristics of the transistor, that is, the on-resistance, drive capability, threshold value, etc., are greatly changed. The design value and characteristics of the circuit itself are different, and the performance expected of the manufactured semiconductor integrated circuit cannot be exhibited.

【0007】

Therefore, in the layout design process, OPC (Optical Proximity Correction) processing is performed on the gate polysilicon pattern of the transistor. This OPC processing predicts how much the wiring width will fluctuate due to the influence of the optical proximity effect from the distance between adjacent wirings, and the wiring width will be the same as the original design value after the fluctuation. Correct the layout data of. As a result, the performance of the transistor of the manufactured semiconductor integrated circuit becomes equivalent to the design value.

【0008】

FIG. 6 is a flow chart showing a procedure example in the layout design method of the conventional semiconductor integrated circuit described above. This conventional method for designing a layout of a semiconductor integrated circuit includes the processes of steps S1 to S10, and is executed in response to each command input by a computer having a general configuration in which a program for designing a layout of the semiconductor integrated circuit is installed.

【0009】

Further, FIG. 7 is an explanatory diagram for concretely explaining the arrangement and wiring process in this conventional layout design method, and the division diagrams (A) to (D) are in a state where the steps in the middle of the layout design process are completed. Layout image examples of are shown below.

【0010】

With reference to FIG. 6, in the layout design method of this conventional semiconductor integrated circuit, first, in step S1, the cell library information in which the above-mentioned logical basic cell and fill cell are registered and the circuit connection corresponding to the netlist of the semiconductor integrated circuit are connected. Read the information as data for automatic placement and routing.

【0011】

In step S2, the power supply wiring of the semiconductor integrated circuit is wired on the board based on the data for automatic placement wiring. For example, as shown in FIG. 7 (A), the power supply wirings 14 and 15 are wired in the lower metal wiring layer, and then the vertical power supply wirings 14'and 15'are wired in the upper metal wiring layer. Via 19 is placed at the overlap of the lower and upper power supply wirings 14 and 14'or the power supply wirings 15 and 15'that have the same potential, and the lower and upper power supply wirings 14 and 14', the power supply wiring 15 and the same potential. Each 15'is electrically connected.

【0012】

In step S3, the arrangement prohibition area of the logical basic cell is set, and the fill cell is embedded and arranged between the power supply wirings in this arrangement prohibition area. For example, as shown in FIG. 7B, the fill cell 25 is spread directly under the vertical power supply wirings 14'and 15', which are the arrangement prohibited areas.

【0013】

In step S4, the type of the logical basic cell included in the circuit connection information is determined, the corresponding logical basic cell is read from the cell library information, and the power supply of the logical basic cell arrangeable area other than the arrangement prohibited area on the semiconductor substrate is used. The logical basic cells are arranged between the wirings based on the automatic arrangement wiring data. For example, as shown in FIG. 7C, the logical basic cells 10 are randomly arranged in the arrangeable area.

【0014】

In step S5, wiring is performed between the arranged logical basic cells based on the circuit connection information of the automatic arrangement wiring data.

【0015】

In step S6, the fill cell is embedded and arranged in the free area of the displaceable area, that is, the power supply wiring of the non-placement area or the free area between the logical basic cell and the logical basic cell. For example, if the illustration of the wiring connection is omitted, as shown in FIG. 7 (D), the thick fill cell 26 and the narrow fill cell 25 are embedded in an empty area in which nothing is arranged in order. Will be done. Here, there are two types of fill cell widths, but one type may be used, or three or more types may be used.

【0016】

In step S7, OPC processing is performed on the gate polysilicon pattern of the transistor, and after the completion, layout data is output, and in step S8, whether the layout data is correctly constructed and whether various restrictions are satisfied, etc. Verify, in step S9, check if there is an error in the verification result, if there is an error, return to step S4 for relocation wiring, if there is no error, proceed to step S10, EB process the layout data, layout Finish the design process.

【0017】

FIG. 8 is a plan view showing an example of a basic cell pattern configuration in another conventional layout design method (see Patent Document 1).

【0018】

The basic cell in this conventional layout design method has a pattern configuration in which a dummy polysilicon pattern 4 is arranged so as to surround the outer circumference of the internal logic portion as shown in FIG. 8 (A), or has a pattern configuration in FIG. 8 (B). It has a pattern configuration in which a dummy polysilicon pattern 41 parallel or perpendicular to the gate polysilicon 3 of the internal logic part is arranged as shown in FIG. It has a pattern configuration in which a dummy polysilicon pattern 42 composed of small parts is arranged.

【0019】

These conventional basic cells are configured so that the distance between the gate polysilicon pattern and the adjacent dummy polysilicon pattern is kept within a certain range and is not affected by the optical proximity effect during manufacturing, and the gate is set in units of basic cells. Since the distance between the polysilicon pattern and the dummy polysilicon pattern is determined, OPC processing can be calculated for each basic cell, eliminating the need to perform OPC processing after automatically arranging and wiring this basic cell during product development.

【0020】

[Patent Document 1]

Japanese Unexamined Patent Publication No. 10-32253 (Fig. 2, Fig. 4. Fig. 6) [0021]

[Problems to be Solved by the Invention]

As described above, in the manufacturing process of semiconductor integrated circuits, the wiring width is expected to be further reduced in the future, the wiring width becomes narrower, and the variation in the wiring width due to the optical proximity effect is relatively large with respect to the wiring width. Therefore, the accuracy of the correction amount of the wiring width by OPC processing is required. In particular, the larger the distance between adjacent wiring patterns, the larger the correction amount of the wiring width by the OPC processing, and the higher the correction amount of high accuracy is required. However, in practice, the amount of calculation of OPC processing increases, the processing time becomes long, OPC processing becomes difficult, and there arises a problem that the performance of the transistor after manufacturing does not match the design value.

【0022】

Further, in the pattern configuration of the basic cell in the conventional layout design method shown in FIG. 8, since the dummy polysilicon pattern is arranged on the outer periphery of the internal logic portion, the cell area of the basic cell increases and the semiconductor integrated circuit is integrated. There is a problem that the density becomes low and the layout area of the semiconductor integrated circuit increases.

【0023】

Therefore, an object of the present invention is to shorten the processing time of the OPC processing without increasing the layout area of the semiconductor integrated circuit.

【0024】

[Means for solving problems]

Therefore, in the layout design of the semiconductor integrated circuit according to the present invention, a logic basic cell which is a circuit pattern corresponding to a logic component of the semiconductor integrated circuit and a fill cell containing a dummy polysilicon pattern which is a pattern exclusively for filling a gap on a substrate are registered. A step of reading cell library information and circuit connection information of a semiconductor integrated circuit as data for automatic placement and routing, a step of wiring a power supply wiring of a semiconductor integrated circuit on a substrate based on the data for automatic placement and routing, and a step of wiring the logic basic cell. The step of setting the placement prohibited area and embedding and arranging the fill cell containing the dummy polysilicon pattern adjacent to the area boundary between the power supply wirings of the placement prohibited area and the power supply wiring of the placeable area other than the placement prohibited area. The fill cell containing the dummy polysilicon pattern is embedded adjacent to the logical basic cell between the placement and routing step of arranging and wiring the logical basic cell based on the automatic placement and routing data and the power supply wiring of the empty area of the placeable area. It includes a step of arranging and a step of correcting the optical proximity effect on the gate polysilicon pattern of the transistor.

【0025】

Further, the program for layout design of a semiconductor integrated circuit according to the present invention includes a logic basic cell which is a circuit pattern corresponding to a logic component of a semiconductor integrated circuit and a fill cell containing a dummy polysilicon pattern which is a pattern exclusively for filling a gap on a substrate. The step of reading the registered cell library information and the circuit connection information of the semiconductor integrated circuit as data for automatic placement and routing, the step of wiring the power supply wiring of the semiconductor integrated circuit on the substrate based on the data for automatic placement and routing, and the logical basis. Between the step of setting the cell placement prohibited area and embedding and arranging the fill cell containing the dummy polysilicon pattern adjacent to the area boundary between the power supply wirings of the placement prohibited area and the power supply wiring of the placeable area other than the placement prohibited area. A fill cell with a dummy polysilicon pattern adjacent to the logical basic cell between the placement and routing step of arranging and wiring the logical basic cell based on the automatic placement and routing data and the power supply wiring of an empty area of the arrangeable area. The computer is made to execute the step of embedding and arranging the transistor and the step of correcting the optical proximity effect on the gate polysilicon pattern of the transistor.

【0026】

Further, in the placement and routing step, the distance in the length direction of the power supply wiring from the placement prohibited area or the logic basic cell to the logic basic cell is 0 times, 1 time, or 2 times the width of the fill cell containing the dummy polysilicon pattern. It is more than doubled.

【0027】

Further, the fill cell containing the dummy polysilicon pattern is wired between the pair of power supply wirings in the width direction of the power supply wiring by the layer of the gate polysilicon pattern, and one of the pair of power supply wirings and It is provided with a contact for connecting the dummy polysilicon wiring between layers.

【0028】

Further, the fill cell containing the dummy polysilicon pattern is wired between the pair of power supply wirings in the width direction of the power supply wiring by the gate polysilicon layer, respectively, and a pair of dummy polysilicon wirings and a pair of dummies. It is equipped with a pair of contacts that individually interconnect a pair of power supply wiring to the polysilicon wiring.

【0029】

BEST MODE FOR CARRYING OUT THE INVENTION

Next, the present invention will be described with reference to the drawings. FIG. 1 is a flow chart showing an embodiment of the layout design method of the present invention. The layout design method of the semiconductor integrated circuit of the present embodiment includes the processes of steps S1 to S16, and responds to each command input by a computer having a general configuration in which the semiconductor integrated circuit layout design program is installed as in the conventional case. Is executed.

【0030】

Further, FIG. 2 is a plan view showing a pattern configuration of a fill cell containing a dummy polysilicon pattern used in the layout design method of the present embodiment. This fill cell with a dummy polysilicon pattern has N wells 17 and P wells 18 connected to power supply wirings 14 and 15 in the cell outer frame 16 like the conventional fill cell shown in FIG. 5, and is added to these. Then, the dummy polysilicon wiring 12 and the contact 13 pattern are provided. The dummy polysilicon wiring 12 is wired between the pair of power supply wirings 14 and 15 by a layer of the gate polysilicon pattern of the transistor in the width direction of the power supply wiring, and the contact 13 is connected to one power supply wiring 14 and the dummy polysilicon. Wiring 12 is interconnected between layers. Further, like the conventional fill cell, it is configured not to have data of the metal wiring layer other than the power supply wirings 14 and 15 so as not to interfere with the metal wiring wired on the upper part.

【0031】

Further, FIG. 3 is an explanatory diagram for specifically explaining the arrangement and wiring process in the layout design method of this embodiment, and the fractions (A) to (E) are completed up to the middle step of the layout design process. An example of the layout image of the state is shown.

【0032】

With reference to FIG. 1, the layout design method of the semiconductor integrated circuit of the present embodiment is as follows: First, in step S1 of FIG. 1, a cell library in which the same logical basic cell and fill cell as before and the fill cell containing the above-mentioned dummy polysilicon pattern are registered. The information and the circuit connection information corresponding to the netlist of the semiconductor integrated circuit are read as the data for automatic placement and routing.

【0033】

In step S2, the power supply wiring of the semiconductor integrated circuit is wired on the board based on the automatic placement wiring data as in the conventional case. For example, as shown in FIG. 3 (A), the power supply wirings 14 and 15 are wired in the lower metal wiring layer, and then the vertical power supply wirings 14'and 15'are wired in the upper metal wiring layer. Via 19 is placed at the overlap of the lower and upper power supply wirings 14 and 14'or the power supply wirings 15 and 15'that have the same potential, and the lower and upper power supply wirings 14 and 14', the power supply wiring 15 and the same potential. Each 15'is electrically connected.

【0034】

In step S13, the arrangement prohibited area of the logical basic cell is set, and the fill cell containing the dummy polysilicon pattern is embedded and arranged between the power supply wirings in this arrangement prohibited area. For example, as shown in FIG. 3 (B), fill cells 11 containing a dummy polysilicon pattern are spread directly under the vertical power supply wirings 14'and 15', which are non-placement areas.

【0035】

In step S14, the type of the logical basic cell included in the circuit connection information is determined, the corresponding logical basic cell is read from the cell library information, and the power supply of the logical basic cell arrangeable area other than the arrangement prohibited area on the semiconductor substrate is supplied. The logical basic cells are arranged between the wirings based on the automatic arrangement wiring data. At this time, in the present embodiment, the distance in the length direction of the power supply wiring from the arrangement prohibited area or the logical basic cell to the logical basic cell is set to 0 times, 1 time, or 2 times or more the width of the fill cell containing the dummy polysilicon pattern. .. For example, as shown in FIG. 3C, the logical basic cells 10 are randomly arranged in the arrangeable area.

【0036】

In step S5, wiring is performed between the arranged logical basic cells based on the circuit connection information of the automatic arrangement wiring data.

【0037】

In step S16, a fill cell containing a dummy polysilicon pattern is embedded and placed adjacent to the logical basic cell between the power supply wirings in the free area of the arrangeable area. For example, if the wiring connection is not shown, as shown in FIG. 3 (D), the fill cell 11 containing the dummy polysilicon pattern is adjacent to the logical basic cell 10 between the power supply wirings in the free area of the deployable area. It is embedded and placed.

【0038】

In step S6, a fill cell containing no dummy polysilicon pattern is arranged between the power supply wirings in the remaining free area of the distributable area as in the conventional embodiment. For example, if the illustration of the wiring connection is omitted, it becomes as shown in FIG. 3 (E), and as in the conventional case, the thick fill cell 26 and the narrow fill cell 25 are arranged in an empty area where nothing is arranged. They are arranged in order and embedded. Here, there are two types of fill cell widths, but one type may be used, or three or more types may be used.

【0039】

In step S7, OPC processing is performed on the gate polysilicon pattern of the transistor as in the past, and after that, the layout data is output, and in step S8, whether the layout data is correctly constructed or various restrictions are satisfied. Verify that it is. At this time, in the present embodiment, verification is performed including a fill cell containing a dummy polysilicon pattern. However, since the dummy polysilicon wiring in the filler cell containing the dummy polysilicon pattern is fixed to the power supply potential and is not in the floating state, a pseudo error does not occur and the layout verification is performed as in the conventional case.

【0040】

In step S9, as in the past, check if there is an error in the layout verification result of step S8, and if there is an error, return to step S4 for relocation wiring, and if there is no error, proceed to step S10 and display the layout data. EB processing is performed and the layout design process is completed.

【0041】

As described above, in the layout design method of the semiconductor integrated circuit of the present embodiment, the logic basic cell or the fill cell containing the dummy polysilicon pattern is always arranged adjacent to the automatically arranged and wired logic basic cell. Therefore, the adjacent distance between the gate polysilicon pattern of the transistor in the logic basic cell and the pattern of the gate polysilicon or dummy polysilicon wiring of other transistors is within a certain range, and the logic basic cell is automatically arranged. In the OPC processing after wiring, the calculation amount of the OPC processing is reduced, the processing time of the OPC processing is shortened, the performance of the transistor after manufacturing can be adjusted to the design value, and the occurrence rate of defective products in the manufacturing process is kept low. be able to.

【0042】

Further, by using the fill cell containing the dummy polysilicon pattern, it is not necessary to arrange the dummy polysilicon pattern on the outer periphery of the internal logic portion of the logic basic cell, the cell area of the basic cell does not increase, and the layout of the semiconductor integrated circuit is laid out. The area does not increase.

【0043】

In the layout design method of the semiconductor integrated circuit of the present embodiment, it has been described that the dummy polysilicon wiring of the filler cell containing the dummy polysilicon pattern is connected to one of the pair of power supply wirings 14 and 15. However, the description is not limited to this, and various modifications are possible, and the same effect can be achieved. For example, FIG. 4 is a plan view showing a pattern configuration example of a fill cell containing a dummy polysilicon pattern used in these modifications.

【0044】

Referring to FIG. 4, the dummy polysilicon patterned fill cell used in these modifications comprises a pair of dummy polysilicon wirings 12, 12'and a pair of contacts 13. A pair of dummy polysilicon wirings 12, 12'are wired between the pair of power wirings 14, 15 by a layer of gate polysilicon in the width direction of the power wiring, respectively, and a pair of contacts 13 are a pair. A pair of power supply wirings 14 and 15 are individually interconnected to the dummy polysilicon wirings 12 and 12'. Further, a pair of dummy polysilicon wirings 12, 12'are wired in a straight line in the modified example of FIG. 4 (A), and are wired in parallel in the modified example of FIG. 4 (B). In the modified example of FIG. 4 (C), the wiring is alternately arranged in parallel in a comb shape.

【0045】

Further, in the layout design method of the semiconductor integrated circuit of the present embodiment, the fill cell containing the dummy polysilicon pattern is embedded and arranged between the power supply wirings in the arrangement prohibited area, but the dummy polysilicon adjacent to the region boundary of the arrangement prohibited area is described. As in the conventional case, a fill cell that does not contain a dummy polysilicon pattern may be arranged except for the fill cell with a pattern, and the same effect can be obtained.

【0046】

[Effect of the invention]

As described above, in the layout design method of the semiconductor integrated circuit according to the present invention, the logical basic cell or the fill cell containing the dummy polysilicon pattern is always arranged adjacent to the automatically arranged and wired logical basic cell, and the logical basic cell is always arranged. The adjacent distance between the gate polysilicon pattern of the inner transistor and the gate polysilicon or dummy polysilicon wiring pattern of the other transistor falls within a certain range. Therefore, in the OPC processing after the automatic placement and routing of the logical basic cell, the calculation amount of the OPC processing is reduced, the processing time of the OPC processing is shortened, the performance of the transistor after manufacturing can be adjusted to the design value, and the manufacturing process. The incidence of defective products can be kept low.

【0047】

Further, by using the fill cell containing the dummy polysilicon pattern, it is not necessary to arrange the dummy polysilicon pattern on the outer periphery of the internal logic part of the logic basic cell, the cell area of the basic cell does not increase, and the layout of the semiconductor integrated circuit is laid out. It has the effect of not increasing the area.

[Simple explanation of drawings]

FIG. 1 is a flow chart showing an embodiment of the layout design method of the present invention.

FIG. 2 is a plan view showing a pattern configuration of a fill cell containing a dummy polysilicon pattern used in the layout design method of FIG.

FIG. 3 is an explanatory diagram for specifically explaining the arrangement and wiring process in the layout design method of FIG. 1.

FIG. 4 is a plan view showing a pattern configuration example of a fill cell containing a dummy polysilicon pattern used in a modified example of the layout design method of FIG.

FIG. 5 is a plan view showing an example of a fill cell pattern configuration in a conventional layout design method for a semiconductor integrated circuit.

FIG. 6 is a flow chart showing a procedure example in the layout design method of the semiconductor integrated circuit of FIG.

FIG. 7 is an explanatory diagram for specifically explaining the arrangement and wiring process in the layout design method of FIG.

FIG. 8 is a plan view showing an example of a pattern configuration of basic cells in another conventional layout design method.

[Explanation of symbols]

Ten Logical basic cell 11 Fill cell with dummy polysilicon pattern 12 Dummy polysilicon wiring 13 Contact 14,15,14', 15'Power supply wiring 16 Cell outer frame 17 N well 18 P well 19 Via 25,26 Fill cell S1 ~ S16 Step