Data processing system, data processor, external device, and data transmission method

The present invention relates to a data processing system, a data processing device, an external device, and a data transmission method that transmit data to and from an external device using at least a serial interface. Regarding.

Conventionally, a data processing device to which a memory card containing a storage medium such as a flash memory is connected is known. A data processing device of this type and a memory card connected to the data processing device will be described with reference to the drawings.

As shown in FIG. 11, the data processing device 100 includes a data processing unit 101, a register 102, a host-side serial interface circuit 103, and a host-side controller 104. Further, the memory card 110 includes a memory 111, a register 112, a card-side serial interface circuit 113, and a card-side controller 114.

The data processing unit 101 of the data processing device 100 reads the data stored in the memory card 110, performs various data processing, performs various data processing, and generates data to be written in the memory card 110. That is, the data processing unit 101 serves as a data processing circuit for various devices that use the memory card 110.

The register 102 is a buffer between the data processing unit 101 and the host-side serial interface 103. That is, when the data processing unit 101 supplies data to the host-side serial interface circuit 103, the data processing device 100 stores the temporary data in the register 102 and then supplies the data to the host-side serial interface circuit 103. Similarly, when the data processing device 100 supplies data from the host-side serial interface circuit 103 to the data processing unit 101, the data processing device 100 stores the temporary data in the register 102 and then supplies the data to the data processing unit 101.

The host-side serial interface circuit 103 converts the data supplied from the data processing unit 101 via the register 102 and the command supplied from the card-side controller 114 into serial signals and supplies them to the memory card 110. Further, the host-side serial interface circuit 103 converts the serial signal data and commands supplied from the memory card 110 into parallel signals and supplies them to the data processing unit 101 and the card-side controller 114.

Further, the host-side serial interface circuit 103 supplies a data and command synchronization signal (CLK) and a chip select signal (CS) to the memory card 110. Further, the host-side serial interface circuit 103 acquires a busy signal (BUSY) and an interrupt signal (INTERRUPT) supplied from the memory card 110.

The host-side controller 104 controls the data processing operation of the data processing unit 101 and the transmission operation of each data of the host-side serial interface circuit 103. Further, the host-side controller 104 supplies a command that is a control command to the memory card 110 to the memory card 110 via the register 112.

On the other hand, the memory 111 of the memory card 110 is composed of, for example, a flash memory or the like, and stores the data supplied from the data processing unit 101.

The register 112 is a buffer between the memory 111 and the card-side serial interface circuit 113. That is, when the memory 111 writes the data from the data processing device 100, the memory card 110 supplies the data to be written to the memory 111 after storing the temporary data in the register 102. Similarly, when the data processing device 100 reads data from the memory 111, the memory card 110 supplies the data to be read after temporarily storing the temporary data in the register 102 to the card-side serial interface circuit 113. This register 112 is a circuit that functions as a page buffer of a flash memory.

Based on the control of the card-side controller 114, the card-side serial interface circuit 113 converts the parallel signal data supplied from the memory 111 and the command supplied from the card-side controller 114 into serial signals and supplies the data to the data processing device 100. To do. Further, the card-side serial interface circuit 113 converts the serial signal data and commands supplied from the data processing device 100 into parallel signals and supplies them to the memory 111 and the card-side controller 114.

Further, the card-side serial interface circuit 113 acquires a data and command synchronization signal (CLK) and a chip select signal (CS) from the data processing device 100. Furthermore, the card-side serial interface circuit 113 supplies a busy signal (BUSY) and an interrupt signal (INTERRUPT) to the data processing device 100.

The card-side controller 114 controls the data storage operation, read operation, erase operation, and the like of the memory 111 based on commands and the like supplied from the data processing device 100. Further, the card-side controller 114 controls the transmission operation of each data of the card-side serial interface circuit 113. Further, the host-side controller 104 acquires a busy signal or an interrupt signal, which is a status signal of the memory card 110, from the memory card 110.

Data transmission between the data processing device 100 and the memory card 110 as described above is performed via a transmission line provided between the host-side serial interface circuit 103 and the card-side serial interface circuit 113.

Between the card-side serial interface circuit 113 of the data processing device 100 and the card-side serial interface circuit 113 of the memory card 110, there are five signal lines, a CLK line, a CS line, a DT line, a BUSY line, and an INT line. It is provided.

Data processed by the data processing unit 101, which is the main data, and written to the memory 111 and data read from the memory 111 to the data processing unit 101 are transmitted to the DT line. Further, a command that is a control command supplied from the data processing device 100 to the memory card 110 and a command supplied from the memory card 110 to the data processing device 100 are transmitted to the DT line. That is, the main data and commands are bidirectionally transmitted as serial signals to the DT line.

In the CLK line, the main data transmitted to the DT line described above and the synchronization signal of the command are supplied from the data processing device 100 to the memory card 110.

A so-called chip select signal is supplied from the data processing device 100 to the memory card 110 to the CS line. This chip select signal indicates that the above-mentioned main data, command and synchronization signals are valid, for example, during a high period.

A busy signal indicating that the memory card 110 is processing is transmitted to the BUSY line. For example, when the memory card 110 is performing the writing process and the access from the data processing device 100 is prohibited, this busy signal is supplied from the memory card 110 to the data processing device 100.

An interrupt signal indicating an interrupt from the memory card 110 to the data processing device 100 is supplied from the memory card 110 to the data processing device 100 to the INT line.

A time chart of various signals transmitted to such a transmission line is shown in FIG. A case of reading the data stored in the memory card 110 will be described using the time chart shown in FIG.

First, time t₁₁The data processing device 100 supplies the chip select signal to the memory card 110 via the CS line. The data processing device 100 supplies a synchronization signal together with the chip select signal via the CLK line. By acquiring this chip select signal, the memory card 110 prepares to acquire a command supplied from the data processing device 100. Then, when the data processing device 100 supplies this chip select signal, it supplies a command indicating a read instruction and its address to the memory card 110 via the DT line.

When the data processing device 100 finishes supplying this read command or the like, the time t₁₂In, this command and the supply of the synchronization signal are stopped. When the memory card 110 finishes acquiring the command, it supplies a busy signal to the data processing device 100 in order to perform control based on the supplied command. That is, the memory card 110 controls to read the main data of the specified address from the memory 111 to the register 112. At this time, the data processing device 100 does not stop the supply of the chip select signal.

When the memory card 110 reads the main data into the register 112, the time t₁₃The supply of busy signals is stopped at. That is, it notifies the data processing device 100 of the ready state indicating that it is ready to transmit the main data.

When the data processing device 100 learns that the supply of the busy signal has stopped, it determines that the control based on the command supplied by the memory card 110 has ended, and the time t₁₄The synchronization signal is supplied to the memory card 110. Then, the memory card 110 transmits the main data to the data processing device 100 via the DT line.

Then, when the memory card 110 ends the transmission of the main data, the data processing device 100 sets the time t.₁₅In, the supply of the synchronization signal and the chip select signal is stopped.

When the internal state of the memory card 110 changes due to the result of this read processing or the like, the memory card 110 is set to the time t.₁₆As shown in, an interrupt signal indicating an interrupt is supplied to the data processing device 100 via the INT line. When this interrupt signal is supplied, the data processing device 100 acquires this interrupt factor from the memory card 110, and therefore supplies a predetermined command to the memory card 110 together with the chip select signal.

As described above, the data processing device 100 includes a DT line for transmitting main data and commands, a CLK line for supplying a synchronization signal, a CS line for supplying a chip select signal, a BUSY line for acquiring a busy signal, and an interrupt signal. An INT line to be acquired is provided to realize data transmission with the memory card 110.

By the way, when considering the miniaturization of the memory card 110, which is the external storage device described above, it is necessary to reduce the number of signal lines between the data processing device 100 and the memory card 110.

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 60-51046</text></patcit>

<p> The present invention has been made in view of such circumstances, and by providing a reserve terminal which is a spare terminal in addition to the data terminal for serial communication of the main data, the main data can be serially communicated. , An object of the present invention is to provide a data processing system, a data processing device, an external device, and a data transmission method capable of adding other functions in combination with a reserve terminal.</p>

<p> The data processing system according to the present invention is a data processing system including an external device and a data processing device that transmits data. The data processing device generates a command to the external device and receives data from the external device. It has a plurality of terminals for communicating with the external device, and the external device has a substantially card shape, a controller for receiving a command from the data processing device, and a plurality of terminals for communicating with the data processing device. However, the terminal of the external device has a data terminal for the external device and the data processing device to serially communicate the main data, and a reserve terminal which is a spare terminal.</p><p> The data processing device according to the present invention is a data processing device that transmits data to an external device, and is used to generate a command to the external device and to communicate with a controller that receives data from the external device and the external device. The plurality of terminals have terminals, and the plurality of terminals have a data terminal for serially communicating main data with the external device and a reserve terminal which is a spare terminal.</p><p> The external device according to the present invention is an external device that transmits data to and from a data processing device, and includes a substantially card shape, a controller that receives commands from the data processing device, and a plurality of terminals for communicating with the data processing device. The terminal has a data terminal for the external device and the data processing device to serially communicate main data, and a reserve terminal which is a spare terminal.</p><p> The data transmission method according to the present invention is a data transmission method in which data is transmitted between an external device and a data processing device, in which the data processing device generates a command to the external device and receives data from the external device and a controller. It has a plurality of terminals for communicating with the external device, and the external device has a substantially card shape, a controller for receiving a command from the data processing device, and a plurality of terminals for communicating with the data processing device. However, the terminal of the external device has a data terminal for serial communication of the main data between the external device and the data processing device, and a reserve terminal which is a spare terminal, and is generated by the data processing device. The main data is serially communicated between the external device and the data processing device in response to the command.</p>

<p> As described above, since the present invention has a data terminal for serial communication of the main data and a reserve terminal which is a spare terminal, the main data is serially communicated, and further in combination with the reserve terminal. Functions can be added.</p>

Hereinafter, the data processing device according to the present invention, the data processing device used in the data transmission method, and the memory card which is an external storage device used in the data processing device will be described with reference to the drawings.

First, the data processing device constituting the data processing system will be described in the present invention. As shown in FIG. 1, the data processing device 10 includes a data processing unit 11, a register 12, a host-side serial interface circuit 13, and a host-side serial interface circuit 13. It is equipped with a host side controller 14. Further, the memory card 20 is a storage medium having a card-like appearance, and is connected to the data processing device 10 to be used as an external storage device. The memory card 20 includes a memory 21, a register 22, a card-side serial interface circuit 23, and a card-side controller 24.

The data processing unit 11 of the data processing device 10 reads the data stored in the memory card 20 and performs various data processing, performs various data processing, and generates data to be written in the memory card 20. The data processing unit 11 serves as a data processing circuit for an audiovisual device such as a computer device using a memory card 20, a digital audio signal recording / playback device, or a camera device.

The register 12 is a buffer between the data processing unit 11 and the host-side serial interface 13. That is, when the data processing device 10 supplies data from the data processing unit 11 to the host-side serial interface circuit 13, the data processing device 10 temporarily stores the data in the register 12 and then supplies the data to the host-side serial interface circuit 13. Similarly, when the data processing device 10 supplies data from the host-side serial interface circuit 13 to the data processing unit 11, the data processing device 10 temporarily stores the data in the register 12 and then supplies the data to the data processing unit 11.

The host-side serial interface circuit 13 converts the data supplied from the data processing unit 11 via the register 12 and the command supplied from the card-side controller 24 into a serial signal and supplies the data to the memory card 20. Further, the host-side serial interface circuit 13 converts the serial signal data and commands supplied from the memory card 20 into parallel signals and supplies them to the data processing unit 11 and the card-side controller 24.

Further, the host-side serial interface circuit 13 supplies various data, command synchronization signals (CLK), and the like to the memory card 20. Further, the host-side serial interface circuit 13 is supplied from the memory card 20 and acquires a STATUS signal indicating the operating state of the memory card 20.

The host-side controller 14 controls the data processing operation of the data processing unit 11 and the transmission operation of each data of the host-side serial interface circuit 13. Further, the host-side controller 14 supplies a command that is a control command to the memory card 20 to the memory card 20 via the register 22.

On the other hand, the memory 21 of the memory card 20 is composed of, for example, a flash memory or the like, and stores the data supplied from the data processing unit 11.

The register 22 is a buffer between the memory 21 and the card-side serial interface circuit 23. When the memory 21 writes data from the data processing device 10, the data to be written after storing temporary data in the register 12 is stored in the memory 21. Supply. Similarly, when the data processing device 10 reads data from the memory 21, the data to be read after temporarily storing the temporary data in the register 12 is supplied to the card-side serial interface circuit 23. That is, the register 22 is a circuit that functions as a so-called page buffer of the flash memory.

The card-side serial interface circuit 23 converts the parallel signal data supplied from the memory 21 and the command supplied from the card-side controller 24 into serial signals under the control of the card-side controller 24 and supplies the data to the data processing device 10. .. Further, the card-side serial interface circuit 23 converts the serial signal data and commands supplied from the data processing device 10 into parallel signals and supplies them to the memory 21 and the card-side controller 24.

Further, the card-side serial interface circuit 23 acquires various data, command synchronization signals (CLK), and the like from the data processing device 10. Further, the card-side serial interface circuit 23 supplies a status signal to the data processing device 10.

The card-side controller 24 controls the data storage operation, read operation, erase operation, and the like of the memory 21 based on commands and the like supplied from the data processing device 10. Further, the card-side controller 24 controls the transmission operation of each data of the card-side serial interface circuit 23. Further, the host-side controller 14 controls to supply the status signal to the memory card 20 to the memory card 20.

Data transmission between the data processing device 10 and the memory card 20 as described above is performed via a transmission line provided between the host-side serial interface circuit 13 and the card-side serial interface circuit 23.

Three signal lines, a CLK line 31, a control line 32, and a DT line 33, are provided between the card-side serial interface circuit 23 of the data processing device 10 and the card-side serial interface circuit 23 of the memory card 20. There is.

The data processed by the data processing unit 11 which is the main data and written to the memory 21 and the data read from the memory 21 to the data processing unit 11 are transmitted to the DT line 33. A command that is a control command supplied from the data processing device 10 to the memory card 20 and a command supplied from the memory card 20 to the data processing device 10 are transmitted to the DT line 33. That is, the main data and commands are bidirectionally transmitted as serial signals to the DT line 33.

Further, a resistor 33a having one end grounded is attached to the DT line 33. This resistor 33a is a so-called pull-down resistor, and when the signal is not transmitted / received by the DT line 33 between the host side serial interface circuit 13 and the card side serial interface circuit 23, the signal level of the DT line 33 is low. Become a level. In other words, when the signal is not transmitted or received by the DT line 33, the signal level of the DT line 33 becomes a constant level determined by the resistance value of the resistor 33a or the like.

Here, a so-called pull-down resistor is adopted as the resistor 33a so that the signal level of the DT line 33 becomes a low level when the signal is not transmitted / received by the DT line 33, but the so-called pull-up is performed as the resistor 33a. A resistor may be adopted so that the signal level of the DT line 33 becomes a high level when the signal is not transmitted or received by the DT line 33.

On the CLK line 31, the main data transmitted to the DT line 33 described above and the synchronization signal of the command are transmitted from the data processing device 10 to the memory card 20.

A control signal is transmitted from the data processing device 10 to the memory card 20 on the control line 32. The main data and commands described above are transmitted during the period during which this control signal is supplied, for example, during the period during which it is high.

Here, in addition to the main data and commands, a STATUS signal indicating the operating state of the memory card 20 is supplied from the memory card 20 to the data processing device 10 to the DT line 33 described above. The status signal from the memory card 20 is supplied during a period during which the main data and commands are not transmitted to the DT line 33, that is, during a period during which no control signal is supplied, for example, during a low period. This status signal includes a busy signal indicating that the memory card 20 is processing. For example, when the memory card 20 is performing the writing process and the access from the data processing device 10 is prohibited, the busy signal is supplied from the memory card 20 to the data processing device 10.

Further, the status signal includes an interrupt signal indicating an interrupt from the memory card 20 to the data processing device 10. For example, when an interrupt instruction is requested from the memory card 20 to the data processing device 10, this interrupt signal is supplied. The busy signal and the interrupt signal are examples, and any signal may be used as a status signal as long as it is a signal indicating the operating state of the memory card 20.

In this way, in order to supply the status signal during the period when the control signal is not supplied, the memory card 20 may be provided with an output circuit as shown in FIG.

The output circuit 25 of the memory card 20 is provided between the card-side serial interface circuit 23 and the input / output terminals of the DT line 33, and includes an input buffer 26, an output buffer 27, a changeover switch 28, and an or circuit 29.

The input buffer 26 is connected to the DT line 33, a serial signal supplied from the data processing device 10 is input, and this serial signal is supplied to the card-side serial interface circuit 23.

The output buffer 27 outputs a serial signal, a busy signal, and an interrupt signal supplied via the changeover switch 28 to the DT line 33.

Further, the busy signal and the interrupt signal supplied from the card-side controller 24 are ORed by the or circuit 23 and supplied to the terminal 28b of the changeover switch 28. Further, the serial signal supplied from the card-side serial interface circuit 23 is supplied to the terminal 28a of the changeover switch 28.

The changeover switch 28 is switched to the terminal 28a side when the control signal is high. When the changeover switch 28 is switched to the terminal 28a side, the serial signal from the card side serial interface circuit 23 is supplied to the output buffer 27. Further, the changeover switch 28 is switched to the terminal 28b side when the control signal is low. When the changeover switch 28 is switched to the terminal 28b side, status signals such as a busy signal and an interrupt signal from the card side controller 24 are supplied to the output buffer 27.

A time chart of various signals transmitted to such a transmission line is shown in FIG. A case of reading the main data stored in the memory card 20 will be described using the time chart shown in FIG.

First, time t₂₁In, the data processing device 10 supplies the control signal to the memory card 20 via the control line 32. The memory card 20 prepares to acquire a command supplied from the data processing device 10 by acquiring this control signal. The data processing device 10 supplies this control signal, and also supplies a command or the like indicating a read instruction to the memory card 20 via the DT line 33. Further, the data processing device 10 supplies a synchronization signal to the memory card 20 via the CLK line 31 together with this command and the like.

When the data processing device 10 finishes supplying this read command or the like, the time t₂₂In, the supply of the command, control signal and synchronization signal is stopped. The synchronization signal is at this time t₂₂It is not necessary to stop the supply at.

When the memory card 20 finishes acquiring the command, the memory card 20 supplies a busy signal to the data processing device 10 via the DT line 33 in order to perform control based on the supplied command. Since the data processing device 10 has not supplied the control signal at this point, it can be determined that the signal supplied from the memory card 20 is a busy signal. When the memory card 20 supplies a busy signal, the memory card 20 reads the main data of the specified address from the memory 21 to the register 22.

When the memory card 20 reads the main data into the register 22, the time t₂₃In, the supply of the busy signal is stopped via the DT line 33. That is, it notifies the data processing device 10 of the ready state indicating that it is ready to supply the main data.

Data processing device 10 is at time t₂₄When it is known that the busy signal supply has stopped, it is determined that the control based on the command supplied by the memory card 20 has ended, and the control signal and the synchronization signal are supplied. Based on the supply of the control signal, the memory card 20 synchronizes the main data with the supplied synchronization signal via the DT line 33 and transmits the main data to the data processing device 10.

When the memory card 20 finishes transmitting the main data, the data processing device 10 sets the time t.₂₅The supply of the synchronization signal and the control signal is stopped at.

If the internal state of the memory card 20 changes due to the result of this read processing or the like, the memory card 20 is set to the time t as necessary.₂₆As shown in the above, an interrupt signal indicating an interrupt is supplied to the data processing device 10 via the DT line 33. Since the data processing device 10 does not supply the control signal, it can be determined that the signal supplied from the memory card 20 is an interrupt signal, and when this interrupt signal is supplied, for example, this interrupt factor is transmitted to the memory card 20. A control signal is supplied to obtain from, and a corresponding command is supplied.

As described above, in the data processing device 10 and the memory card 20, the number of signal lines can be reduced by transmitting the status signal from the memory card 20 using the DT line 33. Therefore, it is not necessary to specially provide a signal line for a busy signal or an interrupt signal, and reliable data transmission can be performed with a simple configuration. In addition, when data is transmitted between the data processing device and the memory card without providing an interrupt signal, polling must always be performed at regular time intervals, but this data processing device 10 requires polling. There is no.

By the way, in the case of data transmission between the data processing device 10 and the memory card 20 as described above, the content of the command supplied from the data processing device 10 to the memory card 20 or the content of the command supplied from the memory card 20 to the data processing device 10 is supplied. The content of the command is predetermined by the host side controller 14 and the card side controller 24. For example, a write command, a read command, an erase command, and the like are predetermined. When these commands are transmitted via the DT line 33, the order of the data, commands, or status signals subsequently transmitted to the DT line 33 is always determined.

Specifically, when a write command is transmitted from the data processing device 10 to the memory card 20, the main data to be written to the memory card 20 after this write command is transmitted from the data processing device 10 to the memory card 20. Be transmitted. The memory card 20 to which the write command and the main data are transmitted outputs a busy signal to the data processing device 10 while the writing process of the main data is being performed, and when the writing process of the main data is completed, the ready signal is data. Output to processing device 10. When a read command is transmitted from the data processing device 10 to the memory card 20, the memory card 20 performs a read process of the main data according to the read command. While the read process is being performed, the memory card 20 outputs a busy signal to the data processing device 10, and when the read process is completed, the memory card 20 outputs a ready signal to the data processing device 10. After the data processing device 10 receives the ready signal, the main data is transmitted from the memory card 20 to the data processing device 10, whereby the main data is read out.

Therefore, as the second data transmission method, a case where the contents of the data transmitted by the DT line 33 and the order thereof are predetermined by commands will be described below.

In this second data transmission method, the state of the data to be transmitted on the DT line 33 is set by switching the control signal. That is, by switching the control signal, the state of the data to be transmitted is determined and the data is transmitted.

The state of the data transmitted by the DT line 33 is set as follows. First, the state in which no control command, that is, a command is supplied from the data processing device 10 to the memory card 20 and the memory card 20 is not performing any processing is set as the "state 0" as the initial state. Subsequently, the state in which commands are being supplied from the data processing device 10 to the memory card 20, for example, the state in which a write command, a read command, an erase command, or the like is being supplied via the DT line 33 is state 1. And. After that, it changes to "state 2" and "state 3" in which processing is performed according to the command supplied in "state 1", and returns to "state 0" after "state 3".

Then, the control signal switches between such "state 0" and "state 3" states. That is, in "state 0", this control signal is low, and when the control signal becomes high from this "state 0" state, it switches to "state 1". Then, when the control signal becomes low from the state of "state 1", it switches to "state 2". Then, when the control signal becomes high from the state of "state 2", it switches to "state 3". Finally, when the control signal becomes low from the state of "state 3", it switches to "state 0".

By switching the control signal in this way, the content of the data transmitted by the DT line 33 is switched. Then, the data processing device 10 and the memory card 20 determine the contents of the data to be transmitted to the next "state 2" and "state 3" according to the contents of the command transmitted in the "state 1", and each state. Perform processing according to.

Specifically, for example, when reading the main data from the memory card 20, the state 1 is first set, and the read command is transmitted from the data processing device 10 to the memory card 20. Next, the state becomes "state 2", and the main data is read by the memory card 20 in response to the read command. During this process, a busy signal is transmitted from the memory card 20 to the data processing device 10, and when the process is completed, a ready signal is transmitted from the memory card 20 to the data processing device 10. Then, when the ready signal is detected by the data processing device 10, the state becomes "state 3", and the main data read from the memory card 20 is transmitted from the memory card 20 to the data processing device 10 via the DT line 33. Then, when the transmission of the main data is completed, the process returns to "state 0".

Alternatively, for example, when writing the main data to the memory card 20, the state 1 is first set, and the write command is transmitted from the data processing device 10 to the memory card 20. Next, in "state 2", the main data to be written to the memory card 20 is transmitted from the data processing device 10 to the memory card 20 via the DT line 33. Next, the state becomes "state 3", and the main data is written by the memory card 20 in response to the write command. During this process, a busy signal is transmitted from the memory card 20 to the data processing device 10, and when the process is completed, a ready signal is transmitted from the memory card 20 to the data processing device 10. Then, when the ready signal is detected by the data processing device 10, the process returns to state 0.

Alternatively, for example, when erasing the main data written in the memory card 20, first, in the "state 1", the erasing command is transmitted from the data processing device 10 to the memory card 20. Next, the state becomes "state 2", and the main data is erased by the memory card 20 in response to the erase command. During this process, a busy signal is transmitted from the memory card 20 to the data processing device 10, and when the process is completed, a ready signal is transmitted from the memory card 20 to the data processing device 10. Then, when the ready signal is detected by the data processing device 10, the process returns to state 0.

In this way, the second data transmission method for controlling the state of data transmission by switching the control signal according to the data transmitted to the DT line 33 is further described with reference to the time charts of FIGS. 4 and 5. This will be described in detail. Here, the time chart shown in FIG. 4 is an example of a time chart when the data processing device 10 reads out the main data written in the memory card 20. The time chart shown in FIG. 5 is an example of a time chart when the data processing device 10 writes the main data to the memory card 20.

First, reading of the main data will be described with reference to FIG.

When no data is transmitted between the data processing device 10 and the memory card 20, the control signal is low, which is the initial state of "state 0". Then, the process related to reading the main data is started from the initial state of this state 0.

Time to start the process related to reading the main data t₃₁In, the data processing device 10 switches the control signal supplied to the memory card 20 via the control line 32 from low to high. Therefore, the state of the data transmitted to the DT line 33 is switched from "state 0" to "state 1". By acquiring this control signal, the memory card 20 determines that the status has changed from "state 0" to "state 1", and prepares to acquire a command supplied from the data processing device 10. Then, in this state 1, the data processing device 10 supplies a read command to the memory card 20 via the DT line 33, and supplies the synchronization signal to the memory card 20 via the CLK line 31. .. Here, the memory card 20 determines the content of the data transmitted via the DT line 33 in the later "state 2" and "state 3" by acquiring the read command in this "state 1" state. To do.

The data processing device 10 is at the time when the supply of the read command is completed.₃₂The control signal is switched from high to low at. That is, it switches from "state 1" to "state 2".

When the "state 2" is reached, the memory card 20 performs processing based on the read command supplied in the "state 1", specifically, the main data of the address specified by the read command is transmitted from the memory 21 to the register 22. Performs the process of reading to. During this process, the memory card 20 supplies a busy signal as a status signal to the data processing device 10 via the DT line 33. That is, in the "state 2", the memory card 20 first outputs a busy signal as a status signal. At this time, since the command supplied to the memory card 20 in the data processing device 10 is a read command and the current state is "state 2", the signal output from the memory card 20 is a status signal. Judge.

After that, when the reading of the main data to the register 22 is completed, the memory card 20 is set to the time t when the reading of the main data to the register 22 is completed.₃₃In, the output of the busy signal as a status signal is stopped via the DT line 33, and the output of the ready signal indicating that the main data is ready to be supplied to the data processing device 10 is started. That is, in the "state 2", the memory card 20 outputs a ready signal as a status signal when the reading of the main data to the register 22 is completed.

In this example, in the "state 2", when the signal output from the memory card 20 via the DT line 33 is high, it is regarded as a busy signal, and when it is low, it is regarded as a ready signal. In this "state 2", the data processing device 10 outputs a signal from the memory card 20 because the command supplied to the memory card 20 is a read command and the current state is "state 2". Can be determined to be a status signal. Therefore, the data processing device 10 can detect that the signal has been switched from the busy signal to the ready signal simply by switching the signal output from the memory card 20 via the DT line 33 from high to low. ..

When the data processing device 10 receives the ready signal from the memory card 20, it determines that the processing of the memory card 20 based on the read command is completed. Then, the time t when it is determined that the processing of the memory card 20 based on the read command is completed.₃₄The control signal is switched from low to high at. That is, it switches from "state 2" to "state 3".

Then, when the "state 3" is reached, the memory card 20 transmits the main data read to the register 22 in the "state 2" to the data processing device 10 via the DT line 33. After that, the time when the transmission of the main data from the memory card 20 to the data processing device 10 is completed t₃₅In, the data processing device 10 stops the supply of the synchronization signal and switches the control signal from high to low. That is, the state is returned from the "state 3" in which the main data is transmitted to the "state 0" in the initial state.

If the internal state of the memory card 20 changes due to the influence of the read processing as described above and it becomes necessary to perform some interrupt processing, the memory card 20 is set to the time t.₃₆As shown in the above, an interrupt signal indicating an interrupt in the state 0 is supplied to the data processing device 10 via the DT line 33. Here, the data processing device 10 is set in advance so that when a signal is supplied from the memory card 20 via the DT line 33 in the state 0, the signal is determined to be an interrupt signal. As a result, this signal is determined by the data processing device 10 to be an interrupt signal. The data processing device 10 that has received the interrupt signal performs necessary processing based on the interrupt signal.

Next, writing the main data will be described with reference to FIG.

When no data is transmitted between the data processing device 10 and the memory card 20, the control signal is low, which is the initial state of "state 0". The process related to writing the main data is started from the initial state of this state 0.

Time to start the process related to writing the main data t₄₁In, the data processing device 10 switches the control signal supplied to the memory card 20 via the control line 32 from low to high. Therefore, the state of the data transmitted to the DT line 33 is switched from "state 0" to "state 1". By acquiring this control signal, the memory card 20 determines that the status has changed from "state 0" to "state 1", and prepares to acquire a command supplied from the data processing device 10. Then, in this state 1, the data processing device 10 supplies a write command to the memory card 20 via the DT line 33, and supplies the synchronization signal to the memory card 20 via the CLK line 31. .. Here, the memory card 20 determines the content of the data transmitted via the DT line 33 in the later "state 2" and "state 3" by acquiring the write command in this "state 1" state. To do.

The data processing device 10 is at the time when the supply of the write command is completed.₄₂In, the control signal is switched from high to low. That is, it switches from "state 1" to "state 2".

In the "state 2", the data processing device 10 transmits the main data to be written to the memory card 20 to the memory card 20 via the DT line 33, and the time when the transmission of this main data to the memory card 20 is completed. t₄₃The control signal is switched from low to high at. That is, it switches from "state 2" to "state 3".

When "state 3" is reached, the memory card 20 is processed based on the write command supplied in "state 1", specifically, the main transmission from the data processing device 10 in "state 2". Performs a process of writing data to the memory 21. During this process, the memory card 20 supplies a busy signal as a status signal to the data processing device 10 via the DT line 33. That is, in the "state 3", the memory card 20 first outputs a busy signal as a status signal. At this time, since the command supplied to the memory card 20 in the data processing device 10 is a write command and the current state is "state 3", the signal output from the memory card 20 is a status signal. Judge.

After that, when the writing of the main data to the register 22 is completed, the memory card 20 is set to the time when the writing of the main data to the register 22 is completed.₄₄In, as a status signal, the output of the busy signal is stopped, and the output of the ready signal indicating that the writing of the main data is completed is started. That is, in the "state 3", the memory card 20 outputs a ready signal as a status signal when the writing of the main data to the register 22 is completed.

In this example, in the "state 3", when the signal output from the memory card 20 via the DT line 33 is high, it is regarded as a busy signal, and when it is low, it is regarded as a ready signal. In this "state 3", the data processing device 10 receives a signal output from the memory card 20 because the command supplied to the memory card 20 is a write command and the current state is "state 3". It can be determined that it is a status signal. Therefore, the data processing device 10 can detect that the signal has been switched from the busy signal to the ready signal simply by switching the signal output from the memory card 20 via the DT line 33 from high to low. ..

When the data processing device 10 receives the ready signal from the memory card 20, it determines that the processing of the memory card 20 based on the write command is completed. Then, the time t when it is determined that the processing of the memory card 20 based on the write command is completed.₄₅In, the data processing device 10 stops the supply of the synchronization signal and switches the control signal from high to low. That is, the state is returned from "state 3", which is the state in which the main data is being written, to "state 0", which is the initial state.

If the internal state of the memory card 20 changes due to the influence of the writing process as described above and it becomes necessary to perform some interrupt processing, the memory card 20 is set to the time t.₄₆As shown in the above, an interrupt signal indicating an interrupt in the state 0 is supplied to the data processing device 10 via the DT line 33. Here, the data processing device 10 is set in advance so that when a signal is supplied from the memory card 20 via the DT line 33 in the state 0, the signal is determined to be an interrupt signal. .. As a result, this signal is determined by the data processing device 10 to be an interrupt signal. Then, the data processing device 10 that has received the interrupt signal performs necessary processing based on the interrupt signal.

As described above, in the data processing device 10 and the memory card 20 to which the present invention is applied, the control signal is switched to determine the content of the data to be transmitted to the DT line 33, whereby the command is commanded by the DT line 33. It is possible to transmit not only the main data but also the status signal and interrupt signal. Therefore, the number of signal lines between the data processing device 10 and the memory card 20 can be reduced. Therefore, it is not necessary to specially provide a signal line for a busy signal or an interrupt signal, and reliable data transmission can be performed with a simple configuration. Further, the overhead of switching the data to be transmitted to the DT line 33 can be reduced, and the efficiency of data transmission is improved.

In the above example, the case of the data processing device 10 and the memory card 20 has been described, but the present invention can be applied to other data processing devices instead of the memory card 20. In this case, it is necessary to set the command to be transmitted in another data processing device in advance, but not only the command to the memory card 20 but also any command can be transmitted.

Further, in the description of the second data transmission method between the data processing device 10 and the memory card 20, the contents of the transmission data of the DT line 33 switched by the control signal are described as state 0, state 1, state 2, and state 3. Although the above four patterns have been described as an example, the above four patterns may be switched to more patterns depending on the content of the command to be transmitted.

Further, in the explanation of the second data transmission method between the data processing device 10 and the memory card 20, the case where the state of the transmission data of the DT line 33 is switched by turning the control signal on and off has been described. As shown in 7, the switching may be performed by a pulse signal. Note that FIGS. 6 and 7 are time charts when a pulse signal is used as the control signal, and FIG. 6 shows the main data written in the memory card 20 by the data processing device 10 as in FIG. The time chart of the time, FIG. 7, is a time chart when the main data is written to the memory card 20 by the data processing device 10 as in FIG.

Further, the memory card 20 described above is provided with, for example, one power supply line, three ground lines, and three reserve lines in addition to the CLK line 31, control line 32, and DT line 33, for a total of 10 It has a book signal line. When three reserve lines are provided, these three reserve lines are used as DT lines to make four DT lines in combination with the previous DT line 33, and these four DT lines are used in parallel. You may try to do it. When three reserve lines are provided, these three reserve lines are used as the CLK line, control line and DT line, respectively, and combined with the previous CLK line 31, control line 32 and DT line 33, Two sets of CLK line, control line and DT line may be provided.

By the way, in the second data transmission method mentioned above, it is possible to deal with external noise and the like by transmitting an error correction code and the like together with the command and the main data transmitted on the DT line 33. However, for the control signal transmitted on the control line 31, "state 0", "state 1", "state 2", "state 3" can be achieved simply by switching from high to low or from low to high. Since it is designed to show the transition of, there is a risk of being affected by external noise.

For example, in the examples given in FIGS. 4 and 5, the control signal is set to low when state 0 and state 2, and the control signal is set to high when state 1 and state 3. Then, the distinction between "state 0" and "state 2" and the distinction between "state 1" and "state 3" are made by following the transition of those states. Therefore, if the transition of the state is not detected correctly, the memory card 20 mistakenly judges "state 0" and "state 2", or mistakenly judges "state 1" and "state 3". There is a risk that it will end up.

For example, as shown in FIG. 4, when reading the main data, if noise is added to the control signal and the memory card 20 mistakenly determines state 1 and state 3, the data processing device There is a possibility that the command sent from 10 to the memory card 20 and the main data read from the memory card 20 collide with each other on the DT line 33.

Further, as shown in FIG. 4, when the main data is read out, noise is added to the control signal, and if the memory card 20 mistakenly determines state 0 and state 2, state 2 is obtained. The busy signal or ready signal to be output when "state 0" is sent when "state 0", or the interrupt signal to be output when "state 0" is sent when "state 2". There is a possibility of chilling.

Further, as shown in FIG. 5, when writing the main data, if noise is added to the control signal and the memory card 20 mistakenly determines state 1 and state 3, the data processing device There is a possibility that the command sent from 10 to the memory card 20 and the status signal output from the memory card 20 will collide on the DT line 33. Alternatively, the data processing device 10 side waits for a ready signal from the memory card 20, the memory card 20 side waits for a command from the data processing device 10, and data transmission / reception on the DT line 33 stops. There is a possibility that it will end up.

Furthermore, as shown in FIG. 5, when writing the main data, if noise is added to the control signal and the memory card 20 mistakenly determines state 0 and state 2, data processing is performed. There is a possibility that the main data sent from the device 10 to the memory card 20 and the interrupt signal output from the memory card 20 collide with each other on the DT line 33.

In order to avoid the above problems, for example, the ready signal should be a signal in which the signal level changes repeatedly at a predetermined cycle, and the state where there is no signal output from the memory card 20 should be detected as a busy signal. Just do it. Hereinafter, an example in which the ready signal and the busy signal are detected in this way will be specifically described.

In the following description, the case of reading the main data written in the memory card 20 will be taken as an example, and the time chart of FIG. 8 and the flowcharts of FIGS. 9 and 10 will be referred to. Here, FIG. 8 is a time chart when reading the main data written in the memory card 20 as in FIG. 4, but in this example, the contents of the busy signal and the ready signal are different from the example of FIG. .. Further, FIG. 9 is a flowchart showing a processing flow on the data processing device 10 side when reading the main data written in the memory card 20, and FIG. 10 is a flowchart showing the main data written in the memory card 20. It is a flowchart which shows the flow of the process on the side of the memory card 20 when reading.

First, the processing on the data processing apparatus 10 side will be described with reference to FIGS. 8 and 9.

When reading the main data from the memory card 20, the data processing device 10 first writes a read command, which is a command for instructing the reading of the main data from the memory card 20, to the register 12. After that, as shown in step S1, the data processing device 10 sets the control signal output from the host-side serial interface circuit 13 to state 1 under the control of the host-side controller 14 (time in FIG. 8). t₅₁). Further, in this "state 1", the data processing device 10 reads a read command from the register 12 to the host-side serial interface circuit 13, attaches an error correction code or the like to the read command, and then sends the read command to the DT line. It is sent to the memory card 20 via 33.

When the transmission of the read command is completed, the data processing device 10 sets the control signal output from the host-side serial interface circuit 13 to "state 2" under the control of the host-side controller 14 (time t in FIG. 8).₅₂). In this "state 2", the data processing device 10 detects the status signal sent from the memory card 20. Then, in step S2, the data processing device 10 determines whether or not a busy signal has been detected.

At this time, the host-side serial interface circuit 13 is concerned when the signal transmitted via the DT line 33 is a substantially constant signal (hereinafter, referred to as a DC signal) with no special change in the signal level. It is determined that the DC signal is a busy signal indicating that the memory card 20 is in a state of not accepting the signal input. Further, when the signal transmitted via the DT line 33 is a signal in which the signal level changes repeatedly at a predetermined cycle (hereinafter, referred to as an AC signal), the signal is a signal of the memory card 20. It is determined that the signal is a ready signal indicating that the input is waiting.

At this time, the host-side serial interface circuit 13 only determines whether the signal transmitted via the DT line 33 is a DC signal or an AC signal. Therefore, the host-side serial interface circuit 13 not only detects the signal as a busy signal when a certain level signal is sent from the memory card 20, but also the memory card 20 stops the output of the signal. Even when it is, it is judged that the status signal is a busy signal.

Then, if a busy signal is detected in step S2, the process proceeds to step S3. In step S3, the data processing circuit 10 determines whether or not the busy signal continues for a predetermined time or longer specified in advance. If the busy signal continues for a predetermined time or longer specified in advance, it is assumed that a timeout has occurred, the process returns to step S1 and the process is repeated. That is, when the busy signal continues for a predetermined time or more specified in advance, the data processing circuit 10 determines that some error has occurred on the memory card 20 side, and returns to "state 1" again to read the command. Re-send.

On the other hand, if the busy signal has not reached a predetermined time specified in advance, the process returns to step S2 and the process is repeated. That is, the data processing circuit 10 repeats the processes of steps S2 and S3 until the status signal from the memory card 20 changes from a busy signal to a ready signal.

As will be described later, the memory card 20 is designed to stop the signal output when an error occurs. At this time, as for the signal level of the DT line 33, since the resistor 33a acting as a so-called pull-down resistor is connected to the DT line 33, the low state is maintained when the immediately preceding state is low, and the immediately preceding state is high. Sometimes it gradually changes to a low state. In any case, these states are detected by the data processing device 10 as a DC signal, that is, as a busy signal. That is, if an error occurs on the memory card 20 side, the busy signal is continued. Therefore, when an error occurs on the memory card 20 side, the occurrence of the error can be detected by the judgments in steps S2 and S3.

In other words, in the data processing device 10 and the memory card 20, when an error occurs in the memory card 20, the data processing device does not send a special signal indicating the occurrence of the error from the memory card 20 to the data processing device 10. The occurrence of an error is detected by 10.

On the other hand, when the processing of the memory card 20 is completed without any error and the memory card 20 is in a state of accepting a signal input from the outside, the status signal output from the memory card 20 is a busy signal. Changes to a ready signal (time t in Fig. 8)₅₃). Here, the ready signal is an AC signal in which the signal level is repeatedly changed at a predetermined cycle as described above. The ready signal is preferably a signal whose signal level changes at a frequency equal to or lower than the frequency of the synchronization signal so that the data processing device 10 can detect it quickly and reliably. Specifically, for example, the signal is set so that the signal level repeats inversion of high, low, high, and low at a frequency of 1/2 of the synchronization signal.

Then, in step S2, when the busy signal is no longer detected, that is, when the ready signal is detected, the process proceeds to step S4. In step S4, the data processing device 10 sets the control signal output from the host-side serial interface circuit 13 to state 3 under the control of the host-side controller 14 (time t in FIG. 8).₅₄). In this "state 3", the data processing device 10 receives the main data read from the memory card 20 by the host-side serial interface circuit 13. The main data received by the host-side serial interface circuit 13 is transferred to the data processing unit 11 via the register 12 under the control of the host-side controller 14.

When the reception of the main data read from the memory card 20 is completed, the data processing device 10 sets the control signal output from the host-side serial interface circuit 13 to low under the control of the host-side controller 14 to "state 0". (Time t in Figure 8)₅₅)。

Then, in step S5, the data processing device 10 determines whether or not the interrupt signal has been detected. Here, the interrupt signal is a signal indicating that the memory card 20 is requesting some kind of interrupt processing. When the interrupt signal is detected, the process proceeds to step S6 (time t in FIG. 8).₅₆). In step S6, the data processing device 10 sends the detected interrupt signal to the data processing unit 11, and then returns to step S1 to repeat the processing in order to perform interrupt processing according to the interrupt signal.

On the other hand, if the interrupt signal is not detected in step S5, the process proceeds to step S7. In step S7, the data processing device 10 determines whether or not there is any processing to be performed on the memory card 20, that is, whether or not there is a command to be sent to the memory card 20. Then, if there is no command to be sent to the memory card 20, the data processing device 10 returns to step S5 and repeats the process, and if there is a command to be sent to the memory card 20, returns to step S1 and sends the command. Repeat the process. That is, if there is a request for some processing to the memory card 20 before the interrupt signal is generated, for example, a request for processing to detect the internal status of the memory card 20, the process returns to step S1 and a command corresponding to the processing is sent. I do.

Next, the processing on the memory card 20 side will be described with reference to FIGS. 8 and 10.

When the main data is read by the data processing device 10, the memory card 20 first has a high control signal output from the host-side serial interface circuit 13 in step S11, and the current state is "state 1". When the memory card 20 recognizes that, the data sent from the host-side serial interface circuit 13 via the DT line 33 is received as a command (time t in FIG. 8).₅₁). When the data transmission from the data processing device 10 is completed, the control signal is switched from low to high.

Next, in step S12, it is determined whether or not an error has occurred when receiving the command in step S11. At this time, for example, the memory card 20 side recognizes that the memory card 20 side is in "state 1", but the data processing device 10 side recognizes that it is in "state 3" and sends the error. This is the case when the data received is not a command.

If an error occurs when receiving the command, the process proceeds to step S13, the signal output from the memory card 20 is stopped, and then the process returns to step S11 to wait for the command to be re-entered from the data processing device 10. That is, when an error occurs when the card-side serial interface circuit 23 receives the command from the host-side serial interface circuit 13, the card-side serial interface circuit 23 stops the signal output and waits for the input of a new command. When the signal output from the memory card 20 is stopped, the data processing device 10 is in a state of detecting a busy signal.

On the other hand, if there is no error when receiving the command, it shifts to "state 2" (time t in Fig. 8).₅₂). Then, the process proceeds to step S14, and the memory card 20 performs processing according to the command received in step S11, and determines whether or not the preparation for sending the main data to the data processing device 10 is completed. If the preparation is not completed, the process proceeds to step S15, and if the preparation is completed, the process proceeds to step S16.

In step S15, the card-side serial interface circuit 23 outputs a busy signal having a constant signal level, and then returns to step S14 to determine whether or not the preparation for sending the main data to the data processing device 10 is complete. repeat. That is, the card-side serial interface circuit 23 continues to output a busy signal having a constant signal level until the preparation for sending the main data to the data processing device 10 is completed.

When the preparation for sending the main data to the data processing device 10 is completed, the process proceeds to step S16, and in step S16, the card-side serial interface circuit 23 sends a ready signal to the host-side serial interface circuit 13 (time t in FIG. 8).₅₃). Here, as described above, the ready signal is, for example, a signal having a frequency of 1/2 of the synchronization signal.

When the ready signal is detected by the data processing device 10, the control signal switches from low to high. That is, it switches from "state 2" to "state 3" (time t in FIG. 8).₅₄). When the "state 3" is reached, in step S17, the card-side controller 24 reads the main data instructed to be read by the command received in step S11 by the DT line 33 via the card-side serial interface circuit 23 on the host side. It is transmitted to the serial interface circuit 13 in synchronization with the synchronization signal transmitted by the CLK line. When all of this main data is received by the data processor 10, the control signal switches from high to low. That is, it switches from "state 3" to "state 0" (time t in FIG. 8).₅₅)。

Next, in step S18, the card-side controller 24 determines whether or not there is any request for interrupt processing. If there is no request for interrupt processing, the process proceeds to step S19, and if there is a request for interrupt processing, the process proceeds to step S20.

In step S19, the card-side controller 24 determines whether or not the control signal supplied from the host-side serial interface circuit 13 has switched from low to high, that is, whether or not it has switched from state 0 to state 1. To judge. Then, when the state is switched to "state 1", the process returns to step S11, and the process is repeated from the reception of the command. On the other hand, if the "state 0" remains, the process returns to step S18 and the process is repeated. That is, the memory card 20 repeats the processes of steps S18 and S19 until an interrupt process occurs or the state switches from "state 0" to "state 1".

On the other hand, if it is determined in step S18 that there is a request for interrupt processing, as shown in step S20 and step 21, the card-side serial interface circuit interrupts until the state switches from "state 0" to "state 1". Output a signal. At this time, when the interrupt signal is detected by the data processing device 20, the control signal supplied from the host-side serial interface circuit 13 is switched from low to high, and the state is switched from state 0 to state 1. It will be. Then, when the state is switched from "state 0" to "state 1", the process returns to step S11, and the memory card 20 repeats the process from the reception of the command. At this time, a command for performing processing according to the interrupt signal transmitted in step S20 is received.

As described above, not only the signal output when the memory card 20 is actually processing is used as a busy signal, but also when there is no signal output from the memory card 20, it is detected as a busy signal. This prevents the memory card 20 from proceeding with data transmission processing while erroneously determining the state. Therefore, the data output from the memory card 20 and the data output from the data processing device 10 may collide with each other, or incorrect data may be exchanged between the memory card 20 and the data processing device 10, or the memory card may be used. It is no longer that the 20 and the data processing device 10 are in a waiting state with each other and data is not transmitted.

<figref num="1">It is a block diagram which shows the data processing apparatus which concerns on this invention, and the memory card used for this data processing apparatus.</figref><figref num="2">It is a circuit diagram which shows the output circuit of the said memory card.</figref><figref num="3">It is a time chart of data transmitted between the data processing apparatus and a memory card.</figref><figref num="4">It is a time chart of data transmitted between the data processing apparatus and a memory card.</figref><figref num="5">It is a time chart of data transmitted between the data processing apparatus and a memory card.</figref><figref num="6">It is a time chart of data transmitted between the data processing apparatus and a memory card.</figref><figref num="7">It is a time chart of data transmitted between the data processing apparatus and a memory card.</figref><figref num="8">It is a time chart of data transmitted between the data processing apparatus and a memory card.</figref><figref num="9">It is a flowchart which shows the process flow on the data processing apparatus side when reading data from a memory card.</figref><figref num="10">It is a flowchart which shows the process flow on the memory card side when reading data from a memory card.</figref><figref num="11">It is a block diagram which shows the conventional data processing apparatus and a memory card.</figref><figref num="12">It is a time chart of data transmitted between a conventional data processing device and a memory card.</figref>

Code description

10 data processor, 11 data processor, 12 registers, 13 host-side serial interface circuit, 14 host-side controller, 20 memory card, 21 memory, 22 registers, 23 card-side serial interface circuit, 24 card-side controller, 31 CLK line , 32 control line, 33 DT line