Method for driving indicator and display device using the same
Abstract
[Task] A good image can be obtained by increasing the peak brightness of the image to be displayed and suppressing the occurrence of a wasteful period.
Solution.In the display driving method for driving a display having a plurality of scanning wirings and a plurality of modulation wirings, a scanning selection signal is supplied to the scanning wirings selected from the plurality of scanning wirings for each horizontal scanning period. A step of supplying a modulated signal modulated based on image data to the plurality of modulation wirings for each horizontal scanning period, and a vertical scanning selection signal selection period in at least two horizontal scanning periods. Make them different from each other within the scanning period.

Term
Term ended
Projected expiry passed 28 June 2022, 4.2 years ago.
- Priority
- Filed
- Published
- Projected expiry
- Today
49 claims: 11 independent, 38 dependent
- 1【特許請求の範囲】 【請求項1】複数の走査配線と複数の変調配線とを有する表示器を駆動するための表示器の駆動方法において、 水平走査期間毎に、前記複数の走査配線から選択された走査配線に走査選択信号を供給する工程、 水平走査期間毎に、前記複数の変調配線に画像データに基づいて変調された変調信号を供給する工程、 を含み、 画像データに基づいて少なくとも2つの水平走査期間及びそれら水平走査期間における前記走査選択信号の選択期間を、垂直走査期間内で、互いに異ならしめるか、 少なくとも2つの行上の画素の輝度を異ならせるべく、それらに対応した少なくとも2つの水平走査期間及び/又はそれら水平走査期間における前記走査選択信号の選択期間を、垂直走査期間内で、互いに異ならしめることを特徴とする駆動方法。
- 2【請求項2】水平走査期間に前記変調配線に供給される変調信号の最大継続期間に対応した長さになるように、当該水平走査期間に前記走査配線に供給される前記走査選択信号の選択期間を定める請求項1記載の駆動方法。
- 3【請求項3】前記走査配線に供給される前記走査選択信号の選択期間を設定し、設定された選択期間に合わせて、水平走査期間に前記変調配線に供給される変調信号の継続期間を定める請求項1記載の駆動方法。
- 4【請求項4】水平走査期間を設定し、設定された水平走査期間に合わせて、当該水平走査期間に前記走査配線に供給される前記走査選択信号の選択期間と、当該水平走査期間に前記変調配線に供給される変調信号の継続期間を定める請求項1記載の駆動方法。
- 5【請求項5】選択された走査配線上の各画素における、表示輝度又は補正画像データの最大値に応じて、当該走査配線に供給される前記走査選択信号の選択期間を定める請求項1記載の駆動方法。
- 6【請求項6】水平走査期間の上限値又は下限値のうち少なくとも何れか一方を定め、それによって定められる可変範囲内で水平走査期間を変更する請求項1~5のうち何れかに記載の駆動方法。
- 7【請求項7】前記水平走査期間の和によって定まる表示画像のフレーム走査期間を、少なくとも複数のフレーム走査期間に亘って一定の値に維持する請求項1~5のうち何れかに記載の駆動方法。
- 8【請求項8】前記水平走査期間に下限値を定め、当該水平走査期間に前記変調配線に供給される変調信号の最大継続期間が該下限値に満たない場合に、当該変調信号にブランキング期間を追加する請求項1~5のうち何れかに記載の駆動方法。
- 9【請求項9】前記水平走査期間に下限値を定め、当該水平走査期間における前記走査選択信号の選択期間が該下限値に満たない場合に、当該走査選択信号にブランキング期間を追加する請求項1~5のうち何れかに記載の駆動方法。
- 10【請求項10】前記水平走査期間に上限値を定め、当該水平走査期間に前記変調配線に供給される変調信号の最大継続期間が該上限値を越えないように、前記変調信号の継続時間を定める請求項1~5のうち何れかに記載の駆動方法。
- 11【請求項11】前記上限値は、前記水平走査期間から所定のブランキング期間を引いた値である請求項10記載の駆動方法。
- 12【請求項12】前記水平走査期間は、クロック数を基準にして、その長さが制御される請求項1~5のうち何れかに記載の駆動方法。
- 13【請求項13】前記画像データは入力された映像信号の輝度データを含み、当該輝度データに応じて、少なくとも前記変調信号の継続時間が変調される請求項1~5のうち何れかに記載の駆動方法。
- 14【請求項14】前記画像データは入力された映像信号の輝度データと補正データとを含み、これら輝度データ及び補正データに応じて、少なくとも前記変調信号の継続時間が定められる請求項1~5のうち何れかに記載の駆動方法。
- 15【請求項15】前記補正データは、所望の輝度と表示輝度の差を補償するための補正データである請求項14記載の駆動方法。
- 16【請求項16】前記補正データは、前記走査配線に生じる電圧降下により表示素子に印加される電圧の変化を補償するための補正データである請求項14記載の駆動方法。
- 17【請求項17】入力された映像信号の輝度データ及び補正データに応じて定められた各水平走査期間のゲイン調整及び/又は上限値調整を行う請求項1~5のうち何れかに記載の駆動方法。
- 18【請求項18】前記水平走査期間の和によって定まる表示画像の垂直走査期間が所定の値を超えないように、入力された映像信号の輝度データ及び補正データに応じて定められた各水平走査期間のゲイン調整を行う請求項1~5のうち何れかに記載の駆動方法。
- 19【請求項19】前記表示器の画面中央の走査配線上の画素の水平走査期間が、少なくとも、前記画面上方又は下方にある別の走査配線上の画素の水平走査期間よりも長い請求項1~5のうち何れかに記載の駆動方法。
- 20【請求項20】前記画像データを、各水平走査期間に対応して設定された倍率でゲイン調整した後に、変調駆動回路に供給する請求項1~5のうち何れかに記載の駆動方法。
- 21【請求項21】表示装置において、 複数の走査配線と複数の変調配線とを有する表示器と、 水平走査期間毎に、前記複数の走査配線から選択された走査配線に走査選択信号を供給する走査駆動回路と、 水平走査期間毎に、前記複数の変調配線に画像データに基づいて変調された変調信号を供給する変調駆動回路と、 を有し、 画像データに基づいて少なくとも2つの水平走査期間及びそれら水平走査期間における前記走査選択信号の選択期間が、垂直走査期間内において、互いに異ならしめるか、 少なくとも2つの行上の画素の輝度を異ならせるべく、それらに対応した少なくとも2つの水平走査期間及び/又はそれら水平走査期間における前記走査選択信号の選択期間を、垂直走査期間内で、互いに異ならしめるように前記走査駆動回路を制御する駆動制御回路を備えたことを特徴とする表示装置。
- 22【請求項22】前記駆動制御回路は、入力された映像信号から各水平走査期間における輝度データの最大値を検出し、その最大値に基づいて、前記走査選択信号の選択期間を設定する請求項21記載の表示装置。
- 23【請求項23】前記駆動制御回路は、入力された映像信号から各水平走査期間における輝度データを補正して得られる補正画像データの最大値を検出し、その最大値に基づいて、前記走査選択信号の選択期間を設定する請求項21記載の表示装置。
- 24【請求項24】前記駆動制御回路は、水平走査期間を変更し得る可変範囲内で設定された水平走査期間に合わせて、前記走査選択信号の選択期間及び前記変調信号の継続期間を定める請求項21記載の表示装置。
- 25【請求項25】前記駆動制御回路は、入力された映像信号から各水平走査期間における輝度データを補正して得られる補正画像データの最大値を検出し、その最大値に基づいて、前記走査選択信号の選択期間を設定するとともに、 前記水平走査期間の和によって定まる表示画像の垂直走査期間が、所定の値となるように少なくとも一つの水平走査期間を調整する請求項21記載の表示装置。
- 26【請求項26】前記少なくとも一つの水平走査期間を調整するゲイン調整器及び/又はリミッターを備えている請求項25記載の表示装置。
- 27【請求項27】前記駆動制御回路は、水平走査期間を調整するために、入力された映像信号から各水平走査期間における輝度データを補正して得られる補正画像データを1フレーム分格納するフレームメモリを備えている請求項21~25のうち何れかに記載の表示装置。
- 28【請求項28】前記フレームメモリは、2つのフレームメモリを有しており、一方にデータを書き込む間に、他方からデータを読み出すように、制御される請求項27記載の表示装置。
- 29【請求項29】前記フレームメモリから、1水平走査期間の補正画像データを複数層に分けて並列に読み出し、 前記各層に対応して設けられた複数のシフトレジスタに入力する請求項27記載の表示装置。
- 30【請求項30】前記駆動制御回路は、設定された各水平走査期間に応じて、前記走査選択信号の選択期間と、前記変調信号の継続時間とを定める請求項21記載の表示装置。
- 31【請求項31】前記水平走査期間の和によって定まる表示画像の垂直走査期間が、少なくとも、複数の垂直走査期間に亘って一定の値に維持される請求項21~25及び30のうち何れかに記載の表示装置。
- 32【請求項32】前記表示器の画面中央の走査配線上の画素の水平走査期間が、少なくとも、前記画面上方又は下方にある別の走査配線上の画素の水平走査期間よりも長い請求項21又は30記載の表示装置。
- 33【請求項33】前記駆動制御回路は、前記画像データを、設定された水平走査期間に合わせて調整する請求項21又は30記載の表示装置。
- 34【請求項34】前記画像データの調整後に、前記変調駆動回路により、該画像データから前記変調信号を生成する請求項33記載の表示装置。
- 35【請求項35】請求項21~25及び30のうち何れかに記載の表示装置に用いられる駆動制御方法において、 前記水平走査期間を決定するためのタイミング信号を生成することを特徴とする駆動制御方法。
- 36【請求項36】所定の走査期間内の最大画像データに基づいて、前記タイミング信号を生成する請求項35記載の駆動制御方法。
- 37【請求項37】前記画像データは、輝度データと補正データとを含む請求項36記載の駆動制御方法。
- 38【請求項38】行毎の画素の最大画像データと平均画像データに基づいて、前記水平走査期間を定める請求項35記載の駆動制御方法。
- 39【請求項39】少なくとも行又は列毎の最大画像データに基づいて、画像データを補正し、メモリに格納された画像データを補正された補正画像データに置き換える請求項35記載の駆動制御方法。
- 40【請求項40】行毎の画素の最大画像データと平均画像データから水平輝度レベル係数(Ah)を求め、 水平輝度レベル係数(Ah)及び係数の上限値(Al)から輝度レベル係数の最小値(Am)を求め、 各画素の画像データを前記輝度レベル係数の最小値(Am)を基に補正する請求項35記載の駆動制御方法。
- 41【請求項41】行毎の画素の最大画像データと平均画像データから水平輝度レベル係数(Ah)を求め、 列毎の画素の最大画像データと平均画像データから垂直輝度レベル係数(Av)を求め、 これら水平輝度レベル係数(Ah)、垂直輝度レベル係数(Av)及び係数の上限値(Al)から輝度レベル係数の最小値(Am)を求め、 各画素の画像データを前記輝度レベル係数の最小値(Am)を基に補正する請求項35記載の駆動制御方法。
- 42【請求項42】請求項35記載の駆動制御方法を実行するプログラム。
- 43【請求項43】請求項35記載の駆動制御方法を実行する集積回路。
- 44【請求項44】請求項35記載の駆動制御方法を実行する集積回路を設計するための設計資産。
- 45【請求項45】クロック信号の周波数を変更することにより、前記水平走査期間を決める請求項1~5のうち何れかに記載の駆動方法。
- 46【請求項46】クロック信号の周波数を変更することにより、前記水平走査期間を決める請求項21~25のうち何れかに記載の表示装置。
- 47【請求項47】クロック信号の周波数を変更することにより、前記水平走査期間を決める請求項35~41のうち何れかに記載の駆動制御方法。
- 48【請求項48】複数の走査配線と複数の変調配線とを有する表示器を駆動するための表示器の駆動方法において、 水平走査期間毎に、前記複数の走査配線から選択された走査配線に走査選択信号を供給する工程、 水平走査期間毎に、前記複数の変調配線に画像データに基づいて変調された変調信号を供給する工程、 を含み、 少なくとも2つの水平走査期間における前記走査選択信号の選択期間を、垂直走査期間内で、互いに異ならしめることを特徴とする駆動方法。
- 49【請求項49】表示装置において、 複数の走査配線と複数の変調配線とを有する表示器と、 水平走査期間毎に、前記複数の走査配線から選択された走査配線に走査選択信号を供給する走査駆動回路と、 水平走査期間毎に、前記複数の変調配線に画像データに基づいて変調された変調信号を供給する変調駆動回路と、 を有し、 画像データに基づいて少なくとも2つの水平走査期間における前記走査選択信号の選択期間が、垂直走査期間内において、互いに異ならしめるように前記走査駆動回路を制御する駆動制御回路を備えたことを特徴とする表示装置。
Independent claims49
1,730 paragraphs in 1 section, as filed
Description: TECHNICAL FIELD [Detailed description of the invention]
【0001】
[Technical field to which the invention belongs]
The present invention relates to a display device for displaying an image on a display element using an electron emitting element, an electroluminescence (EL) element, an LED element, a plasma light emitting element, a liquid crystal element, or the like, and a driving method thereof.
【0002】
In particular, the present invention relates to a multiplexing driving method for a matrix-type display in which a plurality of self-luminous display elements are arranged in a matrix.
【0003】
[Conventional technology]
The plurality of display elements described above control and display signals supplied to a matrix wiring composed of a plurality of row wirings (scanning wirings) and a plurality of column wirings (modulation wirings).
【0004】
Hereinafter, a self-luminous display that emits light from a phosphor to form an image will be described as an example.
【0005】
In this type of display, a phosphor is excited by using the energy of particles emitted from an electron emitting element or the like, and the brightness changes depending on the excitation intensity and / or the excitation time for exciting the phosphor.
【0006】
Such display devices include, for example, JP-A-7-235256 (US Pat. No. 6,313,571), JP-A-8-45415, JP-A-2000-29425 (European Patent No. 936,596), JP-A. It is disclosed in Japanese Patent Publication No. 8-248920.
【0007】
FIG. 76 shows an example of a drive signal for driving a conventional display, and FIG. 77 shows a display state of a 3-by-3 matrix display driven by the drive signal.
【0008】
Here, one vertical scanning period for displaying a one-frame image consists of three horizontal scanning periods, and Sy1, Sy2, and Sy3 indicate scanning signals supplied to the scanning wiring, respectively. Here, in each scanning wiring, the selection period in which a negative voltage is applied is the horizontal scanning period, and in all the scanning wirings, each selection period has a constant value.
【0009】
Sx1, Sx2, and Sx3 indicate modulation signals (data signals) supplied to the modulation wiring, respectively. Here, an example of a modulation signal by the pulse width modulation method that modulates the pulse width according to the brightness level (gradation level) of the pixel is shown, and the modulation signal Sx1 has brightness levels 1, 1, and 3 to be displayed. It is a signal, which is supplied to the modulation wiring in chronological order. Similarly, the modulated signal Sx2 is a signal having a luminance level of 1, 2 or 2 to be displayed, and the modulated signal Sx3 is a signal having a luminance level of 1, 1 or 1 to be displayed.
【0010】
In this way, the brightness of the three pixels on the selected row is determined in each horizontal scanning period while sequentially selecting the scanning wiring. Here, the pixel on the third row and one column that lights the brightness level 3 is the brightest.
【0011】
In general, display devices tend to prefer bright screens. In particular, when a dark image contains a partially bright part, it is desirable that the brightness (peak brightness) of the bright part can be displayed relatively brighter in order to display the details of the dark part of the image with sufficient image quality. ..
【0012】
[Problems to be Solved by the Invention]
However, as described above, in the case of a display device that sequentially selects scanning wiring by time division, that is, so-called line sequential scanning, the maximum value of the lighting time of each pixel is generally limited to the selection period within the horizontal scanning period. Therefore, the display brightness of the display device is also limited accordingly.
【0013】
Further, during the period when the scanning selection signal is applied but the modulation signal is not applied, a voltage is applied to the scanning wiring, although it does not contribute to the lighting of the pixels except for the blanking period required for other processing. It is a wasteful period.
【0014】
An object of the present invention is to provide a driving method of a display device capable of obtaining a good image by increasing the peak luminance of the image to be displayed, and a display device using the driving method.
【0015】
An object of the present invention is to provide a method for driving a display device capable of obtaining a good image by suppressing the occurrence of a wasteful period, and a display device using the same.
【0016】
[Means for solving problems]
The gist of the present invention is, in the method of driving an indicator for driving an indicator having a plurality of scanning wirings and a plurality of modulation wirings, the scanning wiring selected from the plurality of scanning wirings is used for each horizontal scanning period. A step of supplying a scan selection signal and a step of supplying a modulated signal modulated based on image data to the plurality of modulation wirings for each horizontal scanning period, and the scanning selection signal in at least two horizontal scanning periods. The selection period is characterized by being different from each other within the vertical scanning period.
【0017】
In particular, in a method of driving an indicator for driving an indicator having a plurality of scanning wirings and a plurality of modulation wirings, a scanning selection signal is transmitted to the scanning wirings selected from the plurality of scanning wirings for each horizontal scanning period. A step of supplying, a step of supplying a modulated signal modulated based on the image data to the plurality of modulation wirings for each horizontal scanning period, and at least two horizontal scanning periods based on the image data and their horizontal scanning periods. In order to make the selection periods of the scan selection signals in the vertical scan period different from each other, or to make the brightness of the pixels on at least two rows different, at least two horizontal scan periods corresponding to them and / or their horizontal It is better to make the selection period of the scan selection signal in the scan period different from each other within the vertical scan period.
【0018】
In the present invention, it is also preferable to adopt the following configuration, if necessary.
【0019】
The scanning selection signal supplied to the scanning wiring during the horizontal scanning period so that the duration of the modulation signal supplied to each modulation wiring during the horizontal scanning period corresponds to the longest maximum duration. Determine the selection period of.
【0020】
The selection period of the scanning selection signal supplied to the scanning wiring is set, and the duration of the modulated signal supplied to the modulation wiring is determined in the horizontal scanning period according to the set selection period.
【0021】
A horizontal scanning period is set, and according to the set horizontal scanning period, the selection period of the scanning selection signal supplied to the scanning wiring during the horizontal scanning period and the selection period of the scanning selection signal supplied to the modulated wiring during the horizontal scanning period. Determine the duration of the modulated signal.
【0022】
The selection period of the scanning selection signal supplied to the scanning wiring is determined according to the display brightness or the maximum value of the corrected image data in each pixel on the selected scanning wiring.
【0023】
At least one of the upper limit value and the lower limit value of the horizontal scanning period is set, and the horizontal scanning period is changed within the variable range defined by the setting.
【0024】
The frame scanning period of the display image determined by the sum of the horizontal scanning periods is maintained at a constant value over at least a plurality of frame scanning periods.
【0025】
A lower limit value is set for the horizontal scanning period, and a blanking period is added to the modulated signal when the maximum duration of the modulated signal supplied to the modulated wiring during the horizontal scanning period is less than the lower limit value.
【0026】
A lower limit is set for the horizontal scanning period, and when the selection period of the scanning selection signal in the horizontal scanning period is less than the lower limit, a blanking period is added to the scanning selection signal.
【0027】
An upper limit is set for the horizontal scanning period, and the duration of the modulated signal is set so that the maximum duration of the modulated signal supplied to the modulated wiring during the horizontal scanning period does not exceed the upper limit.
【0028】
The upper limit value is a value obtained by subtracting a predetermined blanking period from the horizontal scanning period.
【0029】
The length of the horizontal scanning period is controlled with reference to the number of clocks.
【0030】
The image data includes the luminance data of the input video signal, and at least the duration of the modulated signal is modulated according to the luminance data.
【0031】
The image data includes the luminance data and the correction data of the input video signal, and at least the duration of the modulated signal is determined according to the luminance data and the correction data.
【0032】
The correction data is correction data for compensating for the difference between the desired brightness and the display brightness.
【0033】
The correction data is correction data for compensating for a change in voltage applied to the display element due to a voltage drop occurring in the scanning wiring.
【0034】
Gain adjustment and / or upper limit value adjustment for each horizontal scanning period determined according to the luminance data and correction data of the input video signal are performed.
【0035】
The gain of each horizontal scanning period determined according to the luminance data and correction data of the input video signal is adjusted so that the vertical scanning period of the displayed image determined by the sum of the horizontal scanning periods does not exceed a predetermined value. ..
【0036】
The horizontal scanning period of the pixel on the scanning wiring in the center of the screen of the display is at least longer than the horizontal scanning period of the pixel on another scanning wiring above or below the screen.
【0037】
The image data is gain-adjusted at a magnification set corresponding to each horizontal scanning period, and then supplied to the modulation drive circuit.
【0038】
The horizontal scanning period is determined by changing the frequency of the clock signal.
【0039】
Another gist of the present invention is to send a scan selection signal to a display having a plurality of scan wires and a plurality of modulation wires in a display device and a scan wire selected from the plurality of scan wires for each horizontal scan period. It has a scanning drive circuit for supplying and a modulation driving circuit for supplying a modulation signal modulated based on image data to the plurality of modulation wirings for each horizontal scanning period, and the scanning in at least two horizontal scanning periods. A drive control circuit for controlling the scanning drive circuit so that the selection period of the selection signal is different from each other within the vertical scanning period is provided.
【0040】
In particular, if at least two horizontal scanning periods and the selection periods of the scanning selection signals in those horizontal scanning periods are different from each other within the vertical scanning period, or the brightness of the pixels on at least two rows is different, based on the image data. A drive that controls the scan drive circuit so that at least two horizontal scan periods corresponding to them and / or selection periods of the scan selection signals in those horizontal scan periods are different from each other within the vertical scan period. It is preferable to include a control circuit.
【0041】
In the present invention, it is also preferable to adopt the following configuration, if necessary.
【0042】
The drive control circuit detects the maximum value of the luminance data in each horizontal scanning period from the input video signal, and sets the selection period of the scanning selection signal based on the maximum value.
【0043】
The drive control circuit detects the maximum value of the corrected image data obtained by correcting the luminance data in each horizontal scanning period from the input video signal, and sets the selection period of the scanning selection signal based on the maximum value. Set.
【0044】
The drive control circuit determines the selection period of the scan selection signal and the duration of the modulated signal according to the horizontal scan period set within a variable range in which the horizontal scan period can be changed.
【0045】
The drive control circuit detects the maximum value of the corrected image data obtained by correcting the brightness data in each horizontal scanning period from the input video signal, and sets the selection period of the scanning selection signal based on the maximum value. At the same time, at least one horizontal scanning period is adjusted so that the vertical scanning period of the displayed image determined by the sum of the horizontal scanning periods becomes a predetermined value.
【0046】
It includes a gain adjuster and / or a limiter that adjusts the at least one horizontal scanning period.
【0047】
The drive control circuit includes a frame memory for storing one frame of corrected image data obtained by correcting the luminance data in each horizontal scanning period from the input video signal in order to adjust the horizontal scanning period.
【0048】
The frame memory has two frame memories, and is controlled so as to read data from the other while writing data to one.
【0049】
The corrected image data for one horizontal scanning period is divided into a plurality of layers and read out in parallel from the frame memory, and input to a plurality of shift registers provided corresponding to the respective layers.
【0050】
The drive control circuit determines the selection period of the scan selection signal and the duration of the modulated signal according to each set horizontal scanning period.
【0051】
The vertical scanning period of the displayed image determined by the sum of the horizontal scanning periods is maintained at a constant value over at least a plurality of vertical scanning periods.
【0052】
The horizontal scanning period of the pixel on the scanning wiring in the center of the screen of the display is at least longer than the horizontal scanning period of the pixel on another scanning wiring above or below the screen.
【0053】
The drive control circuit adjusts the image data according to a set horizontal scanning period.
【0054】
After adjusting the image data, the modulation drive circuit generates the modulation signal from the image data.
【0055】
The display is a self-luminous display.
【0056】
The display has a plurality of display elements including an electron emitting element.
【0057】
The horizontal scanning period is determined by changing the frequency of the clock signal.
【0058】
Yet another gist of the present invention is that in the drive control method used in the display device described above, a timing signal for determining the horizontal scanning period is generated.
【0059】
In the present invention, it is also preferable to adopt the following configuration, if necessary.
【0060】
The timing signal is generated based on the maximum image data within a predetermined scanning period.
【0061】
The image data includes luminance data and correction data.
【0062】
The horizontal scanning period is determined based on the maximum image data and the average image data of the pixels for each row.
【0063】
The image data is adjusted based on the maximum image data at least for each row or column, and the image data stored in the memory is replaced with the adjusted adjusted image data.
【0064】
Image for each row determine the horizontal luminance level coefficient (Ah) from the maximum image data and the average image data of the unit, the minimum value of the upper limit of the horizontal luminance level coefficient (Ah) and the coefficient of (Al) luminance level coefficient (Am) The image data of each pixel is obtained and adjusted based on the minimum value (Am) of the luminance level coefficient.
【0065】
The horizontal brightness level coefficient (Ah) is obtained from the maximum image data and average image data of the pixels for each row, and the vertical brightness level coefficient (Av) is obtained from the maximum image data and average image data of the pixels for each column. The minimum value (Am) of the brightness level coefficient is obtained from the coefficient (Ah), the vertical brightness level coefficient (Av), and the upper limit value (Al) of the coefficient, and the image data of each pixel is used as the minimum value (Am) of the brightness level coefficient. Adjust based on.
【0066】
Further, the image data may be adjusted according to the adjustment clock determined based on the minimum value (Am).
【0067】
The horizontal scanning period is determined by changing the frequency of the clock signal.
【0068】
The drive control method is executed by a program.
【0069】
The drive control method is executed by an integrated circuit.
【0070】
A design asset for designing an integrated circuit that executes the above drive control method.
【0071】
BEST MODE FOR CARRYING OUT THE INVENTION
1 (a) to 1 (f) show the form of the drive signal used in the display device, and each of them shows the drive signal for exhibiting the display state as in FIG. 77.
【0072】
FIG. 2 shows the display device of the present invention, in which 1 is a display, 2 is a scanning drive circuit for supplying scanning signals Sy1, Sy2, and Sy3 to display 1, and 3 is a modulation signal Sx1, Sx2, Sx3. Is a modulation drive circuit for supplying the display 1, and these circuits are controlled by a drive control circuit 4 having a 1H control circuit for controlling a selection period of the horizontal scanning period 1H.
【0073】
In short, the display device shown in FIG. 2 supplies a scanning selection signal to the display 1 having a plurality of scanning wirings and a plurality of modulation wirings and the scanning wirings selected from the plurality of scanning wirings every 1H of the horizontal scanning period. The scanning drive circuit 2 for each horizontal scanning period and the modulation driving circuit 3 for supplying the modulation signal modulated based on the image data to the plurality of modulation wirings in at least two horizontal scanning periods. A drive control circuit 4 for controlling the scanning drive circuits so that the selection period of the scanning selection signal is different from each other within the vertical scanning period of 1V is provided.
【0074】
In the form of FIG. 1A, the scanning signals Sy1, Sy2, Sy3 have a selection period length (here, a low level period) in which the corresponding scanning wiring is selected in the horizontal scanning period 1H. It is different, and the low-level scan selection signal is applied only during the period when the high-level modulation signal is applied to any of the modulation wirings. Here, an example of a modulation signal by a pulse width modulation method that modulates the pulse width according to the brightness level of the pixel is shown. The modulation signal Sx1 is a signal having brightness levels 1, 1, and 3, and the modulation signal Sx2 is. It is a signal with brightness levels 1, 2, and 2, and the modulated signal Sx3 is a signal with brightness levels 1, 1, 1. The period during which the scanning selection signal is not applied within the horizontal scanning period 1H is the blanking period.
【0075】
In each horizontal scanning period 1H, the selection periods of the scanning selection signals are different from each other according to the modulation signal having the maximum pulse width (duration) among the modulation signals supplied to the three modulation wirings. You can see that there is. Here, it is preferable to make the horizontal scanning period 1H different according to the brightness level of the pixel determined depending on the input video signal.
【0076】
In the form of FIG. 1B, the low-level selection period in which the scanning selection signals are supplied of the scanning signals Sy1, Sy2, and Sy3 is the horizontal scanning period 1H. The lengths of the three horizontal scanning periods 1H are different from each other, and are 1/3, 2/3, and 3/3 in order compared to the horizontal scanning period shown in FIG. 1 (a). Then, the scan selection signal is applied only during the period in which the modulation signals Sx1, Sx2, and Sx3 are applied to any of the modulation wirings.
【0077】
As described above, in the form of FIG. 1B, the frame frequency is increased and the brightness is further improved by shortening the period during which the scan selection signal is not applied and shortening one vertical scanning period, that is, one frame period. I'm letting you. Further, it is also preferable to extend each horizontal scanning period by an arbitrary magnification and adjust it so as to be equal to the original one frame period.
【0078】
In the form of FIG. 1 (c), the same signals as in FIG. 1 (a) are adopted as the scanning signals Sy1, Sy2, Sy3, and the modulated signals Sx1, Sx2, Sx3 have voltage amplitudes according to the brightness level of the pixels. An example of a modulated signal by an amplitude modulation method that modulates is shown. The modulated signal Sx1 is a signal with luminance levels 1, 1, and 3, the modulated signal Sx2 is a signal with luminance levels 1, 2, and 2, and the modulated signal Sx3 is a signal with luminance levels 1, 1, 1. However, since the length of the selection period is different, the difference in brightness is larger. The high-level voltage amplitude of the modulated signals Sx1, Sx2, Sx3 synchronized in each selection period is selected from three voltage values according to the brightness level.
【0079】
In the form of FIG. 1 (d), the same signals as in FIG. 1 (c) are adopted as the scanning signals Sy1, Sy2, Sy3, and the modulated signals Sx1, Sx2, Sx3 have pulse widths according to the brightness level of the pixels. An example of a modulated signal by a pulse width modulation method is shown. The modulated signal Sx1 is a signal with luminance levels 1, 1, and 3, the modulated signal Sx2 is a signal with luminance levels 1, 2, and 2, and the modulated signal Sx3 is a signal with luminance levels 1, 1, 1. However, since the length of the selection period is different, the difference in brightness is larger.
【0080】
In the forms of FIGS. 1 (c) and 1 (d), even when the same luminance data is displayed, the display luminance of the pixels on a predetermined line is determined according to the user's request and preset specifications. Is more preferably used when increasing the display brightness of pixels on other lines.
【0081】
The form of FIG. 1 (e) shows an example of a modulated signal by a modulation method that modulates both the pulse width and the voltage amplitude according to the brightness level of the pixel as the modulated signals Sx1, Sx2, Sx3. The modulated signal Sx1 is a signal with brightness levels 1, 1, and 3, the modulated signal Sx2 is a signal with brightness levels 1, 2, and 2, and the modulated signal Sx3 is a signal with brightness levels 1, 1, 1. , It is a signal for exhibiting the same display state as in FIG. 77. As the brightness level rises, its voltage amplitude is increased slot by slot. After it reaches a predetermined amplitude value, the pulse width is lengthened in slot units, and the pulse width is set to a predetermined number of slots. On the other hand, for the scanning signals Sy1, Sy2, and Sy3, the selection period is determined according to the pulse width of the modulated signal within the horizontal scanning period 1H.
【0082】
Further, the horizontal scanning period is shortened by changing the form of FIGS. 1 (c) to 1 (e) as necessary and shortening the blanking period in which the scanning selective voltage is not applied as in FIG. 1 (b). It is also preferable to shorten the period of one frame, and it is also preferable that each horizontal scanning period has a constant blanking period. Alternatively, after eliminating or shortening the blanking period, gain is applied to each horizontal scanning period so that it becomes the same as the original one-frame period, or the frequency of the reference clock signal is changed to extend each horizontal scanning period. It is preferable. The waveform obtained by modifying Fig. 1 (b) by this method is shown in Fig. 1 (f). The one-frame period of the form of FIG. 1 (f) is the same as that of FIG. 1 (a) and longer than that of FIG. 1 (b).
【0083】
As described above, in the present invention, in the method of driving the display for driving the display 1 having the plurality of scanning wirings and the plurality of modulation wirings, from the plurality of scanning wirings every 1H of the horizontal scanning period. At least two horizontal steps include a step of supplying a scan selection signal to the selected scan wiring and a step of supplying a modulated signal modulated based on the image data to the plurality of modulation wires every 1H of the horizontal scanning period. It is characterized in that the selection period of the scan selection signal in the scan period is made different from each other within the vertical scan period of 1 V.
【0084】
In each of the forms of FIGS. 1 (a) to 1 (f), the horizontal scanning period is determined according to the brightness level to be lit at each pixel, and the scanning selection signal selection period and the maximum modulation signal are correspondingly determined accordingly. It defines the pulse width as the duration. In particular, the modes of FIGS. 1 (a) to 1 (f) are supplied to the scanning wiring during the horizontal scanning period so as to match the maximum duration (pulse width) of the modulated signal supplied to the modulation wiring during the horizontal scanning period. It is preferably used when determining the selection period of the scanning selection signal to be performed.
【0085】
Further, in the modes of FIGS. 1 (c) to 1 (e), the selection period of the scanning selection signal supplied to the scanning wiring is set in advance, and the modulation wiring is set in the horizontal scanning period so as to match the set selection period. It can be more preferably used when determining the maximum duration of the supplied modulated signal.
【0086】
As the display element used in the display device of the present invention, a display element in which a surface conduction type electron emitting element or an electric field emitting type electron emitting element and a phosphor is combined is preferably used, but other plasma displays are used. Elements, inorganic EL display elements, organic EL display elements, LED display elements, liquid crystal display elements, plasma address type liquid crystal display elements, micromirror elements and the like can be used.
【0087】
Examples of the electron emitting element used in the present invention include surface-conduction electron emitting elements disclosed in US Pat. No. 5,066,883, JP-A-2-257551, JP-A-4-28137, and the like, or BSD. Examples include electron emitting elements such as type, Spindt type, MIS type, MIM type, diamond particle type, carbon nanotubes, graphite nanofibers and other carbon fiber types.
【0088】
The scanning signal used in the present invention may be a signal that can apply a scanning selective voltage and a scanning non-selective voltage according to the display element to be driven in cooperation with the modulation signal, as long as it is a signal. The waveform is not limited to the waveform shown in FIG. 1 (f) or the waveform of the embodiment described later.
【0089】
The modulated signal used in the present invention is a pulse width modulated signal that lengthens the duration (pulse width) at which the voltage level for display is applied as the brightness of the pixel to be displayed increases, or a pixel to be displayed. An amplitude-modulated signal in which the voltage amplitude (peak value) increases as the brightness increases can be mentioned, or it is also preferable to use a modulated signal in which a pulse width-modulated signal and an amplitude-modulated signal are combined. A modulation method that combines a pulse width modulation signal and an amplitude modulation signal is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-39825.
【0090】
Further, it is also possible to use a current modulation signal that increases the current flowing through the display element as the brightness of the pixel to be displayed increases.
【0091】
In the present invention, the length of the selection period in which the scan selection signal is supplied in the horizontal scanning period can be determined according to the input video signal. Alternatively, it can be determined according to the display characteristics separately from the input video signal. That is, in the former case, if the image changes, the selection period in the scanning wiring corresponding to the change, and further, the horizontal scanning period is changed as needed. In the latter case, since the selection period and, if necessary, the horizontal scanning period are predetermined for each scanning wiring, the modulated signal is appropriately modulated within the determined selection period.
【0092】
Further, when the length of the selection period of the horizontal scanning period in each scanning wiring is determined according to the input video signal, it may be optimized for each scanning wiring, or it is optimized in consideration of the brightness of all pixels. It may be converted. In these cases, the selection period or the horizontal scanning period is determined according to the modulated signal where the pulse width of the modulated signal to be supplied to the pixels on the selected scanning wiring is maximized, and each luminance level ( It is not necessary to have a one-to-one correspondence (gradation level), and a single value horizontal scanning period may be assigned to a plurality of consecutive luminance levels.
【0093】
It is also preferable to determine at least one of the upper limit value and the lower limit value for the selection period or the horizontal scanning period, and change the selection period or the horizontal scanning period within a range that does not exceed the respective values. is there.
【0094】
1 When the vertical scanning period is constant, it is also preferable to adjust the gain by expanding or contracting the selection period in each scanning wiring by a predetermined magnification. It is also preferable to adjust the horizontal scanning period by expanding or contracting the length of the blanking period in which the pixels are turned off to adjust one vertical scanning period.
【0095】
In actual signal processing, the luminance data to be lit in each pixel of the display is extracted directly from the input video signal or by converting the input video signal, and a modulation signal is generated based on the luminance data.
【0096】
The modulated signal used in the present invention is not limited to a signal modulated only based on image data, that is, brightness data, but is modulated based on image data (corrected image data) including correction data and the like. It may be a thing.
【0097】
When the display brightness of the pixels deviates from the originally desired brightness to be displayed and a difference occurs, it is also preferable to correct the modulation signal so as to compensate for the difference. For example, if the effective drive voltage applied to the elements constituting the pixel decreases due to the voltage drop due to the resistance of the scanning wiring and / or the modulation wiring and the current flowing there, the decrease should be compensated for. , It is preferable to correct the modulated signal in advance. This amount of reduction also depends on the display state of the pixels on the same scanning wiring. When compensation is performed by increasing the pulse width of the modulated signal, it is preferable to determine the selection period of the horizontal scanning period according to the corrected modulated signal. Specifically, the image data may be corrected before the modulation, and the modulation may be performed based on the corrected image data.
【0098】
Hereinafter, more specific embodiments will be described.
【0099】
(First Embodiment) A total of N × M cold cathode elements (display elements), N in the row direction and M in the column direction, are arranged two-dimensionally in a matrix, and they are provided in the row direction. There is known a configuration having a multi-electron source in which simple matrix wiring is performed by M row wiring (scanning wiring) and N column wiring (modulation wiring) provided in the column direction.
【0100】
As a method of multiplexing a large number of cold cathode elements wired in a matrix, a group of elements for one row of the matrix (element groups for one row are connected to one row wiring) is driven at the same time.
【0101】
That is, a predetermined selective voltage is applied to one row wiring, and a predetermined modulation voltage is applied only to the column wiring connected to the drive target among the N cold cathode elements connected to the row wiring. Is applied, and a plurality of elements for one row are simultaneously driven by the potential difference between the row wiring potential and the column wiring potential. Then, the selected line wiring is switched one after another to scan all the lines, and a two-dimensional image is formed by utilizing the afterimage phenomenon of vision.
【0102】
According to this method, the driving time assigned to each element is secured N times longer than the method of selecting one element at a time, so that there is an advantage that the brightness of the image display device can be increased. ..
【0103】
By the way, in the above configuration, N cold cathode elements for one row are connected to one row wiring, and the connection positions are different for each element. Therefore, when one row of elements is driven at the same time, the brightness of each element varies due to the influence of the voltage drop due to the wiring resistance. Specifically, in the case of a configuration in which the selective voltage is applied from both ends of the row wiring, the voltage drop increases toward the center of the row wiring and decreases toward both ends, so it is the same as N column wirings. Even if a potential modulation voltage is applied, the brightness near the center becomes darker than the brightness near both ends.
【0104】
Therefore, for example, in Japanese Patent Application Laid-Open No. 8-248920, in order to compensate for the decrease in brightness due to the voltage drop due to the wiring resistance of the row wiring, the correction data is calculated by statistical calculation, and the input image data and the correction data are combined. The composition to be synthesized is disclosed. In the same publication, as shown in FIG. 3, the correction data output from the memory means 207 is multiplied by the image data by the multiplier 208 provided for each row wiring, and the corrected image data is multiplied by the modulation circuit. It is configured to transfer to 209.
【0105】
Here, 201 is a display, 202 is a scanning drive circuit, 203 is a control circuit, 204 is a totalizer, 205 is a shift register, and 206 is a latch circuit.
【0106】
In the correction performed to compensate for the decrease in brightness due to the voltage drop of the row wiring, it is possible to multiply the input image data by the correction data or add the correction data as in the above publication. Although disclosed in Japanese Patent Application Laid-Open No. 248920, at this time, an overflow problem peculiar to a digital circuit may occur.
【0107】
That is, if the corrected image data obtained by multiplying or adding the correction data to the image data is directly input to the conventional modulated signal generator, the data width that can be handled by the modulated signal generator is exceeded. In that case, bit wrapping or the like occurs, and the displayed image is inverted.
【0108】
Explaining with a specific example, when a circuit is designed with a data width of, for example, 8 bits within one horizontal scanning period, the maximum value of data that can be handled is "255 (decimal number)". If "250" is input as image data and the correction data to be added to it is "33", the correction image data is "283", but the pulse width output by the modulation signal generator is "283". , But the bit wraps and becomes "27". In this way, when the corrected image data is input to the modulation signal generator, the portion that should have high brightness is displayed darkly, and the image may be distorted.
【0109】
In this case, the data value is reduced in advance by providing a limiter that limits the maximum value of the image data, uniformly applying a gain to the image data, or performing correction using a look-up table (LUT). By doing so, it is advisable to prevent overflow or uniformly apply a gain to the corrected image data so as not to overflow.
【0110】
As a result of examination by the present inventors, it is possible to prevent the basic problem that bit wrapping occurs and image distortion such as display image inversion occurs, and correction due to voltage drop is applied to obtain good image quality. Display is now possible. However, when observing the displayed image strictly, the method using the limiter and the method using the LUT correction display all the image data exceeding the maximum value with the same brightness, and the gradation is lost depending on the image, resulting in unnatural image reproduction. It may become. In addition, in the method of applying gain, the brightness may be impaired depending on the image.
【0111】
That is, correcting the voltage drop that occurs in the scanning wiring is nothing but correcting the decrease in brightness due to the voltage drop by increasing the drive time. However, for the correction that requires the extension of the drive time, limiting the drive time to the maximum time limited by the horizontally determined horizontal scanning time is nothing but reducing the brightness.
【0112】
In this embodiment, as a display device suitable for solving the above-mentioned problems, a driving method for controlling a horizontal scanning period is adopted. That is, the display device of the present embodiment has a display in which a plurality of display elements are connected in a matrix by a plurality of scanning wirings and a plurality of modulation wirings, and the resistance component of the scanning wirings with respect to the input image data. A corrected image data calculating means for calculating the corrected image data corrected for the influence of the generated voltage drop, a line maximum value detecting means for detecting the maximum value of the corrected image data for each scanning wiring, and the line maximum value detecting means. The selection period control means that determines the selection period of each scanning wiring according to the maximum value of the corrected image data detected by the selection period control means, and the scanning of each scanning wiring according to the selection period of each scanning wiring determined by the selection period control means. It is provided with a scanning drive circuit for performing the scanning drive circuit and a modulation drive circuit for applying a modulation signal whose pulse width is modulated according to the corrected image data to each modulation wiring.
【0113】
Further, the method of driving the display device according to the present embodiment is a method of driving the display device including a display device in which a plurality of display elements are connected in a matrix by a plurality of scanning wirings and a plurality of modulation wirings, and is input. A step of calculating the corrected image data in which the influence of the voltage drop generated by the resistance of the scanning wiring is corrected for the obtained image data, a step of detecting the maximum value of the corrected image data for each scanning wiring, and a step of detecting the maximum value of the corrected image data for each scanning wiring. The step of determining the selection time of each scanning wiring according to the maximum value of the detected corrected image data and the scanning of each scanning wiring according to the determined selection time of each scanning wiring are performed, and pulses are performed according to the corrected image data. Includes a step of applying a width-modulated modulation signal to each modulation wiring.
【0114】
In the correction circuit of the present embodiment, the quality deterioration of the display image caused by the voltage drop is calculated according to the input image data, the correction data for compensating for the deterioration is obtained, and the image data is corrected.
【0115】
Further, this correction circuit detects the maximum value of the corrected image data (corrected image data) for each horizontal scanning line, and allocates the selection time of each scanning wiring according to the maximum value.
【0116】
Hereinafter, an overview of the display panel of the image display device according to the present embodiment, electrical connection of the display panel, characteristics of the surface conduction type emission element, a driving method of the display panel, and an image are displayed by such a display panel. After explaining the mechanism of the decrease in the drive voltage due to the electrical resistance of the scanning wiring, the correction method and the apparatus for the influence of the voltage drop, which is a feature of the present embodiment, will be described in detail.
【0117】
(Overview of Image Display Device) FIG. 4 is a perspective view of a display panel used in the present embodiment, and a part of the panel is cut out to show the internal structure. In the figure, 1005 is the rear plate, 1006 is the side wall, 1007 is the face plate, and 1005 to 1007 form an airtight container for maintaining the inside of the display panel in a vacuum.
【0118】
A substrate 1001 is fixed to the rear plate 1005, and N × M cold cathode elements 1002 are formed on the substrate. The row wiring (scanning wiring) 1003, the column wiring (modulation wiring) 1004, and the cold cathode element are connected as shown in FIG.
【0119】
A fluorescent film 1008 is formed on the lower surface of the face plate 1007. Since the image display device according to the present embodiment is a color display device, the fluorescent film 1008 is coated with phosphors of the three primary colors of red, green, and blue used in the field of CRT. The phosphor forms pixels with respect to the position where the emitted electrons (emitted current) from the cold cathode element are irradiated, which are formed in a matrix corresponding to each pixel (picture element) of the rear plate. It is configured.
【0120】
A metal back 1009 is formed on the lower surface of the fluorescent film 1008.
【0121】
The Hv is a high voltage terminal and is electrically connected to the metal back. By applying a high voltage to the Hv terminal, a high voltage is applied between the rear plate and the face plate.
【0122】
In the present embodiment, a configuration in which the pixel has a surface-conduction type emission element as a cold cathode element is adopted.
【0123】
(Characteristics of Surface Conduction Type Emission Device) The surface conduction type emission element has the emission current Ie pair element applied voltage Vf characteristic and the element current If vs. element applied voltage Vf characteristic as shown in FIG. Since the emission current Ie is significantly smaller than the element current If and it is difficult to show it on the same scale, the two graphs are shown on different scales.
【0124】
That is, it has the following three characteristics regarding the emission current Ie.
【0125】
First, when a voltage higher than a certain voltage (this is called a threshold voltage Vth) is applied to the device, the emission current Ie increases sharply, while the emission current Ie is hardly detected at a voltage lower than the threshold voltage Vth. That is, it is a non-linear element having a clear threshold voltage Vth with respect to the emission current Ie.
【0126】
Secondly, since the emission current Ie changes depending on the voltage Vf applied to the element, the magnitude of the emission current Ie can be controlled by changing the voltage Vf.
【0127】
Thirdly, since the cold cathode element has a high-speed response, the emission time of the emission current Ie can be controlled by the application time of the voltage Vf.
【0128】
In the display device using the display panel shown in FIG. 4, if the first characteristic is used, it is possible to sequentially scan the display screen and perform display. That is, a voltage equal to or higher than the threshold voltage Vth is appropriately applied to the driving element according to the desired emission brightness, and a voltage less than the threshold voltage Vth is applied to the element in the non-selected state. By sequentially switching the driving elements, it is possible to sequentially scan and display the display screen.
【0129】
Further, by utilizing the second characteristic, the emission brightness of the phosphor can be controlled by the voltage Vf applied to the element, and the image can be displayed.
【0130】
Further, by utilizing the third characteristic, the light emission time of the phosphor can be controlled by the time when the voltage Vf is applied to the element, and the image can be displayed.
【0131】
In the display device of the present embodiment, the amount of the electron beam on the display panel is modulated by using the above-mentioned third characteristic.
【0132】
(Driving Method of Display Panel) The driving method of the display panel of the present embodiment will be specifically described with reference to FIG. 7.
【0133】
FIG. 7 is a timing chart of a drive signal for driving the display panel of the present embodiment.
【0134】
J, J + 1, J + 2, and J + 3 indicate the horizontal scanning period of the input video signal input from the outside to the display device. On the other hand, the display horizontal scanning period I is a selection period for causing the pixel in the i-th row of the display device to emit light.
【0135】
As will be described in detail later, each display horizontal scanning period is assigned to be longer than the time of the maximum pulse width of the modulated wiring on the corresponding scanning wiring.
【0136】
In order to make the pixels in the i-th row emit light, a pulse of the scanning selection voltage Vs is applied to the voltage supply terminal Dxi of the scanning wiring in the i-th row to make the selection state. Further, the voltage supply terminals Dxk (k = 1,2, ... M, where k i) of the other scanning wirings are put into the non-selection state by applying a pulse of the non-selection voltage Vns.
【0137】
In this example, the selective voltage Vs is set to -0.5 VSEL, which is half the voltage VSEL in Fig. 6, and the potential of the non-selective voltage Vns is the ground potential GND.
【0138】
A pulse width modulation signal with a voltage amplitude of Vpwm was supplied to the voltage supply terminal of the modulation wiring. Pulse width supplied to the j-th modulation wiring The pulse width of the modulation signal is determined according to the size (brightness level) of the image data of the pixels in the i-th row and j-th column of the image to be displayed, and is used for all modulation wirings. A pulse width modulation signal corresponding to the size of the image data of each pixel is supplied.
【0139】
In this embodiment, the voltage of the voltage Vpwm is set to +0.5 VSEL.
【0140】
As shown in FIG. 6, the surface-conducting emission element emits electrons when a voltage VSEL is applied to both ends of the element, but does not emit electrons at all when the applied voltage is smaller than the emission threshold value Vth.
【0141】
Further, as shown in FIG. 6, the voltage Vth is characterized in that it is larger than 0.5 VSEL.
【0142】
Therefore, electrons are not emitted from the surface-conducting emission element connected to the scanning wiring to which the non-selective voltage Vns is applied.
【0143】
Similarly, the period during which the output of the pulse width modulation means is at the ground potential (hereinafter referred to as the period when the output is L) is applied to both ends of the surface conductive emission element on the selected scanning wiring. Since the voltage of the voltage pulse is Vs, no electrons are emitted.
【0144】
From the surface-conduction emission element on the scanning wiring to which the selective voltage Vs is applied, electrons are emitted according to the period during which the output of the pulse width modulation means is Vpwm (hereinafter referred to as the period when the output is H). To. When the electrons are emitted, the above-mentioned phosphor emits light according to the amount of the emitted electron beam, so that the pixel can emit light with a brightness corresponding to the emitted time.
【0145】
An image is displayed by performing line sequential scanning for sequentially selecting the rows of such a display panel and performing pulse width modulation.
【0146】
Of the display horizontal scanning periods, the length of the selection period in which the selection voltage Vs is applied differs depending on the modulation signal, and the period in which the selection voltage Vs is not applied is a constant blanking provided as needed. It is a period.
【0147】
In this way, the display horizontal scanning period I is a period corresponding to the maximum value of the pulse width of the modulated signal supplied to the terminals Dy1 to DyN in that period, and the display horizontal scanning period I + 1 is the period corresponding to the terminals Dy1 to Dy1. It is a short period according to the maximum value of the pulse width of the modulated signal supplied to DyN, and the display horizontal scanning period I + 2 corresponds to the maximum value of the pulse width of the modulated signal supplied to terminals Dy1 to DyN. It has been a long period.
【0148】
Therefore, the brightness of the display horizontal scanning period I + 2 is improved.
【0149】
(Regarding the voltage drop in the scanning wiring) As described above, the voltage drop in the scanning wiring of the display panel raises the potential on the scanning wiring and reduces the voltage applied to the surface conduction type emission element. The emission current from the surface conduction type emission element may be reduced.
【0150】
Although it depends on the design specifications and manufacturing method of the surface-conduction type emission element, the element current for one element of the surface-conduction type emission element is about several hundred μA when the voltage VSEL is applied.
【0151】
Therefore, if only one pixel on the selected scanning wiring is made to emit light in a certain horizontal scanning period and the other pixels are not made to emit light, the element current flowing from the modulation wiring into the scanning wiring of the selected line is equivalent to one pixel. Since the current is only (that is, the above-mentioned several hundred μA), there is almost no voltage drop and the emission brightness is not reduced.
【0152】
However, when all the pixels in the selected row are made to emit light in a certain horizontal scanning period, the current for all the pixels flows into the scanning wiring selected from all the modulated wirings, so the total current is a number. It becomes 100mA to several A, and a large voltage drop occurs on the scanning wiring due to the wiring resistance of the scanning wiring.
【0153】
If a voltage drop occurs on the scanning wiring, the voltage applied to both ends of the surface-conducting emission element decreases. Therefore, the emission current emitted from the surface-conduction type emission element decreases, and as a result, the emission brightness decreases.
【0154】
Specifically, when a white cross-shaped pattern is displayed on a black background as shown in FIG. 8A as a display image, when row L is selected, the number of pixels to be lit is small. There is almost no voltage drop on the row scan wiring. As a result, a desired amount of emission current is emitted from the surface-conduction type emission element of each pixel, and light can be emitted with a desired brightness.
【0155】
On the other hand, when driving the row L', all the pixels on the row L'light up, so that a voltage drop occurs on the scanning wiring and the emission current of each pixel from the surface-conducting emission element decreases. To do. As a result, the brightness of the pixels on the row L'is reduced.
【0156】
In this way, the effect of the voltage drop changes due to the difference in the image data of the line for each scanning wiring. Therefore, when displaying the cross pattern as shown in FIG. 8 (a), the cross pattern shown in FIG. 8 (b) is displayed. An image like this was displayed.
【0157】
Note that this phenomenon is not limited to the cross pattern, but also occurs when, for example, a window pattern or a natural image is displayed.
【0158】
Further, more complicatedly, the magnitude of the voltage drop has a property of changing even within one horizontal scanning period by performing modulation by pulse width modulation.
【0159】
When the pulse width modulation signal supplied to each column outputs a pulse width modulation signal having a pulse width corresponding to the size of the data and having a synchronized rising edge with respect to the input data as shown in FIG. Although it depends on the input image data, in general, in one horizontal scanning period, the number of pixels that are lit immediately after the rise of the pulse is large, and then the lights are turned off in order from the place with the lowest brightness. The number of lit pixels decreases over time during a horizontal scanning period.
【0160】
Therefore, the magnitude of the voltage drop that occurs on the scanning wiring also tends to decrease gradually toward the beginning of one horizontal scanning period.
【0161】
Since the output of the pulse width modulated signal changes every time corresponding to one gradation of modulation, the temporal change of the voltage drop also changes every unit time corresponding to one gradation of the pulse width modulated signal.
【0162】
(Calculation method of voltage drop) The voltage drop has the following characteristics.
【0163】
i) At some point in the horizontal scanning period, the voltage drop that occurs on the scanning wiring is a spatially continuous quantity on the scanning wiring and is a very smooth curve.
【0164】
ii) The magnitude of the voltage drop varies depending on the displayed image, but it changes every time corresponding to one gradation of pulse width modulation, but roughly, it is larger at the rising part of the pulse and gradually becomes smaller in time. Either become or maintain its size. That is, in the drive method as shown in FIG. 7, since the modulation signals supplied to each modulation wiring rise at the same time, the magnitude of the voltage drop does not increase in one horizontal scanning period.
【0165】
Therefore, we tried to reduce the amount of calculation by simplifying the calculation using the following approximate model.
【0166】
First, from the feature of i), when calculating the magnitude of the voltage drop at a certain point in time, it is approximately simplified by a regression model that concentrates thousands of modulation wires into several to dozens of modulation wires. I tried to calculate.
【0167】
In addition, from the characteristics of ii), a plurality of reference times were set in one horizontal scanning period, and the time change of the voltage drop was roughly predicted by calculating the voltage drop for each reference time.
【0168】
Specifically, the time change of the voltage drop was roughly predicted by calculating the voltage drop by the regression model described below for a plurality of reference times.
【0169】
(Calculation of voltage drop by degeneracy model) FIG. 9A is a diagram for explaining blocks and nodes when performing degeneracy of the present invention.
【0170】
For the sake of simplicity, FIG. 9 shows only the selected scanning wiring, each modulation wiring, and the surface-conduction emission element connected to the intersection thereof.
【0171】
At a certain time in the horizontal scanning period, the lighting state of each pixel on the selected scanning wiring (that is, whether the output of the modulation means is "H" or "L") is known. It is assumed that there is.
【0172】
In this lighting state, the element current flowing into the scanning wiring selected from each modulation wiring is defined as Ifi (i = 1,2, ... N; i is the column number).
【0173】
Further, as shown in the figure, a block is defined as a group of n modulation wirings, a portion of the selected scanning wiring that intersects with the modulation wiring, and a surface-conduction emission element arranged at the intersection thereof. In this example, it was divided into four blocks by dividing it into blocks.
【0174】
In addition, a position called a node was set at the boundary position of each block. The node is a horizontal position (reference point) for discretely calculating the amount of voltage drop generated on the scanning wiring in the degenerate model.
【0175】
In this example, five nodes, node 0 to node 4, are set at the boundary position of the block.
【0176】
FIG. 9 (b) is a diagram for explaining a degenerate model.
【0177】
In the degenerate model, the n degenerate wirings included in one block in Fig. 9 (a) are degenerated into one, and one degenerate modulation wiring is connected so as to be located in the center of the scanning wiring block. ..
【0178】
Further, a current source is connected to the modulation wiring of each degenerate block, and the total currents IF0 to IF3 in each block flow from each current source.
【0179】
That is, IFj (j = 0,1, ... 3) is a current expressed as in (Equation 1) of Equation 1.
[Number 1]
<img file="JP2003228317A_D0001.tif" />【0180】
Further, in the example of FIG. 9 (a), the potentials at both ends of the scanning wiring are the same as the output voltage Vs of the row drive circuit, whereas in FIG. 9 (b), the GND potential is set as the GND potential in the reduced model. By modeling the current flowing into the scanning wiring selected from the modulated wiring by the above current source, the voltage drop amount of each part on the scanning wiring is calculated by using the feeding part as the reference potential (GND) and the voltage (potential difference) of each part. This is because it can be calculated. That is, it is defined as a reference potential for calculating the voltage drop.
【0181】
Further, the omission of the surface-conduction type emission element is generated regardless of the presence or absence of the surface-conduction type emission element when the same current flows from the modulation wiring when viewed from the selected scanning wiring. This is because the voltage drop itself does not change. Therefore, here, the surface-conduction type emission element is ignored by setting the current value flowing from the current source of each block to the current value (Equation 1) of the sum of the element currents in each block.
【0182】
The wiring resistance of the scanning wiring of each block was set to n times the wiring resistance r of the scanning wiring of one section. Here, one section refers to the section of the scanning wiring between the intersection with a certain modulation wiring and the intersection with the modulation wiring next to it. Further, in this example, it is assumed that the wiring resistance of the scanning wiring in one section is uniform.
【0183】
In such a degenerate model, the voltage drops DV0 to DV4 generated at each node on the scanning wiring can be easily calculated by the product-sum format formula as shown in Equation 2.
[Number 2]
<img file="JP2003228317A_D0002.tif" />【0184】
The equation of Equation 2 can be expressed as (Equation 2) of Equation 3.
[Number 3]
<img file="JP2003228317A_D0003.tif" />【0185】
However, in (Equation 2), aij is the voltage generated at the i-th node when the unit current is injected only into the j-th block in the degenerate model. (Hereafter, this is the definition of aij.) Aij can be easily derived as follows by Kirchhoff's law.
【0186】
That is, in FIG. 9B, the wiring resistance to the supply terminal on the left side of the scanning wiring viewed from the current source of block i is rli (i = 0,1,2,3,4), and the wiring to the supply terminal on the right side. The resistance is defined as rri (i = 0,1,2,3,4), and the wiring resistance between block 0 and the left supply terminal and the wiring resistance between block 4 and the right supply terminal are both defined as rt. Then it becomes like the number 4.
[Number 4]
<img file="JP2003228317A_D0004.tif" />【0187】
Furthermore, if it is set as in Eq. 5, aij can be easily derived as shown in Eq. 6 (Equation 3). However, in Equation 5, A // B is a symbol representing the parallel resistance value of the resistor A and the resistor B, and A // B = A × B / (A + B).
[Number 5]
<img file="JP2003228317A_D0005.tif" />[Number 6]
<img file="JP2003228317A_D0006.tif" />【0188】
(Equation 2) can be easily calculated by Kirchhoff's law, even if the number of blocks is not 4, by considering the definition of aij. Further, even in the case where the power feeding terminals are not provided on both sides of the scanning wiring as in this example but only on one side, the calculation can be easily performed by calculating according to the definition of aij.
【0189】
The parameter aij defined by (Equation 3) does not need to be recalculated every time the calculation is performed, and it is sufficient to calculate once and store it as a table.
【0190】
Furthermore, the total currents IF0 to IF3 of each block defined in (Equation 1) were approximated as shown in Equation 7 (Equation 4).
[Number 7]
<img file="JP2003228317A_D0007.tif" />【0191】
However, in (Equation 4), Count i is a variable that takes 1 when the i-th pixel on the selected scanning line is in the lit state and 0 when it is in the off state. IFS is the amount obtained by multiplying the element current IF that flows when a voltage VSEL is applied to both ends of one surface-conducting emission element by a coefficient α that takes a value between 0 and 1.
【0192】
That is, it is defined as shown in Equation 8 (Equation 5).
[Number 8]
<img file="JP2003228317A_D0008.tif" />【0193】
In (Equation 4), it is assumed that the element current proportional to the number of lights in the block flows from the modulated wiring of each block to the selected scanning wiring. At this time, the element current IF of one element multiplied by the coefficient α is defined as the element current IFS of one element in consideration of the fact that the amount of element current decreases as the voltage of the scanning wiring increases due to the voltage drop. did.
【0194】
FIG. 9 (c) is an example of the result of calculating the voltage drop amount DV0 to DV4 of each node by the degenerate model in a certain lighting state.
【0195】
Since the voltage drop is a very smooth curve, it is assumed that the voltage drop between nodes will approximately take the value shown by the dotted line in the figure.
【0196】
As described above, by using this degenerate model, it is possible to calculate the voltage drop at the position of the node at a desired time point with respect to the input image data.
【0197】
As described above, the amount of voltage drop in a certain lighting state was simply calculated using the degenerate model.
【0198】
The voltage drop that occurs on the selected scan wiring changes over time within a horizontal scan period, which is the lighting state at that time for some time during the horizontal scan period, as described above. Was obtained and predicted by calculating the voltage drop using the contraction model for the lighting state.
【0199】
The number of lights in each block at a certain point in one horizontal scanning period can be easily obtained by referring to the image data of each block.
【0200】
Now, as an example, it is assumed that the number of bits of the input data to the pulse width modulation circuit is 8 bits, and the pulse width modulation circuit outputs a pulse width linear with respect to the size of the input data.
【0201】
That is, when the input data is 0, the output is "L", when the input data is 255, "H" is output during one horizontal scanning period, and when the input data is 128, the first of the one horizontal scanning period. It is assumed that "H" is output for half the period and "L" is output for the other half period.
【0202】
In such a case, the number of lights at the start time of the pulse width modulation signal (the rise time in the example of the modulation signal in this example) can be easily determined by counting the number of input data to the pulse width modulation circuit larger than 0. Can be detected.
【0203】
Similarly, the number of lights at the center time of one horizontal scanning period can be easily detected by counting the number of input data to the pulse width modulation circuit larger than 128.
【0204】
By comparing the image data with respect to a certain threshold value and counting the number of true output of the comparator in this way, the number of lights at an arbitrary time can be easily calculated.
【0205】
Here, for the sake of simplification of the following explanation, a time slot called a time slot is defined.
【0206】
That is, the time slot represents the time from the start time (the rising edge of the pulse in the above example) of the pulse width modulation signal in one horizontal scanning period, and time slot = 0 means the pulse width modulation. It is defined as representing the time immediately after the start time of the signal.
【0207】
Time slot = 64 is defined as representing the time when 64 gradations of time have elapsed from the start time of the pulse width modulation signal.
【0208】
Similarly, "time slot = 128" is defined as representing the time when 128 gradations of time have elapsed from the start time of the pulse width modulation signal.
【0209】
In this example, the pulse width modulation shows an example in which the pulse width is modulated based on the rise time, but similarly, even when the pulse width is modulated based on the pulse fall time, the time is used. It goes without saying that the direction in which the axis advances and the direction in which the time slot advances are opposite, but the same can be applied.
【0210】
(Calculation of correction data from the amount of voltage drop) As described above, the time change of the voltage drop during one horizontal scanning period could be calculated approximately and discretely by performing the iterative calculation using the regression model. ..
【0211】
FIG. 10 shows an example in which the voltage drop is repeatedly calculated for a certain image data and the time change of the voltage drop in the scanning wiring is calculated (the voltage drop shown here and the time change thereof are a certain image. It is an example of data, and it is natural that the voltage drop for another image data makes another change.)
【0212】
In the figure, the voltage drop at each time was calculated discretely by applying the degenerate model to each of the four time points of time slot = 0,64,128,192.
【0213】
In Fig. 10, the amount of voltage drop at each node is connected by a dotted line, but the dotted line is shown to make the figure easier to see, and the voltage drop calculated by this degenerate model is indicated by , , and . Calculated discretely at the position of each node.
【0214】
The inventors tried a method of calculating correction data for correcting image data from the amount of voltage drop as the next step in which the magnitude of the voltage drop and its time change could be calculated.
【0215】
FIG. 11 is a graph in which the emission current emitted from the surface-conducting emission element in the lit state is estimated when the voltage drop shown in FIG. 10 occurs on the selected scanning wiring.
【0216】
The vertical axis represents the amount of emission current at each position at each time as a percentage, assuming that the magnitude of the emission current emitted when there is no voltage drop is 100%, and the horizontal axis represents the horizontal position.
【0217】
As shown in FIG. 11, at the horizontal position (reference point) of node 2. Emission current when time slot = 0 is Ie0, Emission current when time slot = 64 is Ie1, Emission current when time slot = 128 is Ie2, Ie3 emission current when time slot = 192 And.
【0218】
The figure was calculated from the graph of the voltage drop in Fig. 10 and the drive voltage vs. emission current in Fig. 6. Specifically, it is simply a mechanical plot of the value of the emission current when a voltage obtained by subtracting the voltage drop from the voltage VSEL is applied.
【0219】
Therefore, the figure only means the current emitted from the surface-conduction type emission element in the lit state, and the surface-conduction type emission element in the off state does not emit the current.
【0220】
Two methods will be described below as a method of calculating the correction data for correcting the image data from the voltage drop amount.
【0221】
A) First correction data calculation method 12 (a), 12 (b), and 12 (c) are diagrams for explaining the first method of calculating the correction data of the voltage drop from the time change of the emission current of FIG.
【0222】
FIG. 12A is a diagram for explaining a method of calculating correction data for image data having a size of 64 at the position of node 2. The figure schematically shows the pulse waveform of the pulse width-modulated emission current, the wave height of the pulse waveform represents the amount of emission current, and the pulse width of the pulse waveform represents the time when the emission current is emitted. The pulse width of the pulse waveform is a time corresponding to 64 gradations. In order to simplify the explanation, for example, the pulse width may be described as 64 by simplifying the length corresponding to 64 gradations of the pulse width modulation signal.
【0223】
Here, when a pulse width modulated signal having a pulse width of 64 is output at the node 2 position, the loss of the emission current due to the voltage drop is approximately the trapezoid shown in Loss 1 of the figure (a). It was decided to calculate as the area of. This calculation formula (Equation 6) is shown in Equation 9.
[Number 9]
<img file="JP2003228317A_D0009.tif" />【0224】
Therefore, in order to compensate for the total loss of the emitted current, the pulse width to be added to the modulated signal in order to extend the pulse width of the modulated signal, that is, the correction data CData to be added to the image data is approximately several tens ( It was calculated as in Equation 7).
[Number 10]
<img file="JP2003228317A_D0010.tif" />【0225】
The reason why the loss Loss is divided by Ie1 in (Equation 7) is that the emission current at the time slot of 64 is Ie1, and the amount of emission current during the period when the pulse width is expanded by the correction is Ie1. Was approximated to be equal to.
【0226】
Similarly, when a pulse width modulated signal with a pulse width of 128 is output at the position of node 2, the loss of the amount of emission current decrease due to the voltage drop is approximately the same as Loss1 and Loss2 in the figure (b). Calculated as the sum of the two trapezoids shown. That is, it was calculated as in (Equation 8) of Equation 11.
[Number 11]
<img file="JP2003228317A_D0011.tif" />【0227】
Therefore, the pulse width to be added, that is, the correction data CData to be added to the image data having a size of 128 was approximately calculated as shown in Equation 12 (Equation 9).
[Number 12]
<img file="JP2003228317A_D0012.tif" />【0228】
Similarly, when a pulse width modulated signal with a pulse width of 192 is output at the position of node 2, the decrease in the amount of emitted current due to the voltage drop is approximately the same as Loss1 and Loss2 in the figure (c). Calculated as the sum of the three trapezoids shown in Loss3. That is, it was calculated as in (Equation 10) of Equation 13.
[Number 13]
<img file="JP2003228317A_D0013.tif" />【0229】
Therefore, the correction data CData for the image data of size 192 can be approximately calculated as in Equation 11 of Equation 14.
[Number 14]
<img file="JP2003228317A_D0014.tif" />【0230】
Further, when the pulse width of the modulated signal is 0, the voltage drop has no effect on the emission current, so the correction data is set to 0 and the correction data to be added to the image data is also set to 0.
【0231】
By repeating such work, the correction data for the modulated signals with pulse widths of 0,64,128,192 at all nodes were calculated discretely.
【0232】
In this example, the contraction model is applied to the four points of time slots 0,64,128,192, and the voltage drop amount at each time is calculated, so that the correction data is also obtained for the four points of pulse width 0,64,128,192. I was able to do it.
【0233】
However, preferably, by making the time interval for calculating the voltage drop finer by the contraction model, the time change of the voltage drop can be handled more precisely, and the error of the approximate calculation can be reduced.
【0234】
In that case, the calculation may be performed by modifying (Equation 6) to (Equation 11) based on the same idea.
【0235】
FIG. 13A is an example of the result of discretely calculating the correction data for the image data = 0,64,128,192 at the position of each node for the input data by the above method.
【0236】
In the figure, discrete correction data for the same image data are shown by connecting them with a dotted line curve in order to make the figure easier to see.
【0237】
B) Second correction data calculation method 14 (a), (b), and (c) are diagrams for explaining the second method of calculating the correction data of the voltage drop amount from the time change of the emission current of FIG. The figure is an example of calculating correction data for image data of size 64.
【0238】
The amount of emission of luminance is nothing but the amount of emitted charge obtained by integrating the emission current due to the emission current pulse over time. Therefore, in the following, when considering the fluctuation of the brightness due to the voltage drop, the explanation will be given based on the amount of emitted charge.
【0239】
Now, if the emission current when there is no influence of voltage drop is IE and the time corresponding to one gradation of pulse width modulation is Δt, the emission that should be emitted by the emission current pulse when the image data is 64. The amount of charge Q0 can be calculated by multiplying the emission current pulse amplitude IE by the pulse width (64 × Δt) as shown in Equation 15 (Equation 12).
[Number 15]
<img file="JP2003228317A_D0015.tif" />【0240】
However, in reality, a phenomenon occurs in which the emission current decreases due to the voltage drop on the scanning wiring.
【0241】
The amount of charge emitted by the emission current pulse in consideration of the influence of the voltage drop can be approximately calculated as follows. That is, if the emission currents of the time slots = 0 and 64 of node 2 are Ie0 and Ie1, respectively, and the emission current between 0 and 64 is approximated to linearly change between Ie0 and Ie1, the emission during this period is approximated. The amount of charge Q1 can be calculated as the area of the trapezoid in FIG. 14 (b), that is, as shown in Equation 16 (Equation 13).
[Number 16]
<img file="JP2003228317A_D0016.tif" />【0242】
Next, as shown in FIG. 14 (c), it is assumed that the influence of the voltage drop can be eliminated when the pulse width is extended by DC1 in order to compensate for the decrease in the emission current due to the voltage drop.
【0243】
In addition, when the voltage drop is corrected and the pulse width is extended, the amount of emitted current in each time slot is considered to change, but for the sake of simplicity, the time slot is shown in FIG. 14 (c). At = 0, it is assumed that the emission current is Ie0 and the emission current in the time slot = (64 + DC1) is Ie1.
【0244】
Also, the emission current between time slot 0 and time slot (64 + DC1) is close to the value on the line connecting the emission currents at two points with a straight line. Then, the amount of charge Q2 emitted by the corrected emission current pulse can be calculated as shown in Equation 17 (Equation 14).
[Number 17]
<img file="JP2003228317A_D0017.tif" />【0245】
If this is equal to Q0 described above, it becomes the equation of Eq. 18, and if this equation is solved for DC1, it becomes (Equation 15) of Eq. 19.
[Number 18]
<img file="JP2003228317A_D0018.tif" />[Number 19]
<img file="JP2003228317A_D0019.tif" />【0246】
In this way, the correction data when the image data is 64 was calculated.
【0247】
That is, for the image data in which the size of the position of the node 2 is 64, the correction amount CData may be added by CData = DC1 as described in (Equation 15).
【0248】
FIG. 15 shows an example in which correction data for image data having a size of 128 is calculated from the calculated voltage drop amount.
【0249】
Now, when there is no influence of the voltage drop, the amount of discharged charge Q3 to be released by the emission current pulse when the image data is 128 can be calculated as in Equation 20 (Equation 16).
[Number 20]
<img file="JP2003228317A_D0020.tif" />【0250】
On the other hand, the amount of input charge due to the actual emission current pulse affected by the voltage drop can be approximately calculated as follows.
【0251】
That is, let the emission current amounts of the time slots = 0, 64, 128 of node 2 be Ie0, Ie1, and Ie2, respectively. Also, the emission current between 0 and 64 changes linearly between Ie0 and Ie1, and between 64 and 128 changes on the line connecting Ie1 and Ie2 with a straight line. The amount of charged charge Q4 between the time slots from to 128 can be calculated as the sum of the areas of the two trapezoids in Fig. 15 (b), that is, equation 21 (Equation 17).
[Number 21]
<img file="JP2003228317A_D0021.tif" />【0252】
On the other hand, the correction amount of the voltage drop was calculated as follows.
【0253】
The period corresponding to time slots 0 to 64 is defined as period 1, and the period corresponding to 64 to 128 is defined as period 2.
【0254】
It is considered that when the correction is applied, the part of the period 1 is extended by DC1 and extended to the period 1', and the part of the period 2 is extended by DC2 and extended to the period 2'.
【0255】
At this time, it is assumed that the amount of discharged charge becomes the same as that of Q0 described above by making corrections for each period.
【0256】
It goes without saying that the emission currents at the beginning and end of each period change by making corrections, but for the sake of simplicity of calculation, it is assumed that they do not change.
【0257】
That is, it is assumed that the emission current at the beginning of period 1'is Ie0, the emission current at the end of period 1'is Ie1, the emission current at the beginning of period 2'is Ie1, and the emission current at the end of period 2'is Ie2. ..
【0258】
Then, DC1 can be calculated in the same manner as in (Equation 15).
【0259】
Moreover, DC2 can be calculated as shown in Equation 22 (Equation 18) by the same idea.
[Number 22]
<img file="JP2003228317A_D0022.tif" />【0260】
As a result, the correction amount CData obtained by (Equation 19) of Equation 23 may be added to the image data whose position size of node 2 is 128.
[Number 23]
<img file="JP2003228317A_D0023.tif" />【0261】
FIG. 16 shows an example in which correction data for image data having a size of 192 is calculated from the calculated voltage drop amount.
【0262】
Now, when the image data is 192, the amount of charge Q5 emitted by the emission current pulse expected is as shown in equation 24.
[Number 24]
<img file="JP2003228317A_D0024.tif" />【0263】
On the other hand, the amount of charge emitted by the actual emission current pulse affected by the voltage drop can be approximately calculated as follows.
【0264】
That is, the emission current when the time slot = 0 of node 2 is Ie0, the emission current when the time slot = 64 is Ie1, the emission current when the time slot = 128 is Ie2, and the emission current when the time slot = 192. Is Ie3, and the emission current between 0 and 64 changes linearly between Ie0 and Ie1, and between 64 and 128 changes on the line connecting Ie1 and Ie2 with a straight line, and between 128 and 192. If the interval is approximated to change on the line connecting Ie2 and Ie3 with a straight line, the input charge amount Q6 between the time slots from 0 to 192 is the area of the three trapezoids in Fig. 16 (c), that is, , Can be calculated as (Equation 20) of Eq. 25.
[Number 25]
<img file="JP2003228317A_D0025.tif" />【0265】
On the other hand, the correction amount of the voltage drop was calculated as follows.
【0266】
The period corresponding to time slots 0 to 64 is defined as period 1, the period corresponding to 64 to 128 is defined as period 2, and the period corresponding to 128 to 192 is defined as period 3.
【0267】
As before, after the correction, the period 1 part is extended by DC1 and extended to period 1', the period 2 part is extended by DC2 and extended to period 2', and the period 3 part is extended. It is considered that it is extended by DC3 and extended to the period 3'.
【0268】
At this time, it is assumed that the amount of discharged charge becomes the same as that of Q0 described above by making corrections for each period.
【0269】
It was also assumed that the emission currents at the beginning and end of each period did not change before and after the correction.
【0270】
That is, the emission current at the beginning of period 1'is Ie0, the emission current at the end of period 1'is Ie1, the emission current at the beginning of period 2'is Ie1, the emission current at the end of period 2'is Ie2, and the emission current at period 3'is. It is assumed that the initial emission current is Ie3 and the emission current at the end of period 3'is Ie4.
【0271】
Then, DC1 and DC2 can be calculated in the same manner as in (Equation 15) and <Equation 18), respectively.
【0272】
In addition, DC3 can be calculated as in Equation 26 (Equation 21).
[Number 26]
<img file="JP2003228317A_D0026.tif" />【0273】
As a result, as the correction data CData to be added to the image data whose position size of node 2 is 192, the value obtained by (Equation 22) of Equation 27 may be added.
[Number 27]
<img file="JP2003228317A_D0027.tif" />【0274】
As described above, the correction data CData of the image data 64,128,192 with respect to the position of the node 2 was calculated.
【0275】
When the pulse width is 0, the voltage drop has no effect on the emission current, so the correction data is set to 0 and the correction data CData to be added to the image data is also set to 0.
【0276】
So far, two methods have been described for calculating correction data for the size of discrete image data at discrete horizontal positions (nodes).
【0277】
In any of the methods, the correction data is calculated for the discrete image data such as 0,64,128,192 in order to reduce the amount of calculation.
【0278】
That is, if the same calculation is performed on all arbitrary image data, the amount of calculation becomes very large, and the amount of hardware for performing the calculation becomes very large.
【0279】
On the other hand, at the position of a certain node, the larger the image data, the larger the correction data tends to be. As a result, when calculating the correction data for arbitrary image data, the amount of calculation can be significantly reduced by interpolating the points in the vicinity of the image data for which the correction data has already been calculated by linear approximation. This is because it can be done. This interpolation will be described in detail when the discrete correction data interpolation means is described.
【0280】
Further, if the same idea is applied to the positions of all the nodes, the correction data of the image data = 0,64,128,192 at the positions of all the nodes can be calculated.
【0281】
The discrete image data for which the correction data is calculated in this way is called an image data reference value.
【0282】
In this example, the contraction model is applied to the four points of 0,64,128,192 in the time slot, and the voltage drop amount at each time is calculated, so that the correction data is also the four image data reference values of 0,64,128,192. I was able to obtain the correction data for.
【0283】
However, preferably, by making the time interval for calculating the voltage drop finer by using the contraction model, the time change of the voltage drop can be handled more precisely, and the number of discrete image data reference values increases while approximating. Calculation errors can be reduced.
【0284】
Specifically, in FIGS. 14 to 16, in order to simplify the figure, the calculation was performed only at four points of time slots 0,64,128,192, but in reality, every 16 time slots out of time slots 0 to 255 are calculated. When the calculation was performed (that is, the reference value of the image data was set every 16 according to the size of the image data), it was preferable.
【0285】
In that case, the calculation may be performed by modifying (Equation 6) to (Equation 11) or (Equation 12) to (Equation 22) based on the same idea.
【0286】
When the correction data for the image data = 0,64,128,192 at the position of each node was calculated discretely for a certain input data by the above method, the same result as in FIG. 13 (a) was obtained.
【0287】
(Interpolation method of discrete correction data) The correction data calculated discretely is discrete with respect to the position of each node, and does not give correction data at an arbitrary horizontal position (row wiring number). At the same time, the correction data for the image data having the size of some predetermined reference values of the image data at each node position and the correction data for the size of the actual image data is not given. Absent.
【0288】
Here, the correction data suitable for the size of the input image data in each column wiring was calculated by interpolating the correction data calculated discretely.
【0289】
FIG. 13B is a diagram showing a method of calculating correction data corresponding to image data Data at a position of x located between node n and node n + 1.
【0290】
As a premise, it is assumed that the correction data has already been calculated discretely at the positions Xn and Xn + 1 of the node n and the node n + 1.
【0291】
Further, the image data Data shall take a value between Dk and Dk + 1 of the image data reference value, which is the image data for which the correction data has already been calculated discretely.
【0292】
Now, if the discrete correction data for the reference value of the kth image data of node n is expressed as CData [k] [n], the correction data CA of the pulse width Dk at position x is CData [k] [n]. ] And the values of CData [k] [n + 1], it can be calculated as shown in Equation 28 (Equation 23) by linear approximation.
[Number 28]
<img file="JP2003228317A_D0028.tif" />【0293】
However, Xn and Xn + 1 are the horizontal display positions of the nodes n and (n + 1), respectively, and are constants determined when determining the block described above.
【0294】
Further, the correction data CB of the image data Dk + 1 at the position x can be calculated as in (Equation 24) of Equation 29.
[Number 29]
<img file="JP2003228317A_D0029.tif" />【0295】
By linearly approximating the correction data of CA and CB, the correction data CD for the image data Data at position x can be calculated as in (Equation 25) of Eq. 30.
[Number 30]
<img file="JP2003228317A_D0030.tif" />【0296】
As described above, in order to calculate the correction data suitable for the actual position and the size of the image data from the discrete correction data, it can be easily calculated by the methods described in Equations 23 to 25.
【0297】
If the correction data calculated in this way is added to the image data to correct the image data, and pulse width modulation is performed according to the corrected image data (corrected image data), the display image has been a problem in the past. The influence of the voltage drop in the above can be reduced, and the image quality can be improved.
【0298】
Also, regarding the hardware for correction, which has been an issue for some time, the amount of calculation can be reduced by introducing approximations such as degeneracy as explained so far, so it is a very small-scale hardware. It has the excellent merit of being able to be configured with hardware.
【0299】
By the way, it has been clarified that the problem of the decrease in brightness caused by the voltage drop of the scanning wiring can be solved by the above-mentioned correction method, but there is a point to be noted when producing a circuit that realizes such a function.
【0300】
In a digital circuit, there is a limit to the data width (number of bits) that can be handled by the circuit. This data width is generally determined in consideration of the cost of hardware and the like.
【0301】
The increase in the corrected image data due to the addition of the corrected data may cause a so-called overflow problem. That is, when the correction data is simply added to the image data, if the calculation result exceeds the data width that can be handled by the pulse width modulator (modulation circuit 8), bit wrapping or the like occurs. Image distortion such as inversion of the displayed image occurs.
【0302】
Therefore, in the present embodiment, the maximum value of the corrected image data is calculated in advance, and a pulse width modulator having a bit width corresponding to the maximum value is provided.
【0303】
However, for the correction that requires extending the drive time, limit the drive time to the maximum time limited by the realistically determined horizontal scanning time (horizontal scanning time determined by the input image signal). As a result, the brightness of the entire display image is reduced due to the decrease in brightness.
【0304】
Therefore, in the present embodiment, as described above, the scanning time (selection time) of each scanning wiring is appropriately allocated for each frame according to the maximum value of the corrected image data for each horizontal scanning line (scanning wiring).
【0305】
(Explanation of functions of the entire system and each part) Next, the hardware of the image display device having a built-in correction data calculation means will be described.
【0306】
FIGS. 17, 18, and 19 are block diagrams showing an outline of the circuit configuration. FIG. 17 shows a signal processing circuit for inputting a video signal and correcting the input video signal, FIG. 18 shows a drive control circuit for determining a scanning wiring selection period, that is, a horizontal scanning period, and FIG. 19 shows a drive control circuit. , Display panel, scanning drive circuit and modulation drive circuit are shown respectively. The output Dout of the circuit shown in FIG. 17 is input to the circuit shown in FIG. Further, the outputs SD1 to SD8 of the circuit shown in FIG. 18 are input to the circuit shown in FIG.
【0307】
In FIG. 17, 13 is a synchronization signal separation circuit that separates an input video signal into a video signal and a synchronization signal, and 11 is a timing generation circuit that generates a timing signal of each part based on the synchronization signal separated by the synchronization signal separation circuit 13. Reference numeral 7 denotes an RGB conversion means for converting the luminance and color difference signals (YPbPr) separated by the synchronization signal separation circuit 13 into three primary color signals (RGB).
【0308】
Since the video output of a computer is input as a parallel three primary color signal (RGB), in this case, it is not necessary to go through the RGB conversion means 7.
【0309】
In addition, 17 is an inverse γ processing unit that performs inverse γ conversion on an RGB signal, 9 is a data array conversion unit that converts an RGB parallel signal into a serial signal, and 14 is for correcting the voltage drop of the scanning wiring based on the input image data. A correction data calculation means for calculating correction data, 19 is a delay circuit, and 12 is an adder for correcting image data using the correction data calculated by the correction data calculation means 14.
【0310】
In the figure, R, G, and B are RGB parallel input video data, Ra, Ga, and Ba are RGB parallel video data that has undergone inverse γ conversion processing, and SData is parallel and serially converted by the data array conversion unit 9. The serial image data, Data is the delayed serial image data, CD is the correction data calculated by the correction data calculation means 14, and Dout is corrected by adding the correction data CD to the serial image data Data by the adder 12. Image data (corrected image data).
【0311】
In FIG. 18, 26 and 27 are frame memories for temporarily storing corrected image data, memory A and memory B, 21 is a W address generator that generates a write address signal for memories A and B, and 28 is a W address generator. The R address generators 23, 24, 25, and 29 that generate the read address signals from the memories A and B indicate switches that appropriately switch the input and output of the memories A and B, respectively.
【0312】
Further, in the figure, 22 is a line maximum value detector that detects the maximum value of the corrected image data for each horizontal scanning line (scanning wiring), and 34 is the maximum value of the corrected image data detected by the line maximum value detector 22. A microcomputer that calculates and processes the scanning time of each horizontal scanning line (scanning wiring) according to a value, 33 indicates a display timing generating unit that receives a calculation result of the microcomputer 34 and generates a display timing signal.
【0313】
In FIG. 19, 1 is a display panel as shown in FIG. 4, Dx1 to DxM and Dx1'to DxM' are voltage supply terminals for scanning wiring of the display panel, and Dy1 to DyN are voltage supply terminals for modulation wiring of the display panel. Hv indicates a high-voltage supply terminal for applying an acceleration voltage between the face plate and the rear plate, and Va indicates a high-voltage power supply. Further, 2A and 2B are scanning drive circuits that supply scanning signals to each scanning wiring. 5 is 8 shift registers to which outputs SD1 to SD8 from memory A26 or memory B27 are input, 6 is a latch circuit for 1 line of image data, and 8 is a modulated signal whose pulse width is modulated according to the corrected image data. A pulse width modulation circuit that outputs (voltage pulse) to each modulation wiring of the display panel 1 is shown, and a modulation drive circuit is composed of a shift register 5, a latch circuit 6, and a modulation circuit 8.
【0314】
(Synchronous signal separation circuit, timing generation circuit) The image display device of the present embodiment can display a television signal such as NTSC, PAL, SECAM, HDTV, or VGA which is an output of a computer. it can.
【0315】
FIG. 17 describes an example in which the 720p HDTV system is input.
【0316】
The frame frequency of the input image signal 720p is 60Hz, and the horizontal frequency is 45kHz. That is, the total number of scanning lines is 750, of which 720 lines are effective scanning lines.
【0317】
From the input 720p video signal, the synchronization signals Vsync and Hsync are first separated by the synchronization signal separation circuit 13. The synchronously separated vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are supplied to the timing generation circuit 11, and the synchronously separated video signal is supplied to the RGB conversion means 7. Inside the RGB conversion means 7, in addition to the conversion circuit from the brightness and color difference signal YPbPr to the three primary color signals RGB, a low-pass filter (not shown), an A / D converter, etc. are provided, and the signal YPbPr is converted to digital RGB. It is converted into a signal and supplied to the inverse γ processing unit 17.
【0318】
The timing generation circuit 11 has a built-in PLL circuit, generates a timing signal synchronized with the synchronization signals of various video sources, and generates an operation timing signal of each part.
【0319】
Examples of the timing signal generated by the timing generation circuit 11 include a sampling clock MCLK having a predetermined sampling frequency, a timing signal HD for horizontal scanning, and a timing signal VD for vertical scanning.
【0320】
In the present embodiment, the number of sample clocks in one horizontal scanning period (1H) is designed to be 1648, and 1280 of them is set as the number of effective pixels. Therefore, the sampling frequency MCLK is generated by dividing the horizontal synchronization signal by the frequency division ratio of 1: 1648 by the PLL circuit, and the sampling clock MCLK having a sampling frequency of 74.16 MHz is obtained.
【0321】
(Inverse γ processing unit) The CRT has a light emission characteristic of approximately 2.2 powers with respect to the input (hereinafter referred to as the inverse γ characteristic).
【0322】
Therefore, such a characteristic of the CRT has already been taken into consideration in the input video signal, and the input video signal is generally converted according to the γ characteristic of 0.45 so as to have a linear emission characteristic when displayed on the CRT.
【0323】
On the other hand, when the display panel of the present embodiment is modulated by the application time of the drive voltage, the input video signal is converted based on the inverse γ characteristic because it has a light emission characteristic that is substantially linear with respect to the length of the application time. It is necessary to perform (hereinafter referred to as inverse γ conversion).
【0324】
FIG. 20 is a block diagram showing a configuration of an inverse γ processing unit 17 for inverse γ conversion of an input video signal.
【0325】
The inverse γ processing unit 17 of the present embodiment configures the inverse γ conversion process with a memory.
【0326】
As shown in FIGS. 17 and 20, the inverse γ processing unit 17 has 8 bits for the video signals R, G, and B, and the bits of the video signals Ra, Ga, and Ba, which are the outputs of the inverse γ processing unit 17. The number is also 8 bits, and a memory with 8 bits for address and 8 bits for data is used for each color.
【0327】
In each memory, the inverse γ characteristics shown in FIG. 21 are stored as the R table 17R, the G table 17G, and the B table 17B. Note that FIG. 21A shows the data described in the tables 17R, 17G, and 17B in which the input video signal of the conversion table is in the range of 0 to 255. Further, FIG. 21 (b) shows an enlarged display of the input image data in the range of 0 to 48.
【0328】
In the present embodiment, the inverse γ processing unit 17 is configured as an 8-bit input and 8-bit output memory, but in order to improve the conversion accuracy of the inverse γ processing, for example, an 8-bit input and 10-bit output memory is used in reverse. A γ processing unit can also be configured. At this time, it is advisable to store the table of input / output characteristics of 8-bit input and 10-bit output shown in FIG. 21 in the same memory. In FIG. 21, the scale on the left side of the vertical axis of the graph of the 8-bit table and the vertical axis of the graph of the 10-bit table are set to the scale on the right side of FIG. 21 so that the 8-bit table and the 10-bit table can be easily compared. Is displayed.
【0329】
(Data array conversion unit) The data array conversion unit 9 is a circuit that performs parallel / serial conversion of RGB parallel video signals Ra, Ga, and Ba according to the pixel arrangement of the display panel 1. As shown in FIG. 22, the configuration of the data array conversion unit 9 is composed of FIFO (First In First Out) memories 2021R, 2021G, 2021B and selector 2022 for each RGB color.
【0330】
Although not shown in FIG. 22, the FIFO memory has two horizontal pixel-number-word memories, one for odd-numbered lines and one for even-numbered lines. When the video data of the odd-numbered lines is input, the data is written to the FIFO for the odd-numbered lines, while the image data accumulated in the previous horizontal scanning period is read from the FIFO memory for the even-numbered lines. When the video data of the even-numbered lines is input, the data is written to the FIFO for the even-numbered lines, while the image data accumulated in the previous horizontal scanning period is read from the FIFO memory for the odd-numbered lines.
【0331】
The data read from the FIFO memory is parallel-serial converted by the selector 2022 according to the pixel arrangement of the display panel, and is output as RGB serial image data SData. Although the details are not described, the operation is based on the timing control signal from the timing generation circuit 11.
【0332】
(Correction data calculation means) The correction data calculation means 14 is a circuit for calculating the correction data of the voltage drop by the correction data calculation method described above. As shown in FIG. 23, the correction data calculation means is composed of two blocks, a discrete correction data calculation unit 141 and a correction data interpolation unit 142.
【0333】
The discrete correction data calculation unit 141 is a means for calculating the voltage drop amount from the input image signal and discretely calculating the correction data from the voltage drop amount. This means introduces the concept of the degenerate model described above in order to reduce the amount of calculation and the amount of hardware, and calculates the correction data discretely.
【0334】
The discretely calculated correction data is interpolated by the correction data interpolation unit 142, and a correction data CD suitable for the size of the image data and its horizontal display position x is calculated.
【0335】
(Discrete Correction Data Calculation Unit) FIG. 24 is a block diagram showing an outline of a circuit configuration of the discrete correction data calculation unit 141 for calculating the discrete correction data of the present embodiment.
【0336】
As described below, the discrete correction data calculation unit 141 divides the image data into blocks, calculates the statistic (number of lights) for each block, and changes the voltage drop amount over time at the position of each node from the statistic. A function as a voltage drop calculation unit that calculates the amount of light emission, a function that converts the amount of voltage drop for each time into an amount of emission brightness, and a function that integrates the amount of emission brightness in the time direction to calculate the total amount of emission brightness. It is a means for calculating correction data for a reference value of image data at a discrete reference point from them.
【0337】
In FIG. 24 (a), 100a to 100c are lighting number counting means, 101a to 101c are register groups for storing the number of lighting at each time for each block, 102 is the CPU, and 103 are (Equation 2) and (Equation 3). Table memory for storing the described parameter aij, 104 is a temporary register for temporarily storing the calculation result, 105 is the program memory where the CPU program is stored, and 110 is the conversion of the voltage drop amount into the emission current amount. The table memory 106 in which the conversion data to be performed is described is a register group for storing the calculation result of the discrete correction data described above.
【0338】
The lighting number counting means 100a to 100c are composed of a comparator and an adder as shown in FIG. 24 (b). The parallel video signals Ra, Ga, and Ba are input to the comparators 107a to 107c, respectively, and are sequentially compared with the value of Cval. Note that Cval corresponds to the image data reference value set for the image data described above.
【0339】
The comparators 107a to 107c compare Cval with the image data, and output High if the image data is larger and output Low if the image data is smaller.
【0340】
The outputs of the comparators 107a to 107c are added to each other by the adders 108 and 109, further added for each block by the adder 110, and the addition result for each block is used as the number of lights for each block to register groups 101a to 101c. Store.
【0341】
0, 64, 128, and 192 are input as comparison values Cval of the comparators in the lighting number counting means 100a to 100c, respectively. As a result, the lighting number counting means 100a counts the number of image data larger than 0 among the image data, and stores the total for each block in the register 101a.
【0342】
Similarly, the lighting number counting means 100b counts the number of image data larger than 64 among the image data, and stores the total for each block in the register 101b.
【0343】
Similarly, the lighting number counting means 100c counts the number of image data larger than 128 among the image data, and stores the total for each block in the register 101c.
【0344】
Similarly, the lighting number counting means 100d counts the number of image data larger than 192 among the image data, and stores the total for each block in the register 101d.
【0345】
When the number of lights for each block and each time is counted, the CPU 102 reads the parameter table aij stored in the table memory 103 at any time, calculates the voltage drop amount according to (Equation 2) to (Equation 5), and calculates it. The result is stored in the temporary register 104.
【0346】
In this example, the CPU 102 is provided with a product-sum calculation function to smoothly perform the calculation of (Equation 2).
【0347】
As a means for realizing the calculation described in (Equation 2), the product-sum calculation may not be performed by the CPU 102, but may be realized, for example, by using a memory in which the calculation result of the product-sum calculation is stored in advance. In this case, the number of lights of each block is used as an input, and the amount of voltage drop at each node position is stored in the memory for all possible input patterns.
【0348】
When the calculation of the voltage drop amount is completed, the CPU 102 reads the voltage drop amount for each block at each time from the temporary register 104, and refers to the table memory 2 (110) to convert the voltage drop amount into the emission current amount. After conversion, discrete correction data was calculated according to (Equation 6) to (Equation 11) (or (Equation 12) to (Equation 22)).
【0349】
The calculated discrete correction data was stored in the register group 106.
【0350】
(Correction Data Interpolation Unit) FIG. 25 is a diagram for explaining a detailed configuration of the correction data interpolation unit 142 shown in FIG. 23.
【0351】
The correction data interpolation unit 142 is a means for calculating the correction data that matches the display position (horizontal position) of the image data and the size of the image data. By interpolating the correction data calculated discretely, the means calculates the correction data according to the display position (horizontal position) of the image data and the size of the image data.
【0352】
In the figure, 123 is a decoder for determining the node numbers n and n + 1 of the discrete correction data used for interpolation from the display position (horizontal position) x of the image data, and 124 is the decoder for determining the node number n and n + 1 of the discrete correction data used for interpolation, and 124 is the size of the image data. It is a decoder for determining k and k + 1 of (Equation 23) to (Equation 25).
【0353】
The selectors 125 to 128 are selectors for selecting discrete correction data and supplying it to the linear approximation means.
【0354】
Further, 121 to 123 are linear approximation means for performing linear approximation of (Equation 23) to (Equation 25), respectively.
【0355】
FIG. 26 shows a configuration example of the linear approximation means 120. In general, the linear approximation means can be configured by a subtractor, an adder, an adder, a divider, etc., as represented by the operators of (Equation 23) to (Equation 25). The linear approximation means 121 and 122 have the same configuration as the linear approximation means 120.
【0356】
However, it is desirable that the number of column wires between the nodes for which the discrete correction data is calculated and the interval between the image data reference values for calculating the discrete correction data (that is, the time interval for calculating the voltage drop) are raised to a power of 2. The hardware can be configured very easily if configured to. This is because if they are set to a power of 2, Xn + 1-Xn becomes a power of 2 in the divider shown in FIG. 26, so that division can be realized by bit shifting.
【0357】
Also, if the value of Xn + 1-Xn is always a constant value and is a value represented by a power of 2, the addition result of the adder may be shifted by the power of the power and output. There is no need to dare to make a divider.
【0358】
In addition, by setting the interval of nodes for calculating discrete correction data and the interval of image data to the power of 2 in other places, for example, decoders 123 to 124 can be easily manufactured, and in FIG. 26, The operation performed by the subtractor can be replaced with a simple bit operation.
【0359】
(Delay circuit 19) As shown in FIG. 17, the image data SData sorted by the data array conversion unit 9 is input to the correction data calculation means 14 and the delay circuit 19. The correction data interpolation unit of the correction data calculation means 14 refers to the values of the horizontal position information x and the image data SData from the timing control circuit, and calculates the correction data CD corresponding to them.
【0360】
The delay circuit 19 is provided to absorb the time required for calculating the correction data, and when the correction data is added to the image data by the adder 12, the correction data corresponding to the correction data is correctly added to the image data. It is a means of delaying. The means can be configured by using flip-flops.
【0361】
(Adder 12) The adder 12 is a means for adding the correction data CD and the image data Data from the correction data calculation means 14. By performing the addition, the image data Data is corrected and output as the corrected image data Dout to the memory A26 or the memory B27 (see FIGS. 17 and 18).
【0362】
(Regarding the control of the horizontal scanning period) In the conventional display device, the same display horizontal scanning time is uniformly assigned to all the scanning wirings based on one horizontal scanning period determined by the horizontal synchronization signal included in the input video signal. ..
【0363】
On the other hand, in the present embodiment, by adaptively allocating the scanning time of each scanning wiring according to the maximum value of the corrected image data, the voltage drop of the scanning wiring is corrected with high accuracy and the decrease in brightness is suppressed. It is possible to solve the conflicting demands of displaying an image.
【0364】
In reality, even if all the scanning wirings are not scanned with the same display scanning time, the displayed image does not feel strange.
【0365】
In addition, in the image signal of a natural image such as a TV signal, it is not so often that large value data that may cause overflow due to correction appears, and the maximum of each corrected image data when viewed for each horizontal scanning line. It is not efficient to scan all scans with the same horizontal scan time as in the past, as the values vary considerably.
【0366】
Therefore, even if the driving method of the present embodiment is applied, there is no display problem. Then, the decrease in brightness can be suppressed by scanning in the display horizontal scanning period determined by the maximum value of the pulse width of the modulated signal corresponding to each scanning wiring.
【0367】
FIG. 27 is a schematic diagram for explaining the horizontal scanning period used in the present embodiment. The vertical axis of the graph in the figure corresponds to each horizontal scanning wiring. In the figure, 12 horizontal scanning wires are given for simplification of explanation. The horizontal axis of the graph represents time (pulse width). In order to make the explanation easy to understand, the image data width is set to 8 bits, and the state in which the correction data is added to the luminance data is shown in an easy-to-understand manner.
【0368】
In the graph, the bar graph corresponding to each horizontal scanning wiring illustrates the pulse width of the maximum modulated signal in the pixels on the corresponding horizontal scanning wiring, that is, the maximum corrected image data. The white rectangular portion shows the input image data (brightness data) for one line related to the horizontal scanning wiring, and the hatched rectangular portion shows the correction data for the input image data.
【0369】
As shown in the figure, since the maximum value of the corrected image data varies for each horizontal scanning wiring, the scanning time is not uniformly allocated to all the horizontal scanning wiring, but the correction is performed for each horizontal scanning wiring. It can be seen that the display scanning time should be individually allocated so that the maximum value of the image data is accommodated. If the total display horizontal scanning time individually assigned to each horizontal scanning wiring is one frame time or less of the display, one frame image can be displayed within one frame time. In other words, if the average display horizontal scanning time is the conventional horizontal scanning period (255 + blanking period in FIG. 27), one frame of image can be displayed within one frame time. And since the time of one frame of display is not much different from the time of one frame of the input image, the moving image display is smooth.
【0370】
Of course, the display frame time does not necessarily have to be the same as one frame time of the input video, so the display frame time can be slightly expanded or contracted. In that case, the sum of N frames of the display horizontal scanning time individually assigned to each horizontal scanning wiring may be equal to or less than the N frame time of the input video data (where N is a natural number of 2 or more).
【0371】
The display horizontal scanning time assigned in this way is shown by a thick line in the graph. If the scanning wiring is switched and the modulation wiring is driven at the same time, the drive waveform in the display panel may be disturbed and an excessive voltage may be applied to the element. It is desirable to set the display horizontal scanning time with (non-driving time of modulation wiring). Further, in order to secure the time required for data transfer of the corrected image data to the modulation drive circuit (data shift time to the shift register 5), it is preferable to set the lower limit value of the display horizontal scanning time as shown in FIG. 27. ..
【0372】
Maximum corrected image data with 8-bit width image data (maximum: 255) corrected when the scanning wiring resistance is about 5Ω, the element current of the surface conduction type emission element is about 0.1mA, and the number of elements is 720 x 1280 x 3 (RGB). The value is about 350. Therefore, the bit width of the pulse width modulator is designed to be 9 bits.
【0373】
(Line maximum value detector, scanning time calculation processing in the microcomputer) The corrected image data Dout output from the adder 12 is input to the line maximum value detector 22 (FIG. 18). The line maximum value detector 22 performs a process of detecting the maximum value from the corrected image data for one line for each pixel data on each horizontal scanning wiring.
【0374】
Then, the microcomputer 34 calculates the scanning time of each scanning wiring according to the flowchart of FIG. 28 using the maximum value of the corrected image data detected by the line maximum value detector 22.
【0375】
The microcomputer 34 loops and waits until the vertical synchronization signal VD appears (step S11). When the vertical sync signal VD is received, it loops and waits until the horizontal sync signal HD appears (step S12). When the horizontal sync signal HD is received, processing for one line is started.
【0376】
First, the maximum value maxDi (i: line number) of the corrected image data of the horizontal scanning wiring is acquired from the line maximum value detector 22 (step S13). Note that maxDi is a value obtained by converting the value of the corrected image data into the number of clocks (number of Pwmclk) for pulse width modulation.
【0377】
Compare the maximum value maxDi and Dmin of the horizontal scanning wiring of the corrected image data acquired in step S13 (step S14), and if maxDi is smaller than Dmin, set maxDi = Dmin (step S15), otherwise maxDi. Does not change.
【0378】
Here, Dmin is the minimum display scanning time (KHDmin) that must be allocated in consideration of the data transfer time and non-driving time to the modulation drive circuit described above. It is the value of image data (number of Pwmclk) that can be displayed in time (KHDmin).
【0379】
In the present embodiment, the shift clock SCLK of the shift register 5 is obtained by dividing MCLK by 1/2 (details will be described later), and the outputs of the memory A26 and the memory B27 are divided into eight layers and used as the shift register 5. Forward. Therefore, the shift time for transferring data for one line is 1280 x 3 (RGB) / 8 layers = 480 clocks (SCLK number). Then, in anticipation of using 40 clocks for other processing in addition to the shift time, secure 520 clocks (SCLK number) as the minimum display scan time (KHDmin) (hereinafter referred to as the minimum display horizontal scan period). There is also).
【0380】
This 520 clock is 0.63 times the horizontal scanning time of the input image (= 520 / (1648/2)).
【0381】
In the present embodiment, the clock Pwmclk for pulse width modulation is created as follows by phase-locking the horizontal synchronization signal of the input video signal (720P).
【0382】
In this embodiment, the number of clocks in one horizontal scanning period (1H) of the clock Pwmclk for pulse width modulation is designed to be 280. In the conventional driving method, the pulse width is modulated by the time determined by the number of 256 clocks, and the remaining 24 clocks are allocated as the driving time in the scanning circuit (non-driving time: 1.9 μSec).
【0383】
Therefore, the frequency of Pwmclk is generated by phase-locking the horizontal synchronization signal with a frequency division ratio of 1: 280 by the PLL circuit to obtain a frequency of 12.6 MHz.
【0384】
In addition, the non-driving time must be considered within this display horizontal scanning time. It is desirable to provide about 2 μSec as the non-driving time of the modulated wiring. In the present embodiment, since the cycle of Pwmclk is about 79 nSec, 24 clocks (number of Pwmclk) are secured as the non-driving time (non-driving time is 1.9 μSec). Therefore, the value Dmin of the image data that can be displayed with the minimum display horizontal scanning time (KHDmin) is conveniently 280 × 0.63-24 = 153 clocks (Pwmclk number).
【0385】
That is, even if the maximum value maxDi of the corrected image data of one line is smaller than 153 (Dmin), a minimum of 177 (= 280 × 0.63) clock (Pwmclk number) minutes (KHDmin) is allocated as the display scanning time. There must be.
【0386】
The steps of S14 and S15 are for ensuring this minimum display horizontal scanning time (KHDmin). That is, the maximum value maxDi and Dmin of the corrected image data of the horizontal scanning line are compared, and if maxDi is smaller than Dmin, Dmin is substituted for maxDi and the minimum display horizontal scanning time which is the lower limit of the display horizontal scanning period ( KHD min) is secured.
【0387】
The step of S16 calculates the display horizontal scanning time (KHDi).
【0388】
That is, the display horizontal scanning time (KHDi) is calculated in MCLK units from maxDi calculated in Pwmclk units. Specifically, the number of clocks in the horizontal scanning period determined by the frequency of the horizontal synchronization signal of the input video signal is obtained by multiplying maxDi in Pwmclk units by 5.89 (= 1648/280) from the ratio of Pwmclk: 280 and MCLK: 1648. ..
【0389】
For reference, the time of one horizontal scanning period based on the input video signal 720p is 1648/2 = 824 clocks (SCLK number).
【0390】
After the processing up to step S16 is completed based on the maximum value maxDi of the corrected image data of the i-th line in this way, whether or not the line is the final line of the image data, that is, maxDi for all the scanning wirings is input. It is determined whether or not upDi has been calculated (step S17). If it is determined that the final line has not been reached, the processing of steps S12 to S16 is repeated again, and the display horizontal scanning time (KHDi) in which the minimum display horizontal scanning time (KHDmin) is secured is calculated for all the scanning wirings. ..
【0391】
In step S18, a process of adjusting the horizontal scanning time of each scanning wiring is performed so that the total horizontal scanning time of all the scanning wirings falls within a predetermined time. This predetermined time is a time corresponding to the frame frequency (60 Hz) of the input video signal 720p.
【0392】
That is, when the horizontal scanning time of each scanning wiring is simply assigned so as to include the maximum value maxDi of the corrected image data detected by the line maximum value detector 22, the total scanning time is sufficient for one frame period of the input video signal. It may not be.
【0393】
The display horizontal scanning time (KHDi) calculated in this way is calculated in step S18 and compared with the time of one frame of the input video signal. Then, for less than one frame of the input image signal, add, for example, the minimum display horizontal scanning time (KHDmin) as the display blanking period (addition of KHD721, KHD722 ...) and the frame time of the input image. , Adjust the display frame time.
【0394】
After calculating the display horizontal scanning time KHDi of each scanning line in this way, a loop is performed until the vertical synchronization signal VD appears (step S19).
【0395】
After receiving the vertical synchronization signal VD and confirming the end of one frame, the display horizontal scanning time KHDi of each scanning line is loaded into the display timing generator 33 before the start of the next frame (step S20).
【0396】
An example of the display scanning time KHDi of each horizontal scanning line calculated by the above processing is shown in the table of FIG. 29 and FIG. 30.
【0397】
In the present embodiment, the processing performed by the microcomputer 34 can be executed by the CPU 102 of the discrete correction data calculation unit, and the microcomputer 34 can be omitted.
【0398】
In the present embodiment, the number of sample clocks (number of MCLKs) in one horizontal scanning period is designed to be 1648, so that the number of MCLKs in one frame is 750 × 1648 = 1236000 clocks. The number of Pwmclk is 210,000 clocks, which is (280/1648) times that number.
【0399】
As shown in the table of FIG. 29, the value obtained by adding the non-driving time 24 clocks (Pwmclk number) to the maximum value maxDi of the corrected image data in one line, or the shift time and the time required for other processing (minimum display horizontal scanning). Time) 89 clocks (Pwmclk number), whichever is longer, is 1H time (display horizontal scanning time).
【0400】
For example, for the first line, the value 120, which is the sum of maxDi and the non-driving time, exceeds the minimum display horizontal scan time (KHDmin): 89, so the display horizontal scan time is 144 clocks (Pwmclk number), and for the second line. Since the value 60 obtained by adding the non-driving time to maxDi is less than the minimum display horizontal scanning time (KHDmin): 89, the display horizontal scanning time is 89 clocks (Pwmclk number).
【0401】
In addition, FIG. 30 is a graph of the table of FIG. 29. The longer the display horizontal scanning time is assigned to the line with the larger maximum value of the corrected image data, and the minimum display horizontal scanning time (KHDmin): 89 clocks are secured even for the line with the smaller maximum value of the corrected image data. And so on.
【0402】
In addition, the display blanking period is added to the 721 to 728 lines to provide the minimum display horizontal scanning time (KHDmin), but the display blanking period changes depending on the maximum value (maxDi) of each horizontal scanning line of the corrected image data. It is also preferable to let it.
【0403】
In this embodiment, as shown in FIG. 18, two frame memories (memory A26 and memory B27) capable of storing corrected image data for one frame each are provided, and the above-mentioned horizontal scanning time is provided. While performing the arithmetic processing of, one frame of corrected image data is temporarily stored.
【0404】
These two frame memories are provided so that when data is written to one frame memory (for example, memory A26), data can be read from the other frame memory (memory B27). Specifically, in odd-numbered frames, the contacts of switches 23, 24, 25, 29 are selected as a, a, b, and b, respectively, and in even-numbered frames, the reverse is made.
【0405】
The corrected image data Dout output from the adder 12 is written to the memory A26 in the case of odd-numbered frames and in the memory B27 in the case of even-numbered frames according to the write address signal generated by the W address generator 21. The W address generator 21 determines a write address from the horizontal synchronization signal HD, and generates a write address signal in synchronization with MCLK.
【0406】
Further, the corrected image data written in the memory A26 and the memory B27 is read according to the read address signal generated by the R address generation unit 28. The R address generator 28 determines the read timing of the line data for each horizontal scanning line, not the horizontal synchronization signal HD included in the input video signal, but the scanning time KHDi (i is the horizontal line number) calculated individually above. Then, it is determined according to i = 0,1,2 ...).
【0407】
The data read timing signal, that is, the display timing signal KHD is created by the display timing generation unit 33 described below.
【0408】
(Display Timing Generation Unit) FIG. 31 is a block diagram schematically showing a circuit configuration of the display timing generation unit 33.
【0409】
As shown in the figure, the display timing generator 33 includes an H counter 330, a memory 331, a comparator 332, a V counter 333, and a 1/2 frequency divider 334.
【0410】
The H counter 330 counts MCLK and outputs the counter value to the comparator 332. The counter value of the H counter 330 is reset by receiving the input of the vertical synchronization signal VD or the output of the comparator 332.
【0411】
The memory 331 is a storage means in which the horizontal scanning time KHDi of each horizontal scanning line is loaded from the microcomputer 34. The memory 331 sets the display horizontal scanning time KHD1 of the first horizontal scanning line at address 0, the horizontal scanning time KHD2 of the second horizontal scanning line displayed at address 1 to the address (i-1) in the following order. Display of the horizontal scan line of the i-th line Stores the horizontal scan time KHDi. Then, when the address i is input from the V counter 333, the display horizontal scanning time KHDi is output to the comparator 332.
【0412】
The comparator 332 compares the value input from the H counter 330 (count value of MCLK) with the value input from the memory 331 (display horizontal scanning time KHDi), and outputs a signal only when both match. .. Further, this output signal is input to the H counter 330, the V counter 333, and the 1/2 divider 334.
【0413】
The V counter 333 counts the output signal of the comparator 332 and outputs the counter value to the memory 331. The counter value of the V counter 333 is reset in response to the input of the vertical synchronization signal VD.
【0414】
The 1/2 divider 334 divides MCLK by 1/2 to generate the operating clock SCLK of the shift register 5. The 1/2 divider 334 is reset by the output signal of the comparator 332.
【0415】
The display timing generator 33 configured in this way operates as follows.
【0416】
First, the display horizontal scanning time KHDi of each horizontal scanning line is loaded from the microcomputer 34 into the memory 331 before the start of the next frame (before the vertical synchronization signal VD is input). Then, when the vertical synchronization signal VD is input, the counter values of the H counter 330 and the V counter 333 are reset, and the processing of one frame is started.
【0417】
Synchronized with MCLK, the V counter 333 outputs the counter value 0 to the memory 331, and the memory 331 outputs the display horizontal scanning time KHD1 of the first line to the comparator 332 in response to the counter value 0. On the other hand, the H counter 330 counts MCLK and outputs the counter value N to the comparator 332.
【0418】
A signal is output from the comparator 332 when the counter value N of the H counter 330 becomes equal to the display horizontal scanning time KHD1. Since the display horizontal scanning time KHD1 is the number of MCLKs and the comparison processing here is performed in synchronization with MCLK, the output signal from this comparator 332 corresponds to the end of the first line (or the start of the second line). The display timing signal is KHD.
【0419】
Then, when the display timing signal KHD is output, the counter value of the H counter 330 is reset and the counter value of the V counter 333 is incremented. Therefore, from here on, the V counter 333 outputs the counter value 1 to the memory 331, and the memory 331 outputs the display horizontal scanning time KHD2 of the second line to the comparator 332. Since the H counter 330 starts counting MCLK from 0 again, the display timing signal KHD (end of the second line (or the end of the third line (or the third line)) is displayed from the comparator 332 when the count value becomes KHD2 in the same manner as above. (Corresponding to start) is output.
【0420】
This process is repeated in sequence to generate a display timing signal KHD having the number of MCLKs according to each display horizontal scanning time KHDi for all the lines included in one frame.
【0421】
The display timing signal KHD generated in this way is input to the R address generation unit 28. The R address generation unit 28 generates a read address signal according to the display timing signal KHD, and outputs the signal to the memory on the read side via the switch 25.
【0422】
The total number of lines when reading data from memory A26 and memory B27 is preferably 720 or more, which is the effective number of scanning lines, and more preferably, it is about 725 to 750 from the timing design margin. (It goes without saying that if the total number of lines to be read is reduced, the display horizontal scanning time assigned to one line can be increased and the brightness can be increased.). In the present embodiment, the number of read lines of a certain frame is 728. In addition, it was decided to generate the display timing signal KHD so that the total number of Pwmclk in one frame would be constant (so that it would not change for each frame).
【0423】
(Shift register, latch circuit) For the output of memory A26 and memory B27, the corrected image data for one line is divided into eight outputs, and the corrected image data SD1 to SD8 of each layer are output in parallel. Further, the shift register 5 is composed of eight shift registers, and the corrected image data SD1 to SD8 of each layer are received by separate shift registers (see FIGS. 18 and 19).
【0424】
With such a configuration, the data transfer time (shift time) from the memory A26 and the memory B27 to the shift register 5 can be shortened. As a result, the "minimum display horizontal scanning time" (KHDmin) in the scanning time calculation process can be shortened, and the degree of freedom of the display horizontal scanning time assigned to each line can be increased. The same effect can be obtained by making the output and shift registers of the frame memory one and the read time of the frame memory shorter than the write time without layering.
【0425】
The shift register 5 serially / parallel-converts the corrected image data SD1 to SD8 input serially into parallel image data (ID1 to IDN) for each modulation wiring, and outputs the corrected image data to the latch circuit 6. In the latch circuit 6, the data from the shift register 5 is latched by the timing signal Dataload immediately before the start of one horizontal scanning period. The output of the latch circuit 6 is supplied to the modulation circuit 8 as parallel image data D1 to DN.
【0426】
In the present embodiment, the image data IDs 1 to IDN and D1 to DN are 9-bit image data, respectively.
【0427】
The operation timing of the shift register 5 is based on the shift clock SCLK from the display timing generation unit 33.
【0428】
(Details of the modulation circuit) The parallel image data D1 to DN, which are the outputs of the latch circuit 6, are supplied to the modulation circuit 8.
【0429】
As shown in FIG. 32, the modulation circuit 8 is a pulse width modulation circuit (PWM circuit) provided with a PWM counter 80, a comparator 81 for each modulation wiring, and a switch 82 such as a FET, and is supplied from the latch circuit 6. A modulated signal (voltage pulse) whose pulse width is modulated according to the corrected corrected image data D1 to DN is applied to each modulated wiring.
【0430】
The relationship between the image data D1 to DN and the output pulse width of the modulation circuit 8 has a linear relationship as shown in FIG. 33.
【0431】
FIG. 34 shows three examples of output waveforms of the modulation signal output from the modulation circuit 8.
【0432】
In the figure, the upper waveform is the waveform when the input data to the modulation circuit 8 is 0, and the center waveform is the waveform when the input data to the modulation circuit 8 is 255 (this is not driven from the horizontal scanning time of the input video signal). The waveform after subtracting the time, which is the maximum value in the horizontal scanning time in the conventional driving method), and the lower waveform are the waveforms when the input data to the modulation circuit 8 is 350.
【0433】
It can be clearly seen in the figure that when the input data to the modulation circuit 8 is 350, the time is longer than the horizontal scanning time of the input video signal.
【0434】
In FIG. 32, D1 to DN are corrected image data corresponding to each column 1 to N of the modulation wiring supplied from the latch circuit 6, Pwmstart is a synchronous clear signal of the PWM counter, and Pwmclk is the clock of the PWM counter. Further, XD1 to XDN represent the outputs of the first to Nth columns (N = 1280 × 3) of the modulation circuit 8.
【0435】
1 When the horizontal scanning period starts, the latch circuit 6 latches the image data and transfers the data to the modulation circuit 8.
【0436】
The PWM counter 80 starts counting based on Pwmstart and Pwmclk.
【0437】
The comparator 81 provided for each column compares the count value of the PWM counter with the image data of each column, outputs High when the value of the PWM counter is equal to or greater than the image data, and outputs Low during other periods. To do.
【0438】
The output of the comparator 81 is connected to the gate of the switch consisting of CMOS inverters in each row. During the period when the output of the comparator is low, the upper (VPWM side) pMOS transistor in the figure is ON and the lower side (GND side). The nMOS transistor is turned off, and the modulation wiring is connected to the reference voltage source that gives the voltage VPWM.
【0439】
Conversely, during the period when the output of the comparator is High, the upper pMOS transistor in the figure turns off, the lower nMOS transistor turns on, and the modulation wiring is connected to a reference voltage source that gives a GND potential. When each part operates as described above, the pulse width modulation signal output by the modulation circuit 8 becomes a waveform in which the rising edges of the pulses are synchronized as shown in FIG. 34.
【0440】
Although not shown in particular, it goes without saying that the above Dataload and Pwmstart are synchronized with the display timing signal KHD.
【0441】
(Scanning drive circuit) The scanning drive circuits 2A and 2B are selected from reference voltage sources 222 and 223 for connection terminals Dx1 to DxM in order to sequentially scan and select the display panel line by line in one horizontal scanning period. It is a circuit that selectively outputs voltage Vs or non-selective voltage Vns (see Fig. 35).
【0442】
The scanning drive circuits 2A and 2B sequentially switch the selected scanning wiring for each horizontal scanning period in synchronization with the scanning control signal signal Tscan, and all scanning wiring for one frame period, in this case, one vertical scanning period. Scanning selection drive is performed.
【0443】
The scanning control signal Tscan is a signal synchronized with the display timing signal KHD of each scanning wiring generated by the display timing generation unit 33. The display timing signal KHD itself can also be used as the scan control signal Tscan.
【0444】
As shown in FIG. 35, the scanning drive circuits 2A and 2B are composed of M switch arrays 224, shift registers 221 and the like, respectively. These switches are preferably composed of bipolar transistors or FETs.
【0445】
In order to reduce the voltage drop in the scanning wiring, it is preferable that the scanning drive circuit is connected to both ends of the scanning wiring of the display panel 1 and driven from both ends as shown in FIG. In this case, it is preferable to adopt a circuit configuration in which the output order of the scanning signals output from the output terminals can be reversed so that the one-chip integrated circuit can be easily mounted at any end. Such a circuit configuration can be easily designed by using a bidirectional shift register.
【0446】
When an image is displayed by such a display device, it is possible to correct the amount of voltage drop in the scanning wiring, which has been a problem in the past, and to improve the deterioration of the displayed image due to the correction.
【0447】
In addition, by calculating the correction data discretely and interpolating between the points calculated discretely, the correction data can be calculated very easily, and the hardware is very simple. It has a very good effect, such as being able to achieve it with clothing.
【0448】
Then, the voltage drop that occurs in the scanning wiring is corrected, and the image is displayed with the brightness of the resistance value of the scanning wiring to 0Ω (the brightness is displayed larger than when the voltage is dropped by the scanning wiring resistance). ) Can be compatible.
【0449】
(Second Embodiment) In the first embodiment, as described above, the display scanning time calculation process includes the maximum value maxDi of the corrected image data detected by the line maximum value detector 22. Line display Horizontal scan time was assigned. Then, it has become possible to correct the voltage drop of the scanning wiring and display an image without a decrease in brightness. However, depending on the image, the total display horizontal scanning time, which is the sum of one frame of the allocated display horizontal scanning time, may exceed one frame time of the input video. This embodiment improves this point.
【0450】
The difference between the present embodiment and the first embodiment is that the display scanning time of each scanning line is simply allocated so as to include the maximum value maxDi of the corrected image data of the scanning wiring of each horizontal scanning line. At that time, if it is expected that the total horizontal scanning time will exceed one frame period of the input video signal, each display horizontal scanning time and corrected image data will be adjusted so that it fits within one frame period. Is.
【0451】
The overlapping parts such as the overview of the display panel of the image display device according to the present embodiment, the electrical connection of the display panel, the characteristics of the surface-conducting emission element, the driving method of the display panel, and the like are the same as those of the first embodiment. is there.
【0452】
Here, in order to reduce the price of the display device, as shown in FIG. 36, a case where a one-sided scanning configuration is used will be described as an example.
【0453】
In a digital circuit, there is a limit to the data width (number of bits) that can be handled by the circuit. This data width is generally determined in consideration of the cost of hardware and the like. In particular, in the case of a configuration in which pulse width modulation is performed according to the corrected image data as in the present embodiment, it is necessary to modulate the pulse width so as to fit within one horizontal scanning period. That is, an increase in the number of gradations may require an increase in the operating clock of the modulation circuit. Therefore, unnecessary radiation and power consumption may increase, but the operating clock can be lowered by reducing the data width input to the pulse width modulator by using the dither method or the like as necessary.
【0454】
On the other hand, an increase in corrected image data may cause a so-called overflow problem. That is, when the correction data is simply added to the image data, if the calculation result exceeds the data width that can be handled by the pulse width modulator, bit wrapping or the like occurs, and the displayed image is inverted. The image is distorted.
【0455】
Therefore, in the present embodiment, the maximum value of the corrected image data is calculated and determined in advance, and a pulse width modulator having a bit width corresponding to the maximum value is provided.
【0456】
Then, each display horizontal scanning time and corrected image data are adjusted so that the total display horizontal scanning time does not exceed one frame period of the input video signal.
【0457】
(Explanation of Functions of the Whole System and Each Part) The signal processing circuit hardware of the image display device of the present embodiment incorporating the correction data calculation means will be described.
【0458】
FIG. 37 is a block diagram showing an outline of the circuit configuration. FIG. 37 shows a circuit related to determining the scanning time of the scanning wiring. The input (I) of the circuit shown in FIG. 37 is the output from the same circuit as that shown in FIG. Further, the output (II) of the circuit shown in FIG. 37 is input (II) to the circuit shown in FIG. 36. The basic configuration is the same as in FIG.
【0459】
Reference numeral 31 denotes a gain register which is an image data adjusting means for adjusting the corrected image data in response to the calculation result of the microcomputer 34, and this portion is different from the configuration of FIG.
【0460】
Hereinafter, the configuration of the display device of the present embodiment will be described in detail with reference to FIGS. 17, 37, and 36.
【0461】
(Synchronous signal separation circuit, timing generation circuit, reverse γ processing unit) Same as the first embodiment.
【0462】
(Data array conversion unit) Same as the first embodiment.
【0463】
(Correction data calculation means) Same as the first embodiment.
【0464】
(Discrete correction data calculation unit) Same as the first embodiment.
【0465】
(Correction data interpolation unit) Same as the first embodiment.
【0466】
(Delay circuit 19) It is the same as the first embodiment.
【0467】
(Adder 12) Same as the first embodiment.
【0468】
(Regarding the control of the horizontal scanning period) In the actually examined configuration shown in Fig. 36, the scanning wiring resistance is about 5Ω, the element current of the surface conduction type emission element is about 0.5mA, and the number of elements is 720 × 1280 × 3 (RGB). Then, the maximum value of the corrected image data obtained by correcting the 8-bit width image data (maximum: 255) is about 1000. Therefore, the bit width of the pulse width modulator is designed to be 10 bits. Here, the bit width of the pulse width modulator may be set to 8 bits as in the conventional case, and the lower 2 bits may be expressed by the dither method or the like to express the gradation.
【0469】
(Line maximum value detector, scanning time calculation processing in the microcomputer) The corrected image data Dout output from the adder 12 is input to the line maximum value detector 22 (Fig. 37). The line maximum value detector 22 performs a process of detecting the maximum value from the corrected image data for one line for each line data.
【0470】
Then, the microcomputer 34 calculates the horizontal scanning time of each scanning wiring according to the flowchart of FIG. 38 using the maximum value of the corrected image data detected by the line maximum value detector 22.
【0471】
The microcomputer 34 loops and waits until the vertical synchronization signal VD appears (step S21). When the vertical sync signal VD is received, it loops and waits until the horizontal sync signal HD appears (step S22). When the horizontal sync signal HD is received, processing for one line is started.
【0472】
First, the maximum value maxDi (i: line number) of the corrected image data of the scanning wiring is acquired from the line maximum value detector 22 (step S23), and upDi is calculated (step S24). Note that maxDi is a value obtained by converting the value of the corrected image data into the number of clocks (number of Pwmclk) for pulse width modulation.
【0473】
The calculation of upDi is performed according to the flowchart of FIG. Compare the maximum value maxDi and Dmin of the scanning wiring of the corrected image data acquired in step S23 (step S241), and if maxDi is larger than Dmin, set the difference (maxDi-Dmin) to upDi (step S242). , Otherwise, set upDi to 0 (step S243).
【0474】
Here, Dmin is the minimum display horizontal when considering the display horizontal scanning time (KHDmin) that must be allocated at the minimum in consideration of the data transfer time and non-driving time to the above-mentioned modulation means. It is the value (number of Pwmclk) of image data that can be displayed in scanning time (KHDmin).
【0475】
In the present embodiment, the shift clock SCLK of the shift register 5 is obtained by dividing MCLK by 1/2 (details will be described later), and the outputs of the memory A26 and the memory B27 are divided into eight layers and used as the shift register 5. Forward. Therefore, the shift time for transferring data for one line is 1280 x 3 (RGB) / 8 layers = 480 clocks (SCLK number). Then, in addition to the shift time, it is expected that 40 clocks will be used for other processing, and 520 clocks (SCLK number) is secured as the minimum display horizontal scanning time (KHDmin) (hereinafter referred to as the minimum display horizontal scanning period). Sometimes). In this embodiment, the clock Pwmclk for pulse width modulation is the shift clock SCLK with the same frequency.
【0476】
In addition, the non-driving time must be considered within this display horizontal scanning time. It is desirable to provide about 2 μSec as the non-driving time of the modulated wiring. In the present embodiment, the cycle of Pwmclk is about 27 nSec, so 74 clocks (number of Pwmclk) may be secured as the non-driving time. Therefore, the value Dmin of the image data that can be displayed with the minimum display horizontal scanning time (KHDmin) is conveniently 520-74 = 446 clocks (Pwmclk number). That is, even if the maximum value maxDi of the corrected image data of one line is smaller than 446 (Dmin), a minimum of 520 clocks (Pwmclk number) of time (KHDmin) must be allocated as the display horizontal scanning time.
【0477】
The calculation in the flowchart of FIG. 39 is for ensuring this minimum display scanning time (KHDmin). The upDi obtained here represents the amount at which the maximum value maxDi of the corrected image data of the scanning wiring exceeds Dmin (when maxDi is smaller than Dmin, 0 is entered in upDi).
【0478】
For reference, the time of one horizontal scanning period based on the input video signal 720p is 1648/2 = 824 clocks (Pwmclk number).
【0479】
After calculating upDi based on the maximum value maxDi of the corrected image data of the i-th line in this way, whether or not the line is the final line of the image data, that is, maxDi for all scanning lines is input to calculate upDi. Whether or not it is determined (step S25). If it is determined that the final line has not been reached, the processes of steps S22 to S25 are repeated again, and when the upDi for all the scanning lines is calculated, the process proceeds to the next step.
【0480】
In steps S26 and S27, a process of adjusting the horizontal scanning time of each scanning line is performed so that the total horizontal scanning time of all scanning lines falls within a predetermined time. The predetermined time referred to here is a one-frame period of the input video signal, and specifically, is a time corresponding to the frame frequency (60 Hz) of the input video signal 720p.
【0481】
That is, when the horizontal scanning time of each scanning line is simply assigned so as to include the maximum value maxDi of the corrected image data detected by the line maximum value detector 22, the total horizontal scanning time is set to one frame period of the input image signal. In such a case, the gain is adjusted for the horizontal scanning time of each scanning line so that it is within one vertical scanning period (within one frame time) as a whole. is there. Since it is necessary to secure the minimum display horizontal scanning time (KHDmin) for each scanning line as described above, this gain adjustment is performed for upDi.
【0482】
Therefore, first, in step S26, the sum sum SumD of upDi for all scanning lines (720 lines) is calculated. Next, SumD is used to calculate the gain and the scanning time of each scanning line (step S27).
【0483】
The gain calculation and the calculation of the scanning time of each scanning line are performed according to the flowchart of FIG. 40.
【0484】
In the same flowchart, in steps S271 to S276, the gain YG determination process for uniformly multiplying the corrected image data in the frame from the upDi of each scanning line is performed.
【0485】
First, in step S271, ALLD is divided by SumD to obtain YG. This ALLD is the minimum display time (KHDmin) for all scanning wiring from the number of Pwmclk corresponding to the time when the modulation signal drive time can be allocated to the maximum when all scanning wiring is driven by allocating time within one frame period. It is the value after subtracting. The number of effective scanning lines of the input video signal 720p is 720, but the total number of scanning lines is 750. ALLD = 750 × ((1648/2)-KHDmin) = 228000 clocks (Pwmclk number) And.
【0486】
If the YG calculated in this way is greater than 1 (step S272), reset YG to 1 (step S273). The fact that SumD is smaller than ALLD means that even if the horizontal scanning time of each scanning line is simply assigned so as to include the maximum value maxDi of the corrected image data detected by the line maximum value detector 22, the total horizontal scanning time is included. This means that the period of one frame of the input video signal is not exceeded, and there is no need to adjust the gain.
【0487】
Next, if the gain YG is less than 1, use the gain YG obtained here to adjust each display scan time KHDi (i is the number of the horizontal scan line, i = 1,2, ...). (Step S274), the multiplier (DGAIN) of the corrected image data is calculated so as to be within each display scanning time KHDi after this adjustment. (Step S275). Specifically, the display scan time (KHDi) is KHDi = (upDi x YG + KHDmin) x 2-1 The gain DGAIN for the corrected image data is calculated as follows.
【0488】
DGAIN = (upDmax × YG + Dmin) / (upDmax + Dmin) Here, upDmax is the maximum value of upDi in the frame. Calculate as follows. Since KHDi, which determines each horizontal scanning time, uses the number of MCLKs as a unit, it is calculated by doubling it. Here, upDi is in units of Pwmclk numbers.
【0489】
The display horizontal scanning time (KHDi) calculated in this way is calculated in step S276, and is compared with the time of one frame of the input video signal. Then, for less than the input frame time, add, for example, the minimum display scanning time (KHDmin) as the display blanking period (addition of KHD721, KHD722 ...) and display the frame time of the input video. Match the frame times as much as possible.
【0490】
After calculating the gain DGAIN and the display scan time KHDi of each scan line in this way (returning to the flowchart of FIG. 38 again), a loop is performed until the vertical sync signal VD appears (step S28).
【0491】
After receiving the vertical synchronization signal VD and confirming the end of one frame, before the start of the next frame, the display scan time KHDi of each scan line is loaded into the display timing generator 33 (step S29), and the gain DGAIN is set to the gain register 31. Load to (step S30).
【0492】
An example of the display horizontal scanning time KHDi of each scanning wiring calculated by the above processing is shown in FIGS. 41 and 42.
【0493】
In the present embodiment, the processing performed by the microcomputer 34 can be executed by the CPU 102 of the discrete correction data calculation unit, and the microcomputer 34 can be omitted.
【0494】
In this embodiment, the number of sample clocks (the number of MCLKs) in one horizontal scanning period is designed to be 1648, so the number of MCLKs in one frame is 750 × 1648 = 1236000 clocks (the number of Pwmclk is 618000 clocks, which is half of that). ).
【0495】
As shown in the table of FIG. 41, the maximum value maxDi of the corrected image data in one line plus 74 clocks (Pwmclk number) of the non-driving time, or the transfer time (shift time) of the image data and other processing The longer of the required time (minimum display horizontal scanning time) and 520 clocks (number of Pwmclk) is the one horizontal scanning time of the display panel).
【0496】
For example, for the first line, the value 554, which is maxDi plus the non-driving time, exceeds the minimum display horizontal scan time (KHDmin): 520, so the display horizontal scan time is 554 clocks (Pwmclk number), and for the second line. Since the value 394, which is the sum of maxDi and the non-driving time, is less than the minimum display horizontal scanning time (KHDmin): 520, the display horizontal scanning time is 520 clocks (Pwmclk number).
【0497】
In addition, FIG. 42 is a graph of the table of FIG. 41. The longer the display scan time is assigned to the line with the larger maximum value of the corrected image data, and the minimum display scan time (KHDmin): 520 clock is secured even for the line with the smaller maximum value of the corrected image data. Understand.
【0498】
In addition, the display blanking period is added to set the minimum display scanning time (KHDmin) for the 721 to 750 lines, but the display blanking period changes depending on the maximum value (maxDi) of each scanning wiring of the corrected image data.
【0499】
The control method of the two frame memories (memory A26 and memory B27) is the same as that of the above-described embodiment. When YG <1, the above-mentioned flow determines the values of KHDi and DGAIN, which determines the display horizontal scanning period.
【0500】
(Display Timing Generation Unit) The display timing generation unit 33 of the present embodiment is the same as the display timing generation unit 33 (FIG. 31) of the first embodiment.
【0501】
Similar to the first embodiment, the display timing signal KHD having the number of MCLKs according to each display scan time KHDi is generated for all the lines included in one frame.
【0502】
The display timing signal KHD generated in this way is input to the R address generation unit 28. The R address generation unit 28 generates a read address signal according to the display timing signal KHD, and outputs the signal to the memory on the read side via the switch 25.
【0503】
The total number of lines when reading data from memory A26 and memory B27 is preferably 720 or more, which is the effective number of scanning lines, and more preferably, it is about 730 to 750 from the timing design margin. Is good. Needless to say, if the total number of lines to be read is reduced, the display scanning time allocated to one line can be increased and the brightness can be increased. In the present embodiment, the number of read lines in one frame is set to 730, and the display timing signal KHD is generated so that the total number of Pwmclk in one frame is constant and does not change for each frame. in this case, ALLD = 730 (1648 / 2-KHDmin) +20 (1648/2) Will be.
【0504】
(Gain register) As shown in FIG. 37, the corrected image data Dout temporarily stored in the memory A26 or the memory B27 is output to the shift register 5 according to the read address signal of the R address generator 28. ..
【0505】
At this time, the gain register 31 applies a gain to the corrected image data Dout according to the gain DGAIN loaded from the microcomputer 34 in frame units.
【0506】
The gain DGAIN obtained as described above is applied to the corrected image data to adjust the image data. In this way, the pulse width does not exceed a predetermined display horizontal scanning time when modulated by the modulation circuit 8.
【0507】
(Shift register, latch circuit) The configuration and operation of the shift register and latch circuit are basically the same as those in the above-described embodiment, but here, the image data ID1 to IDN and D1 to DN are not 9 bits, respectively. It was 10-bit image data.
【0508】
(Details of Modulation Means) The parallel image data D1 to DN, which are the outputs of the latch circuit 6, are supplied to the modulation circuit 8 shown in FIG. 43. The basic configuration of the modulation circuit 8 is the same as that of the above-described embodiment.
【0509】
The relationship between the 10-bit image data D1 to DN and the output pulse width of the modulation circuit 8 has a linear relationship as shown in FIG.
【0510】
Figure 45 shows three examples of output waveforms of the modulation circuit. In the figure, the upper waveform is the waveform when the input data to the modulation circuit 8 is 0, and the center waveform is the waveform when the input data to the modulation circuit is 750 (horizontal scanning time of the input video signal minus the non-driving time). The waveform at the time of the value (maximum value in the conventional horizontal scanning time) and the waveform on the lower side are the waveforms when the input data to the modulation circuit is 1023. In this case, a time-modulated signal longer than the horizontal scanning time of the input video signal is output.
【0511】
(Scanning Drive Circuit) The configuration and operation of the scanning drive circuit 2 of the present embodiment are the same as those of the first embodiment.
【0512】
In order to reduce the voltage drop in the long scanning wiring as the size of the display increases, two sets of scanning drive circuits are provided on the display panel 1 as shown in the first embodiment. It is also preferable to connect to both ends of the scanning wiring and drive from both ends.
【0513】
According to this embodiment, the amount of voltage drop in the scanning wiring can be corrected, and the deterioration of the display image caused by the voltage drop can be improved.
【0514】
In addition, by calculating the correction data discretely and interpolating between the points calculated discretely, the correction data can be calculated very easily, and the hardware is very simple. You can do that with hardware.
【0515】
Further, as in the first embodiment, the voltage drop occurring in the scanning wiring is corrected and the brightness is corrected by appropriately allocating the display horizontal scanning time of each scanning wiring according to the maximum value of the corrected image data. It is possible to display an image at the same time.
【0516】
Furthermore, after securing the minimum display horizontal scanning time KHDmin, the gain YG is applied to adjust the horizontal scanning period, and the corrected image data is multiplied by the gain DGAIN to adjust the corrected image data for one frame. Even if the corrected image data has a total display horizontal scanning time exceeding a predetermined time, it can be displayed without degrading the image quality.
【0517】
(Third Embodiment) Next, the third embodiment of the present invention will be described.
【0518】
The difference between the present embodiment and the second embodiment is that the display horizontal scanning time of each scanning line is simply assigned so as to include the maximum value maxDi of the corrected image data of the pixels on each scanning wiring. At that time, the processing method when the total horizontal scanning time exceeds one frame period of the input video signal is different. Other parts are the same as those in the second embodiment.
【0519】
In the second embodiment, the gain DGAIN is included in the corrected image data so that the maximum pulse width of the modulated signal corresponding to the display horizontal scanning period KHDi is contained within the display horizontal scanning time KHDi adjusted by the gain YG. Then, pulse width modulation was performed to generate a modulated signal.
【0520】
In the present embodiment, the corrected image data is limited by a limiter so that the corresponding modulated signal fits within the display scanning time KHDi adjusted by the gain YG, and then pulse width modulation is performed.
【0521】
(Explanation of Functions of the Whole System and Each Part) The hardware of the display device of the present embodiment incorporating the correction data calculation means will be described.
【0522】
FIG. 46 is a block diagram showing an outline of the circuit configuration according to the present embodiment. The circuit related to the input of the video signal and the correction of the image data is the same as that shown in FIG. 17 shown in the first and second embodiments. Further, the display panel, the scanning drive circuit, and the modulation drive circuit are the same as those in the second embodiment.
【0523】
(Regarding the operation of the limiter) The main part different from the third embodiment is the part of the limiter 51 and the limit data memory 52 in FIG. 46.
【0524】
The limit data memory 52 stores the limit data value (LimDi) corresponding to the i-th scanning wiring described later. Then, the limit data value (LimDi) stored corresponding to the selected scanning wiring is output to the limiter 51. The limiter 51 replaces the corrected image data having a value equal to or higher than the limit data value (LimDi) output from the limit data memory 52 with the limit data value (LimDi) and outputs the corrected image data.
【0525】
In the second embodiment, the value of the corrected image data is stored in the display scanning time KHDi by multiplying the gain DGAIN by the corrected image data. In the present embodiment, the same effect is realized by replacing the corrected image data having a value equal to or higher than the limit data value (LimDi) with the limit data value (LimDi) by the limiter 51.
【0526】
(Regarding the control of scanning time) Similar to the second embodiment, the scanning time of each scanning wiring is adaptively allocated according to the maximum value of the corrected image data.
【0527】
(Calculation processing of the horizontal scanning period in the line maximum value detector and the microcomputer) The corrected image data Dout output from the adder 12 in FIG. 17 is input to the line maximum value detector 22 (see FIG. 46). Similar to the second embodiment, the line maximum value detector 22 performs a process of detecting the maximum value from the corrected image data for one line for each line data.
【0528】
Then, the microcomputer 34 calculates the horizontal scanning time of each scanning wiring according to the flowchart of FIG. 47 using the maximum value of the corrected image data detected by the line maximum value detector 22.
【0529】
In FIG. 47, steps S31 to S36 are the same operations as steps S21 to S26 in the flowchart (FIG. 38) of the second embodiment. Further, the operation in step S34 also performs the process shown in the flowchart of FIG. 39.
【0530】
From the sum D of upDi and upDi calculated up to step S36, the calculation of the limit data value (LimDi) for each scanning wiring unit that defines the maximum value of each display horizontal scanning drive time (KHDi) and corrected image data (step S37). ) Is performed according to the flowchart of FIG. 48.
【0531】
In the same flowchart, in steps S371 to S373, the gain YG to be uniformly applied within the frame is determined for the upDi of each scanning line.
【0532】
First, as in the second embodiment, in step S371, ALLD is divided by SumD to obtain YG. If the input video signal is 720p ALLD = 750 × ((1648/2)-KHDmin) = 228000 clocks (Pwmclk number) Will be.
【0533】
If the YG calculated in this way is 1 or more (step S372), reset the YG to 1 (step S373).
【0534】
Next, if YG is less than 1, adjust each display horizontal scanning time KHDi using the gain YG obtained here (step S374), and correct it so that it is within each displayed horizontal scanning time KHDi after this adjustment. Calculate the limit data value (LimDi) for the image data. (Step S375). Specifically, the display horizontal scanning time (KHDi) is KHDi = (upDi x YG + KHDmin) x 2-1 And the limit data value (LimDi) for the corrected image data is LimDi = upDi × YG + Dmin Calculate as follows. Since KHDi, which determines each scanning time, uses the number of MCLKs as a unit, it is calculated by doubling it. This is because upDi is in units of Pwmclk numbers.
【0535】
The display horizontal scanning time (KHDi) calculated in this way is calculated in step S376 and compared with the time of one frame of the input video. Then, for less than one frame time of the input image, add, for example, the minimum display horizontal scanning time (KHDmin) as the display blanking period (addition of KHD721, KHD722 ...), and the frame time of the input image. And adjust the display frame time.
【0536】
After calculating the limit data value LimDi and the display horizontal scanning time KHDi of each scanning line in this way, the process returns to the flowchart of FIG. 47 and loops until the vertical synchronization signal VD appears (step S38).
【0537】
After receiving the vertical synchronization signal VD and confirming the end of one frame, before the start of the next frame, the scanning time KHDi of each scanning line is loaded into the display timing generator 33 (step S39), and the limit data value LimDi is set to the limit data. Load into memory 52 (step S40).
【0538】
In the present embodiment, the microcomputer 34 can be omitted by causing the CPU 102 of the discrete correction data calculation unit to execute the processing performed by the microcomputer 34.
【0539】
(Limit data memory, limiter) The corrected image data Dout temporarily stored in the memory A26 or the memory B27 is output to the shift register 5 according to the read address signal of the R address generator 28 (see FIG. 46). ..
【0540】
At this time, the limit data memory 52 limits the value of the corrected image data Dout according to the limit data value LimDi loaded from the microcomputer 34.
【0541】
In the above arithmetic processing, as described above, when the horizontal scanning time of each line is allocated so as to include the maximum value maxDi of the corrected image data detected by the line maximum value detector 22, the total horizontal scanning time is one frame. If the period is exceeded, adjust the gain of the scanning time of each line.
【0542】
Therefore, when the display scanning time KHDi is adjusted by applying a gain YG smaller than 1, corrected image data to be limited is generated. The data is a corrected image that generates a modulated signal with a pulse width corresponding to a time equal to or greater than the value obtained by subtracting the non-driving time from the displayed horizontal scanning time according to the adjustment of the horizontal scanning time by the gain YG. It is data. That is, the corrected image data having the limit data value LimDi or more calculated for each scanning wiring stored in the limit data memory 52 is limited by the limiter 51.
【0543】
That is, the limit data memory 52 outputs LimD1 for the data of the first scanning wiring, LimD2 for the data of the second scanning wiring, and LimDi for the data of the i-th scanning wiring. This can be achieved, for example, by counting an address counter (not shown) with a KHD signal. The limiter 51 replaces the corrected image data having a value equal to or higher than the limit data value (LimDi) output from the limit data memory 52 with the limit data value (LimDi) and outputs the corrected image data. This is to prevent the pulse width from exceeding the selection period of the horizontal scanning period when modulated by the modulation circuit 8.
【0544】
In the present embodiment, with such a configuration, it is possible to correct the voltage drop that occurs in the scanning wiring and to increase the brightness and display the image at the same time.
【0545】
Furthermore, a limiter for the corrected image data can control one frame to display a high-quality image.
【0546】
(Fourth Embodiment) Next, the fourth embodiment of the present invention will be described.
【0547】
The difference between the present embodiment and the third embodiment is the scanning time calculation processing in the microcomputer. When the display horizontal scanning time of each scanning line is simply assigned so as to include the maximum value maxDi of the corrected image data of the scanning wiring, the total horizontal scanning time may exceed one frame period of the input video signal. If it is predicted, the display frame period is controlled by devising the calculation process of the horizontal scanning time in the microcomputer. Other parts are the same as those in the third embodiment.
【0548】
In the third embodiment, the gain YG is multiplied by the display horizontal scan time to adjust the display horizontal scan time KHDi. Further, the corrected image data is limited by a limiter so that the maximum time of the pulse width-modulated modulated signal of the corresponding scanning wiring is equal to or less than the display horizontal scanning time KHDi.
【0549】
On the other hand, in the present embodiment, when the display horizontal scanning time of each scanning line is simply assigned so as to include the maximum value maxDi of the corrected image data of the scanning wiring, the total scanning time is one frame period of the input video signal. This is a method of limiting the display horizontal scanning time exceeding a predetermined standard so as not to exceed the above.
【0550】
(Explanation of Functions of the Whole System and Each Part) The circuit configuration of the image display device according to the present embodiment incorporating the correction data calculation means is shown in the third embodiment (FIGS. 17, 36, This is the same as in Fig. 46).
【0551】
The difference between the present embodiment and the third embodiment is the processing contents described below.
【0552】
(Line maximum value detector, arithmetic processing in the microcomputer) The corrected image data Dout output from the adder 12 in FIG. 17 is input to the line maximum value detector 22 (see FIG. 46). Similar to the second embodiment, the line maximum value detector 22 performs a process of detecting the maximum value from the corrected image data for one line for each line data.
【0553】
Then, the microcomputer 34 calculates the scanning time of each scanning wiring according to the same flowchart as in FIG. 47 using the maximum value of the corrected image data detected by the line maximum value detector 22.
【0554】
In FIG. 47, the operation of the present embodiment is the same as that of the third embodiment except for step S37. The only difference from the third embodiment is the processing content of step S37 (see FIG. 49).
【0555】
From the sum D of upDi and upDi calculated up to step S36 in FIG. 47, the calculation of the limit data (LimDi) for each scanning wiring unit that defines the maximum value of each display horizontal scanning drive time (KHDi) and corrected image data ( Step S37) is performed according to the flowchart of FIG.
【0556】
In the same flowchart, the upDi of each scanning line is uniformly limited within the frame, and the corresponding corrected image data is limited.
【0557】
First, in step S471, LimD is set. As this value, the maximum value that can be taken as the corrected image data minus Dmin, that is, the corrected image corresponding to the minimum scanning time KHDmin from the maximum value of the corrected image data when all the input image data of the scanning wiring are the maximum values. The value obtained by subtracting the data value Dmin should be greater than or equal to the value. Next, in step S472, ALLD is divided by SumD to obtain YG as in the third embodiment.
【0558】
If the YG calculated in this way is greater than 1 (step S473), the process proceeds to the next process (step S478).
【0559】
Next, if YG is less than 1, adjust each display horizontal scan time KHDi as follows.
【0560】
Compare UpDi and LimD corresponding to all scanning wiring, and compare UpDi and LimD (step S474) If the UpDi is larger than LimD, the process moves to step S475, and LimD is substituted for UpDi. Therefore, the new UpDi is limited to values less than or equal to LimD.
【0561】
In step S476, the LimD value is subtracted by 1. Next, SumD is newly calculated in step S477.
【0562】
Then, the process returns to step S472 for calculating YG. Then in S473 YG is compared to 1. If YG is less than 1, steps S474 to S477 are repeated until YG is greater than 1.
【0563】
Limit UpDi until YG is greater than 1, that is, until its sum of display horizontal scan times does not exceed one frame period of the input video signal.
【0564】
When YG becomes larger than 1, the process moves to step S478. In step S478, each display horizontal scan time KHDi is determined from the limited upDi.
【0565】
Specifically, the display horizontal scanning time (KHDi) is KHDi = (upDi + KHDmin) x 2-1 Calculate as follows. That is, it is calculated by adding upDi (corrected image data corresponding to the minimum display horizontal scanning time, subtracted from the corrected image data by a limiter) to the minimum display horizontal scanning time (KHDmin). ..
【0566】
Since KHDi, which determines each display horizontal scanning time, uses the number of MCLKs as a unit, it is calculated by doubling it.
【0567】
Next, in step S479, the limit data value (LimDi) for the corrected image data is set so that the duration from the start to the end of the pulse width modulated signal of the modulation circuit 8 is settled within each display horizontal scanning time KHDi after this adjustment. ), LimDi = upDi + Dmin Calculate as follows.
【0568】
The display horizontal scanning time (KHDi) calculated in this way is calculated in step S480, and is compared with the time of one frame of the input video signal. Then, for less than one frame of the input video signal, the minimum display scanning time (KHDmin) is added as the display blanking period, for example, KHD721, KHD722 ... KHD730, to the input video signal. Match the frame time with the display frame time.
【0569】
After calculating the limit data value LimDi and the display horizontal scanning time KHDi of each scanning line in this way, a loop is performed until the vertical synchronization signal VD appears (see step S38 in FIG. 47).
【0570】
After receiving the vertical synchronization signal VD and confirming the end of one frame, before the start of the next frame, the scanning time KHDi of each scanning line is loaded into the display timing generator 33 (step S39), and the limit data value LimDi is set to the limit data. Load into memory 52 (step S40).
【0571】
In the present embodiment, the processing performed by the microcomputer 34 can be executed by the CPU 102 of the discrete correction data calculation unit, and the microcomputer 34 can be omitted.
【0572】
(Limit data memory, limiter) The corrected image data Dout temporarily stored in the memory A26 or the memory B27 is output to the shift register 5 according to the read address signal of the R address generator 28.
【0573】
At this time, the limit data memory 52 limits the value of the corrected image data Dout according to the limit data value LimDi loaded from the microcomputer 34.
【0574】
That is, the limit data memory 52 outputs LimD1 for the data of the first scanning wiring, LimD2 for the data of the second scanning wiring, and LimDi for the data of the i-th scanning wiring, and the limiter 51 outputs the limit. The corrected image data having a value equal to or higher than the limit data value (LimDi) output from the data memory 52 is replaced with the limit data value (LimDi) and output.
【0575】
In the present embodiment, with such a configuration, it is possible to correct the voltage drop that occurs in the scanning wiring and to increase the brightness and display the image at the same time.
【0576】
Furthermore, if it is predicted that the total display horizontal scanning time of one frame will exceed a predetermined time, for example, the time of one frame of the input image signal, the display horizontal scanning time of one frame is limited from the longest display horizontal scanning time. After making the total time within a predetermined time, a limiter is applied to the corrected image data so as not to exceed the specified display horizontal scanning time. This makes it possible to display a high-quality image.
【0577】
As described above, according to the first to fourth embodiments of the present invention, the horizontal scanning time of each scanning wiring is appropriately allocated according to the maximum value of the corrected image data, so that the entire displayed image can be displayed. It is possible to correct the voltage drop of the scanning wiring with high accuracy and perform high-luminance display without causing a decrease in brightness.
【0578】
Further, by adjusting the horizontal scanning time and the corrected image data, it is possible to prevent the total display horizontal scanning time in one frame from exceeding a predetermined time.
【0579】
In the first to fourth embodiments described above, an example is shown in which the current flowing through the scanning wiring is large and the voltage drop of the scanning wiring is corrected. In the case of FED in which the voltage drop of the scanning wiring hardly occurs, the voltage drop correction unit 40 of FIG. 17 in the first to fourth embodiments is simply the inverse gamma processing unit 17, the data array conversion unit 9, and the data array. It may be composed of a multiplication unit that outputs by multiplying the output of the conversion unit 9 by a coefficient of 1 or more.
【0580】
A multiplication unit that multiplies the output of the data array conversion unit 9 by a coefficient of 1 or more and outputs it in the same manner as the voltage drop correction unit 40 shown in the first to fourth embodiments generates corrected image data larger than the image data. Outputs data larger than the image data input by. Then, by determining the scanning time with respect to the pulse width of the modulated signal, the brightness can be increased corresponding to the coefficient of 1 or more.
【0581】
The embodiment described below is a mode in which the selection period of the horizontal scanning period in at least two scanning wirings is set to be different within one frame period, and the modulation signal and the scanning selection signal are determined accordingly. ..
【0582】
(Fifth Embodiment) FIGS. 50 and 51 are partial block diagrams of the drive control device according to the present embodiment.
【0583】
In FIG. 50, a gain table 10 is provided, and the gain value stored therein is multiplied by the parallel three primary color signals Ra, Rb, and Rc from the inverse γ processing unit 17.
【0584】
Further, in FIG. 51, a limiter 53 for applying a predetermined limit to the output from the memory A26 or the memory B27 is provided.
【0585】
(Gain table) The gain table 10 of FIG. 50 is a circuit for storing the gain to be multiplied by the video signals Ra, Ga, and Ba output from the inverse γ processing unit 17. The gain at this time is not a constant value, but is set to a different value based on the address of the scanning wiring. Details will be described later.
【0586】
(Memory A, Memory B) The operations of the memory A26 and the memory B27 are the same as those of the above-described embodiments.
【0587】
FIG. 52 is a block diagram schematically showing the circuit configuration of the memory A26 used in the present invention. The memory B27 also has a similar circuit configuration. As shown in the figure, the memory A26 includes an address control unit 260 and eight bank memories including the first memory 261 to the eighth memory 268.
【0588】
The address control unit 260 controls the addresses of the first memory 261 to the eighth memory 268 based on the write address signal or the read address signal generated by the W address generation unit 21 or the R address generation unit 28.
【0589】
Each of the first memory 261 to the eighth memory 268 has a storage capacity capable of storing 1/8 of the corrected image data for one frame. When 720p is input as the input video signal, the number of effective pixels in the horizontal direction is 1280, and there are 3 data of R, G, B for each pixel, so the data for one line is 3 ×. There are 1280 = 3840 data. Therefore, each of the first memory 261 to the eighth memory 268 can store 3840/8 = 480 data as the number of data in the horizontal direction. As the number of data in the vertical direction, data for the total number of scanning lines of 750 lines can be stored.
【0590】
The corrected image data Dout output from the adder 12 is written to the memory A26 in the case of odd-numbered frames and in the memory B27 in the case of even-numbered frames according to the write address signal generated by the W address generator 21.
【0591】
At this time, the address control unit 260 enables the bank memory to be written among the first memory 261 to the eighth memory 268 according to the Hbank address (the Hbank address will be described later) included in the write address signal. (The enable line is not shown). Then, the addresses of the first memory 261 to the eighth memory 268 are simultaneously controlled by the address signals having the V address as the upper address and the H address as the lower address.
【0592】
Further, the corrected image data written in the memory A26 and the memory B27 is read according to the read address signal generated by the R address generation unit 28.
【0593】
At this time, the address control unit 260 enables all the bank memories of the first memory 261 to the eighth memory 268, and uses the address signals with the V address as the upper address and the H address as the lower address to enable the first memory 261 to the eighth memory. Control 268 addresses at the same time. Data SD1 to SD8 are read in parallel from each bank memory.
【0594】
The R address generation unit 28 determines the read timing of the line data for each horizontal scanning line according to the display timing signal KHD generated by the display timing generation unit 33 instead of the horizontal synchronization signal HD included in the input image signal. To do. The method of generating the display timing signal KHD will be described later.
【0595】
In the present embodiment, as described above, each of the memory A26 and the memory B27 is composed of a plurality of bank memories, and the corrected image data for one line is layered into eight outputs. The data transfer time (shift time) to 5 can be shortened. The same effect can be obtained by making the output and shift registers of the frame memory one and the read time of the frame memory shorter than the write time without layering.
【0596】
(W Address Generator) FIG. 53 is a block diagram schematically showing the circuit configuration of the W address generator 21. As shown in the figure, the W address generator 21 includes a V counter 210, an H upper counter 211, a comparator 212, and an H counter 213.
【0597】
The V counter 210 is a counter for generating and outputting an address Vcount indicating a vertical address (scanning wiring number), is reset by a vertical synchronization signal HD, counts a horizontal synchronization signal HD, and outputs the count value. To do. When 720p is used as the input signal, the number of scanning wires in the vertical direction is 750, so a 10-bit wide counter is used.
【0598】
The H counter 213 is a counter for outputting an address Hcount indicating a horizontal address (data number in one line), is reset by a horizontal synchronization signal HD, counts MCLK, and outputs the count value. As described above, since the number of horizontal data stored in one bank memory is 480, a 9-bit wide counter is used. The output of the H counter 213 is also input to the comparator 212.
【0599】
The H upper counter 211 is a counter for outputting Hbank indicating the bank memory for writing the corrected image data Dout. The H upper counter 211 is reset by the vertical synchronization signal HD, and counts when MCLK is input while the signal is input to the EN terminal. Since the memory A26 and the memory B27 each have eight banks, a 3-bit wide counter is used as the H upper counter 211.
【0600】
The comparator 212 compares the value stored in advance with the count value input from the H counter 213, and outputs a signal when both values are equal. The output of the comparator 212 is connected to the reset terminal RES1 of the H counter 213 and the EN terminal of the H upper counter 211. The comparator 212 stores a value of "479" as a value corresponding to the number of data (480) in the horizontal direction for one layer (one bank) of the memory A26 and the memory B27.
【0601】
In the above configuration, when the processing of one frame is started, the V counter 210 is first reset by the vertical synchronization signal VD. Then, the H counter 213 and the H upper counter 211 are reset by the horizontal synchronization signal HD. The H counter 213 counts MCLK and outputs the count value as Hcount.
【0602】
The count value output from the H counter 213 is also input to the comparator 212 and compared with the stored value 479. When the count value of the H counter 213 reaches 479, a signal is output from the comparator 212, and the count value of the H counter 213 is reset to 0 again. On the other hand, since a signal is also input to the EN terminal of the H upper counter 211, the H upper counter 211 counts at the next MCLK and outputs the count value as Hbank.
【0603】
Therefore, the H counter 213 repeatedly counts the values from 0 to 479. In addition, the H upper counter 211 increments the Hbank value by 1 for every 480 pieces of data to change the write bank.
【0604】
When the processing for one horizontal line is completed, the V counter 210 counts the horizontal synchronization signal HD and outputs the count value as Vcount. The H upper counter 211 and the H counter 213 are reset by the horizontal synchronization signal HD. After that, the processing of the next horizontal scanning line is repeated in the same manner.
【0605】
(R Address Generator) FIG. 54 is a block diagram schematically showing the circuit configuration of the R address generator 28. As shown in the figure, the R address generator 28 includes a V counter 280, a comparator 281 and an H counter 282.
【0606】
The V counter 280 is a counter for generating and outputting an address Vcount indicating a vertical address (scanning wiring number), and is a display timing signal that is reset by the vertical synchronization signal HD and generated by the display timing generator 33. KHD is counted and the count value is output. When 720p is used as the input signal, the number of scanning wires in the vertical direction is 750, so a 10-bit wide counter is used.
【0607】
The H counter 282 is a counter for outputting an address Hcount indicating a horizontal address (data number in one line), and is reset by the display timing signal KHD generated by the display timing generator 33 to set MCLK. It counts and outputs the count value. As described above, since the number of data in the horizontal direction stored in one bank memory is 480, a 9-bit wide counter is used. The output of the H counter 213 is also input to the comparator 212.
【0608】
The comparator 281 compares the value stored in advance with the count value input from the H counter 282, and outputs a signal when both values are equal. The output of the comparator 281 is connected to the reset terminal RES1 of the H counter 282. The comparator 281 stores a value of "479" as a value corresponding to the number of data (480) in the horizontal direction for one layer (one bank) of the memory A26 and the memory B27.
【0609】
In the above configuration, when the processing of one frame is started, the V counter 280 is first reset by the vertical synchronization signal VD. Then, the H counter 282 is reset by the display timing signal KHD. The H counter 282 counts MCLK and outputs the count value as Hcount.
【0610】
The count value output from the H counter 282 is also input to the comparator 281 and compared with the stored value 479. When the count value of the H counter 282 reaches 479, a signal is output from the comparator 281 and the count value of the H counter 282 is reset to 0 again. Therefore, the H counter 282 repeatedly counts the values from 0 to 479.
【0611】
When the processing for one horizontal line is completed, the V counter 280 counts the display timing signal KHD and outputs the count value as Vcount. The H counter 282 is reset by the display timing signal KHD. After that, the processing of the next horizontal scanning line is repeated in the same manner.
【0612】
Next, a method of generating the display timing signal KHD, that is, a method of controlling the horizontal scanning period will be described.
【0613】
(Regarding the control of the horizontal scanning period) In the present embodiment, instead of setting the horizontal scanning period of each scanning wiring to a constant value, a long scanning time is allocated to the scanning wiring that requires relatively high brightness. Allocate a short scan time for scan wires that do not require brightness.
【0614】
FIG. 55 is a schematic diagram showing an example of a horizontal scanning period of pixels on a plurality of scanning wirings. The vertical axis of the graph in the figure corresponds to each horizontal scanning line (scanning wiring). In the figure, 12 horizontal scanning lines are shown for the sake of simplicity. The horizontal axis of the graph represents time (pulse width).
【0615】
In the graph, the bar graph corresponding to each horizontal scanning line illustrates the corrected image data of the corresponding horizontal scanning line. The white rectangular portion shows the input image data (brightness data) to a certain pixel on the horizontal scanning line, and the hatched rectangular portion shows the correction data for the input image data. The vertical line (solid line) shown on the right side of the bar graph illustrates the displayed horizontal scanning time for each horizontal scanning line.
【0616】
As shown in the figure, of the 12 scanning wirings, the central scanning wiring has a display horizontal scanning period different from that of the scanning wiring at the end. Here, the display horizontal scanning period is set to be longer for the pixels on the horizontal scanning line in the center of the screen, and the display horizontal scanning time is shorter for the pixels on the horizontal scanning lines at the upper and lower ends of the screen. The line display horizontal scanning time changes convexly to the right in the figure.
【0617】
The corrected image data for each horizontal scanning line is subjected to a predetermined gain conversion for each scanning wiring so that the maximum value thereof falls within each display horizontal scanning time set as described above. That is, in the gain conversion at this time, the gain is increased as the pixels are on the horizontal scanning line in the center of the screen, and the gain is decreased as the pixels are on the horizontal scanning line at the upper and lower ends of the screen.
【0618】
If the sum of the display horizontal scanning times individually assigned to each horizontal scanning line is one frame time or less of the input video signal, one frame image can be displayed within one frame time. In other words, if the average display horizontal scanning time is equal to the horizontal scanning period obtained from the horizontal synchronization signal of the input video signal, one frame of image can be displayed within one frame time. In addition, since the human eye is relatively insensitive to the gradual change in brightness that changes from the center of the screen to the edge of the screen, the displayed image looks strange even if the brightness of each line is different, as shown in Fig. 55. I rarely feel.
【0619】
Of course, when the display frame time is slightly changed, the total of several frames of the display horizontal scanning time individually assigned to each horizontal scanning line may be set to be several frames or less of the input video signal.
【0620】
Next, the control of the display scanning time described here will be described in more detail.
【0621】
Maximum corrected image data with 8-bit width image data (maximum: 255) corrected when the scanning wiring resistance is about 5Ω, the element current of the surface conduction type emission element is about 0.1mA, and the number of elements is 720 x 1280 x 3 (RGB). The value will be about 350. Therefore, the bit width of the pulse width modulator is designed to be 9 bits.
【0622】
(Display Timing Generation Unit) FIG. 56 is a block diagram schematically showing a circuit configuration of the display timing generation unit 33. The difference from the configuration shown in FIG. 31 is the control of the memory 331 and the data stored therein.
【0623】
The memory 331 stores in advance the number of MCLKs (1H MCLKs) of each horizontal scanning line in order to set the horizontal scanning period of the pixels on each scanning wiring. The memory 331 is the value obtained by subtracting 1 from the number of MCLKs of the first horizontal scanning line at address 0 (1H number of MCLKs-1), and subtracting 1 from the number of MCLKs of the second horizontal scanning line at address 1. The values are stored in the following order at the address (i-1), which is the number of MCLKs of the horizontal scanning line of the i-th line minus 1. Then, when the address i is input from the V counter 333, the number of MCLKs corresponding to the address i is output to the comparator 332.
【0624】
The comparator 332 compares the value input from the H counter 330 (count value of MCLK) with the value input from the memory 331, that is, the number of MCLKs of each predetermined horizontal scanning line, and when both match. Outputs a signal only to.
【0625】
The display timing generation unit 33 configured in this way generates the display timing signal KHD as follows.
【0626】
First, when the vertical synchronization signal VD is input, the counter values of the H counter 330 and the V counter 333 are reset, and the processing of one frame is started.
【0627】
Synchronized with MCLK, the V counter 333 outputs a counter value of 0 to the memory 331, and in response to this, the memory 331 outputs the number of MCLKs of the first horizontal scanning line, actually "1H number of MCLKs-1". Output to the comparator 332. On the other hand, the H counter 330 counts MCLK and outputs the counter value N to the comparator 332.
【0628】
A signal is output from the comparator 332 when the counter value N of the H counter 330 becomes equal to the number of MCLKs. Since the comparison process here is performed in synchronization with MCLK, the output signal from the comparator 332 becomes the display timing signal KHD corresponding to the end of the first line (or the start of the second line).
【0629】
Then, when the display timing signal KHD is output, the counter value of the H counter 330 is reset and the counter value of the V counter 333 is incremented. Therefore, from here on, the V counter 333 outputs the counter value 1 to the memory 331, and the memory 331 outputs the number of MCLKs of the second horizontal scan line (actually, the number of 1H MCLKs-1) to the comparator 332. It will be. Since the H counter 330 starts counting MCLK from 0 again, the display timing signal KHD (end of the second line (end of the second line (end of the second line)) is displayed from the comparator 332 when the count value reaches the MCLK number of the horizontal scanning line in the same manner as above. Or (corresponding to the start) of the third line) is output.
【0630】
This process is repeated in sequence to generate a display timing signal KHD having the number of MCLKs according to the number of MCLKs of each horizontal scanning line stored in advance in the memory 331 for all the lines included in one frame.
【0631】
The display timing signal KHD generated in this way is input to the R address generation unit 28. As described above, the R address generator 28 generates a read address signal according to the display timing signal KHD, and outputs the signal to the read side memory via the switch 25.
【0632】
The total number of lines when reading data from the memory A26 and the memory B27 is preferably 720 or more, which is the effective number of scanning lines, and more preferably 725 to 750 from the timing design margin, more preferably. , 730 to 749 should be used.
【0633】
As an example, FIGS. 57 and 58 show an example in which the H counter 330 and the V counter 333 are reset by the vertical synchronization signal VD during the processing of the 744th line. The graph shown by the solid line in FIG. 57 illustrates a table of 1H MCLK numbers for each horizontal scanning line stored in the memory 331. FIG. 58 is a table showing the number of 1H MCLKs, the number of SCLKs (the number of Pwmclk), and the number of MAXpwm for each horizontal scanning line.
【0634】
In this way, in the memory 331, there is a table in which the number of MCLKs increases as the horizontal scanning line in the center of the screen increases, and the number of MCLKs decreases as the horizontal scanning lines at the upper and lower ends of the screen decrease. It is stored. As a result, the display horizontal scanning time of the horizontal scanning line changes to a convex state, that is, a state of being relatively short at the top and bottom of the screen and relatively long at the center.
【0635】
Here, a table is used in which the number of 1H MCLKs is set to change stepwise every 60 lines, but it changes smoothly to each horizontal scanning line as shown by the dotted line in FIG. 57. It is also preferable to use the table set in. As the curve at that time, for example, a curve represented by a quadratic equation, a Gaussian curve, or the like can be used.
【0636】
In the present embodiment, 720p is used as the input video signal, and the number of sample clocks (number of MCLKs) in one horizontal scanning period is designed to be 1648, so that the number of MCLKs in one frame is 750 × 1648 = 1236000 clocks. Then, when the number of MCLKs of each horizontal scanning line is set as shown in FIGS. 57 and 58, the total number of MCLKs from the first line to the 743th line is 1235344 clocks, and the total number of MCLKs from the first line to the 744th line is 1235344 clocks. Since is 12366672 clock, the H counter 330 and the V counter 333 are reset by the vertical synchronization signal VD in the middle of the timing of the horizontal scanning line of the 744th line.
【0637】
The MAXpwm number is the maximum value that the corrected image data can take, and more specifically, it is a value converted into the number of clocks (Pwmclk number) for pulse width modulation.
【0638】
The display timing of each horizontal scanning line is determined by the display timing signal KHD, but if the horizontal scanning line is switched and the vertical modulation line is driven (rising and falling) at the same time, the drive waveform in the panel is disturbed and displayed. Excessive voltage may be applied to the element. Therefore, it is not possible to allocate all the time corresponding to the number of 1H MCLKs to the PWM drive time.
【0639】
In this embodiment, the MCLK cycle is about 13.5 nSec and the Pwmclk cycle is about 27 nSec. Since it is sufficient to secure about 2 μSec as the non-driving time for switching the scanning wiring, set 74Pwmclk to the non-driving time.
【0640】
Therefore, the MAXpwm number is a value obtained by subtracting 74 from the Pwmclk number determined by the display timing signal KHD, and is obtained as shown in the table of FIG. 58.
【0641】
(Gain table) FIG. 59 is a block diagram schematically showing the circuit configuration of the gain table 10. As shown in the figure, the gain table 10 includes a memory 220 and a V counter 221.
【0642】
The memory 220 is a storage means for storing a data table in which a scanning wiring number and a gain (GAIN) are associated with each other, and the data stored therein determines a modulation signal according to a set horizontal scanning period. It has become.
【0643】
When the processing for one frame is started, the V counter 221 is first reset by the vertical synchronization signal VD (the count value becomes 0). Then, the V counter 221 counts the horizontal synchronization signal HD and outputs the count value. The output of the V counter 221 is connected to the address of the memory 220, and the memory 220 outputs the gain (GAIN) corresponding to the count value input from the V counter 221. The memory 220 stores a table in which the gain of the first line is output when the count value is 0.
【0644】
The gain GAIN corresponding to each horizontal scanning line is determined as follows from the maximum data value DataMAX of the corrected image data and the MAXpwm corresponding to each horizontal scanning line obtained as described above. GAIN MAXpwm / DataMAX [0645]
Here, DataMAX is obtained by performing the above-mentioned voltage drop correction processing when image data such that all the input data of one horizontal scanning line has the maximum value (255 in the case of 8 bits) is input. This is the value of the corrected image data. That is, when such image data is input, the voltage drop becomes maximum and the corrected image data takes the maximum value. Therefore, the above GAIN is set so that the corrected image data (DataMAX) at this time does not exceed MAXpwm. To do.
【0646】
60 and 61 show an example of the gain table. The graph shown by the solid line in FIG. 60 illustrates a table of gain (GAIN) of each horizontal scanning line stored in the memory 220. FIG. 61 shows the gain (GAIN) added to the table of FIG. 58.
【0647】
In this way, the memory 220 stores a table in which the gain increases toward the horizontal scanning line in the center of the screen and decreases toward the horizontal scanning lines at the upper and lower ends of the screen. There is. As a result, the corrected image data undergoes convex gain conversion according to the display horizontal scanning time of the horizontal scanning line, and is limited to a smaller value as the corrected image data related to the horizontal scanning lines at the upper and lower ends of the screen, and is displayed horizontally. It will fit within the scanning time.
【0648】
Here, a gain table set so that the gain changes stepwise for every 60 lines is used, but the gain changes smoothly for each horizontal scanning line as shown by the dotted line in FIG. 60. It is more preferable to use the set gain table. As the curve at that time, for example, a curve represented by a quadratic equation, a Gaussian curve, or the like can be used. Further, if the horizontal scanning period is set to a stepped shape and the gain table is set to a value having a smooth convex shape, the display luminance change can be displayed smoothly and without discomfort.
【0649】
(Limiter) The corrected image data SD1 to SD8 read from the memory A26 or the memory B27 are input to the limiter 53 of FIG. 51 according to the display timing signal KHD generated by the display timing generation unit 33.
【0650】
The limiter 53 is a circuit that limits the corrected image data SD1 to SD8 so that they fall within the value of MAXpwm or less when the corrected image data SD1 to SD8 exceed MAXpwm. Here, since the value of MAXpwm is different for each horizontal scanning line, the limiter 53 has a different limit value for each horizontal scanning line.
【0651】
The corrected image data SD1 to SD8 output from the limiter 53 are input to separate shift registers 5.
【0652】
(Shift register, latch circuit) The same as in each of the above-described embodiments.
【0653】
In the present embodiment, the image data IDs 1 to IDN and D1 to DN are 9-bit image data, respectively.
【0654】
The operation timing of the shift register 5 is based on the shift clock SCLK from the display timing generation unit 33.
【0655】
(Operation timing of each part) Fig. 62 and Fig. 63 show the timing chart of the operation timing of each part. Further, FIG. 63 is a timing chart in which FIG. 62 is partially enlarged.
【0656】
In FIGS. 62 and 63, Hsync (HD) is a horizontal synchronization signal, and DotCLK (MCLK) is a sampling clock created from the horizontal synchronization signal Hsync by the PLL circuit in the timing generation circuit 11. SRGB is digital image data in parallel for each R, G, B from RGB conversion means 7, and 3MCLK is a clock used for data array conversion of parallel data for each R, G, B into series data. It has three times the frequency of DotCLK (MCLK).
【0657】
Data is the image data after data array conversion, Dout is the corrected image data, SD1 to SD8 is the corrected image data output from memory A26 or memory B27 in multiple layers, and SCLK is the corrected image data SD1 to SD8 to shift register 5. Shift clock for transfer, Dataload is load pulse for latching data to latch circuit 6, Pwmstart is the start signal of pulse width modulation described above, modulation signal XD1 is pulse width modulation signal supplied to modulation wiring 1, Dx1 Is an example of the potential supplied from the scanning drive circuit 2 to the scanning wiring.
【0658】
The KHD is an example of a display timing signal for operating the scanning drive circuit 2 and the modulation driving circuit according to the determined display horizontal scanning period.
【0659】
1 At the start of the horizontal scanning period, digital image data RGB is transferred from the input switching circuit. In the figure, the input image data is represented by R_I, G_I, and B_I in the horizontal scanning period I. The image data R_I, G_I, B_I are multiplied by the gain supplied from the gain table 10. Image data is stored in the data array conversion unit 9 for one horizontal scanning period, and is output as digital image data Data_I in the horizontal scanning period I + 1 according to the pixel arrangement of the display panel.
【0660】
R_I, G_I, and B_I are input to the correction data calculation means 14 during the horizontal scanning period I. In this means, the number of lights described above is counted, and the amount of voltage drop is calculated at the end of the count.
【0661】
Following the calculation of the voltage drop amount, the discrete correction data is calculated, and the calculation result is stored in the register.
【0662】
Moving to the scanning period I + 1, the data array conversion unit 9 outputs the image data Data_I one horizontal scanning period before, and the correction data interpolation unit 142 interpolates the discrete correction data, and the correction data is generated. It is calculated. The interpolated correction data is immediately subjected to gradation number conversion by the gradation number conversion unit and supplied to the adder 12.
【0663】
In the adder 12, the image data Data and the correction data CDz are sequentially added, and the corrected image data Dout is transferred to the multilayer device (memory A, B). In the figure, the contacts of switches 23, 24, 25, and 29 are a, a, b, and a, respectively, so Dout is written to the memory A26. At this time, the Dout one frame before is read from the memory B27.
【0664】
The corrected image data SD1 to SD8 layered from the memory B27 into eight layers are transferred to the shift register 5 after the limit processing is performed by the limiter 53.
【0665】
The eight shift registers 5 store the corrected image data SD1 to SD8 (totally image data for one horizontal scanning period) according to SCLK, perform serial / parallel conversion, and latch the parallel image data ID1 to IDN. Output to circuit 6. The latch circuit 6 latches the parallel image data ID1 to IDN from the shift register 5 according to the rising edge of the Dataload synchronized with the display timing signal KHD, and transfers the latched image data D1 to DN to the pulse width modulation circuit 8.
【0666】
The pulse width modulation circuit 8 outputs a pulse width modulation signal having a pulse width corresponding to the latched image data. In the present embodiment, the display control of each horizontal scanning line is performed based on the display timing signal KHD different from the horizontal synchronization signal HD. Therefore, as shown in the figure, the pulse width modulation signal I-1 may be longer than one horizontal scan period.
【0667】
In this way, the amount of voltage drop in the scanning wiring can be corrected, and the deterioration of the display image caused by the voltage drop can be improved.
【0668】
In addition, by calculating the correction data discretely and interpolating between the points calculated discretely, the correction data can be calculated very easily, and the hardware is very simple. You can do that with hardware.
【0669】
Then, by appropriately allocating the display scanning time of each scanning wiring, the voltage drop that occurs in the scanning wiring is corrected, and the image is displayed with the brightness with respect to the resistance value of the scanning wiring of 0Ω, that is, the voltage due to the scanning wiring resistance. It is possible to achieve both a higher brightness display than when driving in a lowered state.
【0670】
(Sixth Embodiment) FIG. 64 shows a sixth embodiment of the present invention. In the fifth embodiment, gain is applied to the RGB parallel image data Ra, Ga, and Ba that have been subjected to the inverse γ conversion processing by the inverse γ processing unit 17, but in the present embodiment, the reverse is applied. It was decided to apply a gain to the image data R, G, and B before the γ conversion process. The other configurations and operations are the same as those in the fifth embodiment.
【0671】
The gain table 10 is a circuit that multiplies the video signals R, G, and B output from the RGB conversion means 7 by a predetermined gain. The gain at this time is not a constant value, but is set to a different value based on the scanning wiring number related to the video signal.
【0672】
Specifically, as in the fifth embodiment, it has a table in which the scanning wiring number and the gain (GAIN) are associated with each other, and this table has a larger gain as the horizontal scanning line in the center of the screen. Also, the gain is set to decrease toward the horizontal scanning lines at the upper and lower ends of the screen. As a result, the corrected image data undergoes convex gain conversion according to the display scanning time of the horizontal scanning line, and is limited to a smaller value as the corrected image data related to the horizontal scanning lines at the upper and lower ends of the screen, and the display scanning time. It will fit inside.
【0673】
However, since the image data R, G, and B before the inverse gamma conversion process have non-linearity, it is preferable to set a larger gain than in the fifth embodiment.
【0674】
With such a configuration, the same effect as that of the fifth embodiment can be obtained.
【0675】
(7th Embodiment) FIG. 65 shows a 7th embodiment of the present invention. In the fifth embodiment, the gain is applied to the image data, but in the present embodiment, the gain is applied to the correction data for correcting the image data. The other configurations and operations are the same as those in the fifth embodiment.
【0676】
The gain table 10 is a circuit for multiplying the correction data CD output from the correction data calculation means 14 by a predetermined gain. The gain at this time is not a constant value, but is set to a different value based on the scanning wiring number related to the video signal.
【0677】
Specifically, as in the fifth embodiment, it has a table in which the scanning wiring number and the gain (GAIN) are associated with each other, and this table has a larger gain as the horizontal scanning line in the center of the screen. Also, the gain is set to decrease toward the horizontal scanning lines at the upper and lower ends of the screen. As a result, the correction data CD undergoes convex gain conversion, and the correction data related to the horizontal scanning lines at the upper end and the lower end of the screen is limited to a smaller value.
【0678】
Therefore, the corrected image data Dout, which is obtained by adding the correction data after gain conversion to the image data Data output from the delay circuit 19, is set on the horizontal scanning lines at the upper and lower ends of the screen according to the display scanning time of the horizontal scanning line. The corrected image data is limited to a smaller value and fits within the display scanning time.
【0679】
With such a configuration, the same effect as that of the fifth embodiment can be obtained.
【0680】
(8th Embodiment) FIG. 66 shows an 8th embodiment of the present invention. In the fifth embodiment, the gain is applied to the image data, but in the present embodiment, the gain is applied to the corrected image data after correction. The other configurations and operations are the same as those in the fifth embodiment.
【0681】
The gain table 10 is a circuit for multiplying the corrected image data Dout output from the adder 12 by a predetermined gain. The gain at this time is not a constant value, but is set to a different value based on the scanning wiring number related to the video signal.
【0682】
Specifically, as in the fifth embodiment, it has a table in which the scanning wiring number and the gain (GAIN) are associated with each other, and this table has a larger gain as the horizontal scanning line in the center of the screen. Also, the gain is set to decrease toward the horizontal scanning lines at the upper and lower ends of the screen. As a result, the corrected image data Dout undergoes convex gain conversion according to the display scanning time of the horizontal scanning line, and is limited to a smaller value as the corrected image data related to the horizontal scanning lines at the upper and lower ends of the screen, and the display scanning is performed. It will fit in time.
【0683】
With such a configuration, the same effect as that of the fifth embodiment can be obtained.
【0684】
(9th Embodiment) In each of the above embodiments, a gain table having a table in which a scanning wiring number and a gain (GAIN) are associated with each other is used to display scanning time on image data, correction data, or correction image data. Although the configuration is such that the convex gain conversion is performed according to the above, it is also preferable to use the limiter instead of the gain table.
【0685】
At this time, the limit value of the limiter is not a constant value, but is set to a different value based on the scanning wiring number. For example, if the limit value is set to be larger toward the horizontal scanning line in the center of the screen and smaller toward the horizontal scanning lines at the upper and lower ends of the screen, the display horizontal scanning time of the horizontal scanning line can be set. At the same time, the corrected image data related to the horizontal scanning lines at the upper end and the lower end of the screen can be limited to a smaller value so as to be within the display horizontal scanning time.
【0686】
Further, it is even better if the limiter has the limiter characteristics as shown in FIG. 67. That is, if the limit value is a characteristic that gently changes according to the magnitude of the value of the input data, a high-quality display image can be obtained without impairing the gradation of the image data. The limiter characteristic is not limited to that shown in FIG. 67, and it is sufficient that the limiter characteristic has a point where the inclination becomes gentle from the middle. Therefore, the inclination and the position of the point where the inclination changes are appropriately determined.
【0687】
As described above, according to the display devices according to the fifth to ninth embodiments, the voltage drop of the scanning wiring is corrected with high accuracy without causing a decrease in the brightness of the entire displayed image, and the quality is high. Can display various images.
【0688】
Further, the drive control method of the present invention described above can be realized by an integrated circuit integrated on one chip together with a video signal processing circuit or the like. In this case, the frame memory may be excluded and integrated. The drive control method in this case is preferably an RTL soft IP such as VHDL that can be logically synthesized with other IP cores as an IP core (design asset).
【0689】
Alternatively, the drive control method of the present invention may be realized as a program loaded and executed by a microcomputer.
【0690】
In the fifth, sixth, eighth, and ninth embodiments described above, an example is shown in which the current flowing through the scanning wiring is large and the voltage drop of the scanning wiring is corrected. In the case of FED in which the voltage drop of the scanning wiring hardly occurs, the voltage drop correction unit 40 of FIGS. 50, 64, and 66 in each of these embodiments is simply combined with the inverse gamma processing unit 17 and the data array conversion unit 9. , The output of the data array conversion unit 9 may be multiplied by a coefficient of 1 or more and output.
【0691】
Similar to the voltage drop correction unit 40 shown in each of these embodiments generating corrected image data larger than the image data, the data is input by the multiplication unit that outputs the output of the data array conversion unit 9 by multiplying it by a coefficient of 1 or more. Outputs data larger than the image data.
【0692】
Then, by determining the scanning time corresponding to the pulse width of the modulated signal, the brightness can be increased corresponding to the coefficient of 1 or more.
【0693】
Further, in the case of this configuration, by multiplying the gain table 10 by a coefficient of 1 or more in advance, it is possible to omit the multiplication unit that outputs by multiplying the output of the data array conversion unit 9 by a coefficient of 1 or more. is there.
【0694】
In the embodiment described below, a scan selection signal is transmitted to a display unit in which a plurality of display elements are connected in a matrix by a plurality of row wirings and a plurality of column wirings, and one row wiring among the plurality of row wirings. A scanning drive circuit that applies and performs horizontal scanning and sequentially switches the selected row wiring to perform vertical scanning, and a modulation drive that applies a modulation signal according to the image data input to each of the plurality of column wirings. It is equipped with a circuit and a frame memory that can store at least one frame of input video data, and depending on the input image data, the selection time of the line wiring corresponding to the large part of the image data level is lengthened, and the image It is a display device provided with a control means for calculating an operation timing in which the selection time of the row wiring corresponding to a portion having a small data level is shortened and controlling the scanning drive circuit and the modulation drive circuit at the operation timing.
【0695】
Here, the control means includes a multiplication means for multiplying the calculated coefficient by the image data to generate new image data according to the operation timing, and the modulation drive circuit responds to the new image data. It is also preferable to drive the row wiring.
【0696】
The modulation drive circuit is a pulse width modulation circuit that counts a reference clock (PCLK) with a pulse width corresponding to image data and drives the column wiring, and the control means is a reference having a period corresponding to a calculated coefficient. It is also preferable to provide an oscillating means that generates a clock (PCLK) according to the operation timing.
【0697】
It is also preferable that the row maximum value detecting means for detecting the maximum value of the brightness level of the input image data for each row is provided, and the operation timing is calculated according to the output of the row maximum value detecting means.
【0698】
The row maximum value detecting means for detecting the maximum value for each row of the luminance level and the column maximum value detecting means for detecting the maximum value for each column of the luminance level are provided, and the operation timing is the row maximum value detecting means of the row maximum value detecting means. It is also preferable to calculate according to the output and the output of the column maximum value detecting means.
【0699】
The control means is a memory reference means for referencing / rewriting the image data stored in the frame memory, and the calculated coefficient is multiplied by the image data to generate new image data according to the operation timing. It is also preferable that the modulation drive circuit is provided with a video signal rewriting means for rewriting the contents of the frame memory into the new image data, and the modulation drive circuit drives the row wiring according to the new image data.
【0700】
It is also preferable that the control means calculates the maximum value for each row of the image data read into the frame memory, and determines the coefficient according to the calculated maximum value.
【0701】
The control means calculates the maximum value for each row of the image data read into the frame memory and the maximum value for each column of the image data read into the frame memory, respectively, and responds to the calculated maximum value. It is also preferable to determine the coefficient.
【0702】
It is also preferable that the upper limit of the coefficient to be multiplied by the image data is set.
【0703】
The number of rows and wirings is m rows, the number of previous column wirings is n columns, the value for each pixel of the image data is L (x, y), and the upper limit of the coefficient to be multiplied by the image data is Al, rows or columns. When the lower limit of the maximum value of each image data is Lmin and the horizontal scanning period of the input video signal is Th, the control means is LHm (y) = MAX {L (1, y) ~ L (n, y), Lmin} As a result, find the maximum value LHm (1) to LHm (m) of the image data level for each row. LHa = Σ {LHm (1) ~ LHm (m)} / m As a result, find the average value of LHm, LHa. Ah = 1 / LHa As a result, the horizontal image data level coefficient Ah is calculated. LVm (x) = MAX {L (x, 1) ~ L (x, m), Lmin} As a result, find the maximum value of the image data level for each column, LVm (1) to LVm (n). LVa = Σ {LVm (1) ~ LVm (n)} / n As a result, find the average value of LVm, LBa. Av = 1 / LBa As the vertical image data level coefficient Av, Am = MIN {Ah, Av, Al} As a result, the image data level coefficient Am is obtained from the minimum value of each image data level coefficient. L (x, y) = Am · L (x, y) As a result, all pixels are rewritten to the value obtained by multiplying the image data level coefficient Am. And Thi (y) = Th · LHm (y) / LHa It is also preferable to obtain the horizontal scanning times Thi (1) to Thi (m) assigned to each scanning wiring. This method can display an image in which a bar on a bright straight line rotates in the screen on a dark background without degrading the image quality.
【0704】
The number of rows and wirings is m rows, the number of previous column wirings is n columns, the value for each pixel of the image data is L (x, y), and the upper limit of the coefficient to be multiplied by the image data is Al, rows or columns. When the lower limit of the maximum value of each image data is Lmin, the control means LHm (y) = MAX {L (1, y) ~ L (n, y), Lmin} As a result, find the maximum value LHm (1) to LHm (m) of the image data level for each row. LHa = Σ {LHm (1) ~ LHm (m)} / m As a result, find the average value of LHm, LHa. Ah = 1 / LHa As a result, the horizontal image data level coefficient Ah is calculated. Am = MIN {Ah, Al} As a result, the image data level coefficient Am is obtained from the minimum value of each image data level coefficient. L (x, y) = Am · L (x, y) Rewrite to the value obtained by multiplying the image data level coefficient Am for all pixels. Thi (y) = Th · LHm (y) / LHa Therefore, it is also preferable to obtain the horizontal scanning times Thi (1) to Thi (m) assigned to each scanning line.
【0705】
It is also preferable to realize a function equivalent to a part or all of the functions of the control means provided in the image display device with an integrated circuit integrated into one chip or a plurality of integrated circuit chips. Specifically, in order to integrate with the frame memory or excluding the frame memory, this drive control method should be an RTL soft IP such as VHDL that can be logically synthesized with other IP cores as an IP core. Is also preferable.
【0706】
It is also preferable that the control means of the image display device is realized by an image display program.
【0707】
In that case, it is also preferable to store the image display program in a computer-readable recording medium.
【0708】
(10th Embodiment) FIG. 68 shows a schematic configuration of a display device according to the 10th embodiment of the present invention.
【0709】
1 is a display panel as an image display unit. The scanning wirings Dx1 to Dxm, which are the row wirings in the row direction, and the modulation wirings Dy1 to Dy3n, which are the column wirings in the column direction, are arranged in a matrix, and display elements (not shown) are arranged on each intersection. It is equipped with a display element of m rows and 3n columns.
【0710】
Further, the pixels by this display element are repeatedly arranged in the order of red, green, and blue in the row direction, and each one color is a total of 3 pixels, which is a full-color unit pixel. Therefore, the display panel 1 is arranged in a matrix of m rows and n columns for each color, and has m × n full-color unit pixels.
【0711】
Reference numeral 2 denotes a scanning drive circuit as a scanning driving means. Reference numeral 3 denotes a modulation drive circuit as a modulation drive means. The modulation drive circuit 3 is further composed of a shift register 5, a latch circuit 6, and a modulation circuit 8 that performs modulation such as pulse width modulation and voltage amplitude modulation. The modulation circuit 8 may have a drive amplifier in its output stage. 13 is a synchronous separation circuit. 41 is an AD converter. 42 is a control circuit consisting of a microcomputer or a logic circuit. 43 is a frame memory that stores one frame of the image signal. Reference numeral 44 denotes a memory bus for the control circuit 42 to read the contents of the frame memory 43.
【0712】
SS1 is an analog video signal input to the device. SS2 is a synchronization signal separated from the analog video signal SS1. SS3 is a digital image signal (image data) written to the frame memory 43. SS4 is an image signal (image data) read from the frame memory 43.
【0713】
SS5 is a conversion timing signal supplied to the AD converter 41. SS6 is a write timing signal to the frame memory 43. SS7 is a read timing signal from the frame memory 43.
【0714】
SS8 is a modulation control signal that controls the operation of the modulation drive circuit 3. SS9 is a scanning control signal that controls the operation of the scanning drive circuit 2. SS10 is a PWM clock that serves as an operating reference for the modulation circuit 8.
【0715】
The synchronization signal SS2 extracted by the synchronization separation circuit 13 from the analog video signal SS1 input to the apparatus is input to the control circuit 42. The horizontal scanning period of the synchronization signal SS2 extracted here is hereinafter referred to as Th.
【0716】
The control circuit 42 generates various control signals SS6 to SS9 based on the synchronization signal SS2. It also reads and writes the contents of the frame memory 43 through the memory bus 44.
【0717】
The AD converter 41 inputs the analog video signal SS1 according to the conversion timing signal SS5, converts it into a digital signal, and outputs the digital image signal SS3 for writing to the frame memory.
【0718】
The frame memory 43 has a capacity for storing a digital image signal for one frame, inputs a digital image signal SS3 according to the write timing signal SS6, stores a digital image signal for one frame, and stores the digital image signal for one frame, and digital image signal SS4 according to the read timing signal SS7. Is output.
【0719】
The image data level for each color of each pixel of the image for one frame stored in the frame memory 43, that is, the value corresponding to the brightness level of the input video signal is set to Lr (1,1) to Lr (, respectively). Let n, m), Lg (1,1) ~ Lg (n, m), Lb (1,1) ~ Lb (n, m).
【0720】
The following description will be given assuming that the image data level is normalized to 0 to 1 at the time of conversion by the AD converter 41.
【0721】
The operation in which the scanning drive circuit 2 and the modulation drive circuit 3 drive the display panel 1 will be described. The timing diagram at this time is shown in FIG. 69.
【0722】
The control circuit generates a timing signal (scanning control signal) SS9 and a read timing signal SS7 for determining the display horizontal scanning period, and further generates a modulation control signal SS8 and a PWM clock SS10.
【0723】
The scanning drive circuit 2 drives the scanning wiring of the display panel 1 to be sequentially selected according to the scanning control signal SS9. The selection time of this scanning wiring is not constant, and can be driven by the scanning control signal SS9 at an arbitrary time and interval.
【0724】
The modulation drive circuit 3 sequentially inputs the digital image signal SS4 to the shift register 5 in synchronization with the read timing signal SS7, and holds the image data in the latch circuit 6 by the LOAD signal of the modulation control signal SS8. Then, by the START signal of the modulation control signal SS8, a modulation signal having a pulse width and a predetermined voltage amplitude according to the image data held in the latch circuit 6 with reference to the PWM clock SS10 is sent to the modulation wiring of the display panel 1. Output and drive display panel 1.
【0725】
This modulation circuit 8 outputs a modulation signal during the same period as the horizontal scanning cycle Th period when the image signal SS4 is level 1. Further, the image signal SS4 can be input in the range from level 0 to level 2, and when the image signal SS4 is level 2, the modulated signal is output during the period corresponding to the 2Th period.
【0726】
This mechanism can be realized by using a counter having a length that allows the image signal SS4 to correspond to level 2 in the modulation circuit 8 and forcibly resetting the counter for each scanning wiring by the RESET signal of the modulation control signal SS8.
【0727】
Next, a method of determining the timing of the scanning control signal SS9 output from the control circuit 42 will be described. The flow of this process is shown in FIG. 70.
【0728】
In the following description, Al is the image data level coefficient limit value. This is the ratio of the maximum value of the signal SS3 output by the AD converter to the maximum value of the signal SS4 that can be input to the modulation drive circuit 3, which is 2 here.
【0729】
Also, Lmin is the lowest image data level. This is a value obtained by converting the time required to input the image signal SS4 for one line into the modulation drive circuit 3 into the video signal level. It is used to prevent the phenomenon that the horizontal scanning period becomes too short and the next scanning starts before the image signal SS4 for one line is input to the modulation drive circuit 3.
【0730】
In FIG. 70, in step P1 L (x, y) = MAX {Lr (x, y), Lg (x, y), Lb (x, y)} , The maximum value L (1,1) to L (n, m) of the image data level for each pixel is obtained.
【0731】
In step P2 LHm (y) = MAX {L (1, y) ~ L (n, y), Lmin} As a result, the maximum value LHm (1) to LHm (m) of the image data level for each row is obtained.
【0732】
In step P3 LHa = Σ {LHm (1) ~ LHm (m)} / m As a result, the average value LHa of LHm is calculated.
【0733】
In step P4 Ah = 1 / LHa As a result, the horizontal image data level coefficient Ah is obtained.
【0734】
In step P5 LVm (x) = MAX {L (x, 1) ~ L (x, m), Lmin} , The maximum value of the image data level for each column, LVm (1) to LVm (n), is obtained.
【0735】
In step P6 LVa = Σ {LVm (1) ~ LVm (n)} / n As a result, the average value of LVm, LBa, is calculated.
【0736】
In step P7 Av = 1 / LBa To obtain the vertical image data level coefficient Av.
【0737】
In step P8 Am = MIN {Ah, Av, Al} The image data level coefficient Am is obtained from the minimum value of each image data level coefficient.
【0738】
In step P9 Lr (x, y) = Am Lr (x, y) Lg (x, y) = Am Lg (x, y) Lb (x, y) = Am Lb (x, y) As a result, all the pixels are rewritten to the value obtained by multiplying the image data level coefficient Am by the multiplication means.
【0739】
In step P10 Thi (y) = Th · LHm (y) / LHa The horizontal scanning times Thi (1) to Thi (m) assigned to each scanning wiring are obtained. Here, Th is the horizontal scanning period of the input video signal.
【0740】
Since the image data level coefficient limit value Al is provided, the total of the calculated horizontal scanning times Thi (1) to Thi (m) may be shorter than the one-frame period. In that case, vertical blanking. We don't really think about it in this step, as we can extend the period and adjust it.
【0741】
Further, the sum of the horizontal scanning times Thi (1) to Thi (m) assigned to each scanning wiring is m · Th, which is a predetermined value. That is, the horizontal scanning time Thi assigned to each scanning wiring is calculated without changing the sum of the horizontal scanning times of the input video signals. Further, an upper limit value may be set for the selection time allocated to each scanning wiring so that the sum of the horizontal scanning times of the input video signals does not change.
【0742】
By calculating the horizontal scanning time Thi assigned to each scanning wiring as described above and controlling the scanning drive circuit 2 and the modulation drive circuit 3 at the timing based on the calculation, when the image is generally bright, the normal brightness is obtained. It is possible to automatically adjust the brightness so that it becomes brighter when it is partially bright or when it is totally dark. That is, the selection time of each scanning wiring is selected according to the input image so that the lighting time of the pixels on the scanning wiring in the bright part of the image is long and the lighting time of the pixels on the scanning wiring in the dark part of the image is short. By adjusting and driving the image and effectively using the image within one frame period, it is possible to fully demonstrate the capabilities of the image display device and provide a display device having a bright peak brightness.
【0743】
(11th Embodiment) In the 10th embodiment described above, it is also possible to omit obtaining the vertical image data level coefficient Av.
【0744】
In that case, omit the operations of steps P5 to P7 and repeat step P8. Am = MIN {Ah, Al} And correct it. The configuration of other devices and the calculation steps are the same as those in the tenth embodiment.
【0745】
A flowchart of the calculation of this embodiment is shown in FIG.
【0746】
When this embodiment is applied, the change in brightness due to the change in the pattern of the input image tends to be unstable, but the amount of calculation is reduced, which is effective when the cost of the device is emphasized.
【0747】
(12th Embodiment) When a part of the calculation steps performed in the control circuit 42 in the 10th embodiment described above is made into hardware, it can be realized with almost the same configuration.
【0748】
FIG. 72 shows the configuration of the image display device according to the twelfth embodiment.
【0749】
45 and 46 are comparators that compare the two input signals and output the larger one. Reference numeral 47 denotes a line memory composed of shift registers capable of storing data for one scanning line of a video signal. 48 is a multiplier as a video signal rewriting means. Here, the comparators 45 and 46 and the line memory 47 constitute a memory reference means. Further, at least the comparators 45, 46, the line memory 47 and the multiplier 48 may be composed of a plurality of chip integrated circuits or a single chip integrated circuit.
【0750】
The write signal SS3 and its own output are input to the comparator 45, and by inputting a clear signal (not shown) for each scan line, the horizontal maximum value SS13, which is the maximum value of the signal SS3 for each scan line, is obtained. Obtainable.
【0751】
The output of the signal SS3 and the line memory 47 is input to the comparator 46, and the output is input to the line memory 47 again. The line memory 47 shifts the contents by one in synchronization with the conversion timing signal SS5. In addition, the contents are cleared by a clear signal (not shown) for each frame. As a result, the vertical maximum values SS14r, SS14g, and SS14b can be obtained for each RGB.
【0752】
The multiplier (video signal rewriting means) 48 outputs the multiplication result of the read signal SS4 and the multiplication constant SS11 as an image signal for display.
【0753】
The calculation step in the control circuit 42 replaces the flow of FIG. 70 as follows.
【0754】
First, omit step P1.
【0755】
In step P2 "LHm (y) = MAX {SS13, Lmin} As a result, the maximum value LHm (1) to LHm (m) of the image data level for each row is obtained. , In step P5 "LVm (x) = MAX {(SS14r, SS14g, SS14b), Lmin} The maximum value of the image data level for each column, LVm (1) to LVm (n), is obtained. In step P9, the flow is corrected by saying, "The value of Am is output as the multiplication constant SS11."
【0756】
The configuration of other devices and the calculation steps are the same as those in the tenth embodiment.
【0757】
The flow of calculation of this embodiment is shown in FIG. 73.
【0758】
By applying this embodiment, the amount of calculation in the control circuit 42 can be significantly reduced. This embodiment is a display device having a large number of pixels, and is effective when a general-purpose microcomputer having a slow calculation speed must be used as the control circuit 42.
【0759】
(13th Embodiment) In the 12th embodiment described above, the same effect can be obtained by changing the PWM clock SS10 supplied to the modulation circuit 8 without using the multiplier 48. ..
【0760】
In order to change the PWM clock SS10, for example, an oscillation circuit using a PLL may be used as the oscillation means.
【0761】
The configuration of the display device of this embodiment is shown in FIG. 74.
【0762】
The flowchart of the calculation of this embodiment is shown in FIG.
【0763】
In the flow of this calculation, step P9 in the processing flow of FIG. 73 is described as "controlling the oscillation circuit of the PWM clock SS10 (not shown) in the control circuit 42 and multiplying the oscillation frequency of the PWM clock SS10 by 1 / Am". It was corrected.
【0764】
By doing so, the operating speed of the pulse width modulation circuit changes, the lighting time of the selected pixel changes, and as a result, the brightness of the screen changes as a whole.
【0765】
In this configuration, the video signal rewriting means is not used, and the read signal SS4 is used as it is as the display signal SS12. The configuration and calculation steps of other devices are the same as those in the twelfth embodiment.
【0766】
According to the tenth to thirteenth embodiments of the present invention, a good display image with bright brightness can be obtained by effectively utilizing the scanning time.
【0767】
In addition, the brightness can be adjusted so that when the image is totally bright, the brightness is normal, and when the image is partially bright or totally dark, the brightness is brighter. As a result, an effect similar to that of ABL (automatic luminance limiting circuit) is brought about, so that the drive control method according to the present embodiment can be applied as the control method of ABL.
【0768】
Further, in the second embodiment, it is also preferable to use the clock signal PWMCLK having an oscillation frequency of 1 / DGAIN instead of multiplying by DGAIN. According to this method, there is no concern that the number of gradations will decrease.
【0769】
[Effect of the invention]
As described in detail above, according to the present invention, it is possible to increase the peak luminance of the displayed image and obtain a good image. In addition, it is possible to suppress the occurrence of a wasteful period and obtain a good image.
[Simple explanation of drawings]
[Figure 1]
It is a figure which shows the timing chart of a drive signal.
[Figure 2]
It is a block diagram of the display device of this invention.
[Fig. 3]
It is a block diagram which shows a display device.
[Fig. 4]
It is a figure which shows the appearance of the display device used in this invention.
[Fig. 5]
It is a schematic diagram for demonstrating the resistance of the wiring of a display panel.
[Fig. 6]
It is a figure which shows the characteristic of an electron emitting element.
[Fig. 7]
It is a figure which shows the drive timing chart of the display by one Embodiment of this invention.
[Fig. 8]
It is a figure explaining the influence on the display state of a voltage drop.
[Fig. 9]
It is a figure explaining the degenerate model of a voltage drop.
[Fig. 10]
It is a figure which shows the voltage drop amount calculated discretely.
[Fig. 11]
It is a figure which shows the change amount of the emission current calculated discretely.
[Fig. 12]
It is a figure for demonstrating the calculation method of correction data.
[Fig. 13]
It is a figure for demonstrating the interpolation method of correction data.
[Fig. 14]
It is a figure for demonstrating another calculation method of correction data.
[Fig. 15]
It is a figure which shows the calculation example of the correction data when the size of image data is 128.
[Fig. 16]
It is a figure which shows the calculation example of the correction data when the size of image data is 192.
[Fig. 17]
It is a block diagram which shows the outline of the video signal processing circuit of the display device used in this invention.
[Fig. 18]
It is a block diagram which shows the outline of the drive control circuit of the display device which concerns on one Embodiment of this invention.
[Fig. 19]
It is a block diagram which shows the outline of the display device which concerns on one Embodiment of this invention.
[Fig. 20]
It is a block diagram which shows the structure of the inverse γ processing part.
[Fig. 21]
It is a figure which shows the input / output characteristic of the inverse γ processing part.
[Fig. 22]
It is a block diagram which shows the structure of the data array conversion part.
[Fig. 23]
It is a block diagram which shows the structure of the correction data calculation means.
[Fig. 24]
It is a block diagram which shows the structure of the discrete correction data calculation part.
[Fig. 25]
It is a block diagram which shows the structure of the correction data interpolation part.
[Fig. 26]
It is a block diagram which shows the structure of the linear approximation means of the correction data interpolation part.
[Fig. 27]
It is a schematic diagram for demonstrating the control method of the horizontal scanning period by one Embodiment of this invention.
[Fig. 28]
It is a flowchart of the arithmetic processing for calculating the horizontal scanning period which concerns on one Embodiment of this invention.
[Fig. 29]
It is a table diagram which shows an example of the scanning time of each scanning wiring obtained by the arithmetic processing of FIG. 28.
[Fig. 30]
It is a graph which shows an example of the scanning time of each scanning wiring obtained by the arithmetic processing of FIG. 28.
[Fig. 31]
It is a block diagram which shows the structure of the display timing generation part.
[Fig. 32]
It is a block diagram which shows the structure of the modulation circuit used in this invention.
[Fig. 33]
It is a figure which shows the relationship between the image data and the output pulse width of the same modulation means.
[Fig. 34]
It is a schematic diagram which shows an example of the output waveform of the modulation signal used in this invention.
[Fig. 35]
It is a block diagram which shows the structure of the scanning drive circuit of the display device used in this invention.
[Fig. 36]
It is a block diagram which shows the outline of the display device which concerns on 2nd Embodiment of this invention.
[Fig. 37]
It is a block diagram which shows the outline of the drive control circuit of the display device which concerns on 2nd Embodiment of this invention.
[Fig. 38]
It is a flowchart of the arithmetic processing for calculating the horizontal scanning period which concerns on 2nd Embodiment of this invention.
[Fig. 39]
It is a flowchart of a part of arithmetic processing which concerns on 2nd Embodiment of this invention.
[Fig. 40]
It is a flowchart of a part of arithmetic processing which concerns on 2nd Embodiment of this invention.
[Fig. 41]
It is a figure which shows an example of the horizontal scanning time of each scanning wiring by 2nd Embodiment of this invention.
[Fig. 42]
It is a graph which shows an example of the scanning time of each scanning wiring obtained by the scanning time calculation processing by 2nd Embodiment of this invention.
[Fig. 43]
It is a block diagram which shows the structure of the modulation circuit used in this invention.
[Fig. 44]
It is explanatory drawing which shows the relationship between the image data and the output pulse width of the same modulation means.
[Fig. 45]
It is a schematic diagram which shows an example of the output waveform of the modulation signal used in this invention.
[Fig. 46]
It is a block diagram which shows the outline of the drive control circuit of the display device which concerns on 3rd Embodiment of this invention.
[Fig. 47]
It is a flowchart of arithmetic processing for calculating the scanning period which concerns on 3rd Embodiment of this invention.
[Fig. 48]
It is a flowchart of a part of arithmetic processing which concerns on 3rd Embodiment of this invention.
[Fig. 49]
It is a flowchart of a part of the arithmetic processing which concerns on 4th Embodiment of this invention.
[Fig. 50]
It is a block diagram which shows the outline of the signal processing circuit of the display device which concerns on 5th Embodiment of this invention.
[Fig. 51]
It is a block diagram which shows the outline of the drive control circuit of the display device which concerns on 5th Embodiment of this invention.
[Fig. 52]
It is a block diagram which shows the structure of a frame memory.
[Fig. 53]
It is a block diagram which shows the structure of the W address generation part.
[Fig. 54]
It is a block diagram which shows the structure of the R address generation part.
[Fig. 55]
It is a schematic diagram for demonstrating the control of the horizontal scanning period used in this invention.
[Fig. 56]
It is a blog diagram which shows the structure of the display timing generation part.
[Fig. 57]
It is explanatory drawing which shows an example of the display timing signal used in this invention.
[Fig. 58]
It is a table diagram for demonstrating an example of a display timing signal.
[Fig. 59]
It is a block diagram which shows the structure of a gain table.
[Fig. 60]
It is explanatory drawing which shows an example of the gain table used in this invention.
[Fig. 61]
It is a table diagram for demonstrating an example of a gain table.
[Fig. 62]
It is a timing chart which shows the operation timing of each part of the display device by 5th Embodiment of this invention.
[Fig. 63]
It is a timing chart which shows the operation timing of each part of a display device.
[Fig. 64]
It is a block diagram which shows the outline of the signal processing circuit of the display device which concerns on 6th Embodiment of this invention.
[Fig. 65]
It is a block diagram which shows the outline of the signal processing circuit of the display device which concerns on 7th Embodiment of this invention.
[Fig. 66]
It is a block diagram which shows the outline of the signal processing circuit of the display device which concerns on 8th Embodiment of this invention.
[Fig. 67]
It is explanatory drawing which shows the characteristic of the limiter used in the 9th Embodiment of this invention.
[Fig. 68]
It is a block diagram which shows the outline of the display device by 10th Embodiment of this invention.
[Fig. 69]
It is a figure which shows the timing chart of each part of the display device by 10th Embodiment of this invention.
[Fig. 70]
It is a flowchart of arithmetic processing.
[Fig. 71]
It is a flowchart of arithmetic processing by 11th Embodiment of this invention.
[Fig. 72]
It is a block diagram which shows the outline of the display device according to the twelfth embodiment of this invention.
FIG. 73.
It is a flowchart of arithmetic processing.
[Fig. 74]
It is a block diagram which shows the outline of the display device by 13th Embodiment of this invention.
[Fig. 75]
It is a flowchart of arithmetic processing.
[Fig. 76]
It is a figure which shows the drive signal waveform of the conventional display device.
[Fig. 77]
It is a schematic diagram which shows the matrix type display.
[Explanation of symbols]
1 Display panel (display) 1001 board 1002 Cold cathode element 1003 line wiring (scanning wiring) 1004 row wiring (modulation wiring) 1005 rear plate 1006 side wall 1007 face plate 1008 Fluorescent film 1009 metal back 2,2A, 2B scanning drive circuit 221 shift register 222 Reference voltage source for selective voltage Vs 223 Reference voltage source for non-selective voltage Vns 224 switch array 3 Modulation drive circuit 4 Drive control circuit 5 shift register 6 Latch circuit 7 RGB conversion means 8 Modulation circuit 80 counter 81 Comparator 82 switch 9 Data array converter 10 gain table 11 Timing generation circuit 12 adder 13 Synchronous signal separation circuit 14 Correction data calculation means 141 Discrete correction data calculation unit 142 Correction data interpolation section 17 Inverse gamma processing unit 17R R table 17G G table 17BB table 19 Delay circuit 21 W address generator 210 V counter 211 H Upper counter 212 Comparator 213 H counter 22 line maximum detector 26 Memory A 260 Address control unit 261 ~ 268 1st memory ~ 8th memory 27 Memory B 28 R address generator 280 V counter 281 Comparator 282 H counter 31 Gain register 33 Display timing generator 330 H counter 331 memory 332 Comparator 333 V counter 334 1/2 divider 34 Microcomputer 40 Voltage drop compensator 41 AD converter 42 Control circuit 43 frame memory 44 memory bus 45,46 Comparator 47 line memory 48 Multiplier (video signal rewriting means) 51 Limiter 52 Limit data memory 53 limiter
28 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US7436377B2 | Cited by | United States of America | Applicant |
| JP2004361794A | Cited by | Japan | Search report |
| JP2009522590A | Cited by | Japan | Search report |
| JP2009522590A | Cited by | Japan | Examiner |
| JP2013137506A | Cited by | Japan | Search report |
| JP2005156960A | Cited by | Japan | Examiner |
| JP2013092548A | Cited by | Japan | Search report |
| US12057061B2 | Cited by | United States of America | Applicant |
12 members in 3 offices
Priority claims14
| Document | Office | Kind | Date |
|---|---|---|---|
| 2001210066(P2001210066) | Japan | – | |
| 2001210066 | Japan | A | |
| 2001232591(P2001232591) | Japan | – | |
| 2001232591 | Japan | A | |
| 2001364562(P2001364562) | Japan | – | |
| 2001364562 | Japan | A | |
| 2002190675 | Japan | A | |
| 20012001210066 | – | – | – |
| 20012001232591 | – | – | – |
| 20012001364562 | – | – | – |
| JP20010210066 | – | – | – |
| JP20010232591 | – | – | – |
| JP20010364562 | – | – | – |
| JP20020190675 | – | – | – |
Members12
| Document | Office | Kind | |
|---|---|---|---|
| EP1276093A2 | European Patent Office (EPO) | A2 | |
| US2003016189A1 | United States of America | A1 | |
| JP2003228317AThis record | Japan | A | |
| US2005231498A1 | United States of America | A1 | |
| US6985141B2 | United States of America | B2 | |
| JP2006209152A | Japan | A | |
| JP3870129B2 | Japan | B2 | |
| JP2007249247A | Japan | A | |
| US7292236B2 | United States of America | B2 | |
| JP4086880B2 | Japan | B2 | |
| JP4194641B2 | Japan | B2 | |
| EP1276093A3 | European Patent Office (EPO) | A3 |
20 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Cancellation because of no payment of annual feesLAPS | LAPS | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Certificate of patent or registration of utility modelJAPANESE INTERMEDIATE CODE: R150R150 | R150 | |
| First payment of annual fees (during grant procedure)JAPANESE INTERMEDIATE CODE: A61A61 | A61 | |
| Written decision to grant a patent or to grant a registration (utility model)JAPANESE INTERMEDIATE CODE: A01A01 | A01 | |
| Decision of grant or rejection writtenTRDD | TRDD | |
| Transfer to examiner for re-examination before appeal (zenchi)AppealJAPANESE INTERMEDIATE CODE: A911A911 | A911 | |
| Written amendmentJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Decision of refusalJAPANESE INTERMEDIATE CODE: A02A02 | A02 | |
| Written amendmentJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Notification of reasons for refusalJAPANESE INTERMEDIATE CODE: A131A131 | A131 | |
| Written amendmentJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Notification of reasons for refusalJAPANESE INTERMEDIATE CODE: A131A131 | A131 | |
| Report on retrievalJAPANESE INTERMEDIATE CODE: A971007A977 | A977 |
Numbers
- Publication
- 2003-228317
- Publication, DOCDB
- 2003228317
- Publication, EPODOC
- JP2003228317
- Application
- 190675
- Application, DOCDB
- 2002190675
- Application, EPODOC
- JP20020190675
Titles3
- English
- METHOD FOR DRIVING INDICATOR AND DISPLAY DEVICE USING THE SAME
- Japanese
- 【発明の名称】表示器の駆動方法及びそれを利用した表示装置
- English
- INDUSTRIAL APPLICABILITY: A method of driving a display device and a display device using the same.
Classification
- IPC, 4
- H04N5 66
- G09G3 20
- G09G3 22
- H04N9 12