Semiconductor device and manufacturing method thereof

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention is a thin film transistor (hereinafter, leave TFT will) semiconductor device and its manufacturing method having a circuit composed of. For example, the present invention relates to a device typified by a liquid crystal display device (equipped with a liquid crystal module) and an electronic device equipped with such a device as a component.

【0002】

In the present specification, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics, and the electro-optical device, the light emitting device, the semiconductor circuit, and the electronic device are all semiconductor devices.

【0003】

[Conventional technology]

In recent years, attention has been focused on a technique for forming a thin film transistor (TFT) using a semiconductor thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and their development is urgently needed, especially as switching elements for image display devices.

【0004】

Conventionally, a liquid crystal display device has been known as an image display device. Active matrix type liquid crystal display devices have come to be widely used because high-definition images can be obtained as compared with passive type liquid crystal display devices. In an active matrix type liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, optical modulation of the liquid crystal layer arranged between the pixel electrode and the counter electrode is performed, and this is performed. The optical modulation is recognized by the observer as a display pattern.

【0005】

The applications of such active matrix type liquid crystal display devices are expanding, and the demand for high definition, high aperture ratio, and high reliability is increasing along with the increase in screen size. At the same time, there are increasing demands for improved productivity and lower costs.

【0006】

[Problems to be Solved by the Invention]

Conventionally, when a TFT is manufactured using aluminum as the gate wiring material of the above-mentioned TFT, the TFT malfunctions or TFT characteristics due to the formation of protrusions such as hillocks and whiskers by heat treatment and the diffusion of aluminum atoms into the channel formation region. Was causing a decline in. Therefore, when a metal material that can withstand heat treatment, typically a metal element having a high melting point, is used, problems such as an increase in wiring resistance occur as the screen size increases, resulting in an increase in power consumption. Etc. were caused.

【0007】

Therefore, it is an object of the present invention to provide a structure of a semiconductor device and a method for manufacturing the same, which realizes low power consumption even if the screen is enlarged.

【0008】

[Means for solving problems]

In the present invention, the gate electrode structure uses a material film containing TaN or W as the main component in order to prevent diffusion into the channel formation region as the first layer, and Al, Cu, Ag, or Au is mainly used as the second layer. The resistance of the wiring is reduced by using a low resistance material film as a component and forming a laminated structure using a material film containing Ti or TiN as the main component as the third layer.

【0009】

The configuration of the invention disclosed herein includes a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film. This semiconductor device is composed of a pixel portion including a first n-channel TFT having a source wiring made of the same material as the gate electrode, a second n-channel TFT, and a third n-channel TFT. The semiconductor device is characterized by having a drive circuit including a circuit and a terminal portion made of the same material as the gate electrode.

【0010】

In the above configuration, the gate electrode has a material film containing TaN as a main component (first layer), a material film containing Al as a main component (second layer), and a material film containing Ti as a main component (third layer). It is characterized by having a laminated structure with a layer).

【0011】

Alternatively, in the above configuration, the gate electrode has a material film containing W as a main component (first layer), a material film containing Al as a main component (second layer), and a material film containing Ti as a main component (first layer). It is characterized by having a laminated structure with the third layer).

【0012】

Alternatively, in the above configuration, the gate electrode has a material film containing W as a main component (first layer), a material film containing Al as a main component (second layer), and a material film containing TiN as a main component (first layer). It is characterized by having a laminated structure with the third layer).

【0013】

With such a gate electrode structure, when the ICP (Inductively Coupled Plasma) etching method is used, the end portion of the gate electrode can be tapered.

【0014】

In the present specification, the taper angle refers to the angle formed by the horizontal plane and the side surface of the material layer. Further, in the present specification, for convenience, a side surface having a tapered angle is referred to as a tapered shape, and a portion having a tapered shape is referred to as a tapered portion.

【0015】

Further, in the above configuration, the EEMOS circuit or the EDMOS circuit is formed by the second n-channel type TFT and the third n-channel type TFT. Further, the drive circuit of the present invention is formed entirely of an MIMO circuit composed of an n-channel TFT, and the TFT of the pixel portion is also formed of an n-channel TFT to simplify the process. A general drive circuit is designed based on a CMOS circuit in which an n-channel type semiconductor element and a p-channel type semiconductor element are complementarily combined, but in the present invention, a drive circuit in which only an n-channel type TFT is combined is used. To form.

【0016】

Further, the configuration of the invention for realizing the above structure is a method for manufacturing a semiconductor device having a drive circuit, a pixel portion, and a terminal portion on an insulating surface, which comprises a step of forming a semiconductor layer on the insulating surface. A step of forming a first insulating film on the semiconductor layer, a step of forming a gate electrode, a source wiring of a pixel portion, and an electrode of a terminal portion on the first insulating film, and the semiconductor using the gate electrode as a mask. A step of adding an impurity element that imparts n-type to the layer to form an n-type impurity region, a step of etching the gate electrode to form a tapered portion, a source wiring of the pixel portion, and the terminal portion. This is a method for manufacturing a semiconductor device having a step of forming a second insulating film covering the semiconductor device and a step of forming a gate wiring and a source wiring of a drive circuit on the second insulating film.

【0017】

In the above configuration, in the step of forming the gate electrode, the source wiring of the pixel portion, and the electrode of the terminal portion, a material film containing TaN as a main component is formed, and a material film containing Al as a main component is formed. It is characterized in that a material film containing Ti as a main component is formed and laminated, and then etched with a mask to form the film. Further, in the above configuration, in the step of forming the gate electrode, the source wiring of the pixel portion, and the electrode of the terminal portion, a material film containing W as a main component is formed, and a material film containing Al as a main component is formed. However, it is characterized in that a material film containing Ti as a main component is formed and laminated, and then etched with a mask to form the film.

【0018】

Further, according to the present invention, it is possible to manufacture a liquid crystal display device having the pixel unit and the drive circuit shown in the above configuration, or a light emitting device having the OLED having the pixel unit and the drive circuit shown in the above configuration.

【0019】

Further, according to the present invention, since the manufacturing process of the p-channel type TFT is reduced, the manufacturing process of the liquid crystal display device or the light emitting device can be simplified, and the total manufacturing cost can be reduced.

【0020】

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described below.

【0021】

First, an underlying insulating film is formed on the substrate, and then a semiconductor layer having a desired shape is formed by a first photolithography step.

【0022】

Next, an insulating film (including a gate insulating film) covering the semiconductor layer is formed. The first conductive film, the second conductive film, and the third conductive film are laminated and formed on the insulating film. These laminated films are subjected to a first etching process by a second photolithography step, and a gate electrode composed of a first conductive layer and a second conductive layer, a source wiring of a pixel portion, and an electrode of a terminal portion are formed. Form. In the present invention, the gate electrode is first formed, and then the gate wiring is formed on the interlayer insulating film.

【0023】

Next, while leaving the resist mask formed in the second photolithography step as it is, an impurity element (phosphorus, etc.) that imparts n-type to the semiconductor is added to self-consistently n-type impurity region (high concentration). ) Is formed.

【0024】

Next, while the resist mask formed in the second photolithography step remains as it is, the second etching process is performed by changing the etching conditions to obtain the first conductive layer (first width) having a tapered portion. A second conductive layer (second width) and a third conductive layer (third width) are formed. The first width is larger than the second width, and the second width is larger than the third width. Here, the electrode composed of the first conductive layer, the second conductive layer, and the third conductive layer serves as the gate electrode (first gate electrode) of the n-channel TFT.

【0025】

As the first conductive layer in contact with the insulating film, a material film containing TaN or W as a main component may be used in order to prevent diffusion into the channel forming region. Further, as the second conductive layer, a low resistance material film containing Al, Cu, Ag, or Au as a main component may be used. Further, as the third conductive layer, a material film containing Ti having a low contact resistance as a main component may be used.

【0026】

As the first conductive layer, W, which is a material having a relatively low electric resistance value, is used, and as the second conductive layer, aluminum (Al-Si) containing 2 wt% Si having high heat resistance is used. , It is preferable to use Ti as the third conductive layer to further increase the heat resistance of the second conductive layer. However, when Ti is used as the third conductive layer, if heat treatment is performed at 350 ° C or higher in a later process (thermal activation treatment, etc.), alloying occurs at the Ti / Al-Si interface, resulting in high resistance. Therefore, it is preferable to use TiN as the third conductive layer when the heat treatment is performed at 350 ° C. or higher in a later step. In addition, when irradiating laser light in a later step (laser activation treatment, etc.), the nitride easily absorbs the laser light and may damage the irradiated surface, so TiN is used as the third conductive layer. It is possible to protect the damage caused by the laser beam by using Ti as the fourth conductive layer.

【0027】

Next, after removing the resist mask, the first gate electrode is used as a mask, and an impurity element that passes through the insulating film to impart n-type to the semiconductor layer is added.

【0028】

After that, a resist mask is formed by a third photolithography method, and an impurity element that selectively imparts n-type is added in order to reduce the off-current of the TFT of the pixel portion.

【0029】

Next, an interlayer insulating film is formed to form a transparent conductive film. Next, the transparent conductive film is patterned by the fourth photolithography method to form pixel electrodes. Then, a contact hole is formed by a fifth photolithography step. Here, a contact hole that reaches the impurity region, a contact hole that reaches the gate electrode, and a contact hole that reaches the source wiring are formed.

【0030】

Next, a conductive film made of a low-resistance metal material is formed, and a gate wiring, an electrode connecting the source wiring and the impurity region, and an electrode connecting the pixel electrode and the impurity region are formed by the sixth photolithography step. .. In the present invention, the gate wiring is electrically connected to the first gate electrode or the second gate electrode through a contact hole provided in the interlayer insulating film. Further, the source wiring is electrically connected to the impurity region (source region) through a contact hole provided in the interlayer insulating film. Further, the electrode connected to the pixel electrode is electrically connected to the impurity region (drain region) through a contact hole provided in the interlayer insulating film.

【0031】

In this way, a total of 6 photolithography steps, that is, a pixel portion having a pixel TFT (n-channel type TFT) with 6 masks and an EEMOS circuit (n-channel type TFT) as shown in FIG. 7 (A) are formed. It is possible to form an element substrate including a drive circuit having the drive circuit. Although an example of manufacturing a transmissive display device is shown here, it is also possible to manufacture a reflective display device by using a highly reflective material for the pixel electrodes. When a reflection type display device is manufactured, it can be formed at the same time as the gate wiring, so that the element substrate can be formed with the number of masks of five.

【0032】

It is also possible to manufacture an active matrix type light emitting device having an OLED (Organic Light Emitting Device). Also in the light emitting device, the drive circuit is formed entirely of n-channel TFTs, and the pixel portion is also formed of a plurality of n-channel TFTs. In a light emitting device using an OLED, at least a TFT that functions as a switching element and a TFT that supplies a current to the OLED are provided in each pixel. An n-channel TFT is a TFT that is electrically connected to an OLED and supplies a current to the OLED regardless of the pixel circuit configuration and driving method.

【0033】

The OLED has a layer (hereinafter referred to as an organic light emitting layer) containing an organic compound (organic light emitting material) from which luminescence (Electroluminescence) generated by applying an electric field can be obtained, an anode, and a cathode. Luminescence in organic compounds includes light emission (fluorescence) when returning from the single-term excited state to the ground state and light emission (phosphorescent light) when returning from the triple-term excited state to the ground state. , Either one of the above-mentioned light emission may be used, or both light emission may be used.

【0034】

In this specification, all the layers formed between the anode and the cathode of the OLED are defined as the organic light emitting layer. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer and the like. Basically, OLED has a structure in which anode / light emitting layer / cathode are laminated in order, and in addition to this structure, anode / hole injection layer / light emitting layer / cathode and anode / hole injection layer / It may have a structure in which a light emitting layer, an electron transporting layer, a cathode, etc. are laminated in this order.

【0035】

Further, when the enhancement type and the depletion type are combined to form the EDMOS circuit as shown in FIG. 7 (B), a mask is formed in advance before forming the conductive film, and the periodic table is formed on the semiconductor to be the channel formation region. Elements belonging to Group 15 (preferably phosphorus) or elements belonging to Group 13 of the periodic table (preferably boron) may be selectively added. In this case, the element substrate can be formed with seven masks.

【0036】

Further, although the n-channel type TFT has been described here, it goes without saying that the p-channel type TFT can be formed by using the p-type impurity element instead of the n-type impurity element. In that case, all the drive circuits are formed by the p-channel type TFT, and the pixel portion is also formed by the p-channel type TFT.

【0037】

The present invention having the above configuration will be described in more detail with reference to the following examples.

【0038】

(Example) [Example 1] Examples of the present invention will be described with reference to FIGS. 1 to 6. Here, a method of simultaneously producing the pixel portion and the TFT of the drive circuit (only the n-channel type TFT) provided around the pixel portion on the same substrate will be described in detail.

【0039】

In FIG. 1A, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate 100. Further, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this example may be used.

【0040】

Then, as shown in FIG. 1A, a silicon oxide film, a silicon nitride film, or a silicon nitride film (SiO) is placed on the substrate 100._xN_y) Etc. to form an underlying insulating film 101 made of an insulating film such as). A typical example is a two-layer structure as the underlying insulating film 101, SiH.₄, NH₃, And N₂The first silicon oxynitride film 101a formed using O as a reaction gas is 50 to 100 nm, SiH.₄, And N₂A structure is adopted in which the second silicon oxynitride film 101b, which is formed by using O as a reaction gas, is laminated to a thickness of 100 to 150 nm. Further, a silicon nitride film having a film thickness of 10 nm or less may be used as the underlying insulating film 101. When the silicon nitride film is used, in addition to the effect as a blocking layer, it also has the effect of improving the gettering efficiency in the gettering step performed later. Since nickel tends to move to a region having a high oxygen concentration during gettering, it is extremely effective to use a silicon nitride film as the underlying insulating film in contact with the semiconductor film. Further, a three-layer structure in which the first silicon oxide nitride film, the second silicon oxide nitride film, and the silicon nitride film are sequentially laminated may be used.

【0041】

The semiconductor film used as the active layer is obtained by crystallizing an amorphous semiconductor film formed on the base film 101. The amorphous semiconductor film is formed with a thickness of 30 to 60 nm, and then a metal element having a catalytic action (nickel in this example) that promotes crystallization is applied to the surface of the amorphous semiconductor film in terms of weight. A nickel acetate solution containing 1 to 100 ppm of nickel is applied with a spinner to form a catalyst-containing layer.

【0042】

Heat treatment for crystallization is performed while maintaining the state in which the amorphous semiconductor film and the catalyst element-containing layer are in contact with each other. In this embodiment, the heat treatment is performed by the RTA method. The lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to about 600 to 1000 ° C, preferably about 650 to 750 ° C. Even if the temperature becomes such a high temperature, the semiconductor film is only instantaneously heated, and the substrate 100 itself is not distorted and deformed. In this way, the amorphous semiconductor film can be crystallized to obtain a crystalline semiconductor film.

【0043】

Further, in order to increase the crystallization rate (ratio of crystal components in the total volume of the film) and repair defects left in the crystal grains, the crystalline semiconductor film is irradiated with laser light. It is also possible to use excimer laser light having a wavelength of 400 nm or less and the second and third harmonics of the YAG laser as the laser. In any case, pulsed laser light with a repetition frequency of about 10 to 1000 Hz is used, and the laser light is applied to the optical system at 100 to 400 mJ / cm.²The crystalline semiconductor film 104 may be laser-treated with an overlap rate of 90 to 95%.

【0044】

Although an example using a pulse laser is shown here, a continuous oscillation laser may be used, and continuous oscillation is possible in order to obtain crystals having a large particle size when crystallizing an amorphous semiconductor film. It is preferable to apply the second to fourth harmonics of the fundamental wave by using a solid-state laser. Typically, Nd: YVO₄The second harmonic (532 nm) or third harmonic (355 nm) of the laser (primary wave 1064 nm) may be applied. When using a continuously oscillating laser, a continuously oscillating YVO with an output of 10W₄The laser light emitted from the laser is converted into harmonics by a nonlinear optical element. Also, YVO in the resonator₄There is also a method of inserting a crystal and a non-linear optical element to emit harmonics. Then, preferably, the laser beam having a rectangular or elliptical shape is formed on the irradiation surface by an optical system, and the object to be processed is irradiated. The energy density at this time is 0.01 to 100 MW / cm²Degree (preferably 0.1-10 MW / cm²)is required. Then, the semiconductor film may be moved and irradiated relative to the laser beam at a speed of about 10 to 2000 cm / s.

【0045】

Here, a technique of irradiating a laser beam after performing thermal crystallization using nickel as a metal element that promotes crystallization of silicon was used, but an excimer laser of pulse oscillation or an excimer laser of pulse oscillation was used without adding nickel. Continuous oscillation laser (YVO₄The amorphous silicon film may be crystallized by the second harmonic of the laser).

【0046】

Next, the gettering treatment shown below is performed in order to remove the catalytic element contained in the crystalline semiconductor film. A barrier layer is formed on the crystalline semiconductor film. As the barrier layer, when heat treatment is performed, the catalytic element (nickel) can be moved to the gettering site, and further, a porous film is formed in which the etching solution used in the step of removing the gettering site does not soak. For example, a chemical oxide film or a silicon oxide film (SiOx) formed by treating with ozone water may be used. In the present specification, a membrane having such properties is particularly referred to as a porous membrane.

【0047】

Next, a semiconductor film containing a rare gas element is formed as a gettering site. In this embodiment, 1 × 10 rare gas elements are added at the stage of film formation by plasma CVD method or sputtering method, or at the stage of addition by ion implantation method or ion implantation method after film formation.¹⁹~1×10²²/cm³, Preferably 1x10²⁰~1×10²¹/cm³A semiconductor film containing the above concentration is formed.

【0048】

After that, heat treatment such as RTA method using a lamp light source and heat treatment using a furnace is performed to move the catalytic element to the gettering site in the vertical direction. This heat treatment also serves as annealing. As the heating conditions, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to about 600 to 1000 ° C, preferably about 700 to 750 ° C.

【0049】

After the gettering process is completed, the gettering site made of an amorphous semiconductor is selectively etched and removed. As an etching method, ClF₃Dry etching without plasma, or hydrazine or tetraethylammonium hydrooxide (chemical formula (CH)₃)₄It can be performed by wet etching with an alkaline solution such as an aqueous solution containing NOH). At this time, the barrier layer 106 functions as an etching stopper. Further, the barrier layer 106 may then be removed with hydrofluoric acid. In order to improve crystallization, laser light may be irradiated after the crystallization step.

【0050】

Then, the obtained crystalline semiconductor film is etched into a desired shape to form the semiconductor layers 102 to 106 separated in an island shape.

【0051】

Further, after forming the semiconductor layers 102 to 106, an impurity element that imparts p-type may be added in order to control the threshold value (Vth) of the n-channel TFT. Group 13 elements of the periodic law such as boron (B), aluminum (Al), and gallium (Ga) are known as impurity elements that impart p-type to semiconductors.

【0052】

Next, the gate insulating film 107 covering the semiconductor layers 102 to 106 separated in an island shape is formed. The gate insulating film 107 is formed by a plasma CVD method or a sputtering method, and is formed of an insulating film containing silicon with a thickness of 40 to 150 nm. Of course, as this gate insulating film, an insulating film containing silicon can be used as a single layer or a laminated structure.

【0053】

When using a silicon oxide film, use the plasma CVD method for TEOS (Tetraethyl Ortho Silicate) and O.₂The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C, and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm.²It can be formed by discharging with. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. after formation.

【0054】

On the gate insulating film 107, a film 108a containing tungsten (W) as a main component is mainly used as the first conductive film having a thickness of 20 to 100 nm, and aluminum (Al) is mainly used as the second conductive film having a thickness of 100 to 500 nm. A film 108b as a component and a film 108c containing titanium (Ti) as a main component are laminated and formed as a third conductive film having a film thickness of 20 to 100 nm. The total film thickness of the laminate made of these conductive films is preferably less than 600 nm in terms of the stepped surface in consideration of the subsequent process. Here, a tungsten film having a thickness of 50 nm, an alloy (Al-Ti) film of aluminum and titanium having a thickness of 500 nm, and a titanium film having a thickness of 30 nm are sequentially laminated on the gate insulating film 107.

【0055】

Not limited to the above materials, Ta, W, Ti, Mo, Al can be used as the conductive material of the first conductive film, the second conductive film, or the third conductive film which becomes the gate electrode by the subsequent etching. , Cu, or an alloy material or compound material containing the element as a main component can be appropriately used. Further, as the first conductive film, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. For example, a combination in which the first conductive film is formed of a tungsten (W) film, the second conductive film is an alloy of aluminum and silicon (Al-Si) film, and the third conductive film is a titanium nitride (TiN) film. Alternatively, the first conductive film is formed of a tungsten (W) film, the second conductive film is a Cu film, the third conductive film is a titanium (Ti) film, or the first conductive film is tantalum ( A combination of a TaN) film, the second conductive film being an aluminum (Al-Ti) film and the third conductive film being a titanium (Ti) film, or the first conductive film being a tantalum nitride (TaN) film. The second conductive film is made of an aluminum (Al-Ti) film, the third conductive film is made of a titanium nitride (TiN) film, or the first conductive film is made of a tantalum nitride (TaN) film. , The second conductive film may be a Cu film and the third conductive film may be titanium (Ti).

【0056】

Next, as shown in FIG. 1 (B), masks 110 to 115 made of resist are formed by a light exposure step, and a first etching process for forming a gate electrode and wiring is performed. The first etching process is performed under the first and second etching conditions. ICP (Inductively Coupled Plasma) etching method may be used for etching. Using the ICP etching method, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted to form a film with a desired tapered shape. Can be etched. The etching gas is Cl.₂, BCl₃, SiCl₄, CCl₄Chlorine-based gas or CF represented by₄,SCIENCE FICTION₆, NF₃Fluorine-based gas represented by, or O₂Can be used as appropriate.

【0057】

The etching gas used is not limited, but here BCl₃And Cl₂And O₂It is suitable to use. Each gas flow rate ratio is 65/10/5 (sccm), and 450W RF (13.56MHz) power is applied to the coil type electrode at a pressure of 1.2Pa to generate plasma and perform etching for 117 seconds. 300W RF (13.56MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, a quartz disk provided with a coil) is a disk having a diameter of 25 cm. The Al-Ti film and the titanium film are etched under the first etching condition to form a tapered end portion of the second conductive film and the third conductive film. The etching rates of the Al-Ti film and the titanium film under the first etching condition are almost the same.

【0058】

After this, change to the second etching condition and use CF as the etching gas.₄And Cl₂And O₂With and, each gas flow rate ratio is set to 25/25/10 (sccm), and 500W RF (13.56MHz) power is applied to the coil type electrode at a pressure of 1Pa to generate plasma and generate plasma for about 30 seconds. Etching. 20W RF (13.56MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF₄And Cl₂Under the second etching condition in which the above is mixed, the W film, the Al-Ti film, and the titanium film are all etched to the same extent. In order to etch without leaving a residue on the gate insulating film, it is advisable to increase the etching time at a rate of about 10 to 20%.

【0059】

In this first etching process, by making the shape of the mask made of resist suitable, the first conductive layer, the second conductive layer, and the third conductive layer are affected by the effect of the bias voltage applied to the substrate side. The edges of the layer have a tapered shape. The angle of this tapered portion is 15 to 45 °. In this way, the first conductive layer 117 to 122 (the first conductive layer 1117a to 1122a and the second conductive layer) composed of the first conductive layer, the second conductive layer, and the third conductive layer by the first etching process. Conductive layers 117b to 122b and a third conductive layer 117c to 122c) are formed. Reference numeral 116 denotes a gate insulating film, and the region not covered by the conductive layers 117 to 122 of the first shape is etched by about 20 to 50 nm to form a thinned region.

【0060】

Here, a sample was prepared and an experiment under etching conditions was conducted. As the sample, a tungsten film having a thickness of 50 nm, an alloy (Al-Ti) film of aluminum and titanium having a thickness of 500 nm, and a titanium film having a thickness of 30 nm were sequentially laminated on a quartz substrate as in this example. FIG. 13 is a photographic diagram observed by SEM immediately after etching under the same conditions as the first etching treatment. Therefore, the shape of the conductive layer shown in FIG. 13 can be regarded as the conductive layer having the first shape.

【0061】

Next, the second etching process is performed as shown in FIG. 1 (C) without removing the masks 110 to 115 made of the resist. BCl for etching gas₃And Cl₂Each gas flow rate ratio is set to 20/60 (sccm), and 600W RF (13.56MHz) power is applied to the coil type electrode at a pressure of 1.2Pa to generate plasma and perform etching. 100W RF (13.56MHz) power is applied to the substrate side (sample stage). The second conductive layer and the third conductive layer are etched according to the third etching condition performed in the second etching process. In this way, the aluminum film and the titanium film containing a small amount of titanium are anisotropically etched under the third etching condition to perform the second-shaped conductive layers 124 to 129 (first conductive layers 124a to 129a and second conductive layers). Layers 124b to 129b and a third conductive layer 124c to 129c) are formed. Reference numeral 123 denotes a gate insulating film, and the region not covered by the conductive layers 117 to 122 of the second shape is slightly etched to form a thinned region. Further, in FIGS. 1 (B) and 1 (C), the length of the tapered portion of the first conductive layer is shown as the same, but in reality, there is a dependence on the wiring width, so that the length depends on the wiring width. The length of the tapered portion of the conductive layer of 1 changes.

【0062】

Here, too, a sample was prepared and an experiment under etching conditions was conducted. As the sample, a tungsten film having a thickness of 50 nm, an alloy (Al-Ti) film of aluminum and titanium having a thickness of 500 nm, and a titanium film having a thickness of 30 nm were sequentially laminated on a quartz substrate as in this example. FIG. 14 is a photographic drawing observed by SEM immediately after the etching was performed under the same conditions as the first etching treatment and the second etching treatment was performed. Therefore, the shape of the conductive layer shown in FIG. 14 can be regarded as the conductive layer having the second shape.

【0063】

Further, in this embodiment, the first etching treatment (first etching condition, second etching condition) and the second etching treatment (third etching condition) were continuously performed without touching the atmosphere. An example is shown, but the present invention is not particularly limited, and after etching, the etching may be taken out of the chamber, the reaction gas or the like may be exhausted, and then the etching may be performed again under different conditions.

【0064】

Then, the first doping treatment is performed without removing the mask made of the resist, and an impurity element that imparts n-type to the semiconductor layer is added. The mask made of resist may be removed before the first doping treatment. The doping treatment may be performed by an ion doping method, a laser doping method, or an ion implantation method. The condition of the ion doping method is that the dose amount is 1.5 × 10.¹⁴atoms / cm²Then, the acceleration voltage is set to 60 to 100 keV. Elements belonging to Group 15, typically phosphorus (P) or arsenic (As), are used as impurity elements that impart n-type. In this case, the conductive layers 124 to 128 of the second shape serve as masks for the impurity elements that impart the n-type, and the first impurity regions 123 to 127 are formed in a self-aligned manner. 1 × 10 in the first impurity region 130-134¹⁶~1×10¹⁷/cm³Add an impurity element that imparts n-type in the concentration range of.

【0065】

Next, as shown in FIG. 2A, masks 135 and 136 made of resist are formed and a second doping treatment is performed. The mask 135 is a mask that protects the channel formation region of the semiconductor layer forming one of the n-channel TFTs of the drive circuit and the surrounding region, and the mask 136 is the channel formation region of the semiconductor layer that forms the TFT of the pixel portion. It is a mask that protects the area around and around it. Further, in FIG. 2A, for convenience, the length of the tapered portion of the first conductive layer is shown as the same, but in reality, the length of the tapered portion of the first conductive layer changes depending on the wiring width. ing. Therefore, when a plurality of wirings having different wiring widths are provided on the same substrate, the widths of the doped regions are also different.

【0066】

The condition of the ion doping method in the second doping treatment is that the dose amount is 1.5 × 10.¹⁵atoms / cm²Then, the acceleration voltage is set to 60 to 100 keV and phosphorus (P) is doped. Here, an impurity region is formed in each semiconductor layer by utilizing the difference in film thickness between the second-shaped conductive layers 124 to 128 and the gate insulating film 123. Of course, phosphorus (P) is not added to the area covered with the masks 135 and 136. In this way, the second impurity regions 180 to 182 and the third impurity regions 137 to 141 are formed. 1 × 10 in the third impurity region 137-141²⁰~1×10²¹/cm³An impurity element that imparts n-type is added in the concentration range of. In addition, the second impurity region is formed at a lower concentration than the third impurity region due to the difference in film thickness of the gate insulating film, and is 1 × 10¹⁸~1×10¹⁹/cm³Impurity elements that impart n-type are added in the concentration range of.

【0067】

In the steps up to the above, an impurity region having an n-type conductive type is formed in each semiconductor layer. The conductive layers 124 to 127 of the second shape serve as gate electrodes. Further, the conductive layer 128 having the second shape serves as one electrode that forms a holding capacitance in the pixel portion. Further, the conductive layer 129 of the second shape forms the source wiring in the pixel portion.

【0068】

Next, the first interlayer insulating film 151 that covers almost the entire surface is formed. The first interlayer insulating film 151 is formed of an insulating film containing silicon and hydrogen with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method. A suitable example thereof is a silicon oxide film having a film thickness of 150 nm formed by a plasma CVD method. Of course, the first interlayer insulating film 151 is not limited to the silicon oxide nitride film, and an insulating film containing other silicon may be used as a single layer or a laminated structure.

【0069】

After that, a step of activating the impurity elements added to each semiconductor layer is performed. This activation is achieved by heat treatment using a furnace annealing furnace or a clean oven. The temperature of the heat treatment is 400 to 700 ° C, typically 410 to 500 ° C in a nitrogen atmosphere. When performing such thermal activation, it is preferable to use titanium nitride instead of titanium, which is the material of the third layer of the conductive layer, in order to improve heat resistance. In addition to this, a laser annealing method or a rapid thermal annealing method (RTA method) can also be applied.

【0070】

At the same time as the above activation treatment, nickel used as a catalyst during crystallization is gettered in a third impurity region 137 to 141 containing a high concentration of phosphorus, and the nickel concentration in the semiconductor layer mainly serving as a channel formation region is increased. It will be reduced. As a result, the TFT having a channel forming region has a low off-current value and good crystallinity, so that high field effect mobility can be obtained and good characteristics can be achieved.

【0071】

Next, as shown in FIG. 3, a second interlayer insulating film 152 made of an organic insulating material is formed on the first interlayer insulating film 151. Next, a contact hole reaching the source wiring 127 and a contact hole reaching each impurity region are formed.

【0072】

After that, wiring and pixel electrodes are formed using Al, Ti, Mo, W and the like. For example, a laminated film of a Ti film having a film thickness of 50 to 250 nm and an alloy film having a film thickness of 300 to 500 nm (an alloy film of Al and Ti) is used. In this way, the source or drain wirings 153 to 158, the gate wiring 160, the connection wiring 159, the pixel electrode 161, and the capacitance wiring 162 are formed.

【0073】

As described above, the drive circuit 406 having the n-channel type TFT401, the n-channel type TFT402, and the n-channel type TFT403 and the pixel portion 407 having the n-channel type TFT404 and the holding capacity 405 can be formed on the same substrate. it can. In the present specification, such a substrate is referred to as an active matrix substrate for convenience. The n-channel type TFT401 and the n-channel type TFT403 have the same structure.

【0074】

Further, in the conventional method, depending on the doping conditions, the impurity element may wrap around below the gate electrode, and an impurity region that overlaps with the gate electrode and has a concentration gradient may be generated by about 0.1 μm. The example is 0.5 μm or more, preferably 1 μm or more, which is different from the conventional TFT structure.

【0075】

The n-channel TFT 402 has a channel forming region 165, a second impurity region 166 that does not partially overlap with the second-shaped conductive layer 125 forming the gate electrode, and a third impurity region 167 that functions as a source region or drain region. have.

【0076】

The n-channel TFT 403 has a channel forming region 168, a second impurity region 169 that partially overlaps with the second-shaped conductive layer 126 forming the gate electrode, and a third impurity region 170 that functions as a source region or a drain region. have.

【0077】

These n-channel TFTs form a shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like. In particular, for a buffer circuit having a high drive voltage, the structure of n-channel type TFT 401 or 403 is suitable for the purpose of preventing deterioration due to hot carrier effect.

【0078】

The pixel TFT 404 of the pixel portion 407 has a channel forming region 171, a first impurity region 172 formed outside the second-shaped conductive layer 128 forming the gate electrode, and a third that functions as a source region or a drain region. It has an impurity region 173. Further, a third impurity region 176 and a second impurity region 177 are formed in the semiconductor layer that functions as one electrode of the holding capacity 405. The holding capacity 405 is formed of a capacitance wiring 162 and a semiconductor layer 106 with an insulating film (the same film as the gate insulating film) as a dielectric.

【0079】

A top view of such a pixel portion 407 is shown in FIG. FIG. 4 shows a top view of almost one pixel, and the reference numerals given are the same as those in FIG. The cross-sectional structures of the A-A'and B-B'lines correspond to FIG. In the pixel structure of FIG. 4, by forming the gate wiring and the gate electrode on different layers, the gate wiring and the semiconductor layer can be superimposed, and the gate wiring has a function as a light-shielding film. Further, the end portion of the pixel electrode is arranged so as to overlap the source wiring so that the gap between the pixel electrodes is shielded from light, so that the formation of the light shielding film (black matrix) can be omitted. As a result, it is possible to improve the aperture ratio as compared with the conventional case.

【0080】

[Example 2] In this embodiment, a step of manufacturing a liquid crystal module from the active matrix substrate obtained in Example 1 will be described below.

【0081】

An alignment film is formed on the active matrix substrate shown in FIG. 3 and a rubbing process is performed. In this example, before forming the alignment film, a columnar spacer for maintaining the substrate spacing was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacer, a spherical spacer may be sprayed on the entire surface of the substrate.

【0082】

Next, a facing substrate is prepared. The facing substrate is provided with a color filter in which a coloring layer and a light-shielding layer are arranged corresponding to each pixel. A light-shielding layer was also provided in the drive circuit portion. A flattening film was provided to cover the color filter and the light-shielding layer. Next, a counter electrode made of a transparent conductive film was formed on the flattening film in the pixel portion, an alignment film was formed on the entire surface of the facing substrate, and a rubbing treatment was performed.

【0083】

Then, the pixel portion, the active matrix substrate on which the drive circuit is formed, and the facing substrate are bonded together with a sealing material. A filler is mixed in the sealing material, and the two substrates are bonded together at a uniform interval by the filler and the columnar spacer. Then, a liquid crystal material is injected between the two substrates, and the liquid crystal material is completely sealed with a sealant. A known liquid crystal material may be used as the liquid crystal material. In this way, the liquid crystal module is completed. Then, if necessary, the active matrix substrate or the facing substrate is divided into a desired shape. Further, a polarizing plate or the like was appropriately provided by using a known technique. Then, the FPC was attached using a known technique.

【0084】

The configuration of the liquid crystal module thus obtained will be described with reference to the top view of FIG.

【0085】

The top view shown in FIG. 5 shows the pixel section, drive circuit, external input terminal 209 to which FPC (Flexible Printed Circuit) 211 is attached, wiring 210 connecting the external input terminal to the input section of each circuit, etc. The active matrix substrate on which the above is formed and the opposing substrate 200 provided with a color filter or the like are bonded to each other via a sealing material 207.

【0086】

A light-shielding layer 203a is provided on the opposite board side so as to overlap the gate wiring side drive circuit 201a, and a light-shielding layer 803b is formed on the opposite board side so as to overlap the source wiring side drive circuit 201b. Further, the color filter 202 provided on the opposite substrate side on the pixel portion 205 is provided with a light-shielding layer and colored layers of each color of red (R), green (G), and blue (B) corresponding to each pixel. Has been done. When actually displaying, a color display is formed with three colors of a red (R) colored layer, a green (G) colored layer, and a blue (B) colored layer, and the arrangement of the colored layers of each of these colors is It is optional.

【0087】

Here, the color filter 202 is provided on the facing substrate in order to achieve colorization, but the present invention is not particularly limited, and the color filter may be formed on the active matrix substrate when the active matrix substrate is produced.

【0088】

Further, in the color filter, a light-shielding layer is provided between adjacent pixels to block light from a portion other than the display area. Further, here, the light-shielding layers 203a and 203b are also provided in the area covering the drive circuit, but the area covering the drive circuit is particularly covered with a cover when the liquid crystal display device is later incorporated as a display unit of an electronic device. A configuration may be configured in which a light-shielding layer is not provided. Further, when the active matrix substrate is produced, a light-shielding layer may be formed on the active matrix substrate.

【0089】

Further, without providing the light-shielding layer, a colored layer constituting a color filter is appropriately arranged between the facing substrate and the facing electrode so as to block light by stacking a plurality of layers, and a place other than the display area (each pixel electrode). The gap) and the drive circuit may be shielded.

【0090】

Further, FPC211 composed of a base film and wiring is bonded to the external input terminal with an anisotropic conductive resin. Furthermore, the mechanical strength is increased by the reinforcing plate.

【0091】

The liquid crystal module produced as described above can be used as a display unit of various electronic devices.

【0092】

[Example 3] In Example 1, an example of a reflective display device in which the pixel electrodes are made of a reflective metal material is shown, but in this embodiment, the pixel electrodes are formed of a translucent conductive film. Figure 6 shows an example of the transmissive display device. When the pixel electrode is formed of a transparent conductive film, a transmissive display device can be formed, although the number of photomasks is increased by one.

【0093】

After forming the interlayer insulating film according to the first embodiment, a pixel electrode made of a light-transmitting conductive film is formed. As the conductive conductive film having translucency, ITO (indium tin oxide alloy) and indium zinc oxide alloy (In)₂O₃-ZnO), zinc oxide (ZnO), etc. may be used.

【0094】

After that, a contact hole is formed in the interlayer insulating film. Next, a connection electrode that overlaps with the pixel electrode is formed. This connection electrode is connected to the drain region through a contact hole. At the same time as this connection electrode, another TFT source electrode or drain electrode is also formed.

【0095】

Further, although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as a part of the drive circuits.

【0096】

The active matrix substrate is formed as described above. Using this active matrix substrate, a liquid crystal module is manufactured according to Example 2, a backlight 310 and a light guide plate 311 are provided, and the active matrix substrate is covered with a cover 312 to complete the active matrix type liquid crystal display device shown in FIG. The cover 312 and the liquid crystal module are attached using an adhesive or an organic resin. Further, when the substrate and the opposing substrate are bonded to each other, the substrate may be surrounded by a frame and an organic resin may be filled between the frame and the substrate for adhesion. Further, since it is a transmissive type, the polarizing plate 309 is attached to both the active matrix substrate and the facing substrate.

【0097】

[Example 4] The n-channel type TFT shown in Example 1 is an element belonging to Group 15 of the periodic table (preferably phosphorus) or an element belonging to Group 13 of the periodic table (preferably boron) in the semiconductor serving as the channel formation region. By adding the above, the enhancement type and the depletion type can be made separately.

【0098】

Further, when forming an MIMO circuit by combining n-channel type TFTs, when forming between enhancement type TFTs (hereinafter referred to as EEMOS circuit), and when forming a combination of enhancement type and depletion type (hereinafter, EDMOS circuit). There is).

【0099】

Here, an example of the EEMOS circuit is shown in FIG. 7 (A), and an example of the EDMOS circuit is shown in FIG. 7 (B). In FIG. 7 (A), both 31 and 32 are enhancement type n-channel TFTs (hereinafter referred to as E type NTFT). Further, in FIG. 7B, 33 is an E-type NTFT and 34 is a depletion-type n-channel TFT (hereinafter referred to as D-type NTFT).

【0100】

In FIGS. 7A and 7B, VDH is a power supply line to which a positive voltage is applied (positive power supply line), and VDL is a power supply line to which a negative voltage is applied (negative power supply line). .. The negative power supply line may be a power supply line having a ground potential (ground power supply line).

【0101】

Further, FIG. 8 shows an example in which a shift register is manufactured using the EEMOS circuit shown in FIG. 7 (A) or the EDMOS circuit shown in FIG. 7 (B). In FIG. 8, 40 and 41 are flip-flop circuits. Further, 42 and 43 are E-type NTFTs, and a clock signal (CL) is input to the gate of the E-type NTFT42, and a clock signal (CL bar) with inverted polarity is input to the gate of the E-type NTFT43. Further, the symbol shown by 44 is an inverter circuit, and as shown in FIG. 8 (B), the EEMOS circuit shown in FIG. 7 (A) or the EDMOS circuit shown in FIG. 7 (B) is used. Therefore, it is possible to configure all the drive circuits of the display device with n-channel TFTs.

【0102】

In addition, this Example can be freely combined with any one of Examples 1 to 3.

【0103】

[Example 5] In this embodiment, a pixel structure (IPS system) different from that of the first embodiment is shown in FIG. 9, and a cross-sectional structure is shown in FIG. A-A'cross-sectional view and H-H'cross-sectional view are shown, respectively.

【0104】

This embodiment shows an example of an active matrix type liquid crystal display device of an IPS (In-Plane Switching) system (also referred to as a transverse electric field system). The IPS method is characterized in that both the pixel electrodes and the common wiring (hereinafter referred to as common wiring) are formed on one substrate and an electric field is applied in the lateral direction, and the long axis of the liquid crystal molecules is almost on the substrate surface. The orientation is controlled in the parallel direction. The viewing angle can be widened by using this IPS system.

【0105】

In FIG. 9, 1101 is the first semiconductor layer, 1102 and 1103 are the second semiconductor layers, 1104 is the first electrode, 1105 is the second electrode, 1106 is the source wiring, 1107 is the gate wiring, and 1108 and 1109 are. Common wiring, 1110 is a connection electrode, and 1111 is a pixel electrode. The pixel electrodes and the common wiring are arranged so as to generate an electric field parallel to the substrate surface. Further, the common wiring is arranged so as to overlap with the source wiring to improve the aperture ratio of the pixel portion.

【0106】

Further, as shown in FIG. 10, the first electrode 1104, the second electrode 1105, and the source wiring 1106 are simultaneously formed on the insulating film covering the first semiconductor layer and the second semiconductor layer. Further, the pixel electrode 1111, the connection electrode 1110, the gate wiring 1107, and the common wiring 1109 are simultaneously formed on the interlayer insulating film covering the source wiring.

【0107】

Further, the first electrode is electrically connected to the gate wiring, and the first electrode overlapping the first semiconductor layer functions as a gate electrode.

【0108】

Further, although the rectangular pixel electrode is shown in this embodiment, the viewing angle may be further widened by using the shape of the pixel electrode and the common electrode as a doglegged electrode structure.

【0109】

Further, the holding capacity is formed by a second semiconductor layer, an insulating film covering the second semiconductor layer, and a second electrode. This second electrode is electrically connected to the gate wiring of adjacent pixels. Further, an impurity element that imparts n-type is added to the second semiconductor layer.

【0110】

In this embodiment, if the mask pattern of the first embodiment is changed, the pixel configuration can be obtained in the same process as that of the first embodiment.

【0111】

After obtaining the states shown in FIGS. 9 and 10 using Example 1, a liquid crystal display device is obtained by the method shown in Example 2. The gap between the pixels is shielded from light by using a color filter provided on the facing substrate as in the second embodiment. However, since it is an IPS system, it is necessary to change the orientation process.

【0112】

[Example 6] In this embodiment, in the TFT (channel length: L / channel width: W = 10 μm / 8 μm) of the drive circuit obtained in the first embodiment, the impurity region (also referred to as the Lov region) overlapping the gate electrode The relationship between length and reliability in the channel length direction is shown.

【0113】

Here, the time until the maximum value (μFE (max)) of the mobility of the TFT fluctuates by 10% when the length of the Lov region is a certain length is assumed to be the lifetime of the TFT, and the inverse of the drain voltage. Is plotted on a semi-log graph, and the value of the drain voltage having a life of 10 years is derived as a 10-year guaranteed voltage from the obtained linear relationship.

【0114】

In this example, the on-current value of the TFT fluctuates by 10% when the length of the Lov region in the channel length direction (also called the Lov length) is 0.5 μm, 0.78 μm, 1 μm, 1.5 μm, and 1.7 μm, respectively. Assuming the life of the TFT, plot the inverse of the drain voltage on a semi-log graph, and derive the value of the drain voltage with a life of 10 years as the 10-year guaranteed voltage from the obtained linear relationship. The results obtained are shown in FIG.

【0115】

Figure 15 also shows the results obtained in the transient stress test using the drain voltage value, which takes 20 hours for the TFT on-current value to fluctuate by 10%, as the 20-hour guaranteed voltage.

【0116】

As shown in Fig. 15, assuming that it is used for a 16V system device, and considering a 20% margin, the length of the Lov region of the n-channel TFT that is 19.2V (16 × 1.2) or more is It is desirable that the 20-hour guaranteed voltage is 1 μm or more, and the 10-year guaranteed voltage is 1.5 μm or more.

【0117】

[Example 7] In this embodiment, FIG. 16 shows an example of manufacturing a light emitting display device provided with an organic light emitting device (OLED).

【0118】

FIG. 16 (A) is a top view of a module having an OLED, a so-called EL module, and FIG. 16 (B) is a cross-sectional view of FIG. 16 (A) cut along A-A'. A pixel portion 902, a source side drive circuit 901, and a gate side drive circuit 903 are formed on a substrate 900 having an insulating surface (for example, a glass substrate, a crystallized glass substrate, a plastic substrate, etc.). These pixel portions and drive circuits can be obtained according to the first embodiment.

【0119】

Further, 918 is a sealing material, 919 is a protective film made of aluminum nitride, aluminum nitride, or a DLC film, and the pixel portion and the drive circuit portion are covered with the sealing material 918, and the sealing material is covered with the protective film 919. There is. Further, it is sealed with a cover material 920 using an adhesive. The cover material 920 may be a base material having any composition such as plastic, glass, metal, and ceramics. Further, the shape of the cover material 920 and the shape of the support are not particularly limited, and may be a flat surface, a curved surface, a bendable shape, or a film shape. It is desirable to use a cover material 920 made of the same material as the substrate 900, for example, a glass substrate in order to withstand deformation due to heat or external force. Process to 10 μm). It is desirable to further process it to form a recess (depth 50 to 200 μm) on which the desiccant 921 can be placed. In addition, when manufacturing an EL module with multi-chamfering, after bonding the substrate and cover material, CO₂It may be divided by using a laser or the like so that the end faces match.

【0120】

Although not shown here, circularly polarized light called a circularly polarized light composed of a retardation plate (λ / 4 plate) or a polarizing plate is used to prevent the background from being reflected due to reflection of the metal layer used (here, a cathode or the like). The means may be provided on the substrate 900.

【0121】

The 908 is a wiring for transmitting a signal input to the source side drive circuit 901 and the gate side drive circuit 903, and receives a video signal or a clock signal from an FPC (flexible printed circuit) 909 which is an external input terminal. Further, the light emitting device of this embodiment may be digitally driven or analog driven, and the video signal may be a digital signal or an analog signal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to this FPC. The light emitting device in the present specification includes not only the light emitting device main body but also a state in which an FPC or PWB is attached to the light emitting device main body. It is also possible to form complex integrated circuits (memory, CPU, controller, D / A converter, etc.) on the same board as these pixel parts and drive circuits, but it is difficult to manufacture with a small number of masks. is there. Therefore, it is preferable to mount an IC chip equipped with a memory, a CPU, a controller, a D / A converter, etc. by a COG (chip on glass) method, a TAB (tape automated bonding) method, or a wire bonding method.

【0122】

Next, the cross-sectional structure will be described with reference to FIG. 16 (B). An insulating film 910 is provided on the substrate 900, a pixel portion 902 and a gate side drive circuit 903 are formed above the insulating film 910, and the pixel portion 902 is electrically connected to the current control TFT 911 and its drain. It is formed by a plurality of pixels including the pixel electrode 912. Actually, a plurality of TFTs are created in one pixel, but for simplification, only the current control TFT 911 is shown here. The gate-side drive circuit 903 is formed of n-channel TFTs 913 and 914.

【0123】

These TFTs (including 911, 913, and 914) may be prepared according to the n-channel TFT of Example 1 above.

【0124】

Further, in a display device having an OLED, a drive method in which a circuit is designed so that a constant current is applied to the OLED to supply a current, and a voltage applied to the OLED so that a constant current is supplied to the OLED. There is a drive method in which the circuit is designed to adjust the voltage, and a drive method in which the circuit is designed so that a constant current is supplied to the OLED, but regardless of the drive method, it is electrically connected to the OLED. In addition, the on-current (I) of the TFT that supplies current to the OLED (in the present specification, this TFT is referred to as a current control TFT and corresponds to the current control TFT 911 in FIG. 16)._on) Determines the brightness of the pixel.

【0125】

In this embodiment, an n-channel type TFT is used for the switching TFT802 and an n-channel type TFT is used for the current control TFT911. However, the present invention is not limited to this configuration, and three TFTs provided in one pixel are provided. , 4, 5, 6 or more. The switching TFT and the current control TFT may be formed by a p-channel type TFT. However, when the OLED cathode is used as the pixel electrode, the current control TFT is preferably an n-channel type TFT, and when the OLED anode is used as the pixel electrode, the current control TFT is a p-channel type TFT. desirable.

【0126】

Further, it is desirable to use an insulating film having high flatness and high translucency as the insulating film 808 provided between the active layer of the TFT and the OLED. Specifically, the organic resin film by the coating method and the silicon nitride film by the sputtering method may be laminated. Alternatively, it is preferable to perform a flattening treatment after forming the insulating film. As the flattening treatment, a known technique for improving flatness, for example, a polishing step called chemical-mechanical polishing (hereinafter referred to as CMP) may be used. When CMP is used, for example, it is preferable to use a CMP abrasive (slurry) for the insulating film in which fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in a KOH-added aqueous solution. The insulating film is removed by about 0.1 to 0.5 μm by CMP to flatten the surface. It is desirable that the OLED has a film thickness as uniform as possible because the light emission varies when the film thickness of the organic compound layer is non-uniform.

【0127】

The insulating films 807 and 808 provided between the active layer of TFT and the OLED not only block the diffusion of impurity ions such as alkali metal ions and alkaline earth metal ions, but also actively actively block alkali metal ions and alkalis. A material that adsorbs impurity ions such as earth metal ions is preferable, and a material that can withstand the subsequent process temperature is also suitable. An example of a material that meets these conditions is a silicon nitride film containing a large amount of fluorine. The concentration of fluorine contained in the silicon nitride film is 1 × 10.¹⁹/cm³As described above, preferably, the composition ratio of fluorine in the silicon nitride film may be 1 to 5%. Fluorine in the silicon nitride film binds to alkali metal ions, alkaline earth metal ions, etc. and is adsorbed in the film. Further, as another example, an organic resin film containing fine particles composed of an antimony (Sb) compound, a tin (Sn) compound, or an indium (In) compound that adsorbs alkali metal ions, alkaline earth metal ions, etc., for example, antimony pentoxide. Fine particles (Sb₂O₅ NH₂An organic resin film containing O) can also be mentioned. The organic resin film contains fine particles having an average particle size of 10 to 20 nm, and has very high light transmittance. The antimony compound represented by the antimony pentoxide fine particles easily adsorbs impurity ions such as alkali metal ions and alkaline earth metal ions.

【0128】

In addition, AlN is another material for the insulating films 807 and 808 provided between the active layer of the TFT and the OLED._XO_YThe layer indicated by may be used. An aluminum nitride layer (AlN) obtained by forming a film using a sputtering method, for example, using an aluminum nitride (AlN) target in an atmosphere in which argon gas, nitrogen gas, and oxygen gas are mixed._XO_YThe layer (shown by) is a film containing 2.5 atm% to 47.5 atm% of nitrogen, and in addition to having the effect of blocking water and oxygen, it has high thermal conductivity and heat dissipation effect, and is also translucent. Has the characteristic of being very high. In addition, impurities such as alkali metals and alkaline earth metals can be prevented from entering the active layer of the TFT.

【0129】

The pixel electrode 912 electrically connected to the electrode 809, which is electrically connected to one of the impurity regions 806 of the current control TFT 911, functions as an anode of the OLED. As the anode, a conductive film having a large work function, typically an oxide conductive film, is used. As the oxide conductive film, indium oxide, tin oxide, zinc oxide or a compound thereof may be used. Further, a bank 915 made of an inorganic insulator or an organic insulator is formed at both ends of the pixel electrode 912, and an EL layer 916 and an OLED cathode 917 are formed on the pixel electrode 912.

【0130】

As the EL layer 916, an EL layer (a layer for causing light emission and carrier movement for that purpose) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, a low molecular weight organic EL material or a high molecular weight organic EL material may be used. Further, as the EL layer, a thin film made of a light emitting material (singlet compound) that emits light (fluorescence) by singlet excitation or a thin film made of a light emitting material (triplet compound) that emits light (phosphorescence) by triplet excitation can be used. It is also possible to use an inorganic material such as silicon carbide as the charge transport layer and the charge injection layer. Known materials can be used as these organic EL materials and inorganic materials.

【0131】

The cathode 917 also functions as wiring common to all pixels and is electrically connected to the FPC909 via the connection wiring 908. As a material used for the cathode 917, it is preferable to use a metal having a small work function (typically, a metal element belonging to Group 1 or Group 2 of the periodic table) or an alloy containing these. The smaller the work function, the higher the luminous efficiency. Therefore, as the material used for the cathode, an alloy material containing Li (lithium), which is one of the alkali metals, is preferable. Further, all the elements included in the pixel portion 902 and the gate side drive circuit 903 are covered with the cathode 917, the sealing material 918, and the protective film 919.

【0132】

As the sealing material 918, it is preferable to use a material that is transparent or translucent with respect to visible light as much as possible. Further, it is desirable that the sealing material 918 is a material that does not allow moisture or oxygen to permeate as much as possible.

【0133】

After completely covering the OLED with the sealing material 918, at least the AlON film, AlN film, and Al as shown in FIG.₂O₃It is preferable to provide a protective film 919 made of a single layer or a laminate selected from a film or a DLC film on the surface (exposed surface) of the sealing material 918. Further, a protective film may be provided on the entire surface including the back surface of the substrate. Here, it is necessary to be careful not to form a protective film on the portion where the external input terminal (FPC) is provided. A mask may be used to prevent the protective film from being formed, or a tape such as masking tape used in the CVD apparatus may be used to cover the external input terminal portion to prevent the protective film from being formed.

【0134】

By encapsulating the OLED with the sealing material 918 and the protective film with the above structure, the OLED can be completely blocked from the outside, and substances that promote deterioration due to oxidation of the EL layer such as moisture and oxygen invade from the outside. You can prevent it from happening. In addition, if a film having thermal conductivity (AlON film, AlN film, etc.) is used as the protective film, the heat generated when the film is driven can be dissipated. Therefore, a highly reliable light emitting device can be obtained.

【0135】

Further, the pixel electrode may be used as a cathode, and the EL layer and the anode may be laminated to emit light in the direction opposite to that in FIG. An example is shown in FIG. Since the top view is the same, it is omitted.

【0136】

The cross-sectional structure shown in FIG. 17 will be described below. As the substrate 1000, a semiconductor substrate or a metal substrate can be used in addition to the glass substrate and the quartz substrate. An insulating film 1010 is provided on the substrate 1000, and a pixel portion 1002 and a gate side drive circuit 1003 are formed above the insulating film 1010. The pixel portion 1002 is electrically connected to the current control TFT 1011 and its drain. It is formed by a plurality of pixels including the pixel electrode 1012. Further, the gate side drive circuit 1003 is formed by combining an n-channel type TFT 1013 and an n-channel type TFT 1014.

【0137】

The pixel electrode 1012 functions as the cathode of the OLED. Banks 1015 are formed at both ends of the pixel electrode 1012, and an EL layer 1016 and an OLED anode 1017 are formed on the pixel electrode 1012.

【0138】

The anode 1017 also functions as wiring common to all pixels and is electrically connected to the FPC 1009 via the connection wiring 1008. Further, all the elements included in the pixel portion 1002 and the gate side drive circuit 1003 are covered with the anode 1017, the sealing material 1018, and the protective film 1019. Further, the cover material 1021 and the substrate 1000 were bonded together with an adhesive. In addition, a recess is provided in the cover material, and the desiccant 1021 is installed.

【0139】

As the sealing material 1018, it is preferable to use a material that is transparent or translucent with respect to visible light as much as possible. Further, it is desirable that the sealing material 1018 is a material that does not allow moisture or oxygen to permeate as much as possible.

【0140】

Further, in FIG. 17, since the pixel electrode is used as the cathode and the EL layer and the anode are laminated, the light emitting direction is the direction of the arrow shown in FIG.

【0141】

Although not shown here, in order to prevent the background from being reflected due to the reflection of the metal layer used (here, the pixel electrode that serves as the cathode), a circularly polarizing plate made of a retardation plate (λ / 4 plate) or a polarizing plate is used. Circularly polarized light means called may be provided on the cover material 1020.

【0142】

In addition, this embodiment can be freely combined with any of Example 1, Example 4, and Example 6.

【0143】

Although it is possible to configure the drive circuit using the shift register shown in the fourth embodiment, a decoder using only the n-channel TFT is used instead of the shift register, and the source drive circuit and the gate drive circuit are all E. The case of forming with the mold TFT will be described below with reference to FIGS. 18 to 20.

【0144】

FIG. 18 is an example of a gate side drive circuit. In FIG. 18, 400 is a decoder of the gate side drive circuit, and 401 is a buffer part of the gate side drive circuit. The buffer unit refers to a portion in which a plurality of buffers (buffer amplifiers) are integrated. Further, the buffer refers to a circuit that drives without giving the influence of the latter stage to the front stage.

【0145】

First, the gate side decoder 400 will be described. First, 402 is the input signal line of the decoder 400 (hereinafter referred to as the selection line), where A1, A1 bar (signal with inverted polarity of A1), A2, A2 bar (signal with inverted polarity of A2) ,. .. An, An bar (signal with inverted polarity of An) is shown. That is, it can be considered that 2n selection lines are lined up.

【0146】

The number of selection lines is determined by the number of rows of gate wiring output from the gate side drive circuit. For example, if it has a VGA display pixel part, the number of gate wiring is 480, so a total of 18 selection lines are required for 9 bits (corresponding to n = 9). The selection line 402 transmits the signal shown in the timing chart of FIG. As shown in FIG. 19, assuming that the frequency of A1 is 1, the frequency of A2 is 2.^-1Double, A3 frequency is 2^-2Double, An frequency is 2^-(N-1)Double.

【0147】

Further, 403a is a first-stage NAND circuit (also referred to as a NAND cell), 403b is a second-stage NAND circuit, and 403c is an n-stage NAND. The NAND circuit requires the number of gate wirings, and n pieces are required here. That is, in this embodiment, the decoder 400 is composed of a plurality of NAND circuits.

【0148】

Further, in the NAND circuits 403a to 403c, n-channel type TFTs 404 to 409 are combined to form a NAND circuit. Actually, 2n TFTs are used in the NAND circuit 403. Further, each gate of the n-channel type TFTs 404 to 409 is connected to one of the selection lines 402 (A1, A1 bar, A2, A2 bar ... An, An bar).

【0149】

At this time, in the NAND circuit 403a, the n-channel type TFTs 404 to 406 having a gate connected to either A1, A2 ... An (these are called positive selection lines) are connected in parallel with each other. , Negative power line as a common source (V_DL) It is connected to 410 and is connected to output line 411 as a common drain. In addition, n-channel TFTs 407 to 409 having a gate connected to either the A1 bar, the A2 bar ... An bar (these are called negative selection lines) are connected in series with each other and are connected to each other at the circuit end. The source of the n-channel TFT409 located at is the positive power line (V)._DH) 412, and the drain of the n-channel TFT 407 located at the other end of the circuit is connected to the output line 411.

【0150】

As described above, in this embodiment, the NAND circuit includes n n-channel TFTs connected in series and n n-channel TFTs connected in parallel. However, in the n NAND circuits 403a to 403c, the combinations of the n-channel TFT and the selection line are all different. That is, only one output line 411 is always selected, and a signal is input to the selection line 402 so that the output line 411 is selected in order from the end.

【0151】

Next, the buffer unit 401 is formed by a plurality of buffers 413a to 413c corresponding to each of the NAND circuits 403a to 403c. However, the buffers 413a to 413c may all have the same structure.

【0152】

Further, the buffers 413a to 413c are formed by using the n-channel type TFT 414 to 416. The output line 411 from the decoder is input as the gate of the n-channel TFT 414 (first n-channel TFT). The n-channel TFT414 is a positive power line (V)_DH) 417 is used as the source, and the gate wiring 418 following the pixel portion is used as the drain. In addition, the n-channel type TFT415 (second n-channel type TFT) is a positive power supply line (V)._DH) 417 as a gate, negative power line (V)_DL) 419 is the source, and the gate wiring 418 is the drain, and it is always on.

【0153】

That is, in this embodiment, the buffers 413a to 413c are connected in series to the first n-channel TFT (n-channel TFT 414) and the first n-channel TFT, and are drained from the first n-channel TFT. Includes a second n-channel TFT (n-channel TFT 415) gated by.

【0154】

In addition, the n-channel type TFT416 (third n-channel type TFT) uses the reset signal line (Reset) as a gate and the negative power supply line (V)._DL) 419 is the source, and the gate wiring 418 is the drain. Negative power line (V)_DL) 419 may be the ground power line (GND).

【0155】

At this time, there is a relationship of W1 <W2 between the channel width of the n-channel type TFT415 (referred to as W1) and the channel width of the n-channel type TFT414 (referred to as W2). The channel width is the length of the channel formation region in the direction perpendicular to the channel length.

【0156】

The operation of buffer 413a is as follows. First, when a negative voltage is applied to the output line 411, the n-channel type TFT 414 is in an off state (a state in which no channel is formed). On the other hand, since the n-channel type TFT 415 is always on (a state in which a channel is formed), the voltage of the negative power supply line 419 is applied to the gate wiring 418.

【0157】

However, when a positive voltage is applied to the output line 411, the n-channel type TFT 414 is turned on. At this time, since the channel width of the n-channel type TFT 414 is larger than the channel width of the n-channel type TFT 415, the potential of the gate wiring 418 is pulled by the output on the n-channel type TFT 414 side, and as a result, the voltage of the positive power supply line 417 becomes higher. Added to gate wiring 418.

【0158】

Therefore, the gate wiring 418 outputs a positive voltage (a voltage that turns on the n-channel TFT used as a pixel switching element) when a positive voltage is applied to the output line 411, and a negative voltage to the output line 411. Is applied, a negative voltage (a voltage that turns off the n-channel TFT used as a pixel switching element) is always output.

【0159】

The n-channel TFT416 is used as a reset switch that forcibly lowers the gate wiring 418 to which a positive voltage is applied to a negative voltage. That is, when the selection period of the gate wiring 418 is completed. A reset signal is input to apply a negative voltage to the gate wiring 418. However, the n-channel TFT416 can be omitted.

【0160】

The gate wiring is sequentially selected by the gate side drive circuit of the above operation. Next, the configuration of the source side drive circuit is shown in FIG. The source-side drive circuit shown in FIG. 20 includes a decoder 421, a latch 422, and a buffer section 423. Since the configurations of the decoder 421 and the buffer unit 423 are the same as those of the gate side drive circuit, the description thereof is omitted here.

【0161】

In the case of the source-side drive circuit shown in FIG. 20, the latch 422 consists of a first-stage latch 424 and a second-stage latch 425. Further, the first-stage latch 424 and the second-stage latch 425 each have a plurality of unit units 427 formed of m n-channel type TFTs 426a to 426c. The output line 428 from the decoder 421 is input to the gates of m n-channel type TFTs 426a to 426c forming the unit unit 427. Note that m is an arbitrary integer.

【0162】

For example, in the case of VGA display, the number of source wires is 640. When m = 1, 640 NAND circuits are required, and 20 selection lines (corresponding to 10 bits) are required. However, if m = 8, the required NAND circuit is 80, and the required selection line is 14 (corresponding to 7 bits). That is, assuming that the number of source wirings is M, the number of required NAND circuits is (M / m).

【0163】

Then, the sources of the n-channel type TFT 426a to 426c are connected to the video signal lines (V1, V2 ... Vk) 429, respectively. That is, when a positive voltage is applied to the output line 428, the n-channel type TFT 426a to 426c are turned on all at once, and the video signals corresponding to each are taken in. Further, the video signal thus captured is held in the capacitors 430a to 430c connected to each of the n-channel type TFTs 426a to 426c.

【0164】

The second-stage latch 425 also has a plurality of unit units 427b, and the unit unit 427b is formed of m n-channel type TFTs 431a to 431c. All the gates of the n-channel type TFT 431a to 431c are connected to the latch signal line 432, and when a negative voltage is applied to the latch signal line 432, the n-channel type TFT 431a to 431c are turned on all at once.

【0165】

As a result, the signal held in the capacitors 430a to 430c is held in the capacitors 433a to 433c connected to each of the n-channel type TFT 431a to 431c, and at the same time, is output to the buffer 423. Then, as described with reference to FIG. 19, the output is output to the source wiring 434 via the buffer. The source wiring is sequentially selected by the source side drive circuit of the above operation.

【0166】

As described above, by forming the gate-side drive circuit and the source-side drive circuit only with the n-channel type TFT, it is possible to form all the pixel portions and the drive circuit with the n-channel type TFT. In addition, this embodiment can also be applied to the case where either one of the source side drive circuit and the gate side drive circuit is used as an external IC chip.

【0167】

In addition, this embodiment can be freely combined with any one of Examples 1 to 6.

【0168】

[Example 8] In Example 1, an example in which thermal activation was performed was shown, but here, when activating using laser light, an example in which the conductive layer has a four-layer structure instead of a three-layer structure is used. Shown.

【0169】

First, the step of forming the gate insulating film is carried out in the same manner according to Example 1. Next, as the first conductive film, a W film is formed by a sputtering method. As for the film formation conditions, a W target is used, the pressure is 0.2 Pa, the sputter power is 1 kW, the substrate temperature is 200 ° C, the Ar flow rate is 20 sccm, and the distance between the substrate and the target is 60 mm, and a film formation of 30 to 50 nm is performed.

【0170】

Next, as a second conductive film, an Al-Si film is formed by a sputtering method. Film formation conditions are 300 to 500 nm using an Al target (Si: 2 wt%), pressure is 0.4 Pa, sputter power is 4 kW, substrate temperature is room temperature, Ar flow rate is 50 sccm, and the distance between the substrate and the target is 60 mm. I do.

【0171】

Next, as a third conductive film, a TiN film is formed by a sputtering method. The film formation conditions are Ti target, pressure 0.2Pa, sputtering power 12kW, substrate temperature room temperature, N.₂A film formation of 20 to 100 nm is performed with a flow rate of 50 sccm and a distance between the substrate and the target of 400 mm.

【0172】

Next, as a fourth conductive film, a Ti film is formed by a sputtering method. As for the film forming conditions, a Ti target is used, the pressure is 0.1 Pa, the sputter power is 12 kW, the substrate temperature is room temperature, the Ar flow rate is 20 sccm, and the distance between the substrate and the target is 400 mm, and 20 to 100 nm is formed. This fourth conductive film is provided to reflect the laser beam and protect the gate electrode at the time of subsequent activation by the laser beam.

【0173】

Next, etching may be performed in the same manner as in Example 1 to form a conductive layer to be a gate electrode. In this embodiment, the fourth conductive film is formed, but the etching rate is almost the same as that of the third conductive film.

【0174】

Subsequent steps may follow Example 1. However, in this embodiment, instead of the thermal activation shown in Example 1, activation using the second harmonic and the third harmonic of the pulsed or continuously oscillated YAG laser is performed.

【0175】

When activating by irradiating laser light, if the material of the uppermost layer is TiN, the TiN film absorbs the laser energy and is easily damaged.

【0176】

The present inventors conducted the following experiments.

【0177】

A 50 nm tungsten film is formed on the substrate as the first conductive film, a 500 nm Al-Si film is formed on the second conductive film, and a 50 nm titanium nitride film is further formed as the third conductive film. After forming under the above sputter conditions, it was irradiated with YAG laser light. The laser light conditions are 120.6 mJ / cm for each laser energy density.², 95.8mJ / cm²And said.

【0178】

Photographs observed with a microscope after irradiating the laser beam are FIGS. 21 (A) and 21 (B). Figure 21 (A) shows the laser energy density of 120.6 mJ / cm.²Figure 21 (B) shows 95.8 mJ / cm.²Is. In each case, stripes or cracks were observed, which were thought to be caused by the irradiation of laser light. From this result, it can be read that the TiN film is easily damaged by the laser beam.

【0179】

On the other hand, a 50 nm tungsten film is formed as the first conductive film, a 500 nm Al-Si film is formed on the second conductive film, and a 20 nm titanium nitride film is further formed as the third conductive film. After forming a 30 nm titanium film as a fourth conductive film, YAG laser light was irradiated. The laser light conditions are 120.6 mJ / cm for each laser energy density.²And said. FIG. 21 (C) is a photographic diagram observed with a microscope after irradiating the laser beam. No particular change was seen even when irradiated with laser light, and it can be seen that it was protected by the fourth conductive film.

【0180】

By adopting the four-layer structure shown in this example, activation by laser light can be enabled. In particular, when the substrate is a material having low heat resistance such as a plastic substrate, it is useful to have a four-layer structure because it is activated by laser light.

【0181】

Further, although an example having a four-layer structure is shown in this example, even when the three-layer structure is used, the third conductive film can be either a 50 nm tungsten film or a 50 nm titanium film, both of which are the third conductive films. No change was observed on the irradiated surface of.

【0182】

In addition, this embodiment can be freely combined with any one of Examples 1 to 7.

【0183】

[Example 9] Various modules (active matrix type liquid crystal module, active matrix type EL module, active matrix type EC module) can be completed by the drive circuit and the pixel unit formed by carrying out the present invention. That is, by carrying out the present invention, all electronic devices incorporating them are completed.

【0184】

Such electronic devices include video cameras, digital cameras, head-mounted displays (goggles-type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.). Can be mentioned. Examples of these are shown in FIGS. 11 and 12.

【0185】

FIG. 11A is a personal computer, which includes a main body 2001, an image input unit 2002, a display unit 2003, a keyboard 2004, and the like.

【0186】

FIG. 11B is a mobile computer (mobile computer), which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, an operation switch 2204, a display unit 2205, and the like.

【0187】

FIG. 11C is a player that uses a recording medium on which a program is recorded (hereinafter referred to as a recording medium), and includes a main body 2401, a display unit 2402, a speaker unit 2403, a recording medium 2404, an operation switch 2405, and the like. This player can use a DVD (Digtial Versatile Disc), a CD, or the like as a recording medium for listening to music, watching movies, playing games, or playing the Internet.

【0188】

FIG. 12A is a portable book (electronic book), which includes a main body 3001, a display unit 3002, 3003, a storage medium 3004, an operation switch 3005, an antenna 3006, and the like.

【0189】

FIG. 12B shows a display, which includes a main body 3101, a support base 3102, a display unit 3103, and the like. The present invention can complete a display with a diagonal of 10 to 50 inches.

【0190】

As described above, the scope of application of the present invention is extremely wide, and it can be applied to manufacturing methods of electronic devices in all fields. Further, the electronic device of this embodiment can be realized by using any combination of Examples 1 to 8.

【0191】

[Effect of the invention]

According to the present invention, in a semiconductor device typified by an active matrix type liquid crystal display device and a light emitting device having an active matrix type OLED, a good display can be realized even if the area of the pixel portion is increased and the screen is enlarged. Since the resistance of the source wiring of the pixel portion has been significantly reduced, the present invention can be applied to, for example, a large screen having a diagonal of 40 inches or a diagonal of 50 inches.

[Simple explanation of drawings]

[Figure 1]

The figure which shows the manufacturing process of AM-LCD.

[Figure 2]

The figure which shows the manufacturing process of AM-LCD.

[Fig. 3]

The figure which shows the manufacturing process of AM-LCD.

[Fig. 4]

The figure which shows the top view of the pixel.

[Fig. 5]

The figure which shows the appearance of the liquid crystal module.

[Fig. 6]

The figure which shows the cross section of the transmissive liquid crystal display device.

[Fig. 7]

The figure which shows the structure of the NMOS circuit.

[Fig. 8]

The figure which shows the structure of the shift register.

[Fig. 9]

The figure which shows the top view of the pixel part of this invention.

[Fig. 10]

The figure which shows the cross-sectional view of the pixel part of this invention.

[Fig. 11]

The figure which shows an example of an electronic device.

[Fig. 12]

The figure which shows an example of an electronic device.

[Fig. 13]

Observation SEM photograph after etching.

[Fig. 14]

Observation SEM photograph after etching.

[Fig. 15]

It is a figure which shows the relationship between the reliability (20-hour guarantee voltage, 10-year guarantee voltage) in the TFT of a drive circuit, and the Lov length.

[Fig. 16]

The figure which shows the top surface and the cross section of an EL module.

[Fig. 17]

The figure which shows the cross section of an EL module.

[Fig. 18]

The figure which shows the structure of the gate side drive circuit.

[Fig. 19]

The figure which shows the timing chart of a decoder input signal.

[Fig. 20]

The figure which shows the structure of the drive circuit on a source side.

[Fig. 21]

The figure which shows the observation photograph of the metal film surface after laser irradiation.