Field effect transistor, electroptical device using the same, semiconductor device and electronic apparatus

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a field effect transistor (hereinafter abbreviated as FET), and an electro-optical device, a semiconductor device, and an electronic device using the field effect transistor (hereinafter, abbreviated as FET). It relates to the configuration of a FET having excellent characteristics.

【0002】

[Conventional technology]

SOI (Silicon on Insulator) technology, in which a semiconductor layer composed of a single crystal silicon layer is formed on an insulator and a semiconductor device such as a transistor element is formed on the semiconductor layer, speeds up the element, reduces power consumption, and highly integrates the element. It has advantages such as siliconization, and can be applied to an electro-optical device such as a liquid crystal device, for example.

【0003】

By the way, in a general bulk semiconductor device, since the channel region of the MOSFET can be fixed to a predetermined potential through the base substrate, the electrical characteristics such as the withstand voltage of the device are deteriorated by the parasitic bipolar phenomenon caused by the potential change in the channel region. Does not deteriorate. On the other hand, in the MOSFET of the SOI structure, since the lower part of the channel is completely separated by the underlying insulating film, the channel region cannot be fixed to a predetermined potential as described above, and the channel region is electrically connected. It becomes a floating state.

【0004】

At this time, surplus carriers are generated by the impact ionization phenomenon due to the collision between the carriers accelerated by the electric field near the drain region and the crystal lattice, and the surplus carriers are accumulated in the lower part of the channel. When surplus carriers accumulate in the lower part of the channel and the channel potential rises in this way, the source-channel-drain NPN (in the case of N-channel type) structure operates as an apparent bipolar element, and the device is affected by an abnormal current. There is a problem that the electrical characteristics deteriorate, such as the deterioration of the withstand voltage between the source and drain. A series of phenomena caused by the electrically floating state of these channel portions is called a substrate floating effect.

【0005】

Therefore, conventionally, a technique has been adopted in which a body contact region electrically connected to the channel region by a predetermined path is provided and excess carriers accumulated in the channel region are pulled out from the body contact region to suppress the substrate floating effect. Has been done. A semiconductor device including a MOSFET having an SOI structure having a body contact region of this type is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-246562.

【0006】

[Problems to be Solved by the Invention]

However, the MOSFET having an SOI structure having a body contact region has the following problems. Especially in the case of N-channel MOSFET, the parasitic bipolar phenomenon due to impact ions depends on the gate width. FIG. 16 is a diagram showing the relationship between the gate width and the drain voltage at which the parasitic bipolar phenomenon occurs. The horizontal axis shows the gate width and the vertical axis shows the drain voltage at which the parasitic bipolar phenomenon occurs. This characteristic indicates that the higher the applied drain voltage, the shorter the gate width, the more the parasitic bipolar phenomenon occurs. The dashed line shown in FIG. 16 indicates that the gate width corresponding to the drain electrode used is equal to the length of the lead-out area under the gate electrode, but depending on the conditions, it may be longer than the length of the lead-out area under the gate electrode. Even with small gate widths, parasitic bipolar phenomena may occur at lower drain voltages. As a result, there arises a problem that the electrical characteristics of the MOSFET are deteriorated, such as a decrease in the withstand voltage between the source and the drain and a kink (abnormal rise of the current) in the subthreshold region in the current-voltage characteristic.

【0007】

For example, when this type of MOSFET is used in a peripheral drive circuit of a liquid crystal device, the peripheral drive circuit requires a transistor having a high current supply capacity. For this reason, in the peripheral drive circuit, it is originally desired to use a transistor having a large gate width that can take a large amount of on-current. However, the gate width cannot be unnecessarily increased due to the limitation that the above-mentioned problems due to the parasitic bipolar phenomenon must be avoided. As a countermeasure, a method such as connecting transistors with a small gate width in parallel can be considered, but in that case, the number of transistors constituting the peripheral drive circuit increases, the occupied area becomes large, and the circuit configuration becomes complicated. Such a problem arises. This kind of problem is common not only to electro-optical devices such as liquid crystal devices but also to semiconductor devices using MOSFETs.

【0008】

The present invention has been made to solve the above problems, and can more reliably suppress substrate floating effects such as parasitic bipolar phenomenon in a MOSFET having an SOI structure having a body contact region, and has electrical characteristics. The purpose is to provide an excellent FET. Another object of the present invention is to provide an electro-optical device and a semiconductor device capable of downsizing, simplifying, and improving the driving ability of a circuit by using such a FET.

【0009】

[Means for solving problems]

In order to achieve the above object, in the first FET of the present invention, a semiconductor layer is provided on the insulating layer and a gate electrode is provided above the semiconductor layer via a gate insulating film, and the semiconductor layer is provided with a gate electrode. A partially depleted SOI-type FET in which a source region and a drain region of a first conductive type and a channel region of a second conductive type that is a reverse conductor of the first conductive type are formed, and the semiconductor layer is It has an extending portion extending in a direction intersecting the direction in which the source region, the channel region, and the drain region are lined up on the side of the channel region, and the extending portion extends to the outside of the gate electrode. A second conductive type body contact region located and a lead-out region having a second conductive type impurity diffusion region located below the gate electrode are formed between the channel region and the body contact region. The second conductive type impurity concentration in the impurity diffusion region is higher than the second conductive type impurity concentration in the channel region.

【0010】

The device of interest of the present invention is a FET having a body contact region that is already well known. In the case of this type of FET, a predetermined voltage is applied to the body contact region in order to pull out the surplus carriers under the channel region in order to suppress the substrate floating effect. However, according to the device simulation performed by the present inventor, most of the voltage applied to the body contact region drops (or rises in potential) in this region due to the large resistance of the extraction region under the gate electrode. Therefore, there is almost no potential gradient in the channel region. Therefore, it is considered that it is difficult to extract the holes generated by the impact ionization existing inside the channel region away from the body contact region, the substrate potential tends to rise, and the parasitic bipolar phenomenon occurs.

【0011】

From this, the present inventor has come to the conclusion that if the resistance of the extraction region under the gate electrode is made smaller than the resistance of the channel region, excess carriers (holes) generated by impact ionization can be easily extracted. That is, according to the FET of the present invention, a second conductive type impurity diffusion region is formed in a portion of the conventional lead-out region located below the gate electrode, and the lead-out region is larger than the second conductive type impurity concentration in the channel region. Since the concentration of the second conductive type impurities in the impurity diffusion region is higher, the extraction region under the gate electrode is more depleted than the channel region when a voltage equal to or higher than the threshold voltage is applied to the gate electrode. The spread becomes small and the resistance becomes low. Therefore, since the potential drop in the drawing region is small, it becomes easy to pull out the surplus carriers. As a result, the substrate floating effect such as the parasitic bipolar phenomenon can be suppressed more reliably, and the FET having excellent electrical characteristics can be realized.

【0012】

In order to obtain the above-mentioned actions and effects of the present invention, it is sufficient that the impurity concentration in the impurity diffusion region in the extraction region is higher than the impurity concentration in the channel region, but the impurity diffusion region in the extraction region and the body contact Regarding the magnitude relationship of the impurity concentration with the region, it is desirable that the impurity concentration of the second conductive type in the impurity diffusion region of the extraction region is smaller than the impurity concentration of the second conductive type in the body contact region.

【0013】

If the impurity concentration in the impurity diffusion region of the extraction region is equal to the impurity concentration in the body contact region, the impurity concentration of the second conductive type in the impurity diffusion region is sufficiently high, and the reverse conductivity type draws out high concentrations of each other. The impurity diffusion region of the region and the source / drain region are in close contact with each other. As a result, junction breakdown is likely to occur, and the withstand voltage between the source / drain region and the body contact region may decrease. From this point of view, if the impurity concentration in the impurity diffusion region in the extraction region is set to be smaller than the impurity concentration in the body contact region, junction breakdown is less likely to occur, and the source / drain region and the body contact are made. Sufficient withstand voltage between the area can be secured.

【0014】

When the pattern is viewed in a plan view, the edge extending in the gate width direction of the impurity diffusion region in the extraction region may be designed to be located inside the edge extending in the gate width direction of the channel region. desirable.

【0015】

If the design is such that the edge extending in the gate width direction of the impurity diffusion region in the extraction region coincides with the edge extending in the gate width direction of the channel region, depending on the alignment error of each pattern in the manufacturing process, etc. It is also possible that the impurity diffusion region in the extraction region protrudes into the source region or drain region. In that case, since the impurity diffusion region and the source / drain region are of the reverse conductive type, junction breakdown easily occurs. Therefore, if the edge extending in the gate width direction of the impurity diffusion region in the extraction region is designed to be located inside the edge extending in the gate width direction of the channel region, an alignment margin is generated by that amount. Therefore, even if there is some alignment error in the manufacturing process, the structure can be made so that junction breakdown is unlikely to occur.

【0016】

Further, the impurity diffusion region in the extraction region extends to the outside of the gate electrode on the body contact region side, and the impurity diffusion region has an offset structure in which the gate electrode is not located above the body contact region. It is desirable to have a configuration.

【0017】

According to this configuration, the impurity diffusion region of the extraction region extends to the body contact region side, and that portion is used as the offset region, thereby ensuring the withstand voltage between the source / drain region and the body contact region. it can.

【0018】

Further, it is desirable to form an edge impurity diffusion region in which a second conductive type impurity is injected at a concentration higher than that of the channel region at the edge portion of the channel region opposite to the extraction region.

【0019】

Ion implantation for controlling the threshold voltage of the FET is performed in the channel region, but the edge opposite to the extraction region of the channel region is adjacent to the oxide film, and when this oxide film is formed, it is within the channel region. The impurities are eaten, and a parasitic transistor having a lower threshold voltage than the FET of the main body is formed in this portion. Then, the electrical characteristics of the FET deteriorate, such as a kink in the current-voltage characteristics. Therefore, if an edge impurity diffusion region having an impurity concentration higher than that of the channel region is formed, parasitic transistors are not formed and the electrical characteristics can be maintained satisfactorily.

【0020】

Further, the concentration of the second conductive type impurities can be made equal in the impurity diffusion region and the edge impurity diffusion region in the extraction region.

【0021】

The impurity concentration can be set individually for the impurity diffusion region and the edge impurity diffusion region in the extraction region, but even if the impurity concentration is set equally in these two regions, each function can be exhibited without any problem. .. When the impurity concentrations are set to be equal, the above two impurity diffusion regions can be formed at the same time in one ion implantation step, so that the manufacturing process is not complicated.

【0022】

The capacitance can be formed by the capacitance electrode region in which the second conductive type impurities are injected at a concentration higher than that of the channel region, the same insulating film as the gate insulating film, and the same conductive layer as the gate electrode.

【0023】

If the field effect transistor and the capacitive electrode are used, for example, in the pixel portion of the electro-optical device, the display quality of the electro-optic device can be improved.

【0024】

Further, when the three impurity concentrations of the capacitive electrode region, the impurity diffusion region in the extraction region, and the edge impurity diffusion region are set to be equal, the three impurity diffusion regions are simultaneously formed in one ion implantation step. Therefore, the manufacturing process is not complicated.

【0025】

The semiconductor layer has extending portions extending in a direction intersecting the direction in which the source region, the channel region, and the drain region are lined up on both sides of the channel region, and both the body contact region and the drawing region extend in the extending direction. And may be provided respectively.

【0026】

According to this configuration, the surplus carriers below the channel can be pulled out from both sides of the channel region, so that the surplus carriers inside the channel region can be pulled out more easily. Therefore, the parasitic bipolar phenomenon is less likely to occur as compared with the case where the surplus carriers are pulled out from one side of the channel region, and the gate width can be effectively increased. As a result, it is possible to realize a FET having a sufficiently large on-current. Further, this configuration basically has an advantage that a parasitic transistor does not occur at the edge of the channel region.

【0027】

Further, a configuration having a second conductive type first impurity diffusion layer formed on the surface of the channel region and a second conductive type second impurity diffusion layer formed below the first impurity diffusion layer. It is desirable to do.

【0028】

Here, the first impurity diffusion layer located on the surface of the channel region is formed by an ion implantation step for normal threshold voltage control. According to the above configuration, since the same conductive type second impurity diffusion layer is formed below the first impurity diffusion layer, the neutral region in the channel region, which normally has high resistance, has a low resistance. Therefore, it is possible to easily pull out the surplus carrier.

【0029】

In the second FET of the present invention, a semiconductor layer is provided on the insulating layer and a gate electrode is provided above the semiconductor layer via a gate insulating film, and the first conductive type source region and drain are provided in the semiconductor layer. A partially depleted SOI-type field effect transistor in which a region and a second conductive type channel region of the inverse conductive type are formed in the first conductive type, and the potential of the source region is set in the source region. A contact for fixing is formed, and a second conductive type body contact region is formed along the edge extending in the gate length direction of the source region, and the edge extending in the gate length direction of the channel region is formed. A second conductive type impurity diffusion region connected to the body contact region is formed along the above, and the concentration of the second conductive type impurity in the channel region, the impurity diffusion region, and the body contact region increases in this order. It is characterized by being.

【0030】

The first FET of the present invention has a structure in which the extraction region and the body contact region are extracted to the side of the channel region, and the relationship between the potentials of the source region and the drain region is reversed when applied to an arbitrary circuit. It is intended for FETs with a structure that can be used even if. On the other hand, the second FET of the present invention is intended for a FET having a so-called source tie structure, which is used by fixing the potential relationship between the source region and the drain region, for example, when used in an inverter circuit. There is.

【0031】

The action and effect of the second FET of the present invention are the same as those of the first FET of the present invention, and the spread of the depletion layer is smaller in the impurity diffusion region at the edge of the channel region than in the original channel region. Since the resistance is low, the surplus carriers can be easily pulled out. As a result, the substrate floating effect such as the parasitic bipolar phenomenon can be suppressed more reliably, and the FET having excellent electrical characteristics can be realized.

【0032】

Further, in addition to the body contact region formed along the edge of the source region and the impurity diffusion region formed along the edge of the channel region, a second conductive body contact region is formed inside the source region. At the same time, a second conductive type impurity diffusion region connected to the body contact region is formed inside the channel region, and the second conductive type impurity concentration of the channel region, the impurity diffusion region, and the body contact region is formed. However, a configuration in which the values increase in this order may be adopted.

【0033】

That is, a body contact region for extracting excess carriers and an impurity diffusion region may be formed inside the source region or channel region as well as a portion along the edge of the source region or channel region. According to this configuration, it becomes easy to pull out the surplus carriers even in a transistor having a particularly large gate width. Further, the occupied area can be reduced as compared with arranging the transistors having a small gate width in parallel, which is advantageous in terms of layout.

【0034】

When adopting the source tie structure, it is desirable to arrange the contacts so that a part of the contact covers the body contact area and a part of the contact covers the source area.

【0035】

According to this configuration, the contact functions not only for fixing the potential in the source region but also for pulling out the carrier from the body contact region, so that there is an advantage that only one contact is required.

【0036】

A single crystal silicon layer can be used as the semiconductor layer. According to this configuration, it is possible to provide a FET having high carrier mobility and a large current driving capability.

【0037】

The electro-optical device of the present invention is characterized by including the above-mentioned FET of the present invention. According to this configuration, an electro-optical device having high display quality can be realized by providing a FET having excellent electrical characteristics.

【0038】

In particular, when the electro-optic device has a display unit composed of a plurality of pixels and a drive circuit unit for driving the display unit, it is desirable to use the FET of the present invention for the drive circuit unit. Since a FET having a particularly high current drive capability is required in the drive circuit section, according to this configuration, this requirement can be satisfied, and a FET having a large gate width can be used, so that the number of transistors to be used is large. There are advantages such as a small number of drives, a small occupied area of the drive circuit unit, and a simplification of the circuit configuration.

【0039】

The electronic device of the present invention is characterized by including the above-mentioned electro-optical device of the present invention. According to this configuration, it is possible to realize an electronic device provided with a display unit including an electro-optical device having high display quality.

【0040】

The semiconductor device of the present invention is characterized by including the above-mentioned FET of the present invention. According to this configuration, it is possible to realize a semiconductor device having excellent electrical characteristics in terms of current-voltage characteristics, withstand voltage, and the like.

【0041】

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 7. FIG. 1 is a schematic configuration diagram of a liquid crystal light bulb which is an example of an electro-optic device using the FET of the present invention for a peripheral drive circuit, and FIG. 2 is a cross-sectional view taken along the line HH'of FIG. This liquid crystal light bulb is an active matrix type liquid crystal panel, and uses an SOI substrate on the element substrate side.

【0042】

In the configuration of the liquid crystal light bulb 10 of the present embodiment, as shown in FIGS. 1 and 2, a sealing material 24 is provided on the TFT array substrate 15 so as to be along the edge of the facing substrate 20, and the inside thereof. In parallel with this, a light-shielding film 25 (peripheral parting) is provided as a frame. In the outer region of the sealing material 24, a data line drive circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array board 15, and a scanning line drive circuit 104 is provided on two sides adjacent to this side. It is provided along.

【0043】

Further, on the remaining side of the TFT array substrate 15, a plurality of wirings 105 for connecting between the scanning line drive circuits 104 provided on both sides of the image display area are provided. Further, at at least one corner portion of the opposing substrate 20, a conductive material 106 for establishing electrical conduction between the TFT array substrate 15 and the opposing substrate 20 is provided. Then, as shown in FIG. 2, the opposing substrate 20 having substantially the same contour as the sealing material 24 shown in FIG. 1 is fixed to the TFT array substrate 15 by the sealing material 24, and the TFT array substrate 15 and the opposing substrate 20 are attached to each other. The TN liquid crystal 26 is enclosed between the two. Further, the opening provided in the sealing material 24 shown in FIG. 1 is a liquid crystal injection port 27, which is sealed by the sealing material 28.

【0044】

Here, an example of a circuit diagram of the scanning line drive circuit 104 is shown in FIG. The scan line drive circuit 104 is composed of a shift register 107 and a buffer 108. Further, since the scanning line drive circuit 104 is arranged on the substrate at a position where light is completely blocked and it is not necessary to consider the light leakage current, the entire scanning line drive circuit 104 is composed of a partially depleted transistor having a thick semiconductor layer. can do. Further, if it is desired to increase the drive frequency, the shift register 107 needs to be driven at a high speed. In that case, it is preferable to use a completely depleted transistor capable of reducing the parasitic capacitance. Since the buffer 108 requires a large current driving ability to drive the scanning line, it is preferable to use a partially depleted transistor. As described above, in the peripheral drive circuit, the whole may be composed of the partially depleted type transistor, or the partially depleted type transistor and the completely depleted type transistor may be used properly depending on each circuit. Further, in a circuit such as the transmission gate 110, only one transistor, for example, a partially depleted transistor can be substituted.

【0045】

FIG. 4 shows a plan layout of the transmission gate 110 in the portion surrounded by a solid circle in FIG. In FIG. 4, reference numeral 30 indicates a single crystal silicon layer pattern, 31 indicates a second polysilicon layer pattern, 32 indicates an Al wiring layer pattern, and 33 indicates a contact pattern. As shown in this figure, the transmission gate 110 is composed of four partially depleted transistors including an N-channel transistor 40 and a P-channel transistor 41. Among them, a FET having a body contact region, which is the object of the present invention, is used for the N-channel transistor 40.

【0046】

FIG. 5 is a plan view showing only the FETs indicated by the alternate long and short dash line circles in FIG. 4. FIG. 6 is a cross-sectional view taken along the line AA'of FIG. As shown in FIGS. 5 and 6, the FET 50 of the present embodiment has a T-shaped single crystal silicon layer 53 (semiconductor layer) formed on a support substrate 51 via an embedded silicon oxide film 52 (insulating layer). Have. Of the single crystal silicon layer 53, an N-type (first conductive type) source region 54 is formed on the lower side in FIG. 5, and an N-type drain region 55 is formed on the upper side, between the source region 54 and the drain region 55. A channel region 56 in which P-type (second conductive type) impurities are injected is formed on the surface for threshold voltage control. The FET 50 of the present embodiment is not used by fixing the potential of either the source region 54 or the drain region 55, and can cope with the reversal of the potential relationship between the source region 54 and the drain region 55. It is a thing. The structure of the source region 54 and the drain region 55 is a structure having a low concentration region on the channel region 56 side and a high concentration region on the outside, so-called LDD (Lightly Doped). A Drain) structure may be adopted. A T-shaped gate electrode 58 is formed on the single crystal silicon layer 53 via a gate insulating film 57 made of a silicon oxide film.

【0047】

The single crystal silicon layer 53 has an extending portion 53a extending in a direction substantially orthogonal to the direction in which the source region 54, the channel region 56, and the drain region 55 are arranged (on the right side in FIG. 5) on the side of the channel region 56. ing. Then, in the extending portion 53a, the P-shaped body contact region 60 located outside the gate electrode 58 and the P-shaped body contact region 60 located below the gate electrode 58 between the channel region 56 and the body contact region 60. A lead-out region 62 having an impurity diffusion region 61 is formed. In the case of the present embodiment, the edge extending in the gate width direction of the impurity diffusion region 61 in the extraction region 62 is aligned substantially linearly with the edge extending in the gate width direction of the channel region 56. On the other hand, a P-shaped edge impurity diffusion region 63 is formed at the edge of the channel region 56 opposite to the extraction region 62. The conductive type of the impurity diffusion region 61 and the body contact region 60 in the channel region 56 and the extraction region 62 are all P-type, but the magnitude relationship of the impurity concentration is that of the channel region 56, the impurity diffusion region 61, and the body contact region 60. It is getting bigger in order. Further, the impurity concentrations in the impurity diffusion region 61 and the edge impurity diffusion region 63 in the extraction region 62 are equal.

【0048】

Here, giving specific examples of the dimensions, impurity concentration, etc. of the FET 50 having the above configuration, the film thickness of the embedded silicon oxide film 52: 300 to 1000 nm (for example, 400 nm), the film thickness of the single crystal silicon layer 53: 200 to 500 nm (400 nm as an example), gate insulating film 57 film thickness: 60 nm, gate electrode 58 material: N + type, polysilicon, gate electrode 58 film thickness: 350 nm, gate length: 4 μm, lead area length: 3.5 μm, Ion implantation conditions for channel region 56 are ion type: B + (boron), implantation energy: 45KeV, dose amount: 5 × 10.¹¹/cm², The ion implantation conditions of the impurity diffusion region 61 in the extraction region 62 are ion type: B +, implantation energy: 80 KeV, dose amount: 1 × 10¹³/cm², Ion implantation conditions for body contact area 60 are ion type: B +, implantation energy: 45KeV, dose amount: 2 × 10¹⁵/cm², Source region 54, drain region 55 ion implantation conditions are ion type: P + (phosphorus), implantation energy: 100KeV, dose amount: 2 × 10¹⁵/cm², Ion implantation conditions in the LDD region (low concentration region) when adopting the LDD structure are ion type: P +, implantation energy: 160KeV, dose amount: 4 × 10¹²/cm²,.

【0049】

17 and 18 show the configuration of the conventional FET with respect to FIGS. 5 and 6. The conventional FET 200 shown in FIGS. 17 and 18 has the same shape as that of FIGS. 5 and 6, but the impurity diffusion region is not formed in the extraction region 62. When a voltage equal to or higher than the threshold voltage is applied to the gate electrode 58 with respect to the FET 200, as shown in FIG. 19, the depletion layer 65 greatly expands in the lead-out region 62 under the gate electrode 58 as well as the channel region 56, and this portion Resistance increases. As a result, it has become difficult to extract the surplus carriers existing inside the channel region 56 away from the body contact region 60.

【0050】

On the other hand, in the FET 50 of the present embodiment, the impurity diffusion region 61 is formed in the extraction region 62, and the impurity diffusion region 61 of the extraction region 62 has a higher impurity concentration than the channel region 56. Therefore, as shown in FIG. 7, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 58, the extraction region 62 under the gate electrode 58 has a smaller spread of the depletion layer 65 than the channel region 56, and the extraction region 62 has lower resistance than the conventional structure. Therefore, since the potential drop in the extraction region 62 of the potential applied to the body contact region 60 becomes small, it becomes easy to extract the surplus carriers in the channel region 56. As a result, the substrate floating effect such as the parasitic bipolar phenomenon can be suppressed more reliably, and the FET having excellent electrical characteristics can be realized. Furthermore, since the impurity concentration in the impurity diffusion region 61 of the extraction region 62 is smaller than that in the body contact region 60, the junction breakdown between the channel region 56 and the body contact region 60 is less likely to occur, and the source-drain Sufficient pressure resistance can be secured.

【0051】

Further, in the case of the present embodiment, the edge impurity diffusion region 63 is formed at the edge of the channel region 56, and the parasitic transistor is not formed at the edge of the channel region 56 opposite to the extraction region 62. Therefore, the current-voltage characteristics are not kinked, and the electrical characteristics can be maintained well. Further, since the impurity concentrations of the impurity diffusion region 61 and the edge impurity diffusion region 63 in the extraction region 62 are equal, the above two impurity diffusion regions can be formed at the same time in one ion implantation step, which complicates the manufacturing process. Never become.

【0052】

Further, as shown in FIG. 20, it is formed by a single crystal silicon layer 53b which is the same layer as the semiconductor layer 53 of the FET 50 of the present embodiment, a gate insulating film 57 (not shown), and the same thin film as the gate electrode 58. The capacitance portion 300 formed by the capacitance electrode 58a can be connected. Impurities can be doped into the single crystal silicon layer 53a, which is the lower electrode of the capacitance portion 300, by an ion implantation step of forming the extraction region 62 of the channel region 56 and the edge impurity diffusion region 63 at the edge of the channel region 56. it can. That is, since the above three impurity diffusion regions can be formed in one ion implantation step, the manufacturing process is not complicated.

【0053】

Then, in the liquid crystal light valve 10 of the present embodiment, by providing the FET 50 having the above configuration in the peripheral drive circuit such as the transmission gate 110 of the scanning line drive circuit 104, a problem such as a parasitic bipolar phenomenon occurs. Since a FET with a large gate width and high current drive capability can be used without this, the number of transistors used in the circuit can be reduced, the occupied area of the drive circuit section can be reduced, and the circuit configuration can be simplified. It is possible to obtain effects such as being able to.

【0054】

[Second Embodiment] Hereinafter, a second embodiment of the present invention will be described with reference to FIG. FIG. 8 is a plan view showing the configuration of the FET of the present embodiment. The basic configuration of the FET of this embodiment is the same as that of the first embodiment, only the plane pattern of the impurity diffusion region of the extraction region is different. Therefore, in FIG. 8, the same components as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

【0055】

In the case of the first embodiment, the edge extending in the gate width direction of the impurity diffusion region 61 in the extraction region 62 and the edge extending in the gate width direction of the channel region 56 are arranged substantially linearly. On the other hand, in the FET 72 of the present embodiment, as shown in FIG. 8, the edge extending in the gate width direction of the impurity diffusion region 70 in the extraction region 62 extends in the gate width direction of the channel region 56. It is located inside the edge. That is, the dimension of the impurity diffusion region 70 in the extraction region 62 in the gate length direction is narrower than that of the first embodiment. Similarly, the edge extending in the gate width direction of the edge impurity diffusion region 71 is located inside the edge extending in the gate width direction of the channel region 56.

【0056】

Also in the FET 72 of the present embodiment, the same effect as that of the first embodiment can be obtained, such that the substrate floating effect such as the parasitic bipolar phenomenon can be surely suppressed and the FET having excellent electrical characteristics can be realized. ..

【0057】

Further, in the case of the configuration of the first embodiment, it is conceivable that the impurity diffusion region 61 in the extraction region 62 protrudes into the source region 54 or the drain region 55 depending on the alignment error of each pattern in the manufacturing process. In that case, since the impurity diffusion region 61 and the source / drain region are of the reverse conductive type, junction breakdown easily occurs. On the other hand, in the case of the present embodiment, since the edge of the impurity diffusion region 70 in the extraction region 62 is located inside the edge of the channel region 56, an alignment margin is formed, and the alignment margin is formed during the manufacturing process. Even if there is some alignment error, junction breakdown is unlikely to occur, and the structure can be made resistant to pattern deviation.

【0058】

[Third Embodiment] Hereinafter, a third embodiment of the present invention will be described with reference to FIG. FIG. 9 is a plan view showing the configuration of the FET of the present embodiment. The basic configuration of the FET of this embodiment is the same as that of the first embodiment, only the plane pattern of the lead-out region is different. Therefore, in FIG. 9, the same components as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

【0059】

In the case of the first embodiment, the edge of the gate electrode 58 was located on the boundary line between the impurity diffusion region 61 and the body contact region 60 in the extraction region 62. On the other hand, in the FET 74 of the present embodiment, as shown in FIG. 9, the edge of the gate electrode 58 is closer to the channel region 56 than the boundary between the impurity diffusion region 61 and the body contact region 60 in the extraction region 62. positioned. That is, most of the impurity diffusion region 61 in the extraction region 62 is located below the gate electrode 58, but a part near the body contact region 60 protrudes to the outside of the gate electrode 58, and this protrusion The portion 75 has an offset structure. This offset length can be, for example, about 1 to 3 μm.

【0060】

The FET 74 of the present embodiment also has the same effects as those of the first and second embodiments, such that the substrate floating effect such as the parasitic bipolar phenomenon can be reliably suppressed and the FET having excellent electrical characteristics can be realized. be able to.

【0061】

Further, in particular, according to the configuration of the present embodiment, the impurity diffusion region 61 of the extraction region 62 is extended to the body contact region 60 side, and the portion is made into an offset structure so that the source / drain regions 54 and 55 are formed. Sufficient pressure resistance between the body contact area 60 and the body contact area 60 can be secured.

【0062】

[Fourth Embodiment] Hereinafter, a fourth embodiment of the present invention will be described with reference to FIGS. 10 and 11. FIG. 10 is a plan view showing the configuration of the FET of the present embodiment. The FET of the present embodiment is different from the first to third embodiments in that a lead-out region and a body contact region are provided on both sides of the channel region.

【0063】

As shown in FIG. 10, the FET 77 of the present embodiment has a rectangular single crystal silicon layer 78. Of the single crystal silicon layer 78, an N-type source region 79 is formed on the lower side and an N-type drain region 80 is formed on the upper side in FIG. 10, and a P-type channel region is formed between the source region 79 and the drain region 80. 81 is formed. Similar to the above, the FET 77 of the present embodiment can cope with the reversal of the potential relationship between the source region 79 and the drain region 80. An H-shaped gate electrode 82 is formed on the single crystal silicon layer 78 via a gate insulating film.

【0064】

The single crystal silicon layer 78 extends in a direction (horizontal direction in FIG. 10) substantially orthogonal to the direction in which the source region 79, the channel region 81, and the drain region 80 are arranged on both sides of the channel region 81. have. Then, in the extending portions 78a and 78b, between the P-shaped body contact regions 83a and 83b located outside the gate electrode 82 and the channel region 81 and the body contact regions 83a and 83b, below the gate electrode 82. A drawing region 85a, 85b having a P-type impurity diffusion region 84a, 84b located in is formed. In the case of the present embodiment, the edges extending in the gate width direction of the impurity diffusion regions 84a and 84b in the extraction regions 85a and 85b are substantially linear with the edges extending in the gate width direction of the channel region 81. .. The conductive types of the impurity diffusion regions 84a and 84b and the body contact regions 83a and 83b in the channel region 81 and the extraction regions 85a and 85b are all P-type, and the magnitude relationship of the impurity concentration is the channel region 81 and the impurity diffusion regions 84a and 84b. , The point that the body contact areas increase in the order of 83a and 83b is the same as that of the above embodiment.

【0065】

According to the configuration of the FET 77 of the present embodiment, the surplus carriers below the channel can be pulled out from both sides of the channel region 81, so that the channel is pulled out from only one side of the channel region as compared with the first to third embodiments. The surplus carriers inside the region 81 are more easily pulled out. Therefore, the parasitic bipolar phenomenon is less likely to occur as compared with the structures of the first to third embodiments, and the gate width can be effectively increased. As a result, it is possible to realize a FET having a sufficiently large on-current. Further, in this configuration, there is basically no parasitic transistor generated at the edge of the channel region 81, and there is an advantage that an abnormal portion of the current-voltage characteristic does not occur.

【0066】

Further, as shown in FIG. 11, the length of the portion extending in the gate length direction of the H-shaped gate electrode 82 is shortened with respect to the one shown in FIG. 10, and the drawer areas 85a and 85b (body contact area 83a) are shortened. , 83b) may be adopted in FET 77', which has a structure in which the length in the gate length direction is shortened. That is, this configuration is a configuration in which the extraction regions of the FETs of the first embodiment shown in FIG. 5 are on both sides. In FIG. 11, the same components as those in FIG. 10 are designated by the same reference numerals, and the description thereof will be omitted.

【0067】

[Fifth Embodiment] Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG. The planar pattern of the FET of this embodiment is the same as that of the first embodiment, only the impurity profile in the thickness direction of the semiconductor layer is different. FIG. 12 is a cross-sectional view showing the configuration of the FET of the present embodiment, and corresponds to FIG. 6 showing the cross-sectional structure of the FET of the first embodiment. Therefore, in FIG. 12, the same components as those in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted.

【0068】

In the first embodiment, P-type impurities are injected only on the surface of the channel region 56 for controlling the threshold voltage. On the other hand, in the case of the FET 87 of the present embodiment, as shown in FIG. 12, P-type impurities are injected into the surface of the channel region 56 for threshold voltage control, that is, the region that becomes the depletion layer when a voltage is applied, and the first In addition to the formation of the impurity diffusion layer 88 of 1, P-type impurities are also injected into the lower part of the channel region 56, that is, the region that becomes a neutral region when a voltage is applied, and a second impurity diffusion layer 89 is formed. ing.

【0069】

To give a specific example, the ion implantation conditions for forming the first impurity diffusion layer 88 are the same as in the first embodiment, ion type: B + (boron), implantation energy: 45KeV, dose amount: 5 ×. Ten¹¹/cm²The ion implantation conditions for forming the second impurity diffusion layer 89 are ion type: B +, implantation energy: 130 KeV, dose amount: 1 × 10.¹²/cm²Is. Thus, the ion implantation energy is higher when the second impurity diffusion layer 89 is formed than when the first impurity diffusion layer 88 is formed, and therefore, when the second impurity diffusion layer 89 is formed, the deep portion of the single crystal silicon layer 53 is formed. Ion implantation is performed so that the peak of the impurity concentration appears in.

【0070】

According to the configuration of the present embodiment, since the same conductive type second impurity diffusion layer 89 is formed in the neutral region below the first impurity diffusion layer 88, it is usually compared with the extraction region 62. Even the neutral region in the channel region 56, which has a high resistance, is reduced in resistance, and the extraction of excess carriers can be further facilitated.

【0071】

[Sixth Embodiment] Hereinafter, the sixth embodiment of the present invention will be described with reference to FIG. Whereas the FET of the first to fifth embodiments has a structure in which the potential relationship may be reversed between the source region and the drain region, the FET of the present embodiment has a structure of the source region and the drain region. This is an example of a FET with a source tie structure that is used with a fixed potential relationship.

【0072】

In the FET 90 of the present embodiment, as shown in FIG. 13, the gate electrode 92 is arranged so as to intersect the rectangular single crystal silicon layer 91, and among the single crystal silicon layers 91, the lower part in FIG. An N-type source region 93 is formed on the side, an N-type drain region 94 is formed on the upper side, and a P-type channel region 95 is formed between the source region 93 and the drain region 94.

【0073】

P-shaped body contact regions 96a and 96b are formed along the edge of the source region 93 extending in the gate length direction on the single crystal silicon layer 91, and further extend in the gate length direction of the channel region 95. P-type impurity diffusion regions 97a and 97b connected to the body contact regions 96a and 96b are formed along the edges. The conductive type of the channel region 95, the impurity diffusion region 97a, 97b, and the body contact region 96a, 96b are all P type, and the impurity concentrations of the channel region 95, the impurity diffusion region 97a, 97b, and the body contact region 96a, 96b are in this order. It's getting bigger. Further, a contact 98 is provided so as to straddle the source region 93 and the body contact region 96b on one side.

【0074】

The FET 90 of the present embodiment is a FET having a source tie structure such as that used in an inverter circuit, but the action and effect of this FET 90 are almost the same as those of the FET of the above embodiment. That is, since the impurity diffusion regions 97a and 97b at the edge of the channel region 95 have a higher impurity concentration than the original channel region 95, the spread of the depletion layer becomes smaller, and this portion has lower resistance, so that the body contact region It becomes easier to pull out surplus carriers from 96a and 96b. As a result, the substrate floating effect such as the parasitic bipolar phenomenon can be surely suppressed, and the FET having excellent electrical characteristics can be realized.

【0075】

Further, by providing the contact 98 so as to straddle the source region 93 and the body contact region 96b, the contact 98 functions as a potential fixing of the source region 93 and also as a pull-out of a surplus carrier from the body contact region 96b. It also works, so it has the advantage of requiring only one contact.

【0076】

[7th Embodiment] Hereinafter, the 7th embodiment of the present invention will be described with reference to FIG. Similar to the sixth embodiment, the FET of the present embodiment is an example of a FET having a source tie structure in which the potential relationship between the source region and the drain region is fixed and used, and also inside the source region and the channel region. An example in which a pull-out area for the surplus carrier is provided is shown. Therefore, in FIG. 14, the same components as those in FIG. 13 are designated by the same reference numerals, and detailed description thereof will be omitted.

【0077】

In the FET of the present embodiment, as shown in FIG. 14, the body contact region 96a, 96b formed along the edge of the source region 93 and the impurity diffusion region 97a, formed along the edge of the channel region 95. In addition to 97b, a P-shaped body contact region 96c extending in the gate length direction is formed in the substantially central portion of the source region 93, and the gate length direction connected to the body contact region 96c is formed inside the channel region 95. A P-type impurity diffusion region 97c extending to the surface is formed. The relationship between the impurity concentrations is the same as that of the body contact regions 96a and 96b and the impurity diffusion regions 97a and 97b at the edges of the source region 93 and the channel region 95, and the largest in this order is the channel region 95, the impurity diffusion region 97c and the body contact region 96c. It has become. Further, the impurity concentrations of the edge body contact regions 96a and 96b and the central body contact region 96c are the same, and the impurity concentrations of the edge impurity diffusion regions 97a and 97b and the central impurity diffusion region 97c are the same.

【0078】

The FET of the present embodiment has a body contact region 96c for extracting excess carriers and an impurity diffusion region not only along the edges of the source region 93 and the channel region 95 but also in the central portion of the source region 93 and the channel region 95. It formed 97c. According to this configuration, it becomes easy to pull out the surplus carriers even in a transistor having a large gate width. Further, the occupied area can be reduced as compared with arranging the transistors having a small gate width in parallel, and the configuration is advantageous in terms of layout.

【0079】

[Electronic Equipment] Hereinafter, the configuration of a projection type liquid crystal display device will be described with reference to FIG. 15 as an example of an electronic equipment using the above liquid crystal light bulb. FIG. 15 is a diagram showing a schematic configuration of an optical system of a projection type display device 1100 in which three liquid crystal light bulbs described above are prepared and used as liquid crystal devices 962R, 962G and 962B for RGB, respectively.

【0080】

A light source device 920 and a uniform illumination optical system 923 are adopted as the optical system of the projection type display device 1100 of this example. The projection type display device 1100 includes a color separation optical system 924 that separates the luminous flux W emitted from the uniform illumination optical system 923 into red (R), green (G), and blue (B), and each color luminous flux R. Light valves 925R, 925G, 925B that modulate G and B, a color synthesis prism 910 that resynthesizes the modulated color luminous flux, and a projection means that magnifies and projects the synthesized luminous flux onto the surface of the projection surface 100. It is equipped with a projection lens unit 906. It also has a light guide system 927 that guides the blue luminous flux B to the corresponding light bulb 925B.

【0081】

The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931, and the two lens plates 921 and 922 are arranged so as to be orthogonal to each other with the reflection mirror 931 interposed therebetween. The two lens plates 921 and 922 of the uniform illumination optical system 923 include a plurality of rectangular lenses arranged in a matrix. The luminous flux emitted from the light source device 920 is divided into a plurality of partial luminous fluxes by the rectangular lens of the first lens plate 921. Then, these partial luminous fluxes are superimposed near the three light bulbs 925R, 925G, and 925B by the rectangular lens of the second lens plate 922. Therefore, by using the uniform illumination optical system 923, even if the light source device 920 has a non-uniform illuminance distribution within the cross section of the emitted luminous flux, the three light valves 925R, 925G, and 925B can be uniformly illuminated. It becomes possible to illuminate.

【0082】

Each color separation optical system 924 is composed of a blue-green reflective dichroic mirror 941, a green reflective dichroic mirror 942, and a reflective mirror 943. First, in the blue-green reflection dichroic mirror 941, the blue light beam B and the green light beam G contained in the light beam W are reflected at a right angle and head toward the green reflection dichroic mirror 942. On the other hand, the red light flux R passes through the blue-green reflection dichroic mirror 941 and is reflected at a right angle by the rear reflection mirror 943, and is emitted from the emission portion 944 of the red light flux R to the color synthesis optical system side.

【0083】

Next, of the blue light beam B and the green light beam G reflected by the blue-green reflection dichroic mirror 941, only the green light beam G is reflected at a right angle by the green reflection dichroic mirror 942 and is colored from the exit portion 945 of the green light beam G. It is emitted to the side of the synthetic optical system. Further, the blue light flux B that has passed through the green reflection dichroic mirror 942 is emitted from the exit portion 946 of the blue light flux B toward the light guide system 927. In this example, the distances from the emission portion of the luminous flux W of the uniform illumination optical element to the emission portions 944, 945, and 946 of each color light flux in the color separation optical system 924 are set to be substantially equal to each other.

【0084】

Condensing lenses 951 and 952 are arranged on the emission side of the emission unit 944 of the red luminous flux R by the color separation optical system 924 and the emission side of the emission unit 945 of the green luminous flux G, respectively. Therefore, the red luminous flux R and the green luminous flux G emitted from each emitting portion are incident on and parallelized with these condenser lenses 951 and 952, respectively.

【0085】

The red light flux R and green light flux G parallelized in this way are modulated by incident on the light bulbs 925R and 925G, and image information corresponding to each color light is added. That is, these liquid crystal devices are switched and controlled according to the image information by a driving means (not shown), whereby each color light passing therethrough is modulated.

【0086】

On the other hand, the blue luminous flux B is guided to the corresponding light bulb 925B via the light guide system 927, and is similarly modulated according to the image information here. The light bulbs 925R, 925G, and 925B of this example are further polarized light means 960R, 960G, and 960B on the incident side, polarization means 961R, 961G, and 961B on the outgoing side, and liquid crystal devices 962R, 962G arranged between them. , 962B.

【0087】

By the way, the light guide system 927 is arranged between the condenser lens 954, the incident side reflection mirror 971 and the exit side reflection mirror 972, which are arranged on the emission side of the emission portion 946 of the blue light beam B, and these reflection mirrors. It is composed of an intermediate lens 973 and a condenser lens 953 placed in front of the light valve 925B. The blue luminous flux B emitted from the emitting unit 946 is guided to the liquid crystal device 962B via the light guide system 927 and modulated. As for the optical path length of each color luminous flux, that is, the distance from the emission portion of the luminous flux W to each liquid crystal device 962R, 962G, 962B, the blue luminous flux B is the longest, and therefore the light amount loss of the blue luminous flux is the largest. However, the light loss can be suppressed by interposing the light guide system 927.

【0088】

Each color luminous flux R, G, B modulated through the light bulbs 925R, 925G, 925B is incident on the color synthesis prism 910 and synthesized here. Then, the light synthesized by the color synthesis prism 910 is magnified and projected onto the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.

【0089】

According to this configuration, it is possible to realize a projection type liquid crystal display device having high display quality.

【0090】

The technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the specific description of the shape, size, film thickness, impurity concentration, etc. of each planar pattern of the FET shown in the above embodiment is only an example, and can be changed as appropriate. Further, in the above embodiment, an example of a liquid crystal light bulb is shown as an example of an electro-optical device, but the FET of the present invention is applied not only to a liquid crystal device but also to various electro-optical devices such as an electroluminescence device and a plasma display device. It is possible to do. Further, the present invention may be applied not only to an electro-optical device but also to a semiconductor device in which a large number of FETs are integrated. As a result, it is possible to realize a semiconductor device having excellent electrical characteristics in terms of current-voltage characteristics, withstand voltage, and the like.

【0091】

[Effect of the invention]

As described in detail above, according to the present invention, in a MOSFET having an SOI structure having a body contact region, a substrate floating effect such as a parasitic bipolar phenomenon can be more reliably suppressed, and excellent electrical characteristics are obtained. FET can be provided. Further, by using such a FET, it is possible to provide an electro-optical device or a semiconductor device capable of reducing the size and simplification of a circuit and improving the driving ability.

[Simple explanation of drawings]

[Figure 1]

It is a top view which shows the schematic structure of the liquid crystal light bulb which is the electro-optical device of 1st Embodiment of this invention.

[Figure 2]

It is a cross-sectional view taken along the line HH'of FIG. 1 showing the schematic configuration of the liquid crystal light bulb.

[Fig. 3]

The same is a circuit diagram showing a configuration example of a scanning line drive circuit in a liquid crystal light bulb.

[Fig. 4]

It is a pattern layout diagram which shows the part of the transmission gate of the scanning line drive circuit.

[Fig. 5]

It is a top view which shows the structure of the FET of this embodiment which constitutes the transmission gate.

[Fig. 6]

It is a cross-sectional view taken along the line AA'in FIG. 5 showing the configuration of the FET.

[Fig. 7]

In the same cross-sectional view, it is a figure which shows the state of the expansion of the depletion layer.

[Fig. 8]

It is a top view which shows the structure of the FET of the 2nd Embodiment of this invention.

[Fig. 9]

It is a top view which shows the structure of the FET of the 3rd Embodiment of this invention.

[Fig. 10]

It is a top view which shows the structure of the FET of the 4th Embodiment of this invention.

[Fig. 11]

It is a plan view which shows the modification of the FET.

[Fig. 12]

It is sectional drawing which shows the structure of the FET of the 5th Embodiment of this invention.

[Fig. 13]

It is a top view which shows the structure of the FET of the 6th Embodiment of this invention.

[Fig. 14]

It is a top view which shows the structure of the FET of the 7th Embodiment of this invention.

[Fig. 15]

It is a schematic block diagram which shows the projection type liquid crystal display device (electronic device) of one Embodiment of this invention.

[Fig. 16]

It is a figure which shows the relationship between the gate width and the drain voltage which a parasitic bipolar phenomenon occurs.

[Fig. 17]

It is a top view which shows the structure of the conventional FET which has a body contact area.

[Fig. 18]

It is a cross-sectional view taken along the line AA'in FIG. 17 showing the configuration of the FET.

[Fig. 19]

In the same cross-sectional view, it is a figure which shows the state of the expansion of the depletion layer.

[Fig. 20]

It is a top view which shows the structure of the capacitance part connected with the FET which constitutes the transmission gate of the 1st Embodiment of this invention.

[Explanation of symbols]

10 Liquid crystal light bulb (electro-optical device) 50,72,74,77,77', 87,90 FET (Field Effect Transistor) 51 Support board 52 Embedded Silicon Oxide Film (Insulation Layer) 53,78,91 Single crystal silicon layer (semiconductor layer) 53a Extension 54,79,93 Source area 55,80,94 drain area 56,81,95 channel area 57 Gate insulating film 58,82,92 Gate electrode 60,83a,83b,96a,96b Body contact area 61,84a, 84b, 97a, 97b Impurity diffusion region 62,70,85a,85b Drawer area 63,71 Edge impurity diffusion region 65 Depletion 75 offset part 88 First impurity diffusion layer 89 Second impurity diffusion layer 98 contacts 99 Conductive layer