Semiconductor device and its manufacturing method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor device and a technique for manufacturing the same, and more particularly to a technique effective when applied to a semiconductor device having a power MISFET (Metal Insulator Semiconductor Feild Effect Transistor) having a trench gate structure.

【0002】

[Conventional technology]

As a semiconductor device used for a switching element such as a power amplifier circuit or a power supply circuit, for example, a semiconductor device having a power transistor (high voltage element) called a power MISFET is known. The power MISFET has a multi-cell structure in which a plurality of MISFETs having a fine pattern are connected in parallel in order to obtain a large amount of power.

【0003】

In the power MISFET, what is called a vertical type or a horizontal type is known, and in a vertical type, what is called a trench gate structure is also known. Here, the MISFET is an insulated gate type field effect transistor in which an insulating film is interposed between the channel forming region (semiconductor) and the gate electrode, and a gate insulating film made of a silicon oxide film is generally used. MOSFET (Metal Oxide Semiconductor Field Effect Transistor) )It is called. Further, the one in which the current flows in the thickness direction (depth direction) of the semiconductor substrate is called the vertical type, and the one in which the current flows in the surface direction of the semiconductor substrate is called the horizontal type. In addition, an electron channel (conductive path) is formed in the channel forming region between the source region and the drain region (under the gate electrode), and an n-type (or n-channel conductive type) is formed, and a hole channel is formed. It is called p-type (p-channel conductive type). The trench gate structure is a gate structure in which a gate electrode is provided inside a groove provided on the main surface of the semiconductor substrate with an insulating film interposed therebetween. A power MISFET having a trench gate structure is described in, for example, Japanese Patent Application Laid-Open No. 7-249770.

【0004】

[Problems to be Solved by the Invention]

In power MISFETs with a trench gate structure, cell miniaturization is progressing with each generation. With the miniaturization of cells, the width of the groove (trench width) in which the gate electrode is formed is also reduced. Reducing the width of the groove has the following two advantages. FIG. 23 (a) is a schematic cross-sectional view of a power MISFET having a conventional trench gate structure, and FIG. 23 (b) is a schematic cross-sectional view when the width of the groove of FIG. 23 (a) is reduced. In FIG. 23, 30 is a semiconductor substrate, 30a is an n + type semiconductor layer, 30b is an n-type semiconductor layer, 32 is a p-type semiconductor region, 33 is a groove, 33W is a groove width, 34 is a silicon oxide film, and 35 is a gate. Electrodes, 36 is an n + type semiconductor region, 37 is a p + type semiconductor region, 38 is an insulating film, 39 is a source electrode layer, 40 is a drain electrode layer, Ce is a cell, and CeP is a cell pitch. The fine pattern MISFET mainly has a channel forming region, a gate insulating film, a gate electrode 35, a source region, and a drain region. The channel formation region is formed by the p-type semiconductor region 32, the gate insulating film is formed by the silicon oxide film 34, the gate electrode 35 is formed by the polysilicon (single crystal silicon) film, and the source region is the n + type semiconductor region 36. The drain region is formed by an n + type semiconductor layer 30a and an n-type semiconductor layer 30b.

【0005】

The first merit is that the conduction loss can be reduced. As shown in FIG. 23, when the width 33W of the groove 33 is reduced, the cell pitch CeP can be reduced and the number of cells Ce can be increased, so that the gate width per unit area can be increased. By increasing the gate width per unit area, the on-resistance (Ron) can be reduced, so that the conduction loss of the power MISFET can be reduced.

【0006】

The second advantage is that switching loss can be reduced. By reducing the width 33W of the groove 33, it is possible to reduce the facing area where the bottom surface of the gate electrode 35 and the n-type semiconductor layer 30b, which is the drain region, face each other, and directly reduce the parasitic capacitance (Cgd) between the gate and drain. Therefore, the switching loss of the power MISFET can be reduced.

【0007】

However, as a side effect, the gate resistance (Rg) increases. As shown in FIG. 23, since the gate electrode 35 is formed inside the groove 33, if the width 33W of the groove 33 is reduced, the cross-sectional area of the gate electrode 35 is reduced and the gate resistance is increased. In particular, if the cell layout is striped in an attempt to reduce the parasitic capacitance between the gate and drain, the gate resistance will increase significantly. This increase in gate resistance becomes a factor that increases the switching loss. Therefore, the present inventor focused on the structure of the gate electrode 35 and made the present invention.

【0008】

An object of the present invention is to provide a technique capable of suppressing an increase in gate resistance due to a reduction in the width of a groove in a semiconductor device having a trench gate structure.

【0009】

Another object of the present invention is to provide a technique capable of reducing conduction loss and switching loss in a semiconductor device having a trench gate structure.

【0010】

Another object of the present invention is to provide a technique capable of obtaining stable and reproducible transistor characteristics in a semiconductor device having a trench gate structure.

【0011】

The above and other objects and novel features of the present invention will become apparent in the description and accompanying drawings herein.

【0012】

[Means for solving problems]

A brief description of typical inventions disclosed in the present application is as follows. (1) Within the first semiconductor region on the main surface of the semiconductor substrate, the second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region, and the second semiconductor region. A groove formed in a third semiconductor region having the same conductivity as the first semiconductor region and in the first, second and third semiconductor regions and extending in the first direction of the main surface of the semiconductor substrate. A second semiconductor device having an insulating film formed inside and outside the groove and a conductor formed on the insulating film inside and outside the groove, which is perpendicular to the first direction. In the plane including the direction, the width of the conductor formed outside the groove in the second direction is larger than the width of the conductor formed in the groove in the second direction, and the conductivity formed outside the groove. The thickness of the body is larger than the width of the conductor formed in the groove in the second direction.

【0013】

(2) In the semiconductor device according to the means (1), the semiconductor substrate has the conductor as a gate electrode, the first semiconductor region as a drain, and the second semiconductor region as a channel forming region. A MISFET having a third semiconductor region as a source region is formed. A semiconductor device characterized by this.

【0014】

(3) Within the first semiconductor region on the main surface of the semiconductor substrate, the second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region, and the second semiconductor region. A groove formed in a third semiconductor region having the same conductivity as the first semiconductor region and in the first, second and third semiconductor regions and extending in the first direction of the main surface of the semiconductor substrate. A second semiconductor device having an insulating film formed inside and outside the groove and a conductor formed on the insulating film inside and outside the groove, which is perpendicular to the first direction. In the plane including the direction, the width of the conductor formed outside the groove in the second direction is larger than the width of the conductor formed in the groove in the second direction, and the third semiconductor region is the said. The conductor formed outside the groove is formed vertically below and outside the vertically below, and is in contact with the groove.

【0015】

(4) In the semiconductor device according to the means (3), the third semiconductor region includes a first portion located vertically below the conductor formed outside the groove and conductivity formed outside the groove. It has a second portion located outside the vertical lower part of the body, and the peak concentration of the first portion of the third semiconductor region is lower than the peak concentration of the second portion of the third semiconductor region, and the second portion The impurity concentration is set higher than the peak concentration in the semiconductor region.

【0016】

(5) In the semiconductor device according to the means (3), the semiconductor substrate has the conductor as a gate electrode, the first semiconductor region as a drain, and the second semiconductor region as a channel forming region. A MISFET having a third semiconductor region as a source region is formed.

【0017】

(6) In the semiconductor device according to the means (3), the semiconductor substrate has the first semiconductor region as a drain region on one side surface side of two side surfaces in the second direction of the groove. A first MISFET having the second semiconductor region as a channel forming region, the third semiconductor region as a source region, and the conductor as a gate electrode is formed, and the other of the two sides of the groove in the second direction. On the side surface side of the above, a second MISFET having the first semiconductor region as a drain region, the second semiconductor region as a channel forming region, the third semiconductor region as a source region, and the conductor as a gate electrode is formed. There is.

【0018】

(7) In the semiconductor device according to the means (6), on the two side surface sides of the groove, the third semiconductor region is a first portion located vertically below the conductor formed outside the groove. The first portion of the third semiconductor region has a second portion located outside the vertical lower portion of the conductor formed outside the groove, and the peak concentration of the first portion is the peak of the second portion of the third semiconductor region. The impurity concentration is set to be lower than the concentration and higher than the peak concentration in the second semiconductor region.

【0019】

(8) A first semiconductor region on the main surface of the semiconductor substrate, a second semiconductor region formed in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region, and the first and second semiconductors. A groove formed in the region and extending in the first direction of the main surface of the semiconductor substrate and a position in the second semiconductor region in contact with the groove, which is the same conductive type as the first semiconductor region. The third semiconductor region of the above, the insulating film formed in the groove and the outside of the groove, and the conductor formed on the insulating film in the groove and outside the groove, and is perpendicular to the first direction. In the plane including the two directions, the width of the conductor formed outside the groove in the second direction is larger than the width of the conductor formed in the groove in the second direction, and the third semiconductor region is: It is composed of a first portion near the groove and a second portion far from the groove, and the first portion of the third semiconductor region has a lower peak value of impurity concentration than the second portion of the third semiconductor region, and the second semiconductor region This is a method for manufacturing a semiconductor device having a higher peak value of impurity concentration than that, and the first portion of the third semiconductor region is formed before the groove is formed.

【0020】

(9) In the method for manufacturing a semiconductor device according to the means (8), the second portion of the third semiconductor region is formed after the conductor is formed.

【0021】

(10) In the method for manufacturing a semiconductor device according to the means (8), the conductor is a gate electrode, the first semiconductor region is a drain region, and the second semiconductor region is a channel forming region. The third semiconductor region is a source region.

【0022】

(11) A first semiconductor region on the main surface of the semiconductor substrate, a second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region, and the first and second semiconductors. A groove formed in the region and extending in the first direction of the main surface of the semiconductor substrate, and a groove formed in the first and second semiconductor regions in contact with the groove to form the first semiconductor region. A semiconductor device having the same conductive type third semiconductor region, an insulating film formed inside and outside the groove, and a conductor formed on the insulating film inside and outside the groove. In the plane including the second direction perpendicular to the first direction, the width of the conductor formed outside the groove in the second direction is larger than the width of the conductor formed in the groove in the second direction. The third semiconductor region is further composed of a first portion near the groove and a second portion far from the groove, and an impurity concentration peak in the first portion of the third semiconductor region is an impurity in the second portion of the third semiconductor region. It is lower than the concentration peak.

【0023】

(12) In the semiconductor device according to the means (11), the first portion of the third semiconductor region is formed vertically below the conductor formed outside the groove.

【0024】

(13) In the semiconductor device according to the means (11), the second portion of the third semiconductor region is formed outside the vertical lower side of the conductor formed outside the groove.

【0025】

(14) In the semiconductor device according to the means (11), the semiconductor substrate has the conductor as a gate electrode, the first semiconductor region as a drain region, and the second semiconductor region as a channel formation region. A MISFET having the third semiconductor region as a source region is formed.

【0026】

(15) A method for manufacturing a semiconductor device, which comprises the following steps: (A) A step of forming a first semiconductor region on the main surface of a semiconductor substrate, and (b) a step of forming a second semiconductor region having a conductive type opposite to that of the first semiconductor region in the first semiconductor region. , (C) A step of forming a groove extending in the first direction of the main surface of the semiconductor substrate in the first and second semiconductor regions, and (d) forming a conductor in and out of the groove. And (e) after the step (d), the region in contact with the second semiconductor region has the same conductive type as the second semiconductor region, and the impurity concentration is higher than the impurity concentration in the second semiconductor region. The process of forming the third semiconductor region with.

【0027】

(16) In the method for manufacturing a semiconductor device according to the means (15), the width of the conductor formed outside the groove in the plane including the second direction perpendicular to the first direction is the width in the second direction. , Larger than the width of the conductor formed in the groove in the second direction.

【0028】

(17) A method for manufacturing a semiconductor device, which comprises the following steps: (A) A step of forming a first semiconductor region on the main surface of a semiconductor substrate, and (b) a step of driving a first impurity having a conductive type opposite to that of the first semiconductor region into the first semiconductor region. c) A step of forming a groove extending in the first direction of the main surface of the semiconductor substrate in the first semiconductor region, and (d) a step of forming a conductor in and out of the groove, ( e) After the step (d), a step of driving a second impurity having the same conductive type as the first impurity into the semiconductor substrate and having a larger dose than the first impurity.

【0029】

(18) In the method for manufacturing a semiconductor device according to the means (17), the width of the conductor formed outside the groove in the plane including the second direction perpendicular to the first direction is the width in the second direction. , Larger than the width of the conductor formed in the groove in the second direction.

【0030】

(19) The method for manufacturing a semiconductor device according to the means (17) includes, after the step (b), (f) a step of heat-treating the semiconductor substrate.

【0031】

(20) In the method for manufacturing a semiconductor device according to the means (19), the heat treatment temperature in the step (f) is 900 ° C. or higher.

【0032】

(21) The method for manufacturing a semiconductor device according to the means (17) further includes a step of forming an insulating film in the groove between the steps (c) and (d).

【0033】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiment of the invention, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

【0034】

(Embodiment 1) In the present embodiment, an example in which the present invention is applied to a semiconductor device having a power MISFET will be described.

【0035】

FIG. 1 is a plan layout view showing a schematic configuration of a semiconductor device according to the first embodiment of the present invention, FIG. 2 is a schematic plan view showing a gate electrode pattern of the semiconductor device of FIG. 1, and FIG. 3 is a schematic plan view. , FIG. 2 is an enlarged schematic plan view of a portion of region A shown in FIG. 2, FIG. 4 is a schematic cross-sectional view taken along the line AA of FIG. 3, and FIG. 5 is an enlarged schematic view of a part of FIG. FIG. 6 is a schematic cross-sectional view in which a part of FIG. 4 is enlarged. In FIG. 7, (a) is an impurity concentration distribution diagram along the line B-B'of FIG. 6, (b). ) Is an impurity concentration distribution diagram along the C-C'line in FIG.

【0036】

As shown in FIG. 1, the semiconductor device of the present embodiment is mainly composed of a semiconductor chip 20 having a rectangular plane. A source electrode layer 17 and a gate electrode layer 18 are arranged on the main surface (circuit forming surface) of the semiconductor chip 20. The source electrode layer 17 and the gate electrode layer 18 are used as external terminals (bonding pads), and connecting means such as a bonding wire that mediates electrical conduction with the outside is connected. A drain electrode layer is arranged on the back surface of the semiconductor chip 20 opposite to the main surface.

【0037】

The power MISFET is mounted on the semiconductor device. The power MISFET has a multi-cell structure in which a plurality of MISFETs having a fine pattern are connected in parallel in order to obtain a large amount of power. As shown in FIGS. 2 and 3, the power MISFET of the present embodiment is along the first direction in a plane including the first direction of the main surface of the semiconductor chip 20 and the second direction perpendicular to the first direction. It has a striped cell layout in which a plurality of extending cells Ce are arranged along the second direction.

【0038】

As shown in FIG. 4, the semiconductor chip 20 is mainly composed of a semiconductor substrate (semiconductor substrate) 1. As the semiconductor substrate 1, for example, a semiconductor substrate in which an n-type semiconductor layer 1b made of single crystal silicon is provided on the main surface of an n + type semiconductor layer 1a made of single crystal silicon is used. The n-type semiconductor layer 1b is set to have a lower impurity concentration than the n + type semiconductor layer 1a. The n-type semiconductor layer 1a is, for example, 1.0E 16cm.^-3The impurity concentration is set to about 2, and the n + type semiconductor layer 1a is, for example, 2.0E 19cm.^-3It is set to a certain degree of impurity concentration.

【0039】

A plurality of fine MISFETs are formed on the semiconductor substrate 1. Each MISFET mainly has a channel forming region, a gate insulating film, a gate electrode 9, a source region, and a drain region. The channel formation region is formed by, for example, a p-type semiconductor region (well region) 3 provided in the n-type semiconductor layer 1b. The gate insulating film is formed of, for example, a silicon oxide film 7 which is an insulating film. The source region is formed by an n-type semiconductor region 4 provided in the p-type semiconductor region 3 and an n + -type semiconductor region 11 provided in the p-type semiconductor region 3 in contact with the n-type semiconductor region 4. .. The drain region is formed of an n-type semiconductor layer 1b and an n + type semiconductor layer 1a.

【0040】

A groove 6 recessed in the depth direction is formed on the main surface of the semiconductor substrate 1. The groove 6 extends along the first direction of the main surface of the semiconductor substrate 1 and is provided for each cell Ce. A drain electrode layer 19 is provided on the back surface (the other main surface) opposite to the main surface of the semiconductor substrate 1 in contact with the n + type semiconductor layer 1a. The drain electrode layer 19 is formed of, for example, a metal film whose main material is gold (Au).

【0041】

The silicon oxide film 7 is formed over the inside and outside of the groove 6, and the gate electrode 9 is composed of a conductor formed on the silicon oxide film 7. In the present embodiment, the gate electrode 9 is connected to the first portion (embedded portion) 9a embedded in the groove 6 with the silicon oxide film 7 interposed therebetween and protrudes from the groove 6. It has a configuration with two parts (protruding parts) 9b. The first portion 9a and the second portion 9b are formed along the extending direction of the groove 6. That is, the power MISFET has a trench gate structure.

【0042】

The gate electrode 9 is mainly composed of, for example, a polysilicon (polycrystalline silicon) film 8a into which impurities that reduce the resistance value have been introduced, and a tungsten silicide (WSi) film 8b having a higher conductivity than the polysilicon film 8a. It is configured to have. In the present embodiment, the first portion 9a of the gate electrode 9 is formed of a polysilicon film 8a, and the second portion 9b is composed of a polysilicon film 8a and a WSi film 8b provided on the polysilicon film 8a. ..

【0043】

Each MISFET has a source region consisting of an n-type semiconductor region 4 and an n + -type semiconductor region 11, a channel formation region consisting of a p-type semiconductor region 3, and an n-type semiconductor layer in the depth direction from the main surface of the semiconductor substrate 1. The drain region consisting of 1b and the n + type semiconductor layer 1a is sequentially arranged. That is, each MISFET is configured as a vertical type in which a current flows in the thickness direction of the semiconductor substrate 1, and further, an electron channel (conductive passage) is formed in a channel forming region between the source region and the drain region (under the gate electrode). It is composed of an n-channel conductive type that can be used.

【0044】

The main surface (upper surface) of the second portion 9b of the gate electrode 9 is covered with an insulating film 10 formed in the same pattern as the second portion 9b, and the two side surfaces of the second portion 9b in the second direction are It is covered with a sidewall spacer 13 formed by self-alignment with respect to this second portion 9b. The insulating film 10 and the sidewall spacer 13 are formed of an insulating film such as a silicon oxide film.

【0045】

A groove 14 recessed in the depth direction is formed on the main surface of the semiconductor substrate 1. The groove 14 extends along the first direction and is provided between the respective gate electrodes 9. A p + type semiconductor region 15 is provided below the groove 14, and the p + type semiconductor region 15 is formed in the p-type semiconductor region 3.

【0046】

A barrier metal film 16 is formed on the main surface of the semiconductor substrate 1 so as to cover the second portion 9b of the gate electrode 9, and a source electrode layer 17 is formed on the barrier metal film 16. The source electrode layer 17 is electrically connected to the n + type semiconductor region 11 and the p + type semiconductor region 15 via the barrier metal film 16. The second portion 9b of the gate electrode 9 is electrically separated from the barrier metal film 16 and the source electrode layer 17 by the insulating film 10 and the sidewall spacer 13.

【0047】

The gate electrode 9 of each MISFET is formed integrally with the gate lead-out wiring extending so as to surround the cell array portion in which a plurality of cells Ce are arranged, and the gate lead-out wiring is electrically connected to the gate electrode layer 18. ing. The gate electrode layer 18 is formed in the same layer as the source electrode layer 17, and is formed of, for example, aluminum or a metal film made of an alloy mainly composed of aluminum.

【0048】

As shown in FIGS. 4 and 5, the gate electrode 9 is formed in a first portion 9a embedded in a groove 6 formed in the semiconductor substrate 1 with a silicon oxide film 7 interposed therebetween, and in the first portion 9a. It is configured to have a second portion (protruding portion) 9b that is connected and protrudes from the groove 6. With such a configuration, the width W1 in the second direction of the first portion 9a is reduced by reducing the width 6W in the second direction of the groove 6, but the width W2 in the second direction of the second portion 9b is reduced. Since the width 6W of the groove 6 in the second direction is not reduced even if the width is reduced, it is possible to suppress an increase in the gate resistance (Rg) due to the reduction of the width 6W of the groove 6.

【0049】

In the plane including the second direction perpendicular to the first direction of the main surface of the semiconductor substrate 1, the width W2 of the second portion 9b of the gate electrode 9 in the second direction is the width W1 of the first portion 9a in the second direction. Is bigger than. With such a configuration, the resistance in the second portion 9b can be reduced, so that the increase in the gate resistance (Rg) due to the reduction of the width 6W of the groove 6 can be further suppressed. A silicon oxide film 7 is interposed between the overhanging portion of the second portion 9b of the gate electrode 9 and the main surface of the semiconductor substrate 1, and the silicon oxide film 7 separates the two from each other. ing.

【0050】

The thickness t of the second portion 9b of the gate electrode 9 is thicker than the width W1 of the first portion 9a. With this configuration, the resistance in the second portion 9b can be reduced, so that the increase in gate resistance (Rg) due to the reduction in the width 6W of the groove 6 can be further suppressed.

【0051】

The first portion 9a of the gate electrode 9 is formed of a polysilicon film 8a, and the second portion 9b is composed of a polysilicon film 8a and a WSi film 8b provided on the polysilicon film 8a. With such a configuration, the resistance in the second portion 9b can be reduced, so that the increase in the gate resistance (Rg) due to the reduction of the width 6W of the groove 6 can be further suppressed.

【0052】

Two MISFETs are formed in one cell Ce. These two MISFETs share a gate electrode 9. One MISFET has a channel formed on one side of two sides opposite to each other in the first direction of the first part 9a of the gate electrode 9, and the other MISFET has the first part of the gate electrode 9. A channel is formed on the other side of the two sides opposite to each other in the first direction of 9a.

【0053】

The source region is composed of an n-type semiconductor region 4 near the groove 6 and an n + -type semiconductor region 11 far from the groove 6. The n-type semiconductor region 4 is formed in contact with the groove 6 vertically below the second portion 9b of the gate electrode 9, and the n + type semiconductor region 11 is formed outside vertically below the second portion 9b of the gate electrode 9. It is formed in contact with region 4. That is, the source region is an n-type semiconductor region 4 formed in contact with the groove 6 vertically below the second portion 9b of the gate electrode 9, and an n-type semiconductor region outside the vertically downward portion of the second portion 9b of the gate electrode 9. It has a configuration having an n + type semiconductor region 11 formed in contact with 4.

【0054】

Here, when there is no n-type semiconductor region 4, that is, when the source region is arranged apart from the groove 6, the gate electrode is misaligned due to the misalignment of the mask when the gate electrode 9 is formed with reference to the groove 6. The channel length of the MISFET having a channel forming region on one side surface side of the first portion 9a of 9 was different from the channel length of the MISFET having a channel forming region on the other side surface side of the second portion 9a of the gate electrode 9. Due to the structure, the characteristics such as the on-resistance (Ron) and threshold voltage (Vth) of the power MISFET will vary. To deal with this, it is necessary to form the source region deeply, but in this case, the channel forming region and the groove 6 must also be formed deeply. Since it is extremely difficult to form a narrow and deep groove 6 in the processing process, it is difficult to proceed with miniaturization. Further, if the source region, the channel formation region, and the groove 6 are deep, the parasitic capacitance increases, so that the switching loss increases.

【0055】

On the other hand, in the present embodiment, the structure is such that the n-type semiconductor region 4 is provided in contact with the groove 6 vertically below the second portion 9b of the gate electrode 9, that is, the groove 6 is in contact with the source region. Therefore, even if the mask is misaligned when the gate electrode 9 is formed with reference to the groove 6, the channel length on one side surface side of the first portion 9a of the gate electrode 9 and the first gate electrode 9 Since the channel length on the other side surface side of the portion 9a is constant, variations in the on-resistance, threshold voltage, and the like can be suppressed. As a result, stable and reproducible transistor characteristics can be obtained.

【0056】

Further, since it is not necessary to form a deep source region, the channel formation region and the groove 6 can be made shallow, which facilitates miniaturization. Moreover, since it is not necessary to form a deep source region, an increase in parasitic capacitance can be suppressed. As a result, an increase in switching loss can be suppressed.

【0057】

As shown in FIG. 7, the n + type semiconductor region 11 has, for example, a peak concentration of 1E20 to 5E20 cm.^-3The impurity concentration is set to about 1, and the n-type semiconductor region 4 has, for example, a peak concentration of 1E18 to 1E20 cm.^-3The peak concentration of the p-type semiconductor region 3 is set to about 1E16 to 1E18 cm, for example.^-3It is set to a certain degree of impurity concentration. That is, the n-type semiconductor region 4 is set to have a lower impurity concentration than the n + -type semiconductor region 11 and a higher impurity concentration than the p-type semiconductor region 3. The reason for making such a concentration relationship is shown below.

【0058】

The n + type semiconductor region 11 is 1E20 to 5E20 cm for ohmic contact with the source electrode layer 17.^-3It is necessary to make the concentration as high as possible. If the concentration of the n-type semiconductor region 4 is increased to the same level as that of the n + -type semiconductor region 11, the n-type semiconductor region 4 becomes too deep and the channel length becomes extremely short. If this happens, punch-through is likely to occur, and sufficient pressure resistance cannot be obtained.

【0059】

When the concentration of the n-type semiconductor region 4 is increased to the same level as that of the n + -type semiconductor region 11, the reason why the n-type semiconductor region 4 becomes deep is that the heat treatment received after formation is different. Since the n + type semiconductor region 11 is formed after the gate electrode is processed, the heat treatment required for activation, for example, 900 ° C. for about 20 minutes, is sufficient, but the n-type semiconductor region 4 forms the groove 6 and the gate electrode. Since it is necessary to already form the semiconductor in the step before the process, the number of heat treatment steps such as the gate oxidation step increases, and the n-type semiconductor region 4 becomes deep.

【0060】

As described above, by setting the n-type semiconductor region 4 to an impurity concentration lower than that of the n + type semiconductor region 11 and higher than that of the p-type semiconductor region 3, the n-type semiconductor region 4 can be formed shallowly. Sufficient withstand voltage can be obtained.

【0061】

Next, the manufacture of the semiconductor device will be described with reference to FIGS. 8 to 18. 8 to 18 are schematic cross-sectional views during the manufacturing process of the semiconductor device.

【0062】

First, the semiconductor substrate 1 shown in FIG. 8 is prepared, and then the insulating film 2 is formed on the main surface of the semiconductor substrate 1.

【0063】

Next, as shown in FIG. 9, the p-type semiconductor region 3 is formed on the main surface of the semiconductor substrate 1. The p-type semiconductor region 3 is formed by introducing an impurity (for example, boron) into the main surface of the semiconductor substrate 1 by an ion implantation method and then subjecting it to a heat treatment for activating it.

【0064】

Next, as shown in FIG. 10, an n-type semiconductor region 4 is formed on the main surface of the p-type semiconductor region 3. The n-type semiconductor region 4 is formed by introducing an impurity (for example, arsenic) into the main surface of the p-type semiconductor region 3 by an ion implantation method, and then subjecting it to an activating heat treatment. For the introduction of impurities, for example, the dose amount is 1E14 ~ 5E14cm.^-2It is performed under the condition that the amount of energy is about 80 Kev. The heat treatment for activating impurities is performed under the conditions of 900 ° C. or higher.

【0065】

Next, the insulating film 2 is removed, and then, as shown in FIG. 11, a mask 5 made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate 1. The mask 5 is formed by a pattern having an opening in the groove forming region on the main surface of the semiconductor substrate 1.

【0066】

Next, the mask 5 is used as an etching mask, and the semiconductor substrate 1 is etched to form the groove 6.

【0067】

Next, after removing the mask 5, thermal oxidation treatment is performed to form a silicon oxide film 7 on the inner wall of the groove 6 and the main surface (inside and outside of the groove 6) of the semiconductor substrate 1 as shown in FIG. The silicon oxide film 7 is used as a gate insulating film. The thermal oxidation treatment is performed by, for example, a wet oxidation method at about 850 ° C. In this step, the n-type semiconductor region 4 is subjected to high-temperature heat treatment when forming the silicon oxide film 7, but the n-type semiconductor region 4 has a peak concentration of 1E18 to 1E20 cm.^-3Since it is set to a degree, it is possible to suppress the diffusion in which the n-type semiconductor region 4 extends in the depth direction.

【0068】

When a silicon oxide film is formed on the inner wall of the groove 6 and the main surface of the semiconductor substrate 1 by thermal oxidation treatment, the upper edge portion of the groove 6 (the corner portion sandwiched between the side surface of the groove and the main surface of the substrate) is formed. Since the film thickness of the silicon oxide film is thinner than that of other portions, it causes a decrease in gate withstand voltage. This decrease in film thickness can be suppressed by forming a silicon oxide film by a dry oxidation method of 1100 ° C. or higher. When the silicon oxide film 7 is formed by this dry oxidation method, the n-type semiconductor region 4 is further subjected to a high temperature heat treatment. Therefore, the n-type semiconductor region 4 needs to be set to an impurity concentration with as little diffusion as possible according to the temperature conditions when the silicon oxide film 7 is formed.

【0069】

Next, as shown in FIG. 13, a polysilicon film 8a is formed on the main surface of the semiconductor substrate 1 by, for example, a CVD method so as to embed the groove 6, and then a WSi film 8b is formed on the polysilicon film 8a, for example, CVD. It is formed by the method, and then an insulating film 10 made of, for example, a silicon oxide film is formed on the WSi film 8b by the CVD method.

【0070】

Next, the insulating film 10, the WSi film 8b, and the polysilicon film 8a are sequentially patterned to form the gate electrode 9 as shown in FIG. In this step, a gate electrode 9 having a first portion 9a embedded inside the groove 6 of the semiconductor substrate 1 and a second portion 9b connected to the first portion 9a and protruding from the groove 6 is formed. Further, in this step, the gate electrode 9 is formed so that the width of the second portion 9b in the second direction is wider than the width of the first portion 9a in the second direction. Further, in this step, the gate electrode 9 is formed so that the thickness of the second portion 9b is thicker than the width of the first portion 9a in the second direction.

【0071】

Next, as shown in FIG. 15, an n + type semiconductor region 11 is formed on the main surface of the p-type semiconductor region 3. In the n + type semiconductor region 11, the gate electrode 9 and the insulating film 10 are used as masks for introducing impurities, impurities (for example, arsenic) are introduced into the main surface of the semiconductor substrate 1 by an ion implantation method, and then heat treatment is performed to activate the n + type semiconductor region 11. Formed by applying. For the introduction of impurities, for example, the dose amount is 5E15 ~ 1E16cm.^-2It is performed under the condition that the amount of energy is about 80 Kev. The heat treatment for activating impurities is performed under the conditions of 900 ° C. or higher. In this step, the n-type semiconductor region 4 formed in contact with the groove 6 vertically below the second portion 9b of the gate electrode 9, and the n-type semiconductor region 4 formed vertically below the second portion 9b of the gate electrode 9. A source region having an n + type semiconductor region 11 formed in contact with the semiconductor region 11 is formed.

【0072】

Next, as shown in FIG. 16, an insulating film 12 made of, for example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 including the gate electrode 9, and then RIE (Reactive Ion Etching) is formed on the insulating film 12. ) Etc. are applied to form sidewall spacers 13 on each of the two side surfaces of the second portion 9b of the gate electrode 9 in the second direction, as shown in FIG. The sidewall spacer 13 is self-aligned with respect to the second portion 9b of the gate electrode 9. By this step, the second portion 9b of the gate electrode 9 is covered with the sidewall spacer 13 and the insulating film 10.

【0073】

Next, the insulating film 10 and the sidewall spacer 13 are used as an etching mask to etch the main surface of the semiconductor substrate 1, and as shown in FIG. 18, a groove recessed from the main surface of the semiconductor substrate 1 in the depth direction. Form 14. The groove 14 is formed in self-alignment with respect to the insulating film 10 and the sidewall spacer 13.

【0074】

Next, the insulating film 10 and the sidewall spacer 13 are used as masks for introducing impurities, and impurities (for example, boron) are selectively introduced into the bottom of the groove 14 by an ion implantation method, and the grooves are as shown in FIG. A p + type semiconductor region 15 is formed in a portion of the p-type semiconductor region 3 facing the bottom surface of 14.

【0075】

Next, a barrier metal film 16 is formed on the entire surface of the semiconductor substrate 1 including the inside of the groove 14 by, for example, a sputtering method, and then, for example, aluminum or an alloy containing aluminum as a main component is formed on the entire surface of the barrier metal film 16. The metal film is formed by, for example, a sputtering method, and then the metal film and the barrier metal film 16 are sequentially patterned to form the source electrode layer 17 and the gate electrode layer 18. The source electrode layer 17 is electrically connected to the p + type semiconductor region 15 and the n + type semiconductor region 11 via the barrier metal film 16. By this step, the source electrode layer 17 and the gate electrode 9 can be separated by self-alignment.

【0076】

Next, a protective film made of, for example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1, and then the protective film is patterned to expose a part of the surface of the source electrode layer 17, an opening and a gate electrode layer. The semiconductor device shown in FIGS. 1 to 4 is almost completed by forming an opening that exposes a part of the surface surface of 18 and then forming a drain electrode layer 19 on the back surface opposite to the main surface of the semiconductor substrate 1. To do.

【0077】

As described above, the following effects can be obtained according to the present embodiment. (1) The gate electrode 9 is connected to the first portion 9a embedded in the groove 6 formed in the semiconductor substrate 1 with the silicon oxide film 7 interposed therebetween and the first portion 9a, and protrudes from the groove 6. It is configured to have a second portion (protruding portion) 9b. With this configuration, the width W1 of the first part 9a is reduced when the width 6W of the groove 6 is reduced, but the width W2 of the second part 9b is not reduced even if the width 6W of the groove 6 is reduced. , The increase in gate resistance (Rg) due to the reduction of the width 6W of the groove 6 can be suppressed.

【0078】

Further, since the increase in the gate resistance (Rg) due to the reduction of the width 6W of the groove 6 can be suppressed, the conduction loss and the switching loss of the power MISFET can be reduced.

【0079】

(2) The width W2 of the second portion 9b of the gate electrode 9 is larger than the width W1 of the first portion 9a. With this configuration, the resistance in the second portion 9b can be reduced, so that the increase in gate resistance (Rg) due to the reduction of the groove width 6W can be further suppressed.

【0080】

(3) The thickness t of the second portion 9b of the gate electrode 9 is thicker than the width W1 of the first portion 9a. With this configuration, the resistance in the second portion 9b can be reduced, so that the increase in gate resistance (Rg) due to the reduction of the groove width 6W can be further suppressed.

【0081】

(4) The first portion 9a of the gate electrode 9 is formed of a polysilicon film 8a, and the second portion 9b is composed of a polysilicon film 8a and a WSi film 8b provided on the polysilicon film 8a. With such a configuration, the resistance in the second portion 9b can be reduced, so that the increase in the gate resistance (Rg) due to the reduction of the groove width 6W can be further suppressed.

【0082】

(5) The source region consists of an n-type semiconductor region 4 formed in contact with the groove 6 vertically below the second portion 9b of the gate electrode 9, and an n-type semiconductor outside the vertically downward portion of the second portion 9b of the gate electrode 9. It has a configuration having an n + type semiconductor region 11 formed in contact with the region 4. With such a configuration, even if the masks are misaligned when the gate electrode 9 is formed with reference to the groove 6, the channel length on one side surface side of the first portion 9a of the gate electrode 9 and the gate Since the channel length on the other side surface side of the first portion 9a of the electrode 9 is constant, variations in on-resistance, threshold voltage, and the like can be suppressed. As a result, stable and reproducible transistor characteristics can be obtained.

【0083】

Further, since it is not necessary to form a deep source region, the channel formation region and the groove 6 can be made shallow, which facilitates miniaturization. Moreover, since it is not necessary to form a deep source region, an increase in parasitic capacitance can be suppressed. As a result, an increase in switching loss can be suppressed.

【0084】

(6) The n-type semiconductor region 4 is set to have a lower impurity concentration than the n + -type semiconductor region 11 and a higher impurity concentration than the p-type semiconductor region 3. With such a configuration, the n-type semiconductor region 4 can be formed shallowly, so that a sufficient withstand voltage can be obtained.

【0085】

(Embodiment 2) FIG. 19 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to the second embodiment of the present invention.

【0086】

As shown in FIG. 19, the semiconductor device of this embodiment has basically the same configuration as that of the first embodiment, and the configuration of the gate electrode 9 is different.

【0087】

That is, in the gate electrode, the first portion 9a and the second portion 9b are composed of the polysilicon film 8a and the WSi film 8b. With such a configuration, the resistance in the first portion 9a and the second portion 9b can be reduced, so that the increase in the gate resistance (Rg) due to the reduction of the groove width 6W can be further suppressed.

【0088】

(Embodiment 3) FIG. 20 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to the third embodiment of the present invention.

【0089】

As shown in FIG. 20, the semiconductor device of this embodiment has basically the same configuration as that of the first embodiment, and the following configurations are different.

【0090】

That is, in the above-described first embodiment, the p + type semiconductor region 15 which is a contact region is formed directly under the groove 14, but in the present embodiment, the groove 14 is omitted and the main surface of the semiconductor substrate 1 is formed. The p + type semiconductor region 15 is formed by self-alignment with respect to the sidewall spacer 13. By applying the present invention to such a semiconductor device, the same effect as that of the above-described first embodiment can be obtained.

【0091】

(Embodiment 4) FIG. 21 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to the fourth embodiment of the present invention.

【0092】

As shown in FIG. 21, the semiconductor device of this embodiment basically has the same configuration as that of the first embodiment, and the following configurations are different.

【0093】

That is, in the above-described first embodiment, the source electrode layer 17 is self-aligned to the n + type semiconductor region 11 and the p + type semiconductor region 15 through the connection hole defined by the sidewall spacer 13. In the present embodiment, an interlayer insulating film 21 made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate 1 so as to cover the second portion 9b of the gate electrode 9, and the interlayer insulating film 21 is known as photolithography. A connection hole is formed by technology, and the source electrode layer 17 is connected to the n + type semiconductor region 11 and the p + type semiconductor region 15 through the connection hole. By applying the present invention to such a semiconductor device, the same effect as that of the above-described first embodiment can be obtained.

【0094】

(Embodiment 5) FIG. 22 is a schematic plan view showing a schematic configuration of a semiconductor device according to the third embodiment of the present invention.

【0095】

As shown in FIG. 22, the semiconductor device of this embodiment has basically the same configuration as that of the first embodiment, and the following configurations are different.

【0096】

That is, the power MISFET mounted on the semiconductor device has a mesh structure in which the gate electrodes 6 are formed in a stitch shape. By applying the present invention to such a semiconductor device, the same effect as that of the above-described first embodiment can be obtained.

【0097】

Although the invention made by the present inventor has been specifically described above based on the above-described embodiment, the present invention is not limited to the above-described embodiment and can be variously modified without departing from the gist thereof. Of course.

【0098】

For example, the present invention can be applied to a semiconductor device having an IGBT (Insulated Gate Bipolar Transistor) having a trench gate structure.

【0099】

Further, the present invention can be applied to a power IC (Integrated Circuit) in which a cell array unit composed of a plurality of transistor cells composed of transistor elements having a trench gate structure and a control circuit unit are mixedly mounted on the same semiconductor substrate.

【0100】

[Effect of the invention]

A brief description of the effects obtained by representative of the inventions disclosed in the present application is as follows.

【0101】

According to the present invention, in a semiconductor device having a trench gate structure, it is possible to suppress an increase in gate resistance due to a reduction in the width of the groove.

【0102】

According to the present invention, in a semiconductor device having a trench gate structure, conduction loss and switching loss can be reduced.

【0103】

According to the present invention, in a semiconductor device having a trench gate structure, stable and reproducible transistor characteristics can be obtained.

[Simple explanation of drawings]

[Figure 1]

It is a plane layout view which shows the schematic structure of the semiconductor device which is Embodiment 1 of this invention.

[Figure 2]

It is a schematic plan view which shows the gate electrode pattern of the semiconductor device of FIG.

[Fig. 3]

It is a schematic plan view which enlarged a part (region A) of FIG.

[Fig. 4]

It is a schematic cross-sectional view along the AA line of FIG.

[Fig. 5]

It is a schematic cross-sectional view which enlarged a part of FIG.

[Fig. 6]

It is a schematic cross-sectional view which enlarged a part of FIG.

[Fig. 7]

(a) is an impurity concentration distribution map along the B-B'line of FIG. 6, and (b) is an impurity concentration distribution map along the C-C'line of FIG.

[Fig. 8]

It is a schematic cross-sectional view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention.

[Fig. 9]

FIG. 5 is a schematic cross-sectional view during the manufacturing process of the semiconductor device following FIG.

[Fig. 10]

It is a schematic cross-sectional view in the manufacturing process of the semiconductor device following FIG.

[Fig. 11]

FIG. 5 is a schematic cross-sectional view during the manufacturing process of the semiconductor device following FIG.

[Fig. 12]

It is a schematic cross-sectional view in the manufacturing process of the semiconductor device following FIG.

[Fig. 13]

It is a schematic cross-sectional view in the manufacturing process of the semiconductor device following FIG.

[Fig. 14]

It is a schematic cross-sectional view in the manufacturing process of the semiconductor device following FIG.

[Fig. 15]

FIG. 6 is a schematic cross-sectional view during the manufacturing process of the semiconductor device following FIG.

[Fig. 16]

FIG. 5 is a schematic cross-sectional view during the manufacturing process of the semiconductor device following FIG.

[Fig. 17]

FIG. 5 is a schematic cross-sectional view during the manufacturing process of the semiconductor device following FIG.

[Fig. 18]

FIG. 5 is a schematic cross-sectional view during the manufacturing process of the semiconductor device following FIG.

[Fig. 19]

It is a schematic cross-sectional view which shows the schematic structure of the semiconductor device which is Embodiment 2 of this invention.

[Fig. 20]

It is a schematic cross-sectional view which shows the schematic structure of the semiconductor device which is Embodiment 3 of this invention.

[Fig. 21]

It is a schematic cross-sectional view which shows the schematic structure of the semiconductor device which is Embodiment 4 of this invention.

[Fig. 22]

It is a schematic plan view of the main part which shows the gate electrode pattern of the semiconductor device which is Embodiment 5 of this invention.

[Fig. 23]

(a) is a schematic cross-sectional view of a semiconductor device having a conventional power MISFET, and (b) is a schematic cross-sectional view when the width of the groove shown in (a) is reduced.

[Explanation of symbols]

1 ... Semiconductor substrate 1a ... n + type semiconductor layer 1b ... n-type semiconductor layer 2 ... Insulating film 3 ... p-type semiconductor area 4 ... n-type semiconductor area 5 ... mask 6 ... groove 7 ... Silicon oxide film 8a ... polysilicon film 8b ... Tungsten VDD (WSi) film 9 ... Gate electrode 9a ... Embedded part (first part) 9b ... protruding part (second part) 10 ... Insulating film 11 ... n + type semiconductor area 12 ... Insulating film 13 ... sidewall spacer 14 ... groove 15 ... p + type semiconductor area 16 ... Barrier metal film 17 ... Source electrode layer 18 ... Gate electrode layer 19 ... Drain electrode layer