Semiconductor device and its manufacturing method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, the present invention relates to transistors arranged at high density using silicon selective growth technology and self-aligned contact formation technology, and a method for manufacturing the same.

【0002】

[Conventional technology]

In recent years, miniaturization of devices has been progressing in order to achieve high density of semiconductor devices. At the same time, the mask alignment margin between the contact and the lower layer wiring is reduced to achieve a higher density.

【0003】

As a method of reducing the mask alignment margin between the contact and the lower layer wiring, there is a contact forming technique by self-alignment. As one of the techniques, a contact is opened by covering the lower layer wiring with a silicon nitride film and using an etching method having a large etching selectivity between the silicon oxide film constituting the interlayer insulating film and the silicon nitride film protecting the lower layer wiring. There is a way to do it.

【0004】

As an example of this technique, it is disclosed as a prior art in Japanese Patent Application Laid-Open No. 9-213949. This conventional self-aligned contact forming technique will be described with reference to FIGS. 7 (a) to 7 (e).

【0005】

First, as shown in FIG. 7A, a gate oxide film 2 is formed on the semiconductor substrate 1. After that, the polycrystalline silicon film 3 and the silicon nitride film 24 are sequentially formed, and the unnecessary portion is removed by using the photolithography technique and the anisotropic dry etching technique, so that the polycrystalline silicon film 24 is laminated. A gate electrode consisting of 3 is formed. Next, the low-concentration impurity region 10 is formed on the semiconductor substrate 1 by using the ion implantation technique.

【0006】

Next, as shown in FIG. 7 (b), the silicon nitride film 5 is formed on the entire surface.

【0007】

Next, as shown in FIG. 7 (c), a part of the silicon nitride film 5 is etched back by using an anisotropic dry etching technique to form the side wall film 6 only on the side wall portion of the gate electrode. Then, the high-concentration impurity region 11 is formed by using an ion implantation technique.

【0008】

Subsequently, as shown in FIG. 7 (d), an interlayer insulating film 7 made of a silicon oxide film is formed on the entire surface, and unnecessary portions are removed by using photolithography technology and anisotropic dry etching technology to remove contact holes. Open 8.

【0009】

This anisotropic dry etching technique uses a condition in which the etching rate of the silicon nitride film is smaller than the etching rate of the silicon oxide film, that is, a condition in which the etching selectivity is large.

【0010】

Thereby, even if the upper opening dimension of the contact hole 8 is larger than the distance between the side wall films 6 of the adjacent gate electrodes, the gate electrode is protected by the silicon nitride film 24 and the side wall film 6, and the gate electrode and the gate electrode are protected. The wiring layer 9 formed after this is not electrically short-circuited.

【0011】

Next, as shown in FIG. 7 (e), a conductive film is formed on the entire surface, and an unnecessary portion is removed by using a photolithography technique and an anisotropic dry etching technique to form the wiring layer 9.

【0012】

However, in this technique, since a silicon nitride film that easily traps hot electrons is used as the side wall film 6 of the gate electrode, there is a problem that the transistor characteristics are easily deteriorated. A means for solving this problem is disclosed in the same publication (Japanese Patent Laid-Open No. 9-213949). This technique will be described with reference to FIGS. 8 (a) to 8 (g).

【0013】

First, as shown in FIG. 8A, a gate oxide film 2 is formed on the semiconductor substrate 1. After that, the polycrystalline silicon film 3 and the silicon nitride film 4 are sequentially formed, and the unnecessary part is removed by using the photolithography technique and the anisotropic dry etching technique, so that the polycrystalline silicon film 4 is laminated. A gate electrode consisting of 3 is formed. Next, the low-concentration impurity region 10 is formed on the semiconductor substrate 1 by using the ion implantation technique.

【0014】

Next, as shown in FIG. 8 (b), the silicon oxide film 12 is formed on the entire surface.

【0015】

Next, as shown in FIG. 8 (c), a part of the silicon oxide film 12 is etched back using the anisotropic dry etching technique, and only the side wall portion of the polycrystalline silicon film 3 constituting the gate electrode is the second. Residual formation of the side wall film 13 of 1.

【0016】

This anisotropic dry etching technique uses a condition in which the etching selectivity of the silicon oxide film and the silicon nitride film is large. As a result, by adjusting the etching time, the height of the first side wall film 13 is made about the same as that of the polycrystalline silicon film 3, but the film thickness of the silicon nitride film 4 on the polycrystalline silicon film 3 is greatly reduced. There is no such thing. Then, the high-concentration impurity region 11 is formed by using an ion implantation technique.

【0017】

Subsequently, as shown in FIG. 8 (d), the silicon nitride film 15 is formed on the entire surface with a film thickness similar to that of the first side wall film 13.

【0018】

Next, as shown in FIG. 8 (e), a part of the silicon nitride film 15 is etched back using the anisotropic dry etching technique to form the silicon nitride film 4 on the gate electrode and the polycrystal constituting the gate electrode. The second side wall film 16 is residually formed only on the side wall portion of the silicon film 3. At this time, the etching time is adjusted so that the silicon nitride film 15 does not remain on the side surface of the first side wall film 13.

【0019】

Next, as shown in FIG. 8 (f), an interlayer insulating film 7 made of a silicon oxide film is formed on the entire surface, and unnecessary parts are removed by using photolithography technology and anisotropic dry etching technology to remove contact holes. Open 8.

【0020】

This anisotropic dry etching technique uses a condition in which the etching selectivity of the silicon oxide film and the silicon nitride film is large. As a result, even if the upper opening dimension of the contact hole 8 is larger than the distance between the side wall films 6 of the adjacent gate electrodes, the gate electrodes are the silicon nitride film 4 and the first side wall film 13 and the second side wall film 13. It is protected by the side wall film 16 so that the gate electrode and the wiring layer 9 formed thereafter are not electrically short-circuited.

【0021】

Next, as shown in FIG. 8 (g), a conductive film is formed on the entire surface, and an unnecessary portion is removed by using a photolithography technique and an anisotropic dry etching technique to form the wiring layer 9.

【0022】

Using this technique, the first side wall film 13 and the second side wall film 16 formed on the side surface of the gate electrode are formed between the polycrystalline silicon film 3 forming the gate electrode and the wiring layer 9 formed thereafter. Since it is interposed between them, the gate electrode and the wiring layer are not electrically short-circuited even when the upper opening dimension of the contact hole 8 is larger than the distance between the side wall films of the adjacent gate electrodes.

【0023】

Further, since the lower part of the side wall film of the gate electrode is formed of a silicon oxide film, it is difficult to trap hot carriers as compared with the case of a silicon nitride film. Therefore, the problem that the transistor characteristics are easily deteriorated does not occur.

【0024】

[Problems to be Solved by the Invention]

When forming the second side wall film 16 of the gate electrode, it must be etched back until the silicon nitride film 15 grown on the side surface of the first side wall film 13 is completely eliminated. However, in reality, a part of the silicon nitride film 15 remains on the side surface of the first side wall film 13 due to variations in the film thickness of the silicon nitride film 15 and variations in the anisotropic dry etching rate during etching back. There is a possibility that it will end up.

【0025】

In this case, there is a problem that the size of the bottom of the contact hole 8 becomes smaller than planned, the contact resistance increases, and the operation becomes defective.

【0026】

Further, when the silicon nitride film 15 is etched back, the surface of the high-concentration impurity region 11 is exposed to the etch back atmosphere for a long time, and there is a problem that the transistor characteristics are deteriorated due to etching damage.

【0027】

Further, since the first side wall film 13 is formed of a silicon oxide film, the first in the hydrofluoric acid chemical treatment step for removing the natural oxide film formed on the bottom of the contact before forming the wiring layer. There is a problem that even the side wall film 13 is etched and the polycrystalline silicon film 3 and the wiring layer 9 may be short-circuited.

【0028】

Further, some products use only the low-concentration impurity region 10 as the source / drain region of the transistor and do not form the high-concentration impurity region 11. For example, dynamic random access memory, so-called DRAM, often adopts such a structure. The purpose is to reduce the amount of reverse leakage current at the PN junction between the N-type low-concentration impurity region 10 and the P-well region that form the source / drain region.

【0029】

In the case of such a structure, it is difficult to use a metal material for the wiring layer 9. That is, when a silicide layer, which is a compound of metal and silicon, is formed between the wiring layer 9 and the low-concentration impurity region 10, the depletion layer formed at the PN junction greatly extends to the N- side, and the silicide layer is a depletion layer. This is because it is taken in.

【0030】

Since the silicide layer can be a formation bond center, a so-called GR center, there arises a problem of increasing the amount of reverse leakage current. There is also a means of forming the wiring layer 9 with polycrystalline silicon so that the silicide layer is not formed between the wiring layer 9 and the low-concentration impurity region 10. In this case, there arises a problem that the contact resistance increases as compared with the case of the metal wiring layer.

【0031】

Therefore, the present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a low resistance contact that can be formed by self-alignment, and the characteristics of the transistor are not easily deteriorated. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

【0032】

[Means for solving problems]

In the present invention, a semiconductor device having at least a pair of impurity regions in a semiconductor substrate, the silicon layer formed on the impurity regions, and a gate insulating film formed between the impurity regions on the semiconductor substrate. A gate electrode formed on the gate insulating film, a first silicon nitride film formed on the gate electrode, a silicon oxide film formed on the side surface of the gate electrode, and a part of the upper surface of the silicon layer. It also has a second silicon nitride film formed on the side surface of the silicon oxide film and a conductive layer formed on the silicon layer.

【0033】

Here, the gate electrode is preferably composed of a polycrystalline silicon layer and a metal layer or a metal silicide layer.

【0034】

In this case, the silicon oxide film and the second silicon nitride film form a double sidewall spacer.

【0035】

Under such a configuration, the silicon layer and the gate electrode are insulated only by the silicon oxide film, and the lower end of the second silicon nitride film is in contact with the upper surface of the silicon layer.

【0036】

The conductive layer and the gate electrode are insulated by the first silicon nitride film and the sidewall spacer.

【0037】

It is desirable that a titanium silicide layer is interposed between the conductive layer and the silicon layer.

【0038】

Further, the silicon layer acts to prevent the depletion layer formed in the vicinity of the impurity region from reaching the titanium silicide layer.

【0039】

Further, the present invention is a method for manufacturing a semiconductor device having a semiconductor substrate, in which a gate insulating film is formed on the semiconductor substrate, a gate electrode is formed on the gate insulating film, and a first silicon is formed on the gate electrode. A nitride film is formed, a silicon oxide film is formed on the side surface of the gate electrode, impurity regions are formed on both sides of the gate electrode in the semiconductor substrate, a silicon layer is formed on the impurity region, and one of the upper surfaces of the silicon layer is formed. A second silicon nitrogenized film is formed on the side surface of the silicon oxide film, and a conductive layer is formed on the silicon layer.

【0040】

Preferably, the gate electrode is composed of a polycrystalline silicon layer formed on the gate insulating film and a metal layer or a metal silicide layer formed on the polycrystalline silicon layer.

【0041】

In this case, it is preferable that the silicon layer is formed by selectively growing on the impurity region by the selective epitaxial growth method.

【0042】

Further, it is desirable to form a titanium nitride laminated film on the silicon layer and heat-treat the titanium nitride layer to form a titanium silicide layer.

【0043】

Here, the silicon layer acts to prevent the depletion layer formed in the vicinity of the impurity region from reaching the titanium silicide layer.

【0044】

Further, the silicon oxide film and the second silicon nitride film form a double sidewall spacer.

【0045】

Preferably, the distance between the edge of the impurity region and the second silicon nitride film constituting the sidewall spacer is set so that the hot carriers generated at the edge of the impurity region are not trapped by the second silicon nitride film. Has been done.

【0046】

Further, the present invention is a method for manufacturing a semiconductor device having a semiconductor substrate, in which a gate insulating film is formed on the semiconductor substrate, and a polycrystalline silicon film and a metal layer or a metal silicide film and a first silicon are formed on the entire surface of the semiconductor substrate. The nitride film is sequentially formed, unnecessary parts are removed by lithography and anisotropic dry etching to form a gate electrode, at least the side surface of the polycrystalline silicon film is oxidized in an oxidizing atmosphere, and the anisotropic dry etching is performed. The oxide film is etched back to expose the surface of the silicon substrate, the source / drain region of the transistor is formed by the ion injection method, and the silicon layer is grown on the source / drain region using the selective growth technology of silicon, and the entire surface is formed. A second silicon nitride film is grown on the semiconductor, and the second silicon nitride film is etched back by anisotropic dry etching to expose the selectively grown silicon layer to form an interlayer insulating film made of a silicon oxide film, and lithography is performed. And the contact hole is opened by dry etching.

【0047】

BEST MODE FOR CARRYING OUT THE INVENTION

First, the configuration of the semiconductor device (field effect transistor) of the present invention will be described with reference to FIGS. 1 and 2. Here, FIG. 1 is a cross-sectional view of the semiconductor device, and FIG. 2 is a plan view thereof.

【0048】

The semiconductor device (field effect transistor) of the present invention is selected only on the gate electrode composed of polycrystalline silicon 103 and tungsten silicide 104 having the gate insulating film 102 sandwiched on the semiconductor substrate 101, the impurity region 107, and the impurity region 107. It has grown silicon (silicon layer) 108.

【0049】

Under such a configuration, a double sidewall spacer composed of a silicon oxide film 106 and a second silicon nitride film 109 is provided on all or a part of the side surface of the gate electrode of the transistor, and the selectively grown silicon 108 and the gate electrode are provided. Is insulated only by the silicon oxide film 106 constituting the sidewall spacer, and the lower end of the second silicon nitride film 109 constituting the sidewall spacer is in contact with the upper surface of the selectively grown silicon 108.

【0050】

Further, the conductive material (tungsten) 114 that fills the contact hole (contact hole) 111 and the gate electrode are insulated by a first silicon nitride film 105 formed above the gate electrode and a sidewall spacer.

【0051】

Further, a silicon oxide film 110 is formed on the first silicon nitride film, and the tungsten 114 is covered with a titanium / titanium nitride laminated film 112. Further, a titanium silicide layer 113 is interposed between the tungsten 114 and the silicon 108.

【0052】

Next, a first embodiment of the present invention will be described with reference to the process sequence sectional views of FIGS. 3 (a) to 3 (f). Here, FIGS. 4 (a) to 4 (f) are process order plan views corresponding to the process order sectional views of FIGS. 3 (a) to 3 (f).

【0053】

As shown in FIG. 3A, the surface of the semiconductor substrate 101 is thermally oxidized to a thickness of 5 nm to form a gate oxide film 102. Then, the polycrystalline silicon film 103 containing phosphorus is grown to 100 nm by the CVD method, and then the tungsten silicide 104 is grown to 100 nm by the CVD method or the sputtering method.

【0054】

Then, the first silicon nitride film 105 is grown by the CVD method to 100 nm. Using a photolithography technique and an anisotropic dry etching technique, unnecessary portions of the first silicon nitride film 105, tungsten silicide 104, and polycrystalline silicon film 103 are removed to form a gate electrode.

【0055】

Next, as shown in FIG. 3 (b), the side surfaces of the polycrystalline silicon film 103 and the patterned tungsten silicide 104 patterned by the thermal oxidation method are oxidized to form a silicon oxide film 106 having a size of about 10 nm. ..

【0056】

Next, using an anisotropic dry etching technique, the gate oxide film 102 formed on the silicon substrate 101 between the gate electrodes is etched back to expose the surface of the silicon substrate 101. After that, phosphorus is 1E13 / cm with energy of 30keV.²Ion implantation is performed to form an impurity region 107 that serves as a source and drain region of the transistor.

【0057】

Next, as shown in FIG. 3 (c), 1E20 / cm of phosphorus was added on the impurity region 107 using the selective epitaxial silicon growth technique.³Selectively grow silicon 108 containing it at about 50 nm.

【0058】

Subsequently, as shown in FIG. 3 (d), the second silicon nitride film 109 is grown on the entire surface by the CVD method. This film thickness must be such that the space between the gate electrodes is not embedded. For example, if the gate electrode spacing is 150 nm, the second silicon nitride film 109 is set to about 50 nm. Next, the second silicon nitride film 109 formed on the silicon 108 selectively grown by using the anisotropic dry etching technique is etched back to expose the surface of the silicon 108.

【0059】

Next, as shown in FIG. 3 (e), a silicon oxide film 110 is formed at 500 nm by the CVD method, and the surface is flattened by the CMP method. Next, an unnecessary portion of the silicon oxide film 110 is removed by using a lithography technique and an anisotropic dry etching technique to form a contact hole 111.

【0060】

Here, by selecting a condition in which the etching rate of the silicon nitride film is slower than the etching rate of the silicon oxide film as the condition of the anisotropic dry etching, the dimensions of the upper part of the contact hole 111 as shown in FIG. 3 (e). Is larger than the gate electrode spacing, the gate electrode is covered with the first silicon nitride film 105 and the second silicon nitride film 109, so that a part of the gate electrode is not exposed inside the contact hole 111.

【0061】

Next, as shown in FIG. 3 (f), titanium is grown by 10 nm and titanium nitride is grown by 10 nm by a CVD method or a sputtering method to form a titanium / titanium nitride laminated film 112. Then, by heat-treating at 700 ° C. for 30 seconds, titanium and silicon react to form the titanium silicide layer 113. Then, the tungsten 114 is deposited at 300 nm by the CVD method, and then the unnecessary portion of the tungsten 114 and the titanium / titanium nitride laminated film 112 is removed by the CMP method.

【0062】

Next, a second embodiment of the present invention will be described with reference to the process sequence sectional views of FIGS. 5 (a) to 5 (g). 6 (a) to 6 (g) are process order plan views corresponding to the process order sectional views of FIGS. 5 (a) to 5 (g).

【0063】

As shown in FIG. 5A, the surface of the semiconductor substrate 101 is thermally oxidized to a thickness of 5 nm to form a gate oxide film 102. Then, the polycrystalline silicon film 103 containing phosphorus is grown to 100 nm by the CVD method, and then the tungsten silicide 104 is grown to 100 nm by the CVD method or the sputtering method.

【0064】

Then, the first silicon nitride film 105 is grown by the CVD method to 100 nm. Using a photolithography technique and an anisotropic dry etching technique, unnecessary portions of the first silicon nitride film 105, tungsten silicide 104, and polycrystalline silicon film 103 are removed to form a gate electrode.

【0065】

Next, as shown in FIG. 5 (b), the side surfaces of the polycrystalline silicon film 103 and the patterned tungsten silicide 104 patterned by the thermal oxidation method are oxidized to form a silicon oxide film 106 having a size of about 10 nm. .. Next, the gate oxide film 102 formed on the silicon substrate 101 between the gate electrodes is etched back using the anisotropic dry etching technique to expose the surface of the silicon substrate 101. After that, phosphorus is 1E13 / cm with energy of 30keV.²Ion implantation is performed to form an impurity region 107 that serves as a source and drain region of the transistor.

【0066】

Subsequently, as shown in FIG. 5 (c), 1E20 / cm of phosphorus was added on the impurity region 107 using the selective epitaxial silicon growth technique.³Selectively grow silicon 108 containing it at about 50 nm.

【0067】

Next, as shown in FIG. 5 (d), the second silicon nitride film 109 is grown on the entire surface by the CVD method. This film thickness must be such that the space between the gate electrodes is not embedded. For example, if the gate electrode spacing is 150 nm, the second silicon nitride film 109 is set to about 50 nm. Next, a silicon oxide film 110 is formed at 500 nm by the CVD method, and the surface is flattened by the CMP method.

【0068】

Next, as shown in FIG. 5 (e), an unnecessary portion of the silicon oxide film 110 is removed by using a lithography technique and an anisotropic dry etching technique. By selecting a condition in which the etching rate of the silicon nitride film is slower than the etching rate of the silicon oxide film as the condition of the anisotropic dry etching, as shown in FIG. 5 (e), the upper dimension of the contact hole 111 is the gate electrode spacing. Even if it is larger, the gate electrode is covered with the first silicon nitride film 105 and the second silicon nitride film 109, so that a part of the gate electrode is not exposed.

【0069】

Next, as shown in FIG. 5 (f), the second silicon nitride film 109 formed on the silicon 108 selectively grown by using the anisotropic dry etching technique is etched back to expose the surface of the silicon 108. ..

【0070】

Subsequently, as shown in FIG. 5 (g), titanium is grown by 10 nm and titanium nitride is grown by 10 nm by a CVD method or a sputtering method to form a titanium / titanium nitride laminated film 112. Then, by heat-treating at 700 ° C. for 30 seconds, titanium and silicon react to form the titanium silicide layer 13. Then, the tungsten 114 is deposited at 300 nm by the CVD method, and then the unnecessary portion of the tungsten 114 and the titanium / titanium nitride laminated film 112 is removed by the CMP method.

【0071】

Here, in the above embodiment, the gate electrode is made of polycrystalline silicon 103 and tungsten silicide 104, but the present invention is not limited to this, and is composed of a polycrystalline silicon layer and a metal layer or a metal silicide layer. If so, it may be composed of other materials. For example, the metal layer may be tungsten, and the other metal silicide layer may be titanium silicide.

【0072】

[Effect of the invention]

According to the present invention, since the distance between the end of the drain region where hot carriers are likely to be generated and the sidewall spacer made of a silicon nitride film is large, the hot carriers are trapped by the sidewall spacers and deteriorate the transistor characteristics. Does not occur.

【0073】

Further, according to the present invention, the depletion layer formed at the PN junction greatly extends in the direction of the N-type impurity region, and the silicon formed on the depletion layer increases phosphorus by 1E20 / cm.³Since it is an N + type containing it, the extension of the depletion layer is suppressed and it does not reach the titanium silicide layer. Therefore, the amount of reverse leakage current due to the silicid layer being incorporated into the depletion layer does not increase.

[Simple explanation of drawings]

[Figure 1]

It is sectional drawing of the semiconductor device of this invention.

[Figure 2]

It is a top view of the semiconductor device of this invention.

[Fig. 3]

(a) to (f) are process sequential cross-sectional views showing the first embodiment of the present invention.

[Fig. 4]

(a) to (f) are process order plan views corresponding to the process order sectional views of FIGS. 3 (a) to 3 (f).

[Fig. 5]

(a) to (g) are process sequential sectional views showing a second embodiment of the present invention.

[Fig. 6]

(a) to (g) are process order plan views corresponding to the process order sectional views of FIGS. 5 (a) to 5 (g).

[Fig. 7]

(a) to (e) are process sequential cross-sectional views illustrating a conventional self-aligned contact forming technique.

[Fig. 8]

(a) to (g) are process sequential cross-sectional views showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

101 Semiconductor substrate 102 Gate oxide film 103 polycrystalline silicon 104 Tungsten Silicide 105 1st silicon nitride film 106 Silicon oxide film 107 Impurity region 108 Silicon 109 Second silicon nitride film 110 Silicon oxide film 111 Contact hole 112 Titanium / Titanium Nitride Laminated Membrane 113 Titanium silicide layer 114 Tungsten 115 active region