Digital signal receiver

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a configuration of a digital signal receiving device for receiving and demodulating a digital signal transmitted by an Orthogonal Frequency Division Multiplex (OFDM) transmission method, and more particularly to a configuration of symbol period detection in demodulation processing. ..

【0002】

[Conventional technology]

In recent years, orthogonal frequency division multiplexing (hereinafter referred to as OFDM) transmission method has attracted attention in digital audio broadcasting for mobiles and digital television broadcasting for terrestrial broadcasting.

【0003】

This OFDM transmission method is a method in which a large number of subcarriers (hereinafter referred to as subcarriers) orthogonal to each other are modulated by the digital data to be transmitted, and the modulated waves are multiplexed and transmitted. This method has a feature that when the number of subcarriers used is as large as several hundreds to several thousand, the symbol period of each modulated wave becomes extremely long, so that it is not easily affected by multipath interference.

【0004】

FIG. 9 is a block diagram showing a conventional OFDM symbol period detection circuit 500.

【0005】

The in-phase detection axis signal (I signal) and the orthogonal detection axis signal (Q signal) received by the tuner and passed through the orthogonal demodulation circuit and the A / D converter are input to the input terminal 501.

【0006】

The input I and Q signals are divided into two, one is directly input to the correlator 503, and the other is delayed by the effective symbol period delay memory 502 and then input to the correlator 503.

【0007】

The output of the correlator 503 is input to the moving average circuit 504 that continuously outputs the average value of the guard period width.

【0008】

The output of the moving average circuit 504 passes through the absolute value adder 505 and is input to the symbol period IIR filter (infinite impulse response filter) 506. The IIR filter 506 includes a coefficient circuit 531 that multiplies the output of the absolute value adder 505 by 1 / α, an adder 532, and a symbol period length delay memory 533 that delays the output of the adder 532 by the transmission symbol period length. .. The adder 532 adds and outputs the output of the coefficient circuit 531 and the output of the symbol period length delay memory 533.

【0009】

The correlation output whose maximum peak is emphasized by the IIR filter 506 is input to the symbol pulse generation circuit 508, the maximum peak position is detected, and the symbol period is calculated. The symbol pulse generation circuit 508 outputs a symbol pulse to the terminal 510 corresponding to the symbol period detected in this way.

【0010】

The IIR filter 506 is reset every M symbol (M: natural number) to prevent divergence.

【0011】

Next, the symbol period detection operation will be described. FIG. 10 is a waveform diagram showing an OFDM modulated signal.

【0012】

In OFDM, since the transmitted data is distributed and modulated in hundreds to thousands of subcarriers, the modulation symbol rate of each subcarrier becomes extremely low, and the one-symbol period becomes extremely long.

【0013】

Therefore, as described above, it is less susceptible to the effects of multipath, but further, by setting a period called the guard period before the valid symbol period, the effect of multipath interference can be eliminated as a result. it can.

【0014】

The guard period is formed by cyclically copying the latter half of the valid symbol period. If the delay time of multipath interference is within the guard period, intersymbol interference due to delayed adjacent symbols can be prevented by demodulating only the signal during the valid symbol period at the time of demodulation. The valid symbol period and the guard period are collectively referred to as the "transmission symbol period" or simply the "symbol period".

【0015】

As described in FIG. 9, the supplied I and Q signals are input to the delay memory 502 and the correlator 503. The correlator 503 calculates and outputs the number of correlations between the signal delayed by the effective symbol period by the delay memory 502 and the directly input signal. The output of the correlator 503 is the sum of the absolute values taken by the absolute value adder 505 after the moving average circuit 504 takes the moving average with the guard period width.

【0016】

FIG. 11 is a timing chart for explaining the operation of the symbol period detection circuit 500 shown in FIG.

【0017】

As shown in FIG. 11A, the OFDM signals have guard periods G1, G2, ... added to the beginning of each valid symbol period S1, S2, ....

【0018】

The guard periods G1, G2, ... Are copies of the periods G1', G2', ... within the valid symbol periods S1, S2, ....

【0019】

Therefore, when the effective symbol period is delayed, the timing of the delay signal periods G1, G2, ... And the timing of the periods G1', G2', ... coincide with each other, as shown in FIG. 11 (b).

【0020】

Here, since the period Gn and the period Gn'(n: natural number) have a copying relationship, the correlation of the signals in this period is high.

【0021】

In other periods, the OFDM signal is a noisy signal as shown in the figure, so the correlation value is low.

【0022】

Therefore, as shown in FIG. 11 (c), the output from the correlation, the moving average, and the sum of the absolute values gradually increases from the start timing of the periods G1, G2, ..., And peaks at the end timing of the symbol period. .. Hereinafter, this signal will be referred to as a peak signal.

【0023】

The symbol period detection will be performed based on the peak signal.

【0024】

[Problems to be Solved by the Invention]

FIG. 12 is a timing chart for explaining the peak signal and the signal processing performed by the IIR filter 506 on the peak signal.

【0025】

As shown in FIG. 12 (a), the peak signal as described above actually contains some noise components. Therefore, by passing through the symbol period IIR filter 506, noise is reduced, peaks are emphasized, and the accuracy of symbol period detection is improved. The peak signal after passing through the IIR filter is shown in Fig. 12 (b).

【0026】

As shown in FIG. 12 (c), the symbol pulse is generated by a symbol period counter or the like whose reset pulse is the timing of the peak P1 in FIG. 12 (b).

【0027】

However, the symbol period IIR filter 506 of this circuit requires a symbol period length symbol period delay memory 533, and has a problem that the circuit scale becomes large.

【0028】

The present invention has been made to solve the above-mentioned problems, and provides a digital signal receiving device capable of detecting a symbol period in an OFDM transmission method while suppressing the circuit scale thereof. That is.

【0029】

[Means for solving problems]

The digital signal receiving device according to claim 1 is a digital signal receiving device that receives an orthogonal frequency division multiplex modulation signal having a valid symbol period and a guard period of a waveform that matches a part of the valid symbol period within the transmission symbol period. Therefore, the first delay means that receives the in-phase axis signal and the orthogonal axis signal after the orthogonal detection and delays the period corresponding to the effective symbol period length, and the in-phase axis signal, the orthogonal axis signal, and the first delay means. Correlation detecting means for detecting the correlation with the in-phase axis signal and the orthogonal axis signal after the delay, moving averaging means for receiving the output of the correlation detecting means and performing moving averaging processing for a period corresponding to the guard period length, and moving. A cyclic filter means that performs processing for emphasizing the maximum peak value of the averaging means is provided, and the cyclic filter means includes an addition means that receives a signal corresponding to the output of the moving averaging means to one input, and a transmission symbol period. It has a capacity smaller than the amount of data of, and includes a second delay means that receives the output of the addition means and delays by the transmission symbol period and gives it to the other input of the addition means, based on the output of the moving averaging means. , A control means for controlling the writing and reading of data to the second delay means, and a symbol period detecting means for detecting the maximum peak position of the cyclic filter means and calculating the transmission symbol period.

【0030】

In the digital signal receiving device according to claim 2, in addition to the configuration of the digital signal receiving device according to claim 1, the control means detects a peak of a predetermined value or more based on the output of the moving averaging means. Correspondingly, a peak detection means that outputs a pulse signal, a coarse symbol detection means that receives the pulse signal and generates a symbol pulse whose period matches the symbol interval and corresponds to the boundary of the transmission symbol period, and before and after the symbol pulse. Includes a control signal generating means that generates a signal that controls the second delay means during the required period of.

【0031】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

【0032】

FIG. 1 is a schematic block diagram showing the overall configuration of the digital signal receiving device 1000 of the present invention. Although not particularly limited, the digital signal receiving device 1000 shown in FIG. 1 can be used, for example, as a receiving device for receiving terrestrial digital broadcasting.

【0033】

With reference to FIG. 1, in the digital signal receiving device 1000, the RF signal received from the antenna (not shown) is selected by the tuner 100 and given to the OFDM demodulation unit 102, respectively.

【0034】

The demodulated signal from the OFDM demodulation unit 102 is given to the transport stream decoder (hereinafter referred to as TS decoder) 104, and is given to the MPEG decoding unit 110. That is, the TS decoder 104 extracts the baseband signal from the selected channel.

【0035】

The MPEG decoding unit 110 receives the data stream given by the TS decoder 104 and converts it into a video signal and an audio signal by using the random access memory (hereinafter referred to as RAM) 112 as a buffer for temporarily storing the data. To do.

【0036】

The digital signal receiver 1000 is further stored in the built-in storage device 148 for receiving and storing the signal from the TS decoder 104 via the data bus BS1 and in the built-in storage device 148 via the data bus BS1. An arithmetic processing unit 144 for performing predetermined processing and outputting the data, a ROM 140 for recording a program in the arithmetic processing of the arithmetic processing unit 144, and a memory area for the operation of the arithmetic processing unit 144. It is equipped with a RAM 142 that provides the data, and a high-speed digital interface 146 for inputting / outputting data between the data bus BS1 and the outside. Although not particularly limited, as the built-in storage device 148 and ROM 140, for example, a flash memory capable of electrically writing / reading data can be used.

【0037】

The data after the arithmetic processing unit 144 processes the data stored in the built-in storage device 148 according to the instruction given from the outside is transferred from the on-screen display processing unit 130 to the synthesizer 160.2. Given.

【0038】

The synthesizer 160.2 synthesizes the output from the MPEG decoding unit 110 and the output from the on-screen display processing unit 130, and then gives the output to the video output terminal 164. The output from the video output terminal 164 is given to the display unit 1004.

【0039】

The digital signal receiver 1000 further receives data and the like as a result of processing by the arithmetic processing unit 144 based on the data stored in the built-in storage device 148, and generates sound effects and the like for the image output on the display unit. Then, the additional sound generator 120 for giving to the synthesizer 160.1 and the data processed by the arithmetic processing unit 144 based on the data etc. stored in the built-in storage device 148 are received to generate an audio signal, and the synthesizer is used. It is equipped with a PCM decoder 122 that gives 160.1.

【0040】

The synthesizer 160.1 receives the output from the MPEG decoding unit 110 and the output from the additional sound generator 120 and the PCM decoder 122, and gives the synthesis result to the audio output terminal 162. The audio signal given to the audio output terminal 162 is output as an audio signal from the audio output unit 1002.

【0041】

If necessary, the digital signal receiving device 1000 may be configured to include a modem 150 for exchanging data with and from the outside, and an IC card interface 152 for receiving information from an IC card.

【0042】

An external storage device 180 such as an HDD device for a home server and a remote controller (or keyboard or the like) 182 which is an external input device are connected to the data bus BS1 via a high-speed digital interface 146.

【0043】

Further, the digital signal receiving device 1000 may be integrated with a display unit 1004 that receives video output and displays it on a display, or an audio output unit 1002 such as a speaker that receives an audio output signal and outputs audio. ..

【0044】

FIG. 2 is a block diagram showing the configuration of the OFDM demodulation unit 102 in FIG. With reference to FIG. 2, the OFDM demodulator 102 separates the A / D converter 200, which converts the output of the tuner from analog to digital, and the baseband signal into an in-phase axis (I) signal and an orthogonal axis (Q) signal. It includes an I / Q separation unit 202 and a carrier synchronization unit 204 that corrects an error of less than half of the carrier interval between the transmission carrier frequency and the reception carrier frequency.

【0045】

The OFDM demodulator 102 further includes an OFDM symbol period detection circuit 300, a mode / guard automatic determination circuit 236 that automatically determines the mode and guard of the OFDM signal, and a fast Fourier transform with the number of points according to the determined mode. The FFT circuit 208 that performs the operation, the AFT circuit 210 that corrects the error in the carrier interval unit between the transmission carrier frequency and the reception carrier frequency, the frame decoding circuit 212 that detects the data frame structure and generates the control signal, and the reception in the transmission line. It includes an equalization circuit 214 for correcting the distortion of the signal and a clock synchronous reproduction circuit 238.

【0046】

The OFDM demodulator 102 further includes a frequency deinterleaved circuit 216 that cancels the frequency direction interleaving performed on the transmitting side, a time deinterleaving circuit 218 that cancels the time direction interleaving performed on the transmitting side, and a transmitting side. It includes a demapping circuit 220 for decoding the data arranged according to the modulation method in the above, and a bit deinterleaving circuit 222 for canceling the bit-by-bit interleaving performed on the transmitting side.

【0047】

The OFDM demodulator 102 further includes a bitabi decoding circuit 224 that decodes convolution-encoded data on the transmitting side, a byte deinterleaving circuit 226 that cancels byte-by-byte interleaving performed on the transmitting side, and a transport stream. It includes a TS reproduction circuit 228 that reconstructs data according to the format, and an RS decoding circuit 230 that decodes Reed-Solomon-encoded data on the transmitting side.

【0048】

The RS decoding circuit 230 outputs the result of Reed-Solomon decoding to the TS decoder 104 shown in FIG.

【0049】

FIG. 3 is a block diagram for explaining the configuration of the OFDM symbol period detection circuit 300 shown in FIG.

【0050】

The OFDM symbol period detection circuit 300 includes a guard interval correlation circuit 232 and a symbol synchronization circuit 234.

【0051】

The in-phase detection axis signal (I signal) and the orthogonal detection axis signal (Q signal) separated by the I / Q separation circuit 202 after passing through the quadrature demodulation circuit and the A / D converter 200 received by the tuner are connected to the input terminal 301. Signal) and is input.

【0052】

The guard interval correlation circuit 232 includes a correlator 303 in which one of the two divided I and Q signals is directly input, and a valid symbol period delay memory in which the other of the two divided I and Q signals is input. It is equipped with 302. The effective symbol period delay memory 302 delays the input signal by the effective symbol period and then gives it to the correlator 303.

【0053】

The guard interval correlation circuit 232 further includes a moving average circuit 304 that receives the output of the correlator 303 and continuously outputs the average value of the guard period width. The output of the moving average circuit 304 is given to the carrier synchronization circuit 204.

【0054】

The symbol synchronization circuit 234 includes an absolute value adder 305 that receives the output of the mobile averaging circuit 3, an IIR filter 306 that receives the output of the absolute value adder 305, and a symbol pulse that receives the output of the IIR filter 306 and generates a symbol pulse. It includes a generation circuit 308 and a memory control circuit 320 for controlling the IIR filter 306 based on the output of the absolute value adder 305.

【0055】

The IIR filter 306 includes a coefficient circuit 331 that multiplies the output of the absolute value adder 305 by 1 / α, an adder 332, and a required period length delay memory 333 having a capacity corresponding to the required period length. The adder 332 adds and outputs the output of the coefficient circuit 331 and the output of the required period length delay memory 333.

【0056】

The correlation output whose maximum peak is emphasized by the IIR filter 306 is input to the symbol pulse generation circuit 308, the maximum peak position is detected, and the symbol period is calculated. The symbol pulse generation circuit 308 outputs a symbol pulse to the terminal 310 corresponding to the symbol period detected in this way.

【0057】

As described above, the output of the absolute value adder 305 is also input to the memory control circuit 320. The memory control circuit 320 detects the peak position of the output of the absolute value adder 305, and based on that position, limits the writing to the required period length delay memory 333 to only the necessary part (peak part), and , Generates a memory control signal to output after delaying the valid symbol period.

【0058】

As in the conventional example, the IIR filter 306 is reset for each M symbol in order to prevent divergence.

【0059】

Next, the symbol period detection operation of the demodulator in the present invention will be described. Similar to the conventional example, the symbol period detection is performed based on the peak signal obtained by the correlator 303, the moving average circuit 304, and the absolute value adder 305.

【0060】

As described above, the peak signal actually contains some noise as shown in FIG. 12 (a). Therefore, conventionally, by passing the symbol period IIR filter 506 using the symbol period length delay memory 533, noise is reduced and peaks are emphasized, and the accuracy of symbol period detection is improved. As a result, the peak signal as shown in FIG. 12 (b) was obtained after passing through the IIR filter 506.

【0061】

However, as can be seen from FIG. 12, the portion required for peak enhancement is only a part of the region including the peak portion.

【0062】

Therefore, in the configuration of the present invention described above, only the approximate peak portion is cut out and held by the memory control circuit 320 based on the peak position of the peak signal before emphasis in which the peak position can be detected although it contains some noise. Then, the required period length delay memory 333 in the IIR filter 306 is controlled so as to delay by the transmission symbol period.

【0063】

FIG. 4 is a timing chart for explaining the operation of such a memory control circuit 320.

【0064】

FIG. 4 (a) shows the peak signal before emphasis, and FIG. 4 (b) is a memory control signal generated by the memory control circuit 320 based on FIG. 4 (a). By controlling the write enable signal and the read enable signal of the required period length delay memory 333 based on this memory control signal, it is possible to write or hold only the necessary portion (peak portion). This makes it possible to read after the symbol period is delayed.

【0065】

FIG. 4 (c) shows an emphasized peak signal when the IIR filter 306 of the present invention is used. As shown in FIG. 4 (c), it is possible to generate a symbol pulse using the peak P1 without deteriorating the symbol period detection accuracy as compared with the conventional case.

【0066】

Hereinafter, the configuration and operation of the memory control unit 320 will be described in more detail. FIG. 5 is a block diagram of the memory control unit 320.

【0067】

The memory control circuit 320 includes a peak detection circuit 322, a coarse symbol detection circuit 326, and a control signal generation circuit 328.

【0068】

FIG. 6 shows a waveform diagram of the output of the absolute value addition circuit 305, the output pulse signal of the peak detection circuit 322, the output symbol pulse of the coarse symbol detection circuit 326, and the output of the control signal generation circuit 328.

【0069】

With reference to FIGS. 5 and 6, the output of the absolute value adder 305 is input to the peak detection circuit 322. The peak detection circuit 322 outputs a pulse signal in response to the detection of a peak position of a certain value or more.

【0070】

In the coarse symbol detection circuit 326, the pulse signal is used to generate a symbol pulse that substantially coincides with the symbol boundary and whose period coincides with the symbol interval. For this purpose, the coarse symbol detection circuit 326 includes a clock circuit (not shown) that generates a clock signal and a counter circuit (not shown) that counts the output of the clock signal and outputs a symbol clock signal that is activated in the symbol cycle (FIG.). (Not shown) shall be provided.

【0071】

The control signal generation circuit 328 uses the symbol pulse to turn on the memory write, read, and output of the IIR filter 306 during the required period before and after the symbol pulse, the memory control signal, the write enable signal, and the read. Generate an enable signal.

【0072】

FIG. 7 is a timing chart for explaining the operation of the coarse symbol detection circuit 326, and FIG. 8 is a flowchart for explaining the operation of the coarse symbol detection circuit 326.

【0073】

With reference to FIG. 7, the output pulse signal from the peak detection circuit 322 is a group of pulse signals in which a plurality of pulses stand before and after the actual symbol boundary, as shown in FIG. 7 (a).

【0074】

The coarse symbol detection circuit 326 first acquires the position of the first appearing pulse as a tentative 0th pulse, and ignores a predetermined number of neighboring pulses thereafter as shown in FIG. 7 (b).

【0075】

After this ignoring, the acquired pulse is regarded as the original 0th pulse again, and the position is acquired as shown in FIG. 7 (c).

【0076】

After that, with reference to this 0th pulse position, based on the symbol clock signal output from the counter circuit operating in the above-mentioned symbol cycle, the pulse immediately after the reference time point defined by this symbol clock signal is coarsened. The symbol detection circuit 326 acquires the i-th pulse.

【0077】

Here, in the group of pulse signals including the i-th pulse (integer of i: 0 or more) (or activation of the reference symbol clock) of interest, this i-th pulse (or symbol) from the beginning of this pulse signal group. The pulse in the period until the activation of the clock) is called the "pre-near pulse", and the pulse in the period from the i-th pulse (or activation of the symbol clock) to the end of the pulse signal group is called the "rear-near pulse". Call.

【0078】

As shown in FIGS. 7 (d) and 7 (e), after ignoring the near-neighbor pulse of the 0th pulse and the near-neighbor pulse of the first pulse, respectively, as shown in FIG. 7 (f), the thirst Get the position of one pulse.

【0079】

After that, if the third pulse position can be normally obtained up to the specified number of times L (L: natural number), the 0th pulse position is almost the symbol boundary as shown in FIG. 7 (g). It is judged that it matches. Therefore, the pulse of the symbol interval is generated based on the position.

【0080】

Subsequently, the processing of the timing chart described with reference to FIG. 7 will be described in more detail with reference to the flowchart of FIG.

【0081】

With reference to FIG. 8, when the operation of the coarse symbol detection circuit 326 is started (step S100), the value of N of the counting variable is first reset to 1 (step S102).

【0082】

Subsequently, the coarse symbol detection circuit 326 acquires a tentative 0th pulse position based on the first pulse from the peak detection circuit 322 as described in FIG. 7A (step S104).

【0083】

After acquiring the tentative 0th pulse position, the coarse symbol detection circuit 326 ignores a predetermined number of rear-neighboring pulses (step S106) and acquires the original position of the 0th pulse (step S108).

【0084】

With the 0th pulse acquired in this way as a reference, it is determined whether or not the pulse exists both before and after the activation time of the next symbol clock signal (step S110).

【0085】

If both pulses are present, the preceding and near pulse is ignored with respect to the reference point of the symbol clock (step S112), and the Nth pulse position is acquired by the pulse immediately after the reference point of the symbol clock (step S112). Step S114).

【0086】

Subsequently, it is determined whether or not the interval between the 0th pulse position and the Nth pulse position substantially coincides with the symbol interval × N (step S116). At this time, if the difference between the two is within several clocks and it is determined that they are almost the same, then the value of the variable N is incremented by 1 (step S118), and the value of the variable N is the specified number. It is determined whether or not L has been reached (step S120).

【0087】

If the variable N has not reached the specified number L, the process returns to step S110 again.

【0088】

On the other hand, when the variable N reaches the specified number L, a symbol pulse for the symbol pulse period is generated according to the symbol clock with reference to the 0th pulse position (step S122), and the process ends (step). S140).

【0089】

On the other hand, in step S110, if it cannot be said that pulses exist both before and after the activation time of the next symbol clock signal, the Nth pulse position is acquired (step S130). At this time, the method of acquiring the Nth pulse position is not particularly limited, but the method is performed in the same manner as when the 0th pulse position is acquired in steps S104 to S108 for the group of pulse signals appearing next. be able to.

【0090】

Subsequently, the Nth pulse position is set as the 0th pulse position (step S132). After that, the value of the variable N is reset to 1 again (step S134).

【0091】

Further, even if it cannot be said that the interval between the 0th pulse position and the Nth pulse position substantially coincides with the symbol interval × N in step S116, the process proceeds to step S132.

【0092】

Through the above processing, the coarse symbol detection circuit 326 can use the pulse signal to generate a symbol pulse that substantially matches the symbol boundary and has a period that matches the symbol interval.

【0093】

Therefore, the required period length delay memory 333 only needs to have a capacity corresponding to the required period length, and even if the symbol period becomes long in the OFDM system signal, the circuit scale is suppressed and the OFDM transmission system is used. It is possible to detect the symbol period.

【0094】

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

【0095】

[Effect of the invention]

As described above, according to the present invention, it is possible to significantly reduce the scale of the demodulation circuit in the digital signal receiving device for receiving the OFDM signal.

[Simple explanation of drawings]

[Figure 1]

It is a schematic block diagram which shows the whole structure of the digital signal receiving apparatus 1000 of this invention.

[Figure 2]

It is a block diagram which shows the structure of the OFDM demodulation part 102 in FIG.

[Fig. 3]

It is a block diagram for demonstrating the structure of the OFDM symbol period detection circuit 300 shown in FIG.

[Fig. 4]

It is a timing chart for demonstrating the operation of the memory control circuit 320.

[Fig. 5]

It is a block diagram of a memory control unit 320.

[Fig. 6]

The output waveform diagram of the absolute value addition circuit 305, the peak detection circuit 322, the coarse symbol detection circuit 326, and the control signal generation circuit 328 is shown.

[Fig. 7]

It is a timing chart for demonstrating the operation of the coarse symbol detection circuit 326.

[Fig. 8]

It is a flowchart for demonstrating the operation of the coarse symbol detection circuit 326.

[Fig. 9]

It is a block diagram which shows the conventional OFDM symbol period detection circuit 500.

[Fig. 10]

It is a waveform diagram which shows the OFDM modulation signal.

[Fig. 11]

It is a timing chart for demonstrating the operation of the symbol period detection circuit 500 shown in FIG.

[Fig. 12]

It is a timing chart for demonstrating the peak signal and the signal processing performed by the IIR filter 506 for the peak signal.

[Explanation of symbols]

100 Tuner, 102 OFDM Demodulator, 104 TS Decoder, 110 MPEG Decoder, 120 Addition Sound Generator, 122 PCM Decoder, 130 On-Screen Display Processing Unit, 144 Arithmetic Processing Unit, 146 High Speed Digital Interface, 148 Built-in Storage Device, 150 Modem , 152 card interface, 160 synthesizer, 162 audio output terminal, 164 video output terminal, 180 external storage device, 200 A / D converter, 202 I / Q separator, 204 carrier synchronizer, 208 FFT circuit, 210 AFT circuit , 212 frame decoding circuit, 214 equalization circuit, 216 frequency deinterleaved circuit, 218 hour deinterleaved circuit, 220 demapping circuit, 222 bit deinterleaved circuit, 224 bitabi decoding circuit, 228 TS playback circuit, 230 RS decoding circuit, 232 Guard interval correlation detector, 234 symbol synchronization circuit, 236 mode guard setting / judgment unit, 238 clock synchronization / playback circuit, 300 OFDM symbol period detection circuit, 301 Input terminal, 302 effective symbol period delay memory, 303 correlator, 304 moving average circuit, 305 absolute value adder circuit, 306 IIR filter, 308 symbol pulse generation circuit, 311 terminal, 320 memory control circuit, 333 required period length delay memory, 310 mode judgment circuit, 311 guard judgment circuit, 331 coefficient circuit, 332 adder, 1000 digital broadcast receiver, 1002 audio output, 1004 display.