Non-volatile memory

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a non-volatile storage device that can be electrically erased / written.

【0002】

[Conventional technology]

FIG. 8 shows a conventional non-volatile storage device 801 that can be electrically erased / written in a fixed time.

【0003】

It is provided with a memory cell transistor array 802 in which a memory cell transistor having a floating gate is arranged. Around this memory cell transistor array 802, there is a decoder circuit 806 that selects bit lines and word lines, a sense amplifier circuit 807 that reads memory cell data, and a decoder circuit 806 that controls the high voltage required for erasing / writing. A regulation circuit 805 for output, a booster circuit 804 for generating a high voltage for erasing / writing, and a control logic circuit 803 for controlling circuit operation based on a signal input from the outside are provided.

【0004】

The erase / write operation will be described. During the erase / write operation, the control logic circuit 803 operates the booster circuit 804 to generate a high voltage required for the erase / write. At this time, the control logic circuit 803 outputs to the regulation circuit 805 whether the operation state is the erasing operation or the writing operation.

【0005】

This high voltage is applied to the regulating circuit 805 and determined to a value according to the erasing operation or writing operation mode, and is always controlled to a constant voltage for each operation mode. This controlled high voltage is applied to any memory cell transistor in the memory cell transistor array 802 selected by the decoder circuit 806 for a certain period of time in accordance with the erasing or writing operation.

【0006】

The threshold voltage of the memory cell transistor is controlled by applying a high voltage to the memory cell transistor. That is, when erasing / writing the data of the memory cell transistor, the memory cell transistor is always applied with a constant voltage for a certain period of time. By the above operation, the memory cell transistor is erased / written.

【0007】

Next, the read operation will be described. To read the data written to the memory cell transistor, the decoder circuit 806 selects an arbitrary address in the memory cell transistor array 802, and the sense amplifier circuit 807 selects the drain voltage of the memory cell transistor in the decoder circuit 806. Is applied to convert the value of the flowing drain current into a voltage to read out the memory cell transistor.

【0008】

That is, when reading the data of the memory cell transistor, a constant drain voltage is always applied to the memory cell transistor, and the data is read according to a constant criterion. By the above operation, the memory cell transistor is read out.

【0009】

[Problems to be Solved by the Invention]

As described above, since a high voltage is applied to the memory cell transistor at the time of erasing / writing, a high electric field is applied to the thin tunnel oxide film between the floating gate of the memory cell transistor and the surface of the Si substrate, which is damaged.

【0010】

Therefore, as the erasing / writing operation is repeated, the tunnel oxide film gradually deteriorates and the device characteristics of the memory cell transistor deteriorate. In addition, this high voltage at the time of erasing / writing is set to a high value at the design stage in consideration of manufacturing variations, inspection margins, and a decrease in ability after the device characteristics deteriorate due to repeated rewriting, so inspection is performed. It is necessary to apply a high voltage at all times during the period of use from the start to the lifetime of the EEPROM.

【0011】

Therefore, as shown in FIG. 9, an excessive voltage stress more than necessary is applied to the memory cell transistor at the initial stage of the rewrite life of the EEPROM, and the memory cell transistor has a threshold voltage after erasing and a threshold voltage after writing. The amplitude of the threshold voltage becomes large, and a particularly large electric field is applied to the tunnel oxide film at the beginning of the write operation after erasing and at the beginning of the erasure operation after writing, which is one of the factors that shorten the erasure / write life of the EEPROM. It has become. There is a problem that the rewrite life is shortened due to such erasing / writing voltage stress.

【0012】

An object of the present invention is to provide a non-volatile storage device capable of alleviating electrical stress on a memory cell transistor and significantly increasing the number of rewrites.

【0013】

[Means for solving problems]

The non-volatile storage device (EEPROM) of the present invention verifies the erasure / write depth by the sense amplifier circuit every time after the erasure / write operation, and the erasure / write depth does not satisfy the judgment level set in the sense amplifier circuit. In this case, by rewriting the data of the memory cell transistor that stores the control value of the voltage of the regulate circuit included in the memory cell transistor array and setting the high voltage to be used for subsequent erasing / writing higher than the existing value. The rewrite life of the EEPROM can be improved. That is, in the initial stage of the rewrite life of the EEPROM, the voltage applied to the memory cell transistor is reduced, and in the middle and late stages of the rewrite life, the voltage applied to the memory cell transistor is increased to obtain the memory cell transistor required as the EEPROM. It is characterized by being able to secure the threshold voltage of the above and ensuring a state in which normal operation is possible.

【0014】

Further, the non-volatile storage device (EEPROM) has a non-volatile memory cell transistor that stores the number of erases / writes, and is a circuit that verifies the erase / write depth by the sense amplifier circuit every fixed number of erases / writes. It is possible to reduce the number of times of verification of erasure / write depth.

【0015】

Further, the non-volatile storage device (EEPROM) has a redundant memory cell transistor for detecting and correcting data errors in the memory cell transistor array, includes an error detection and correction circuit, performs error detection during read operation, and causes errors. When detected, the high voltage used for subsequent erasure / writing is made higher than the existing value by rewriting the data of the memory cell transistor that stores the control value of the voltage of the regulate circuit included in the memory cell transistor array. Equipped with a circuit to set, it is possible to eliminate the verification operation of erasing / writing depth.

【0016】

The non-volatile storage device (EEPROM) is a flash EEPROM that rewrites while verifying the erasure / write depth by the verify operation each time the erasure / write time is applied in a plurality of times during the erasure / write operation. If the verification results in NG when the verify operation is performed after a certain erase / write time, the data of the memory cell transistor that stores the control value of the voltage of the regulate circuit included in the memory cell transistor array is rewritten and thereafter. The rewrite life of the flash EEPROM can be improved by providing a circuit that sets the high voltage used for erasing / writing higher than the existing value.

【0017】

Further, in the manufacturing method of the non-volatile storage device (EEPROM) of the present invention, the control value of the voltage of the regulated circuit used at the time of erasing / writing is individually set based on the verification result of the erasing / writing depth of each product. Since it is set, it is possible to suppress the variation in erasing / writing between products, optimize the stress on the memory cell transistor at the initial stage of the rewriting life, and improve the rewriting life of the EEPROM.

【0018】

Further, the non-volatile storage device (EEPROM) of the present invention is a non-volatile storage device that stores a clock signal generation circuit for boosting operation in which the oscillation frequency can be changed in the booster circuit and a control value of the oscillation frequency of the clock signal generation circuit. The memory cell transistor array including the memory cell transistor of the above is provided, and when the erasure / write depth does not satisfy the judgment level set in the sense amplifier circuit, the clock signal generation circuit included in the memory cell transistor array is oscillated. Non-volatile memory cell that stores frequency control values The oscillation frequency of the clock signal generation circuit for boosting operation used for subsequent erasure / writing after rewriting the transistor data is set higher than the existing value and erased / written. By providing a circuit that sets the voltage control value of the regulator circuit used at times higher than the existing value, it is possible to improve the rewrite life of the EEPROM and reduce the power consumption at the initial stage of the rewrite life.

【0019】

Further, the non-volatile storage device (EEPROM) of the present invention has a bias generating circuit that can change the voltage applied to the memory cell transistor at the time of reading in the sense amplifier circuit, and a non-volatile storage that stores the control value of the bias generating circuit. A memory cell transistor array including the memory cell transistors of the above is provided, and when the erasure / write depth does not satisfy the judgment level set in the sense amplifier circuit, the control value of the bias generation circuit included in the memory cell transistor array is provided. By providing a circuit that rewrites the data of the non-volatile memory cell transistor that stores the data and changes the setting of the voltage applied to the memory cell transistor array at the time of subsequent reading with respect to the existing value, the memory can be rewritten by rewriting the EEPROM. It is possible to increase the drain current even after the drain current of the cell transistor has decreased, and it is possible to improve the rewrite life of the EEPROM and reduce the power consumption at the initial stage of the rewrite life.

【0020】

With this configuration, the erasure / write voltage stress is reduced at the initial stage of the EEPROM rewrite life, and after the device characteristics deteriorate, the erasure / write / read voltage is set high again, which is not necessary for the memory cell transistor. By obtaining the threshold voltage, it is possible to secure a state in which normal operation can be performed as EEPROM.

【0021】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 7. (Embodiment 1) FIGS. 1 and 2 show (Embodiment 1) of the present invention.

【0022】

In FIG. 1, 101 is an EEPROM, 102 is a memory cell transistor array, 103 is a control logic circuit, 104 is a booster circuit, 105 is a regulate circuit, 106 is a decoder circuit, 107 is a sense amplifier circuit, and 108 is a regulate circuit setting value. It is a storage memory cell transistor, and the output signal of the sense amplifier circuit 107 is input to the regulation circuit 105.

【0023】

Here, except that the output signal of the sense amplifier circuit 107 shown in FIG. 1 is input to the regulate circuit 105 and the memory cell transistor 108 for storing the regulate circuit set value is provided in the memory cell transistor array 102. Is basically the same as the conventional EEPROM shown in FIG.

【0024】

The erasing / writing operation in such an apparatus of the present invention will be described. During the erasure / write operation, the control logic circuit 103 operates the booster circuit 104 to generate a high voltage required for the erasure / write operation. At this time, the control logic circuit 103 outputs to the regulation circuit 105 whether it is an erasing operation or a writing operation. This high voltage is applied to the regulated circuit 105, and is controlled by the result of reading the data of the memory cell transistor 108 for storing the regulated circuit set value by the sense amplifier circuit 107 and the value according to the erase operation or the write operation mode. Is output.

【0025】

The high voltage output by this control is input to the decoder circuit 106 and applied to any memory cell transistor in the memory cell transistor array 102 selected by the decoder circuit 106 for a certain period of time according to the erasing operation or the writing operation. The threshold voltage of the memory cell transistor is controlled by applying a high voltage to the memory cell transistor.

【0026】

Here, the set value of the regulated voltage is set low in advance, and as shown in FIG. 2, the depth of Vt of the memory cell transistor becomes shallow as the EEPROM is deteriorated by erasing / writing, and the number of rewrites is within the guaranteed number of times. It is not necessary to satisfy the verification detection level, which is stricter than the read detection level. Further, after each time the EEPROM is erased / written, a verification detection level stricter than the read detection level is set and the verification determination is performed by the sense amplifier circuit 107. If this verification determination is passed, subsequent erasing / writing is also performed with the settings of the existing regulation circuit 105.

【0027】

However, if the verification determination fails, the output signal of the sense amplifier circuit 107 is input to the regulation circuit 105, the setting value of the data of the memory cell transistor 108 for storing the regulation circuit setting value is changed, and the data is erased from the next time onward. / Change the setting so that the high voltage value controlled and output by the regulator circuit 105 at the time of writing is higher than the existing voltage. By changing the data setting value of the memory cell transistor 108 for storing the regulated circuit setting value, the depth of Vt of the memory cell transistor after writing from the next time onward can be seen in the switching of the rewriting voltage in FIG. Can be secured.

【0028】

By repeatedly executing the above for the subsequent erasing / writing, the damage to the tunnel oxide film received during erasing / writing is alleviated as the memory cell transistor of the EEPROM, and the deterioration of the device characteristics is suppressed. The rewrite life can be improved. By the above operation, the memory cell transistor is erased / written.

【0029】

(Embodiment 2) FIG. 3 shows (Embodiment 2) of the present invention. 301 is an EEPROM, 302 is a memory cell transistor array, 303 is a control logic circuit, 304 is a booster circuit, 305 is a regulate circuit, 306 is a decoder circuit, 307 is a sense amplifier circuit, and 308 is a memory cell transistor for erasing / writing count storage. And 309 is a counter circuit.

【0030】

The difference between (Embodiment 2) and (Embodiment 1) is that a memory cell transistor 308 for storing the number of erases / writes and a counter circuit 309 are added. Reference numeral 108 denotes a memory cell transistor for storing the regulated circuit set value shown in (Embodiment 1).

【0031】

The difference between the erase / write operation in the apparatus of the present invention and the (first embodiment) example will be described. During the erase / write operation, the control logic circuit 303 stores the erase / write count for the memory cell transistor 308 for storing the erase / write count at the same time as the erase / write to the normal memory cell transistor, and then erases. / Write count The number of times data written in the memory cell transistor 308 is read by the sense amplifier circuit 307, and the read data is input to the counter circuit 309.

【0032】

In the counter circuit 309, when the number of times data reaches a specific number of times such as 1, 10, 100, 1000, 10000, 100000 times, the verification detection level stricter than the read detection level is set for the sense amplifier circuit 307. And make a verify judgment. The operation based on the verification determination result after this is the same as in (Embodiment 1).

【0033】

With this configuration, the same effect as described in (Embodiment 1) can be obtained even if the number of verification determinations is reduced to the minimum. (Embodiment 3) FIG. 4 shows (Embodiment 3) of the present invention.

【0034】

401 is EEPROM, 402 is memory cell transistor array, 403 is control logic circuit, 404 is booster circuit, 405 is regulate circuit, 406 is decoder circuit, 407 is sense amplifier circuit, 408 is redundant memory cell transistor for data error detection and correction. And 409 is an error detection and correction circuit. The difference between (Embodiment 3) and (Embodiment 1) is that a redundant memory cell transistor 408 for data error detection and correction and an error detection and correction circuit 409 are added. Reference numeral 108 denotes a memory cell transistor for storing the regulated circuit set value shown in (Embodiment 1).

【0035】

The difference between the operation of the device of the present invention and that of the device of the present invention (Embodiment 1) will be described. During the erase / write operation, the error detection and correction circuit 409 generates data to be written to the redundant memory cell transistor 408 for data error detection and correction, and at the same time as erasing / writing to the normal memory cell transistor, the redundant memory cell transistor for data error detection and correction. Write to 408.

【0036】

Also, during the read operation, the data of the redundant memory cell transistor 408 for data error detection and correction is read by the sense amplifier circuit 407 at the same time as the data of the normal memory cell transistor, and the read data is detected by the error detection and correction circuit 409 to detect the presence or absence of an error. To do. If the detection result by the error detection and correction circuit 409 is a pass, the read data is normal, and even if the detection result is a fail, the data corrected by the error detection and correction circuit 409 is output, so the read data to the outside. Becomes normal.

【0037】

However, since it can be determined that the erasure / write depth of the memory cell transistor is shallow based on the result of the error detection / correction circuit 409 correction, the regulation circuit is the same as in (Embodiment 1). Change the control voltage of 405.

【0038】

With this configuration, the same effect as described in (Embodiment 1) can be obtained without performing verification determination. (Embodiment 4) FIG. 5 shows (Embodiment 4) of the present invention.

【0039】

501 is a flash EEPROM, 502 is a memory cell transistor array, 503 is a control logic circuit, 504 is a booster circuit, 505 is a regulate circuit, 506 is a decoder circuit, 507 is a sense amplifier circuit, and 509 is a verify circuit. Reference numeral 108 denotes a memory cell transistor for storing the regulated circuit set value shown in (Embodiment 1).

【0040】

The difference between (Embodiment 4) and (Embodiment 1) is that it is a flash EEPROM and uses a verify circuit 509. The difference between the operation of the apparatus of the present invention and the device of the present invention (Embodiment 1) will be described.

【0041】

When the verification operation is performed after a certain erase / write time and the verification results in NG, the data of the memory cell transistor that stores the voltage control value of the regulator circuit 505 included in the memory cell transistor array is rewritten. It is configured to set the high voltage used for subsequent erase / write higher than the existing value.

【0042】

With this configuration, the same effect as that of the above (Embodiment 1) can be obtained even in the flash EEPROM provided with the verify circuit 509. (Embodiment 5) In the inspection step of the non-volatile storage device (EEPROM) of the above (Embodiment 1), the product is manufactured by executing the following steps.

【0043】

In the EEPROM inspection process, the erasure / write depth of each product is verified, and based on the result, the control value of the voltage of the regulate circuit used at the time of erasure / write is set for each product. Set to the value storage memory cell transistor 108.

【0044】

Needless to say, the setting of the memory cell transistor 108 for storing the regulated circuit setting value can be rewritten later depending on the verification determination result. By this procedure, the variation in characteristics between products can be alleviated. It should be noted that the same can be performed in (Embodiment 2) to (Embodiment 4).

【0045】

(Embodiment 6) FIG. 6 shows (Embodiment 6) of the present invention. 601 is EEPROM, 602 is memory cell transistor array, 603 is control logic circuit, 604 is booster circuit, 605 is regulate circuit, 606 is decoder circuit, 607 is sense amplifier circuit, 608 is for oscillating frequency storage of clock signal generation circuit. The memory cell transistor, 609, is a clock signal generation circuit.

【0046】

The difference between (Embodiment 6) and (Embodiment 1) is that the memory cell transistor 608 for storing the oscillation frequency of the clock signal generation circuit and the clock signal generation circuit 609 are used. Reference numeral 108 denotes a memory cell transistor for storing the regulated circuit set value shown in (Embodiment 1).

【0047】

Next, the difference between the operation of the device of the present invention and that of the device of the present invention (Embodiment 1) will be described. A clock signal generation circuit 609 for boosting operation capable of changing the oscillation frequency is provided in the block of the booster circuit 604, and a memory cell transistor 608 for storing the oscillation frequency of the clock signal generation circuit 609 is provided in the memory cell transistor array 602. When the erasure / write depth does not meet the judgment level set in the sense amplifier circuit 607, the memory cell is a non-volatile memory cell that stores the control value of the oscillation frequency of the clock signal generation circuit 609 included in the transistor array 602. The oscillation frequency of the clock signal generation circuit 609 for boosting operation used for subsequent erasing / writing after rewriting the transistor data is set higher than the existing value, and the control value of the voltage of the regulated circuit used for erasing / writing. Is configured to be set higher than the existing value.

【0048】

With this configuration, it is possible to reduce the power consumption at the initial stage of the rewrite life of the EEPROM and obtain the same effect as that of the above (Embodiment 1). (Embodiment 7) FIG. 7 shows (Embodiment 7) of the present invention.

【0049】

701 is an EEPROM, 702 is a memory cell transistor array, 703 is a control logic circuit, 704 is a booster circuit, 705 is a regulate circuit, 706 is a decoder circuit, 707 is a sense amplifier circuit, and 708 is a memory for storing control values of a bias generation circuit. The cell transistor, 709, is a bias generation circuit. Reference numeral 710 is a bias circuit of the memory cell transistor array 702. The difference between (Embodiment 7) and (Embodiment 1) is that the memory cell transistor 708 for storing the control value of the bias generation circuit and the bias generation circuit 709 are used. Reference numeral 108 denotes a memory cell transistor for storing the regulated circuit set value shown in (Embodiment 1).

【0050】

Next, the difference between the operation of the device of the present invention and that of the device of the present invention will be described. The sense amplifier circuit includes a bias generating circuit 709 capable of changing the drain applied voltage to the memory cell transistor at the time of reading, and a memory cell transistor array 702 including a memory cell transistor 708 for storing the control value of the bias generating circuit. If the erasure / write depth does not meet the judgment level set in the sense amplifier circuit, the data of the non-volatile memory cell transistor that stores the control value of the bias generation circuit 709 included in the memory cell transistor array 702 is stored. By providing a circuit that sets the drain applied voltage of the sense amplifier circuit 807 used for subsequent reading after rewriting higher than the existing value, the drain current is increased even after the drain current of the memory cell transistor drops due to the rewriting of the EEPROM. This makes it possible to improve the rewrite life of the EEPROM and reduce the power consumption at the initial stage of the rewrite life.

【0051】

By the above operation, it is possible to reduce the power consumption at the initial stage of the rewrite life of the EEPROM and obtain the same effect as that of the above (Embodiment 1). In this (Embodiment 7), the configuration of the control value storage memory cell transistor 708 and the bias generation circuit 709 is added to the configuration of (Embodiment 1), but the regulation circuit setting value storage is used. Even if the memory cell transistor 108 and its related parts are not provided, better performance can be obtained as compared with the conventional case.

【0052】

[Effect of the invention]

As described above, according to the EEPROM of the present invention, the voltage applied to the memory cell transistor is reduced in the initial stage of the rewrite life of the EEPROM, and the voltage applied to the memory cell transistor is increased in the middle and the latter stages of the rewrite life. It is possible to secure the threshold voltage of the memory cell transistor required as the EEPROM by increasing the value, and by ensuring a state in which normal operation is possible, there is an effect that the rewrite life of the EEPROM can be significantly improved.

【0053】

Further, in the initial stage of the rewriting life of the EEPROM, there is an effect that the oscillation frequency of the clock signal generation circuit for boosting operation can be suppressed to a low level to reduce the power consumption.

【0054】

Further, in the initial stage of the rewriting life of the EEPROM, there is an effect that the drain applied voltage of the sense amplifier circuit can be suppressed to a low level to reduce the power consumption.

[Simple explanation of drawings]

[Figure 1]

Configuration diagram of the memory cell transistor array of EEPROM according to (Embodiment 1) of the present invention and its peripheral portion. [Figure 2]

The figure which showed the number of times of rewriting and the change of Vt of the same embodiment [Fig. 3]

Configuration diagram of the memory cell transistor array of EEPROM according to (Embodiment 2) of the present invention and its peripheral portion. [Fig. 4]

Configuration diagram of the memory cell transistor array of EEPROM according to (Embodiment 3) of the present invention and its peripheral portion. [Fig. 5]

Configuration diagram of the memory cell transistor array of EEPROM according to (Embodiment 4) of the present invention and its peripheral portion. [Fig. 6]

EEPROM memory cell transistor array according to (Embodiment 6) of the present invention and its configuration diagram. [Fig. 7]

Configuration diagram of the memory cell transistor array of EEPROM according to (Embodiment 7) of the present invention and its peripheral portion. [Fig. 8]

Configuration diagram of a conventional EEPROM memory cell transistor array and its peripheral parts [Fig. 9]

The figure which showed the rewrite number of the memory cell transistor of the conventional EEPROM and the change of Vt [Explanation of symbols]

101,301,401,601,701 EEPROM 501 Flash EEPROM 102,302,402,502,602,702 Memory cell transistor array 103,303,403 Control logic circuit 503,603,703 Control logic circuit 104,304,404,504,604,704 Booster circuit 105,305,405,505,605,705 Regulator circuit 106,306,406,506,606,706 Decoder circuit 107,307,407,507,607,707 Sense amplifier circuit 108 Regulator circuit Set value storage memory cell transistor 308 Memory cell transistor for erasing / writing count storage 408 Redundant memory cell transistor for data error detection and correction 608 Memory cell transistor for oscillating frequency storage of clock signal generation circuit 708 Memory cell transistor for storing control value of bias generation circuit 309 counter circuit 409 Error detection and correction circuit 509 verify circuit 609 Clock signal generation circuit 709 bias generation circuit