Improvement in or about data transmission system

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to data transmission and data coding in general, especially the transmission of coded data symbols transmitted as differential signals.

【0002】

[Conventional technology]

A block diagram of a known differential data transmission system known as a Low Voltage Differential Swing (LVDS) system is shown in Figure 1. The system includes a differential transmitter 1 and a differential receiver 2. The first and second outputs of differential transmitter 1 generate voltage signals on conductors 3 and 4, respectively, and the potential difference between conductors 3 and 4 is 100Ω, including two 50Ω resistors 7 and 8. Induces the current flowing through the load. The first terminal of the resistor 7 is connected to the conductor 3, the second terminal of the resistor 7 is connected to the first terminal of the resistor 8, and the second terminal of the resistor 8 is the second conductor 4. It is connected to the. The first resistor 7 and the second resistor 8 meet at the connection point 9 held at 1.2V. That 1.2V voltage is the common mode voltage level within the LVDS system.

【0003】

The voltage on one of the conductors 3 and 4 is set to 1.4V and the voltage on the other conductor is set to 1.0V, so that the conductors are 0.2V above or below the common mode voltage level. Therefore, a 4mA current (0.4V / 100Ω) flows through resistors 7 and 8. The sense of current flow represents the symbol to be transmitted.

【0004】

The signals on conductors 3 and 4 are transmitted through transmission lines 10 and 11 and the conductors at the receiver ends are identified by 5 and 6 (conductor 5 is coupled to conductor 3 and conductor 6 is on conductor 4). Combined). Conductors 5 and 6 are terminated by a 100Ω load, which contains two 50Ω resistors 12 and 13. The first terminal of the resistor 12 is connected to the conductor 5, the second terminal of the resistor 12 is connected to the first terminal of the resistor 13, and the second terminal of the resistor 13 is the second conductor 6. It is connected to the. The voltages on conductors 5 and 6 are 1.4V and 1.0V (or vice versa), and induce a current of 4mA through their resistors. The direction in which the current flows represents the transmitted symbol, and it is that direction that the receiver 2 is configured to detect.

【0005】

The system of FIG. 1 is also shown in FIG. 2, but shows the implementation of transmitter 1 in detail, and the current element and connection corresponding to those in FIG. 1 have the same reference numerals. Transmitter 1 in Figure 2 contains an 8mA current source 14, which is connected to the sources of the MIMO transistors 15 and 16, and the drains of these transistors are connected to the drains of the MIMO transistors 17 and 18, respectively. Has been done. The sources of the NMOS transistors 17 and 18 are coupled to a second 8mA current sink 19. The drains of transistors 15 and 17 are also connected to the first terminal of the resistor 7, the second terminal of the resistor 7 is connected to the first terminal of the resistor 8, and the second terminal of the resistor 8 is connected. Is connected to the drains of transistors 16 and 18. The gate inputs of transistors 15 and 17 are coupled to the first input 20. The gate inputs of transistors 16 and 18 are coupled to the second input 21. The drains of transistors 15 and 17 and the first terminal of the resistor 7 are coupled to the first output conductor 3. The drains of transistors 16 and 18 and the second terminal of the resistor 8 are coupled to the second output conductor 4. To facilitate analysis of the transmitter circuit, resistors 12 and 13 that terminate the far ends of transmission lines 10 and 11 are also shown in FIG.

【0006】

The transitioners 15-18 and the current source 14 and the current sink 19 form a differential amplifier with inputs 20 and 21 and output conductors 3 and 4. The midpoint 9 of the 100Ω load of the differential amplifier is held at 1.2V, as in Figure 1.

【0007】

With input 21 high and input 20 low (eg, logic 1 and logic 0, respectively), transitions 15 and 18 are on and transitions 16 and 17 are off. Therefore, the current flows from the current source 14 to the current sink 19 via the transistors 15 and 18 and through the loads 7 and 8. Similarly, current flows through the termination load, including resistors 12 and 13. Since both of these loads are 100Ω, 8mA splits, 4mA flows through loads 7 and 8, and 4mA flows through loads 12 and 13. Therefore, there is a 0.4V voltage drop across resistors 7 and 8, so conductors 3 and 5 are at 1.4V, and conductors 4 and 6 are at 1.0V.

【0008】

The 100Ω differential termination of the transmission signal has a number of advantages in addition to providing a suitable termination for the transmission line. For example, the transmitted signal does not depend on the power level at the receiver. Therefore, the supply rail difference does not induce any common mode current.

【0009】

As the bandwidth demands on data transmission systems increase, the demand for high-speed parallel transmission of data is increasing. The use of the systems of FIGS. 1 and 2 for such parallel data transmission (ie, the use of such systems in parallel) has a number of drawbacks. The pin count is high because each differential connection (ie, each bit of data) requires two pins. A resistor at the receiver end consumes the same amount of power as a corresponding resistor at the transmitter end, and thus consumes more power at both the transmitter and the receiver. Supplying control signals also requires signal lines, which add to the pin count and power overhead.

【0010】

[Problems to be Solved by the Invention]

It is an object of the present invention to solve or alleviate some or all of the problems listed above.

【0011】

[Means for solving problems]

The present invention provides a signal for transmitting a symbol over a set of at least three parallel channels, the signal being an active signal on each of two of those channels and an inactive signal on the remaining channels for each symbol. The symbols are distinguishable by which two of the channels have the active signal. Preferably, the two activation signals are of different form, allowing them to be distinguished from each other, thereby further distinguishing the symbols.

【0012】

In one embodiment, one of the active signals is an electrical signal at the first voltage level and the other active signal is an electrical signal at the second voltage level. An inert signal is an electrical signal at a voltage level between the first and second voltage levels, eg, electricity at a substantially mid-voltage level between the first and second voltage levels. It is a signal.

【0013】

In an alternative embodiment, one of the active signals is supplied as a current in the first direction and the other active signal is supplied as a current in the second direction, with the first and second directions being opposite to each other. is there. The Inactive signal may have a current that is substantially zero.

【0014】

The present invention also provides a method of transmitting data, which comprises using the signals of the present invention to encode the data as a sequence of symbols.

【0015】

The present invention also provides an encoder that transmits a data symbol from a set of at least three terminals, where the encoder supplies an active signal on each of the two terminals of the set for each of the symbols, while the remaining terminals of the set. It is configured to supply an inert signal on top. Preferably, the encoder is configured to supply the two active signals in different forms so that the active signals are distinguished from each other.

【0016】

In one embodiment, the encoder is configured to supply one of the active signals as an electrical signal at the first voltage level and another active signal as an electrical signal at a second different voltage level. To. The encoder is at an electrical signal at a voltage level intermediate between the first and second voltage levels of the active signal, eg, a substantially midway voltage level between the first and second voltage levels. It is configured to supply an inert signal as an electrical signal.

【0017】

In an alternative embodiment, the encoder is configured to supply one of the active signals as a first-direction current and the other active signal as a second-direction current. The directions of 2 are opposite to each other. The Inactive signal may be supplied by not actively supplying the current signal to the remaining terminals.

【0018】

The encoder may contain a first set and a second set of switches, one switch from each of the first and second sets is connected to each one of the terminals, and the encoder is the first set of switches. The switch is configured to activate one of the active signals on the terminal to which the selected one of the set is connected, and the encoder is connected to the selected one of the second set of switches. It is configured to activate the switch to supply other activation signals on the terminals. The remaining switches may be inactive to provide an inert signal to the remaining or each remaining terminal. Each switch in the first set of switches may be coupled to the first voltage level and each switch in the second set of switches may be coupled to the second voltage level. Each switch in the first set of switches may be coupled to a first current source and each switch in the second set of switches may be coupled to a second current source. Each terminal of the encoder may be coupled to a common connection point via a resistor, and the common connection point is the voltage level on the terminal carrying a certain voltage level / first active signal and the second. It may be at a voltage level intermediate to the voltage level on the terminal carrying the activation signal.

【0019】

The present invention further provides a decoder that receives a data symbol that appears in a set of at least three terminals, which is detecting and responding to which two of the terminals have an active signal and which symbol is being received. Is configured to identify.

【0020】

Preferably, the decoder detects which of the two active signals is of the first form and which is of the second form, and uses that information for said identification of the received symbol. It is configured as follows.

【0021】

The decoder may be configured to detect which of the terminals is at the first active voltage level and which of the terminals is at the second active voltage level, the information being the identification of the received symbol. Used for. Decoders may be configured to compare the voltage on their terminals with a reference voltage.

【0022】

The present invention further provides systems, each containing an encoder and decoder as described above, and the encoder features of the system are selected so that the encoder and decoder adjust appropriately to transfer data between them. Will be done.

【0023】

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described with reference to the accompanying drawings.

【0024】

Figure 3 shows a representation of the data symbols that can be transmitted using the systems in Figures 1 and 2. Figure 3 shows resistors 22 and 23 (receiver resistors in Figures 1 and 2) connected in series between connection points P1 and P2, which would be connected to the conductor from the transmitter, respectively. (Equivalent to 12 and 13). The first data symbol is represented by the current flowing from connection point P1 to connection point P2. The second data symbol is represented by the current flowing from the connection point P2 to the connection point P1.

【0025】

The present invention extends symbol transmission by adding a third resistor, as shown in FIG. FIG. 4 shows resistors 22, 23, and 24 in which the first terminal is connected to the connection points P1, P2, and P3, respectively, and the second terminal is connected to the common connection point Z, respectively. Figure 4 shows six symbols that can be transmitted using that configuration of the resistor. These symbols are the current flowing from the connection point P1 to the connection point P2 via the resistors 22 and 23, the current flowing from the connection point P1 to the connection point P3 via the resistors 22 and 24, and the connection from the connection point P2. Current flowing from point P3 via resistors 23 and 24, current flowing from connection point P3 to connection point P1 via resistors 24 and 22, connection point P2 to connection point P1 via resistors 23 and 22 The current that flows from the connection point P3 to the connection point P2 via the resistors 24 and 23.

【0026】

As shown in FIG. 5, a fourth resistor 25 may be added, which can be coupled between the connection point 24 and the common connection point Z to transmit six more symbols. These symbols are the currents that flow from the connection point P4 to each of the connection points P1, P2, and P3, and vice versa, the current that flows from each of the connection points P1, P2, and P3 to the connection point P4. Further resistors may be added.

【0027】

In a preferred embodiment of the present invention, a set of resistors is adopted in the transmitter and receiver by the methods of FIGS. 1 and 2, and each of the connection points is connected to each transmission line.

【0028】

For each symbol transmitted using the expansion system described above, there are two active junctions, and the symbol transmitted depends on which of the junctions is active and also flows through those two active junctions. It is represented by the direction of the electric current.

【0029】

Therefore, the system of the present invention can have N connection points, where N 3. In such a system, current can flow from any one of the N connection points and be restored through any one of the remaining N-1 connection points. Therefore, the total number (S) of symbols that can be transmitted and thus distinguished is given by:

【0030】

[Number 1]

S = N (N-1) [0031]

The number of bits of information (B) contained in one such symbol is given by:

【0032】

[Number 2]

B = log₂(S) Here, log₂Is the base 2 logarithm.

【0033】

In general, B is a non-integer value. The transmission system, in a simple example, is given the number (B)_U) Is driven by a data encoder operating on the available bits, the number of which is given by:

【0034】

[Number 3]

B_u= int (B) Here, int (B) is the integer part of B.

【0035】

The number of symbols available (S) is given by:

【0036】

[Number 4]

S_u=2^Bu 【0037】

There will be a large number of unused symbols, which may be used for other purposes, such as control signals. One of the unused symbols can also be used to display invalid data, such a symbol that there is no data transmitted to the channel, but nevertheless, for example, that channel is not working. As the receiver knows, it may be transmitted when it is desirable to transmit the symbol anyway. Another use of the spare symbol is to replace the second of the repeating symbols to ensure that the adjacent symbols are always different. These are useful for transmission links that require clock recovery at the receiver end. This is because such a "ditto" symbol D guarantees an edge in the transmitted data. If the symbol S is repeated several times, the column that can be transmitted is SDSD ... If there is an extension period of invalid data, the edges in that data can be maintained by alternating the malformed data symbols with the duplicate symbols.

【0038】

In the N connection system described above, the N input / output pin is the data B_uRequired to send bits. In traditional differential systems, this is 2B_uWill require input / output pins. These ratios give a pin usage factor. This is equal to 75% for 3-connection point systems and further down to an optimal value of 62.5% for 5-connection point systems. For N> 5, pin utilization generally increases. However, it stays below 100% for N <14.

【0039】

The power dissipation of the data link is constant regardless of the number of connection points. This is because there are always only two active junctions. Relative power dissipation compared to the distribution of equal numbers of bits using a connection differential transmission system is (1 / B)._u).

【0040】

The number of connection points that can be used is limited only by the practicability of the physical implementation of the transmission system. For the most practical purposes, it is expected that a 3, 4, or 5 junction system will probably provide the optimal solution.

【0041】

Although the systems have been described by load resistors, they are not an essential feature of the invention. Even without them, the symbol transmitted over a set of three or more conductors depends on which conductor carries the current in one direction and which conductor carries the current in the opposite direction, or to this. Instead, it is still distinguished by which conductor is at high voltage and which is at low voltage.

【0042】

A compatible transmitter used in an N connection point (ie, N conductor) system according to the present invention is shown in FIG. The transmitter is an incoming data bit (B)_u) And two sets of control signals (C)_P1From C_P2And C_N1From C_Nn) Is generated by the encoder 26 and a set of output for transmission that captures the control signal (P).₁From P_n) Consists of transmitters as a whole indicated by reference numeral 27.

【0043】

The transmitter 27 includes a current source 28 and a current sink 29, MIMO transistors 30 to 32, MIMO transistors 33 to 35, resistors 36 to 38, and conductors 39 to 41. The current source 28 is coupled to the respective sources of the MIMO transistors 30 to 32, the drains of the transistors 30 to 32 are connected to the drains of the MIMO transistors 33 to 35, respectively, and the sources of the NMOS transistors 33 to 35. Are all connected to the current sink 29. The drains of the MOSFET transistors 30-32 and the NMOS transistors 33-35 are also connected to the first terminals of resistors 36-38, respectively. Each second terminal of resistors 36-38 is held at 1.2V (common mode voltage). Each of the gates of the photoresist transistors 30 to 32 is the output C of the data encoder 26._P1, C_p2, And C_PnThe gates of the NMOS transistors 33 to 35 are connected to the output C of the data encoder, respectively._N1, C_N2, And C_NnIt is connected to the.

【0044】

One of the photoresist transistors 30 to 32 is the input C_P1From C_PnTurn on by making one of the lows. Similarly, one of the NMOS transistors 33-35 has an input C._N1From C_NnTurn on by setting one of them to high. For example, C_P1Low and C_N2Is high (and C_P2And C_PNHigh and C_N1And C_NnAt low), the MOSFETs 30 and 34 are on, and the rest of the transistors are off. In such a situation, there is a current path from the current source 28 to the resistor 36 via the MIMO transistor 30 and from the resistor 37 to the current sink 29 via the MIMO transistor 34. Further, the second terminals of the resistors 36 and 37 are connected so that current flows from the current source 28 to the current sink 29 via their resistors and transistors 30 and 34. Transistor selection is signal C_P1From C_PnWhich one is low and signal C_N1From C_NnThis is done by the data encoder 26, which selects which one of the is high.

【0045】

In the example given above, output 39 is high (to 1.4V) and output 40 is low (to 1.0V). The remaining output (in this case only output 41, but in an N junction system there would be such an output of N-2) is at 1.2V (common mode voltage). Therefore, the transmitted symbols are represented by the active output (the output that is not in the common mode voltage) and the polarity of the active output (ie, which output is higher and which is lower than the common mode voltage). When the load is connected to those outputs, this polarity is, of course, equivalent to the direction of the current at those two active outputs.

【0046】

FIG. 7 shows signals P1 to P3 on conductors 39-41 from a simulation of the circuit of FIG. 6 operating at a data transfer rate of 500 Mb / s based on 0.35 μm CMOS technology. Initially P1 is high, P3 is low, and P2 is in common mode voltage. After 4ns, P3 shifts to high, P2 shifts to low, and P1 shifts to the common mode voltage. Finally, after 8ns, P2 transitions to high, P3 transitions to low, and P1 transitions to the common mode voltage. Therefore, we show four of the six possible data symbols.

【0047】

FIG. 8 shows a circuit capable of receiving and decoding a signal transmitted using the transmitter of FIG. The receiver of FIG. 8 is composed of a receiver circuit and a data decoder 43 as a whole indicated by reference numeral 42. The receiver 42 is the output P of the transmitter 27.₁From P_NAnd two sets of signals, R_P1From R_PNAnd R_N1From R_NNOccurs. The data decoder 43 is a signal R_P1From R_PNAnd R_N1From R_NNData signal B captured and transmitted by transmitter 27_uTo play.

【0048】

The receiver 42 includes sub-circuits 44 and 44'. The partial circuit 44 includes a current source 45, a MIMO transistors 46 to 48, and a current source 49 to 51, and the signal R._P1From R_PNOccurs.

【0049】

The current source 45 supplies the current I and is coupled to each source of the MIMO transistors 46-48. The drains of the photoresist transistors 46 to 48 are coupled to current sources 49 to 51, respectively, and each of these current sources supplies current I / N. Each of the gates of the photoresist transistors 46 to 48 has an input P.₁, P₂, And P_NIt is connected to the. The drains of the photoresist transistors 46 to 48 are the signals R, respectively._P1From R_pNTo supply.

【0050】

The partial circuit 44'contains a current source 52-54, an NMOS transistor 55-57, and a current source 58, and has a signal R._N1From R_NNOccurs.

【0051】

The current sources 52 to 54 each have a value I / N and are coupled to the drains of the NMOS transistors 55 to 57, respectively. Each source of the NMOS transistors 55-57 is coupled to a current source 58, which has a value N. Each gate of the NMOS transistors 55-57 has an input P₁, P₂, And P_NIt is connected to the. The drains of the NMOS transistors 55 to 57 are signal R, respectively._N1From R_NNTo supply.

【0052】

Input P₁Is high and input P₂Is low and input P_NIs in the common mode voltage, for example. In the partial circuit 44, the gates of the MIMO transistors 46 to 48 will be at 1.4V, 1.0V, and 1.2V, respectively. Since these transistors are designed with sufficient gain, under these circumstances, the transistor with the lowest input voltage, namely transistor 47, conducts most of the current and the other transistors 46 and 48 are substantial. Turns off. Therefore, the output R_P2Goes high via transistor 47 and outputs R_P1And R_PNIs low. Similarly, in a partial circuit 44', the gates of the NMOS transistors 55-57 will be at 1.4V, 1.0V, and 1.2V, respectively. Those transistors are designed so that only the transistor 55 is turned on under those circumstances. Therefore, the output R_N1Is low and output R_N2And R_NNWill be high.

【0053】

The output of the first subcircuit 44, which is high, indicates which of the MIMO transistors 30 to 32 in the transmitter of FIG. 6 was turned on. Similarly, the output of the second part circuit 44'in the row indicates which of the NMOS transistors 35-37 in the transmitter of FIG. 6 was turned on. The decoder 43 decodes this information and reproduces the data transmitted by the transmitter. Alternative implementations of transmitters and receivers are within the scope of the present invention. For example, the receiver in FIG. 8 has a signal line P.₁From P_nIt can be replaced by a number of comparators connected between each of them, and their comparator outputs are decoded to identify the signal line with the highest voltage and the signal line with the lowest voltage, and are therefore transmitted. Decode the symbol. For systems where N> 4, there are two or more lines at a common mode voltage, and a comparator operating on these signals therefore does not produce a reliable output. However, the output of such a comparator corresponds to a "don't care" condition in the decoding logic.

【0054】

[Effect of the invention]

Number of usable bits that can be encoded by the present invention (B)_uIn the above analysis of), we assumed that the set of bits would be encoded into a single symbol. However, it is possible to encode a set of bits into several symbols, which in some cases can lead to more efficient use. For example, two symbols in a three-point system can encode 6x6 = 36 states, which can be used to encode 5 bits of data, leaving 4 states. .. If those symbols were used alone, each would only be able to encode 2 bits, representing a total of 4 bits.

【0055】

In the above example, the transmitted symbol is represented by a constant voltage signal or a constant current signal. As is known for many other data transmission schemes, it is within the scope of the invention to represent the symbol as a variable signal, including, for example, edges or transitions.

【0056】

In the above example, the two transmission lines, i.e., the connection points are active, and it is possible to distinguish between them, as indicated by the arrows in Figures 3 and 4, and therefore of the lines. Make a distinction between the two symbols for each active pair. However, in a more general version of the invention, no distinction is made between those active lines. This halves the number of symbols available, but means that equivalent signals may be used on their active lines. In one example, the symbols are represented by a minority cycle of sine waves transmitted by the differential drive to their active lines. However, the receiver only responds to the presence of sinusoidal waveforms of the appropriate frequency, not the phase difference of the waveforms on those two active lines.

【0057】

The following sections are further disclosed with respect to the above description.

【0058】

(1) A signal for transmitting a symbol on a set of at least three parallel channels, the signal being an active signal on each of the two channels of the channel and an inactive signal on the remaining channels for each symbol. The symbol is a signal that can be distinguished by which two of the channels have the activation signal.

【0059】

(2) In the signal according to the first paragraph, the two active signals are different types of active signals so that the active signals can be distinguished from each other, whereby the symbol can be further distinguished. ..

【0060】

(3) In the signal described in paragraph 2, one of the active signals is an electric signal at the first voltage level, and the other active signal is an electric signal at the second voltage level.

【0061】

(4) In the signal described in paragraph 3, the inert signal is a signal that is an electric signal at a voltage level intermediate between the first voltage level and the second voltage level.

【0062】

(5) In the signal according to paragraph 4, the inert signal is a signal at a substantially intermediate voltage level between the first voltage level and the second voltage level.

【0063】

(6) In the signal described in paragraph 2, one of the active signals is supplied as a current in the first direction, and the other active signal is supplied as a current in the second direction. Signals that are opposite to each other in the second orientation.

【0064】

(7) In the signal according to paragraph 6, the inert signal is a signal having a current that is substantially zero.

【0065】

(8) An encoder that transmits a data symbol from a set of at least three terminals, supplying an activation signal to each of the symbols on the two terminals of the set, while the rest of the set. An encoder configured to supply an inert signal on a terminal.

【0066】

(9) The encoder according to paragraph 8, which is configured to supply the two activation signals in different forms so that the activation signals can be distinguished from each other.

【0067】

(10) The encoder according to paragraph 9, which supplies one of the active signals as an electrical signal at the first voltage level and supplies the other active signal as an electrical signal at a different second voltage level. An encoder configured to do.

【0068】

(11) The encoder according to paragraph 10, wherein the inert signal is supplied as an electric signal at a voltage level intermediate between the first voltage level and the second voltage level of the active signal. Encoder.

【0069】

(12) In the encoder according to paragraph 11, the inert signal is an encoder at a substantially intermediate voltage level between the first voltage level and the second voltage level.

【0070】

(13) The encoder according to paragraph 9, wherein one of the active signals is supplied as a current in the first direction and the other active signal is supplied as a current in the second direction. An encoder whose orientation and the second orientation are opposite to each other.

【0071】

(14) In the encoder according to paragraph 13, the inert signal is supplied by not actively supplying a current signal onto the remaining terminals.

【0072】

(15) The encoder according to any one of paragraphs 9 to 14, including the first set and the second set of switches, and from each of the first set and the second set. One switch is connected to each one of the terminals, and the encoder supplies one of the activation signals on the terminal to which the selected one switch of the first set of switches is connected. The encoder is configured to activate the selected one switch, and the encoder supplies the other activation signal on the terminal to which the selected one switch of the second set of switches is connected. An encoder configured to activate said one selected switch in said second set to do so.

【0073】

(16) In the encoder according to paragraph 15, the remaining switch is an encoder that is inactive for supplying an inert signal on the remaining terminals or each of the remaining terminals.

【0074】

(17) In the encoder according to paragraph 15 or 16, each switch in the first set of switches is coupled to a first voltage level and each switch in the second set of switches has a second voltage. Encoder coupled to the level.

【0075】

(18) In the encoder according to paragraph 15 or 16, each switch in the first set of switches is coupled to a first current source and each switch in the second set of switches has a second current. Encoder coupled to the source.

【0076】

(19) In the encoder according to any one of paragraphs 15 to 18, each terminal of the encoder is coupled to a common connection point via a resistor.

【0077】

(20) In the encoder described in paragraph 19, the common connection point is a voltage level / a voltage level on a terminal carrying the first active signal and a voltage level on the terminal carrying the second active signal. Encoder at an intermediate voltage level.

【0078】

(21) A decoder that receives a data symbol that appears in a set of at least three terminals, which detects which two of the terminals have an active signal and responds to identify which symbol is being received. Decoder configured as.

【0079】

(22) The decoder according to paragraph 21, which detects which of the two active signals is of the first form and which is of the second form, and receives the symbol. A decoder configured to use the information obtained by the detection for identification.

【0080】

(23) The decoder according to paragraph 22, which detects which of the terminals is at the first active voltage level and which of the terminals is at the second active voltage level, and is obtained by the detection. The information is a decoder used to identify the received symbol.

【0081】

(24) The decoder according to paragraph 23, which is configured to compare the voltage level on the terminal with a reference voltage.

【0082】

(twenty five) The decoder according to claim 24, which includes a first receiver subcircuit, a second receiver subcircuit, a data decoder, and a data output, the first receiver subcircuit for each of the terminals. Each switching element is controlled by a signal on the corresponding terminal to supply each output, and each output of the first receiver subcircuit is when the terminal controlling the switching element is at the first voltage level. The second receiver subcircuit is controlled by a signal on the terminal corresponding to each switching element for each of the terminals to supply each output, and each of the second receiver subcircuits. The output indicates when the terminal controlling the switching element is at the second voltage level, and the output of the first receiver subcircuit and the second receiver subcircuit is coupled to the input of the data decoder. In the data decoder, the first receiver subcircuit displays the presence of the first voltage level and the output of the second receiver subcircuit displays the presence of the second voltage level. A decoder configured to determine a transmitted data symbol and display the data symbol on the data output in response to any of the above.

【0083】

(26) The decoder according to paragraph 23, which is configured to detect the first active voltage level and the second active voltage level by comparing the voltage levels on the terminals with each other. A decoder in which the terminal having an active voltage level is identified as the terminal having the highest voltage and the terminal having the second active voltage level is identified as the terminal having the lowest voltage.

【0084】

(27) The decoder according to paragraph 22, which is configured to detect which of the terminals is receiving the current in the first direction and which is receiving the current in the opposite direction. The information obtained by is a decoder used for said identification of the received said symbol.

【0085】

(28) A system that appropriately includes the encoder according to any one of paragraphs 8 to 20 and the decoder according to any one of paragraphs 21 to 27.

【0086】

(29) A method of transmitting data, wherein the data is encoded as a string of symbols using the signal according to any one of paragraphs 1 to 7.

【0087】

(30) A differential data transmission system that transmits encoded data symbols as differential signals. A signal for transmitting a symbol over a set of at least three parallel channels, each channel has its first terminal connected to any one of the connection points P1 to PN, and each channel is a second terminal. Is connected to the common connection point Z. The signal includes an active signal on the channel two above and an inactive signal on the remaining channel for each symbol, and the symbol is distinguishable by which two of the channels have the active signal. ..

[Simple explanation of drawings]

[Figure 1]

It is a block diagram of a known differential data transmission system.

[Figure 2]

It is a circuit diagram of a transmitter suitable for the system of FIG.

[Fig. 3]

It is a representation diagram of the symbol transmitted by the system of FIGS. 1 and 2.

[Fig. 4]

It is a representation diagram of a symbol transmitted by a three-way system according to the present invention.

[Fig. 5]

It is a representation diagram of the symbol transmitted by the four-way system according to this invention.

[Fig. 6]

It is a circuit diagram of the transmitter according to this invention.

[Fig. 7]

It is an example waveform diagram at the output of the circuit of FIG.

[Fig. 8]

It is a circuit diagram of the receiver according to this invention.

[Explanation of symbols]

22 resistor 23 resistor 24 resistor 25 resistor 26 data encoder 27 transmitter 36 resistor 37 resistor 38 resistor 42 receiver 43 Data decoder 44 Receiver partial circuit 44'Receiver partial circuit P1 connection point, signal P2 connection point, signal P3 connection point, signal P4 connection point Z common connection point